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comparison src/cpu/sparc/vm/nativeInst_sparc.hpp @ 0:a61af66fc99e jdk7-b24
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author | duke |
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date | Sat, 01 Dec 2007 00:00:00 +0000 |
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children | 018d5b58dd4f |
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1 /* | |
2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved. | |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
21 * have any questions. | |
22 * | |
23 */ | |
24 | |
25 // We have interface for the following instructions: | |
26 // - NativeInstruction | |
27 // - - NativeCall | |
28 // - - NativeFarCall | |
29 // - - NativeMovConstReg | |
30 // - - NativeMovConstRegPatching | |
31 // - - NativeMovRegMem | |
32 // - - NativeMovRegMemPatching | |
33 // - - NativeJump | |
34 // - - NativeGeneralJump | |
35 // - - NativeIllegalInstruction | |
36 // The base class for different kinds of native instruction abstractions. | |
37 // Provides the primitive operations to manipulate code relative to this. | |
38 class NativeInstruction VALUE_OBJ_CLASS_SPEC { | |
39 friend class Relocation; | |
40 | |
41 public: | |
42 enum Sparc_specific_constants { | |
43 nop_instruction_size = 4 | |
44 }; | |
45 | |
46 bool is_nop() { return long_at(0) == nop_instruction(); } | |
47 bool is_call() { return is_op(long_at(0), Assembler::call_op); } | |
48 bool is_sethi() { return (is_op2(long_at(0), Assembler::sethi_op2) | |
49 && inv_rd(long_at(0)) != G0); } | |
50 | |
51 bool sets_cc() { | |
52 // conservative (returns true for some instructions that do not set the | |
53 // the condition code, such as, "save". | |
54 // Does not return true for the deprecated tagged instructions, such as, TADDcc | |
55 int x = long_at(0); | |
56 return (is_op(x, Assembler::arith_op) && | |
57 (inv_op3(x) & Assembler::cc_bit_op3) == Assembler::cc_bit_op3); | |
58 } | |
59 bool is_illegal(); | |
60 bool is_zombie() { | |
61 int x = long_at(0); | |
62 return is_op3(x, | |
63 VM_Version::v9_instructions_work() ? | |
64 Assembler::ldsw_op3 : Assembler::lduw_op3, | |
65 Assembler::ldst_op) | |
66 && Assembler::inv_rs1(x) == G0 | |
67 && Assembler::inv_rd(x) == O7; | |
68 } | |
69 bool is_ic_miss_trap(); // Inline-cache uses a trap to detect a miss | |
70 bool is_return() { | |
71 // is it the output of MacroAssembler::ret or MacroAssembler::retl? | |
72 int x = long_at(0); | |
73 const int pc_return_offset = 8; // see frame_sparc.hpp | |
74 return is_op3(x, Assembler::jmpl_op3, Assembler::arith_op) | |
75 && (inv_rs1(x) == I7 || inv_rs1(x) == O7) | |
76 && inv_immed(x) && inv_simm(x, 13) == pc_return_offset | |
77 && inv_rd(x) == G0; | |
78 } | |
79 bool is_int_jump() { | |
80 // is it the output of MacroAssembler::b? | |
81 int x = long_at(0); | |
82 return is_op2(x, Assembler::bp_op2) || is_op2(x, Assembler::br_op2); | |
83 } | |
84 bool is_float_jump() { | |
85 // is it the output of MacroAssembler::fb? | |
86 int x = long_at(0); | |
87 return is_op2(x, Assembler::fbp_op2) || is_op2(x, Assembler::fb_op2); | |
88 } | |
89 bool is_jump() { | |
90 return is_int_jump() || is_float_jump(); | |
91 } | |
92 bool is_cond_jump() { | |
93 int x = long_at(0); | |
94 return (is_int_jump() && Assembler::inv_cond(x) != Assembler::always) || | |
95 (is_float_jump() && Assembler::inv_cond(x) != Assembler::f_always); | |
96 } | |
97 | |
98 bool is_stack_bang() { | |
99 int x = long_at(0); | |
100 return is_op3(x, Assembler::stw_op3, Assembler::ldst_op) && | |
101 (inv_rd(x) == G0) && (inv_rs1(x) == SP) && (inv_rs2(x) == G3_scratch); | |
102 } | |
103 | |
104 bool is_prefetch() { | |
105 int x = long_at(0); | |
106 return is_op3(x, Assembler::prefetch_op3, Assembler::ldst_op); | |
107 } | |
108 | |
109 bool is_membar() { | |
110 int x = long_at(0); | |
111 return is_op3(x, Assembler::membar_op3, Assembler::arith_op) && | |
112 (inv_rd(x) == G0) && (inv_rs1(x) == O7); | |
113 } | |
114 | |
115 bool is_safepoint_poll() { | |
116 int x = long_at(0); | |
117 #ifdef _LP64 | |
118 return is_op3(x, Assembler::ldx_op3, Assembler::ldst_op) && | |
119 #else | |
120 return is_op3(x, Assembler::lduw_op3, Assembler::ldst_op) && | |
121 #endif | |
122 (inv_rd(x) == G0) && (inv_immed(x) ? Assembler::inv_simm13(x) == 0 : inv_rs2(x) == G0); | |
123 } | |
124 | |
125 bool is_zero_test(Register ®); | |
126 bool is_load_store_with_small_offset(Register reg); | |
127 | |
128 public: | |
129 #ifdef ASSERT | |
130 static int rdpc_instruction() { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | Assembler::u_field(5, 18, 14) | Assembler::rd(O7); } | |
131 #else | |
132 // Temporary fix: in optimized mode, u_field is a macro for efficiency reasons (see Assembler::u_field) - needs to be fixed | |
133 static int rdpc_instruction() { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | u_field(5, 18, 14) | Assembler::rd(O7); } | |
134 #endif | |
135 static int nop_instruction() { return Assembler::op(Assembler::branch_op) | Assembler::op2(Assembler::sethi_op2); } | |
136 static int illegal_instruction(); // the output of __ breakpoint_trap() | |
137 static int call_instruction(address destination, address pc) { return Assembler::op(Assembler::call_op) | Assembler::wdisp((intptr_t)destination, (intptr_t)pc, 30); } | |
138 | |
139 static int branch_instruction(Assembler::op2s op2val, Assembler::Condition c, bool a) { | |
140 return Assembler::op(Assembler::branch_op) | Assembler::op2(op2val) | Assembler::annul(a) | Assembler::cond(c); | |
141 } | |
142 | |
143 static int op3_instruction(Assembler::ops opval, Register rd, Assembler::op3s op3val, Register rs1, int simm13a) { | |
144 return Assembler::op(opval) | Assembler::rd(rd) | Assembler::op3(op3val) | Assembler::rs1(rs1) | Assembler::immed(true) | Assembler::simm(simm13a, 13); | |
145 } | |
146 | |
147 static int sethi_instruction(Register rd, int imm22a) { | |
148 return Assembler::op(Assembler::branch_op) | Assembler::rd(rd) | Assembler::op2(Assembler::sethi_op2) | Assembler::hi22(imm22a); | |
149 } | |
150 | |
151 protected: | |
152 address addr_at(int offset) const { return address(this) + offset; } | |
153 int long_at(int offset) const { return *(int*)addr_at(offset); } | |
154 void set_long_at(int offset, int i); /* deals with I-cache */ | |
155 void set_jlong_at(int offset, jlong i); /* deals with I-cache */ | |
156 void set_addr_at(int offset, address x); /* deals with I-cache */ | |
157 | |
158 address instruction_address() const { return addr_at(0); } | |
159 address next_instruction_address() const { return addr_at(BytesPerInstWord); } | |
160 | |
161 static bool is_op( int x, Assembler::ops opval) { | |
162 return Assembler::inv_op(x) == opval; | |
163 } | |
164 static bool is_op2(int x, Assembler::op2s op2val) { | |
165 return Assembler::inv_op(x) == Assembler::branch_op && Assembler::inv_op2(x) == op2val; | |
166 } | |
167 static bool is_op3(int x, Assembler::op3s op3val, Assembler::ops opval) { | |
168 return Assembler::inv_op(x) == opval && Assembler::inv_op3(x) == op3val; | |
169 } | |
170 | |
171 // utilities to help subclasses decode: | |
172 static Register inv_rd( int x ) { return Assembler::inv_rd( x); } | |
173 static Register inv_rs1( int x ) { return Assembler::inv_rs1(x); } | |
174 static Register inv_rs2( int x ) { return Assembler::inv_rs2(x); } | |
175 | |
176 static bool inv_immed( int x ) { return Assembler::inv_immed(x); } | |
177 static bool inv_annul( int x ) { return (Assembler::annul(true) & x) != 0; } | |
178 static int inv_cond( int x ) { return Assembler::inv_cond(x); } | |
179 | |
180 static int inv_op( int x ) { return Assembler::inv_op( x); } | |
181 static int inv_op2( int x ) { return Assembler::inv_op2(x); } | |
182 static int inv_op3( int x ) { return Assembler::inv_op3(x); } | |
183 | |
184 static int inv_simm( int x, int nbits ) { return Assembler::inv_simm(x, nbits); } | |
185 static intptr_t inv_wdisp( int x, int nbits ) { return Assembler::inv_wdisp( x, 0, nbits); } | |
186 static intptr_t inv_wdisp16( int x ) { return Assembler::inv_wdisp16(x, 0); } | |
187 static int branch_destination_offset(int x) { return Assembler::branch_destination(x, 0); } | |
188 static int patch_branch_destination_offset(int dest_offset, int x) { | |
189 return Assembler::patched_branch(dest_offset, x, 0); | |
190 } | |
191 void set_annul_bit() { set_long_at(0, long_at(0) | Assembler::annul(true)); } | |
192 | |
193 // utility for checking if x is either of 2 small constants | |
194 static bool is_either(int x, int k1, int k2) { | |
195 // return x == k1 || x == k2; | |
196 return (1 << x) & (1 << k1 | 1 << k2); | |
197 } | |
198 | |
199 // utility for checking overflow of signed instruction fields | |
200 static bool fits_in_simm(int x, int nbits) { | |
201 // cf. Assembler::assert_signed_range() | |
202 // return -(1 << nbits-1) <= x && x < ( 1 << nbits-1), | |
203 return (unsigned)(x + (1 << nbits-1)) < (unsigned)(1 << nbits); | |
204 } | |
205 | |
206 // set a signed immediate field | |
207 static int set_simm(int insn, int imm, int nbits) { | |
208 return (insn &~ Assembler::simm(-1, nbits)) | Assembler::simm(imm, nbits); | |
209 } | |
210 | |
211 // set a wdisp field (disp should be the difference of two addresses) | |
212 static int set_wdisp(int insn, intptr_t disp, int nbits) { | |
213 return (insn &~ Assembler::wdisp((intptr_t)-4, (intptr_t)0, nbits)) | Assembler::wdisp(disp, 0, nbits); | |
214 } | |
215 | |
216 static int set_wdisp16(int insn, intptr_t disp) { | |
217 return (insn &~ Assembler::wdisp16((intptr_t)-4, 0)) | Assembler::wdisp16(disp, 0); | |
218 } | |
219 | |
220 // get a simm13 field from an arithmetic or memory instruction | |
221 static int get_simm13(int insn) { | |
222 assert(is_either(Assembler::inv_op(insn), | |
223 Assembler::arith_op, Assembler::ldst_op) && | |
224 (insn & Assembler::immed(true)), "must have a simm13 field"); | |
225 return Assembler::inv_simm(insn, 13); | |
226 } | |
227 | |
228 // set the simm13 field of an arithmetic or memory instruction | |
229 static bool set_simm13(int insn, int imm) { | |
230 get_simm13(insn); // tickle the assertion check | |
231 return set_simm(insn, imm, 13); | |
232 } | |
233 | |
234 // combine the fields of a sethi stream (7 instructions ) and an add, jmp or ld/st | |
235 static intptr_t data64( address pc, int arith_insn ) { | |
236 assert(is_op2(*(unsigned int *)pc, Assembler::sethi_op2), "must be sethi"); | |
237 intptr_t hi = (intptr_t)gethi( (unsigned int *)pc ); | |
238 intptr_t lo = (intptr_t)get_simm13(arith_insn); | |
239 assert((unsigned)lo < (1 << 10), "offset field of set_oop must be 10 bits"); | |
240 return hi | lo; | |
241 } | |
242 | |
243 // Regenerate the instruction sequence that performs the 64 bit | |
244 // sethi. This only does the sethi. The disp field (bottom 10 bits) | |
245 // must be handled seperately. | |
246 static void set_data64_sethi(address instaddr, intptr_t x); | |
247 | |
248 // combine the fields of a sethi/simm13 pair (simm13 = or, add, jmpl, ld/st) | |
249 static int data32(int sethi_insn, int arith_insn) { | |
250 assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi"); | |
251 int hi = Assembler::inv_hi22(sethi_insn); | |
252 int lo = get_simm13(arith_insn); | |
253 assert((unsigned)lo < (1 << 10), "offset field of set_oop must be 10 bits"); | |
254 return hi | lo; | |
255 } | |
256 | |
257 static int set_data32_sethi(int sethi_insn, int imm) { | |
258 // note that Assembler::hi22 clips the low 10 bits for us | |
259 assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi"); | |
260 return (sethi_insn &~ Assembler::hi22(-1)) | Assembler::hi22(imm); | |
261 } | |
262 | |
263 static int set_data32_simm13(int arith_insn, int imm) { | |
264 get_simm13(arith_insn); // tickle the assertion check | |
265 int imm10 = Assembler::low10(imm); | |
266 return (arith_insn &~ Assembler::simm(-1, 13)) | Assembler::simm(imm10, 13); | |
267 } | |
268 | |
269 static int low10(int imm) { | |
270 return Assembler::low10(imm); | |
271 } | |
272 | |
273 // Perform the inverse of the LP64 Macroassembler::sethi | |
274 // routine. Extracts the 54 bits of address from the instruction | |
275 // stream. This routine must agree with the sethi routine in | |
276 // assembler_inline_sparc.hpp | |
277 static address gethi( unsigned int *pc ) { | |
278 int i = 0; | |
279 uintptr_t adr; | |
280 // We first start out with the real sethi instruction | |
281 assert(is_op2(*pc, Assembler::sethi_op2), "in gethi - must be sethi"); | |
282 adr = (unsigned int)Assembler::inv_hi22( *(pc++) ); | |
283 i++; | |
284 while ( i < 7 ) { | |
285 // We're done if we hit a nop | |
286 if ( (int)*pc == nop_instruction() ) break; | |
287 assert ( Assembler::inv_op(*pc) == Assembler::arith_op, "in gethi - must be arith_op" ); | |
288 switch ( Assembler::inv_op3(*pc) ) { | |
289 case Assembler::xor_op3: | |
290 adr ^= (intptr_t)get_simm13( *pc ); | |
291 return ( (address)adr ); | |
292 break; | |
293 case Assembler::sll_op3: | |
294 adr <<= ( *pc & 0x3f ); | |
295 break; | |
296 case Assembler::or_op3: | |
297 adr |= (intptr_t)get_simm13( *pc ); | |
298 break; | |
299 default: | |
300 assert ( 0, "in gethi - Should not reach here" ); | |
301 break; | |
302 } | |
303 pc++; | |
304 i++; | |
305 } | |
306 return ( (address)adr ); | |
307 } | |
308 | |
309 public: | |
310 void verify(); | |
311 void print(); | |
312 | |
313 // unit test stuff | |
314 static void test() {} // override for testing | |
315 | |
316 inline friend NativeInstruction* nativeInstruction_at(address address); | |
317 }; | |
318 | |
319 inline NativeInstruction* nativeInstruction_at(address address) { | |
320 NativeInstruction* inst = (NativeInstruction*)address; | |
321 #ifdef ASSERT | |
322 inst->verify(); | |
323 #endif | |
324 return inst; | |
325 } | |
326 | |
327 | |
328 | |
329 //----------------------------------------------------------------------------- | |
330 | |
331 // The NativeCall is an abstraction for accessing/manipulating native call imm32 instructions. | |
332 // (used to manipulate inline caches, primitive & dll calls, etc.) | |
333 inline NativeCall* nativeCall_at(address instr); | |
334 inline NativeCall* nativeCall_overwriting_at(address instr, | |
335 address destination); | |
336 inline NativeCall* nativeCall_before(address return_address); | |
337 class NativeCall: public NativeInstruction { | |
338 public: | |
339 enum Sparc_specific_constants { | |
340 instruction_size = 8, | |
341 return_address_offset = 8, | |
342 call_displacement_width = 30, | |
343 displacement_offset = 0, | |
344 instruction_offset = 0 | |
345 }; | |
346 address instruction_address() const { return addr_at(0); } | |
347 address next_instruction_address() const { return addr_at(instruction_size); } | |
348 address return_address() const { return addr_at(return_address_offset); } | |
349 | |
350 address destination() const { return inv_wdisp(long_at(0), call_displacement_width) + instruction_address(); } | |
351 address displacement_address() const { return addr_at(displacement_offset); } | |
352 void set_destination(address dest) { set_long_at(0, set_wdisp(long_at(0), dest - instruction_address(), call_displacement_width)); } | |
353 void set_destination_mt_safe(address dest); | |
354 | |
355 void verify_alignment() {} // do nothing on sparc | |
356 void verify(); | |
357 void print(); | |
358 | |
359 // unit test stuff | |
360 static void test(); | |
361 | |
362 // Creation | |
363 friend inline NativeCall* nativeCall_at(address instr); | |
364 friend NativeCall* nativeCall_overwriting_at(address instr, address destination = NULL) { | |
365 // insert a "blank" call: | |
366 NativeCall* call = (NativeCall*)instr; | |
367 call->set_long_at(0 * BytesPerInstWord, call_instruction(destination, instr)); | |
368 call->set_long_at(1 * BytesPerInstWord, nop_instruction()); | |
369 assert(call->addr_at(2 * BytesPerInstWord) - instr == instruction_size, "instruction size"); | |
370 // check its structure now: | |
371 assert(nativeCall_at(instr)->destination() == destination, "correct call destination"); | |
372 return call; | |
373 } | |
374 | |
375 friend inline NativeCall* nativeCall_before(address return_address) { | |
376 NativeCall* call = (NativeCall*)(return_address - return_address_offset); | |
377 #ifdef ASSERT | |
378 call->verify(); | |
379 #endif | |
380 return call; | |
381 } | |
382 | |
383 static bool is_call_at(address instr) { | |
384 return nativeInstruction_at(instr)->is_call(); | |
385 } | |
386 | |
387 static bool is_call_before(address instr) { | |
388 return nativeInstruction_at(instr - return_address_offset)->is_call(); | |
389 } | |
390 | |
391 static bool is_call_to(address instr, address target) { | |
392 return nativeInstruction_at(instr)->is_call() && | |
393 nativeCall_at(instr)->destination() == target; | |
394 } | |
395 | |
396 // MT-safe patching of a call instruction. | |
397 static void insert(address code_pos, address entry) { | |
398 (void)nativeCall_overwriting_at(code_pos, entry); | |
399 } | |
400 | |
401 static void replace_mt_safe(address instr_addr, address code_buffer); | |
402 }; | |
403 inline NativeCall* nativeCall_at(address instr) { | |
404 NativeCall* call = (NativeCall*)instr; | |
405 #ifdef ASSERT | |
406 call->verify(); | |
407 #endif | |
408 return call; | |
409 } | |
410 | |
411 // The NativeFarCall is an abstraction for accessing/manipulating native call-anywhere | |
412 // instructions in the sparcv9 vm. Used to call native methods which may be loaded | |
413 // anywhere in the address space, possibly out of reach of a call instruction. | |
414 | |
415 #ifndef _LP64 | |
416 | |
417 // On 32-bit systems, a far call is the same as a near one. | |
418 class NativeFarCall; | |
419 inline NativeFarCall* nativeFarCall_at(address instr); | |
420 class NativeFarCall : public NativeCall { | |
421 public: | |
422 friend inline NativeFarCall* nativeFarCall_at(address instr) { return (NativeFarCall*)nativeCall_at(instr); } | |
423 friend NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination = NULL) | |
424 { return (NativeFarCall*)nativeCall_overwriting_at(instr, destination); } | |
425 friend NativeFarCall* nativeFarCall_before(address return_address) | |
426 { return (NativeFarCall*)nativeCall_before(return_address); } | |
427 }; | |
428 | |
429 #else | |
430 | |
431 // The format of this extended-range call is: | |
432 // jumpl_to addr, lreg | |
433 // == sethi %hi54(addr), O7 ; jumpl O7, %lo10(addr), O7 ; <delay> | |
434 // That is, it is essentially the same as a NativeJump. | |
435 class NativeFarCall; | |
436 inline NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination); | |
437 inline NativeFarCall* nativeFarCall_at(address instr); | |
438 class NativeFarCall: public NativeInstruction { | |
439 public: | |
440 enum Sparc_specific_constants { | |
441 // instruction_size includes the delay slot instruction. | |
442 instruction_size = 9 * BytesPerInstWord, | |
443 return_address_offset = 9 * BytesPerInstWord, | |
444 jmpl_offset = 7 * BytesPerInstWord, | |
445 displacement_offset = 0, | |
446 instruction_offset = 0 | |
447 }; | |
448 address instruction_address() const { return addr_at(0); } | |
449 address next_instruction_address() const { return addr_at(instruction_size); } | |
450 address return_address() const { return addr_at(return_address_offset); } | |
451 | |
452 address destination() const { | |
453 return (address) data64(addr_at(0), long_at(jmpl_offset)); | |
454 } | |
455 address displacement_address() const { return addr_at(displacement_offset); } | |
456 void set_destination(address dest); | |
457 | |
458 bool destination_is_compiled_verified_entry_point(); | |
459 | |
460 void verify(); | |
461 void print(); | |
462 | |
463 // unit test stuff | |
464 static void test(); | |
465 | |
466 // Creation | |
467 friend inline NativeFarCall* nativeFarCall_at(address instr) { | |
468 NativeFarCall* call = (NativeFarCall*)instr; | |
469 #ifdef ASSERT | |
470 call->verify(); | |
471 #endif | |
472 return call; | |
473 } | |
474 | |
475 friend inline NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination = NULL) { | |
476 Unimplemented(); | |
477 NativeFarCall* call = (NativeFarCall*)instr; | |
478 return call; | |
479 } | |
480 | |
481 friend NativeFarCall* nativeFarCall_before(address return_address) { | |
482 NativeFarCall* call = (NativeFarCall*)(return_address - return_address_offset); | |
483 #ifdef ASSERT | |
484 call->verify(); | |
485 #endif | |
486 return call; | |
487 } | |
488 | |
489 static bool is_call_at(address instr); | |
490 | |
491 // MT-safe patching of a call instruction. | |
492 static void insert(address code_pos, address entry) { | |
493 (void)nativeFarCall_overwriting_at(code_pos, entry); | |
494 } | |
495 static void replace_mt_safe(address instr_addr, address code_buffer); | |
496 }; | |
497 | |
498 #endif // _LP64 | |
499 | |
500 // An interface for accessing/manipulating native set_oop imm, reg instructions. | |
501 // (used to manipulate inlined data references, etc.) | |
502 // set_oop imm, reg | |
503 // == sethi %hi22(imm), reg ; add reg, %lo10(imm), reg | |
504 class NativeMovConstReg; | |
505 inline NativeMovConstReg* nativeMovConstReg_at(address address); | |
506 class NativeMovConstReg: public NativeInstruction { | |
507 public: | |
508 enum Sparc_specific_constants { | |
509 sethi_offset = 0, | |
510 #ifdef _LP64 | |
511 add_offset = 7 * BytesPerInstWord, | |
512 instruction_size = 8 * BytesPerInstWord | |
513 #else | |
514 add_offset = 4, | |
515 instruction_size = 8 | |
516 #endif | |
517 }; | |
518 | |
519 address instruction_address() const { return addr_at(0); } | |
520 address next_instruction_address() const { return addr_at(instruction_size); } | |
521 | |
522 // (The [set_]data accessor respects oop_type relocs also.) | |
523 intptr_t data() const; | |
524 void set_data(intptr_t x); | |
525 | |
526 // report the destination register | |
527 Register destination() { return inv_rd(long_at(sethi_offset)); } | |
528 | |
529 void verify(); | |
530 void print(); | |
531 | |
532 // unit test stuff | |
533 static void test(); | |
534 | |
535 // Creation | |
536 friend inline NativeMovConstReg* nativeMovConstReg_at(address address) { | |
537 NativeMovConstReg* test = (NativeMovConstReg*)address; | |
538 #ifdef ASSERT | |
539 test->verify(); | |
540 #endif | |
541 return test; | |
542 } | |
543 | |
544 | |
545 friend NativeMovConstReg* nativeMovConstReg_before(address address) { | |
546 NativeMovConstReg* test = (NativeMovConstReg*)(address - instruction_size); | |
547 #ifdef ASSERT | |
548 test->verify(); | |
549 #endif | |
550 return test; | |
551 } | |
552 | |
553 }; | |
554 | |
555 | |
556 // An interface for accessing/manipulating native set_oop imm, reg instructions. | |
557 // (used to manipulate inlined data references, etc.) | |
558 // set_oop imm, reg | |
559 // == sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg | |
560 // | |
561 // Note that it is identical to NativeMovConstReg with the exception of a nop between the | |
562 // sethi and the add. The nop is required to be in the delay slot of the call instruction | |
563 // which overwrites the sethi during patching. | |
564 class NativeMovConstRegPatching; | |
565 inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address);class NativeMovConstRegPatching: public NativeInstruction { | |
566 public: | |
567 enum Sparc_specific_constants { | |
568 sethi_offset = 0, | |
569 #ifdef _LP64 | |
570 nop_offset = 7 * BytesPerInstWord, | |
571 #else | |
572 nop_offset = sethi_offset + BytesPerInstWord, | |
573 #endif | |
574 add_offset = nop_offset + BytesPerInstWord, | |
575 instruction_size = add_offset + BytesPerInstWord | |
576 }; | |
577 | |
578 address instruction_address() const { return addr_at(0); } | |
579 address next_instruction_address() const { return addr_at(instruction_size); } | |
580 | |
581 // (The [set_]data accessor respects oop_type relocs also.) | |
582 int data() const; | |
583 void set_data(int x); | |
584 | |
585 // report the destination register | |
586 Register destination() { return inv_rd(long_at(sethi_offset)); } | |
587 | |
588 void verify(); | |
589 void print(); | |
590 | |
591 // unit test stuff | |
592 static void test(); | |
593 | |
594 // Creation | |
595 friend inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) { | |
596 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)address; | |
597 #ifdef ASSERT | |
598 test->verify(); | |
599 #endif | |
600 return test; | |
601 } | |
602 | |
603 | |
604 friend NativeMovConstRegPatching* nativeMovConstRegPatching_before(address address) { | |
605 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_size); | |
606 #ifdef ASSERT | |
607 test->verify(); | |
608 #endif | |
609 return test; | |
610 } | |
611 | |
612 }; | |
613 | |
614 | |
615 // An interface for accessing/manipulating native memory ops | |
616 // ld* [reg + offset], reg | |
617 // st* reg, [reg + offset] | |
618 // sethi %hi(imm), reg; add reg, %lo(imm), reg; ld* [reg1 + reg], reg2 | |
619 // sethi %hi(imm), reg; add reg, %lo(imm), reg; st* reg2, [reg1 + reg] | |
620 // Ops covered: {lds,ldu,st}{w,b,h}, {ld,st}{d,x} | |
621 // | |
622 class NativeMovRegMem; | |
623 inline NativeMovRegMem* nativeMovRegMem_at (address address); | |
624 class NativeMovRegMem: public NativeInstruction { | |
625 public: | |
626 enum Sparc_specific_constants { | |
627 op3_mask_ld = 1 << Assembler::lduw_op3 | | |
628 1 << Assembler::ldub_op3 | | |
629 1 << Assembler::lduh_op3 | | |
630 1 << Assembler::ldd_op3 | | |
631 1 << Assembler::ldsw_op3 | | |
632 1 << Assembler::ldsb_op3 | | |
633 1 << Assembler::ldsh_op3 | | |
634 1 << Assembler::ldx_op3, | |
635 op3_mask_st = 1 << Assembler::stw_op3 | | |
636 1 << Assembler::stb_op3 | | |
637 1 << Assembler::sth_op3 | | |
638 1 << Assembler::std_op3 | | |
639 1 << Assembler::stx_op3, | |
640 op3_ldst_int_limit = Assembler::ldf_op3, | |
641 op3_mask_ldf = 1 << (Assembler::ldf_op3 - op3_ldst_int_limit) | | |
642 1 << (Assembler::lddf_op3 - op3_ldst_int_limit), | |
643 op3_mask_stf = 1 << (Assembler::stf_op3 - op3_ldst_int_limit) | | |
644 1 << (Assembler::stdf_op3 - op3_ldst_int_limit), | |
645 | |
646 offset_width = 13, | |
647 sethi_offset = 0, | |
648 #ifdef _LP64 | |
649 add_offset = 7 * BytesPerInstWord, | |
650 #else | |
651 add_offset = 4, | |
652 #endif | |
653 ldst_offset = add_offset + BytesPerInstWord | |
654 }; | |
655 bool is_immediate() const { | |
656 // check if instruction is ld* [reg + offset], reg or st* reg, [reg + offset] | |
657 int i0 = long_at(0); | |
658 return (is_op(i0, Assembler::ldst_op)); | |
659 } | |
660 | |
661 address instruction_address() const { return addr_at(0); } | |
662 address next_instruction_address() const { | |
663 #ifdef _LP64 | |
664 return addr_at(is_immediate() ? 4 : (7 * BytesPerInstWord)); | |
665 #else | |
666 return addr_at(is_immediate() ? 4 : 12); | |
667 #endif | |
668 } | |
669 intptr_t offset() const { | |
670 return is_immediate()? inv_simm(long_at(0), offset_width) : | |
671 nativeMovConstReg_at(addr_at(0))->data(); | |
672 } | |
673 void set_offset(intptr_t x) { | |
674 if (is_immediate()) { | |
675 guarantee(fits_in_simm(x, offset_width), "data block offset overflow"); | |
676 set_long_at(0, set_simm(long_at(0), x, offset_width)); | |
677 } else | |
678 nativeMovConstReg_at(addr_at(0))->set_data(x); | |
679 } | |
680 | |
681 void add_offset_in_bytes(intptr_t radd_offset) { | |
682 set_offset (offset() + radd_offset); | |
683 } | |
684 | |
685 void copy_instruction_to(address new_instruction_address); | |
686 | |
687 void verify(); | |
688 void print (); | |
689 | |
690 // unit test stuff | |
691 static void test(); | |
692 | |
693 private: | |
694 friend inline NativeMovRegMem* nativeMovRegMem_at (address address) { | |
695 NativeMovRegMem* test = (NativeMovRegMem*)address; | |
696 #ifdef ASSERT | |
697 test->verify(); | |
698 #endif | |
699 return test; | |
700 } | |
701 }; | |
702 | |
703 | |
704 // An interface for accessing/manipulating native memory ops | |
705 // ld* [reg + offset], reg | |
706 // st* reg, [reg + offset] | |
707 // sethi %hi(imm), reg; nop; add reg, %lo(imm), reg; ld* [reg1 + reg], reg2 | |
708 // sethi %hi(imm), reg; nop; add reg, %lo(imm), reg; st* reg2, [reg1 + reg] | |
709 // Ops covered: {lds,ldu,st}{w,b,h}, {ld,st}{d,x} | |
710 // | |
711 // Note that it is identical to NativeMovRegMem with the exception of a nop between the | |
712 // sethi and the add. The nop is required to be in the delay slot of the call instruction | |
713 // which overwrites the sethi during patching. | |
714 class NativeMovRegMemPatching; | |
715 inline NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address); | |
716 class NativeMovRegMemPatching: public NativeInstruction { | |
717 public: | |
718 enum Sparc_specific_constants { | |
719 op3_mask_ld = 1 << Assembler::lduw_op3 | | |
720 1 << Assembler::ldub_op3 | | |
721 1 << Assembler::lduh_op3 | | |
722 1 << Assembler::ldd_op3 | | |
723 1 << Assembler::ldsw_op3 | | |
724 1 << Assembler::ldsb_op3 | | |
725 1 << Assembler::ldsh_op3 | | |
726 1 << Assembler::ldx_op3, | |
727 op3_mask_st = 1 << Assembler::stw_op3 | | |
728 1 << Assembler::stb_op3 | | |
729 1 << Assembler::sth_op3 | | |
730 1 << Assembler::std_op3 | | |
731 1 << Assembler::stx_op3, | |
732 op3_ldst_int_limit = Assembler::ldf_op3, | |
733 op3_mask_ldf = 1 << (Assembler::ldf_op3 - op3_ldst_int_limit) | | |
734 1 << (Assembler::lddf_op3 - op3_ldst_int_limit), | |
735 op3_mask_stf = 1 << (Assembler::stf_op3 - op3_ldst_int_limit) | | |
736 1 << (Assembler::stdf_op3 - op3_ldst_int_limit), | |
737 | |
738 offset_width = 13, | |
739 sethi_offset = 0, | |
740 #ifdef _LP64 | |
741 nop_offset = 7 * BytesPerInstWord, | |
742 #else | |
743 nop_offset = 4, | |
744 #endif | |
745 add_offset = nop_offset + BytesPerInstWord, | |
746 ldst_offset = add_offset + BytesPerInstWord | |
747 }; | |
748 bool is_immediate() const { | |
749 // check if instruction is ld* [reg + offset], reg or st* reg, [reg + offset] | |
750 int i0 = long_at(0); | |
751 return (is_op(i0, Assembler::ldst_op)); | |
752 } | |
753 | |
754 address instruction_address() const { return addr_at(0); } | |
755 address next_instruction_address() const { | |
756 return addr_at(is_immediate()? 4 : 16); | |
757 } | |
758 int offset() const { | |
759 return is_immediate()? inv_simm(long_at(0), offset_width) : | |
760 nativeMovConstRegPatching_at(addr_at(0))->data(); | |
761 } | |
762 void set_offset(int x) { | |
763 if (is_immediate()) { | |
764 guarantee(fits_in_simm(x, offset_width), "data block offset overflow"); | |
765 set_long_at(0, set_simm(long_at(0), x, offset_width)); | |
766 } | |
767 else | |
768 nativeMovConstRegPatching_at(addr_at(0))->set_data(x); | |
769 } | |
770 | |
771 void add_offset_in_bytes(intptr_t radd_offset) { | |
772 set_offset (offset() + radd_offset); | |
773 } | |
774 | |
775 void copy_instruction_to(address new_instruction_address); | |
776 | |
777 void verify(); | |
778 void print (); | |
779 | |
780 // unit test stuff | |
781 static void test(); | |
782 | |
783 private: | |
784 friend inline NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) { | |
785 NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)address; | |
786 #ifdef ASSERT | |
787 test->verify(); | |
788 #endif | |
789 return test; | |
790 } | |
791 }; | |
792 | |
793 | |
794 // An interface for accessing/manipulating native jumps | |
795 // jump_to addr | |
796 // == sethi %hi22(addr), temp ; jumpl reg, %lo10(addr), G0 ; <delay> | |
797 // jumpl_to addr, lreg | |
798 // == sethi %hi22(addr), temp ; jumpl reg, %lo10(addr), lreg ; <delay> | |
799 class NativeJump; | |
800 inline NativeJump* nativeJump_at(address address); | |
801 class NativeJump: public NativeInstruction { | |
802 private: | |
803 void guarantee_displacement(int disp, int width) { | |
804 guarantee(fits_in_simm(disp, width + 2), "branch displacement overflow"); | |
805 } | |
806 | |
807 public: | |
808 enum Sparc_specific_constants { | |
809 sethi_offset = 0, | |
810 #ifdef _LP64 | |
811 jmpl_offset = 7 * BytesPerInstWord, | |
812 instruction_size = 9 * BytesPerInstWord // includes delay slot | |
813 #else | |
814 jmpl_offset = 1 * BytesPerInstWord, | |
815 instruction_size = 3 * BytesPerInstWord // includes delay slot | |
816 #endif | |
817 }; | |
818 | |
819 address instruction_address() const { return addr_at(0); } | |
820 address next_instruction_address() const { return addr_at(instruction_size); } | |
821 | |
822 #ifdef _LP64 | |
823 address jump_destination() const { | |
824 return (address) data64(instruction_address(), long_at(jmpl_offset)); | |
825 } | |
826 void set_jump_destination(address dest) { | |
827 set_data64_sethi( instruction_address(), (intptr_t)dest); | |
828 set_long_at(jmpl_offset, set_data32_simm13( long_at(jmpl_offset), (intptr_t)dest)); | |
829 } | |
830 #else | |
831 address jump_destination() const { | |
832 return (address) data32(long_at(sethi_offset), long_at(jmpl_offset)); | |
833 } | |
834 void set_jump_destination(address dest) { | |
835 set_long_at(sethi_offset, set_data32_sethi( long_at(sethi_offset), (intptr_t)dest)); | |
836 set_long_at(jmpl_offset, set_data32_simm13( long_at(jmpl_offset), (intptr_t)dest)); | |
837 } | |
838 #endif | |
839 | |
840 // Creation | |
841 friend inline NativeJump* nativeJump_at(address address) { | |
842 NativeJump* jump = (NativeJump*)address; | |
843 #ifdef ASSERT | |
844 jump->verify(); | |
845 #endif | |
846 return jump; | |
847 } | |
848 | |
849 void verify(); | |
850 void print(); | |
851 | |
852 // Unit testing stuff | |
853 static void test(); | |
854 | |
855 // Insertion of native jump instruction | |
856 static void insert(address code_pos, address entry); | |
857 // MT-safe insertion of native jump at verified method entry | |
858 static void check_verified_entry_alignment(address entry, address verified_entry) { | |
859 // nothing to do for sparc. | |
860 } | |
861 static void patch_verified_entry(address entry, address verified_entry, address dest); | |
862 }; | |
863 | |
864 | |
865 | |
866 // Despite the name, handles only simple branches. | |
867 class NativeGeneralJump; | |
868 inline NativeGeneralJump* nativeGeneralJump_at(address address); | |
869 class NativeGeneralJump: public NativeInstruction { | |
870 public: | |
871 enum Sparc_specific_constants { | |
872 instruction_size = 8 | |
873 }; | |
874 | |
875 address instruction_address() const { return addr_at(0); } | |
876 address jump_destination() const { return addr_at(0) + branch_destination_offset(long_at(0)); } | |
877 void set_jump_destination(address dest) { | |
878 int patched_instr = patch_branch_destination_offset(dest - addr_at(0), long_at(0)); | |
879 set_long_at(0, patched_instr); | |
880 } | |
881 void set_annul() { set_annul_bit(); } | |
882 NativeInstruction *delay_slot_instr() { return nativeInstruction_at(addr_at(4));} | |
883 void fill_delay_slot(int instr) { set_long_at(4, instr);} | |
884 Assembler::Condition condition() { | |
885 int x = long_at(0); | |
886 return (Assembler::Condition) Assembler::inv_cond(x); | |
887 } | |
888 | |
889 // Creation | |
890 friend inline NativeGeneralJump* nativeGeneralJump_at(address address) { | |
891 NativeGeneralJump* jump = (NativeGeneralJump*)(address); | |
892 #ifdef ASSERT | |
893 jump->verify(); | |
894 #endif | |
895 return jump; | |
896 } | |
897 | |
898 // Insertion of native general jump instruction | |
899 static void insert_unconditional(address code_pos, address entry); | |
900 static void replace_mt_safe(address instr_addr, address code_buffer); | |
901 | |
902 void verify(); | |
903 }; | |
904 | |
905 | |
906 class NativeIllegalInstruction: public NativeInstruction { | |
907 public: | |
908 enum Sparc_specific_constants { | |
909 instruction_size = 4 | |
910 }; | |
911 | |
912 // Insert illegal opcode as specific address | |
913 static void insert(address code_pos); | |
914 }; |