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comparison src/cpu/sparc/vm/register_sparc.hpp @ 0:a61af66fc99e jdk7-b24

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date Sat, 01 Dec 2007 00:00:00 +0000
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1 /*
2 * Copyright 2000-2007 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 // forward declaration
26 class Address;
27 class VMRegImpl;
28 typedef VMRegImpl* VMReg;
29
30
31 // Use Register as shortcut
32 class RegisterImpl;
33 typedef RegisterImpl* Register;
34
35
36 inline Register as_Register(int encoding) {
37 return (Register)(intptr_t) encoding;
38 }
39
40 // The implementation of integer registers for the SPARC architecture
41 class RegisterImpl: public AbstractRegisterImpl {
42 public:
43 enum {
44 log_set_size = 3, // the number of bits to encode the set register number
45 number_of_sets = 4, // the number of registers sets (in, local, out, global)
46 number_of_registers = number_of_sets << log_set_size,
47
48 iset_no = 3, ibase = iset_no << log_set_size, // the in register set
49 lset_no = 2, lbase = lset_no << log_set_size, // the local register set
50 oset_no = 1, obase = oset_no << log_set_size, // the output register set
51 gset_no = 0, gbase = gset_no << log_set_size // the global register set
52 };
53
54
55 friend Register as_Register(int encoding);
56 // set specific construction
57 friend Register as_iRegister(int number);
58 friend Register as_lRegister(int number);
59 friend Register as_oRegister(int number);
60 friend Register as_gRegister(int number);
61
62 VMReg as_VMReg();
63
64 // accessors
65 int encoding() const { assert(is_valid(), "invalid register"); return value(); }
66 const char* name() const;
67
68 // testers
69 bool is_valid() const { return (0 <= (value()&0x7F) && (value()&0x7F) < number_of_registers); }
70 bool is_even() const { return (encoding() & 1) == 0; }
71 bool is_in() const { return (encoding() >> log_set_size) == iset_no; }
72 bool is_local() const { return (encoding() >> log_set_size) == lset_no; }
73 bool is_out() const { return (encoding() >> log_set_size) == oset_no; }
74 bool is_global() const { return (encoding() >> log_set_size) == gset_no; }
75
76 // derived registers, offsets, and addresses
77 Register successor() const { return as_Register(encoding() + 1); }
78
79 int input_number() const {
80 assert(is_in(), "must be input register");
81 return encoding() - ibase;
82 }
83
84 Register after_save() const {
85 assert(is_out() || is_global(), "register not visible after save");
86 return is_out() ? as_Register(encoding() + (ibase - obase)) : (const Register)this;
87 }
88
89 Register after_restore() const {
90 assert(is_in() || is_global(), "register not visible after restore");
91 return is_in() ? as_Register(encoding() + (obase - ibase)) : (const Register)this;
92 }
93
94 int sp_offset_in_saved_window() const {
95 assert(is_in() || is_local(), "only i and l registers are saved in frame");
96 return encoding() - lbase;
97 }
98
99 inline Address address_in_saved_window() const; // implemented in assembler_sparc.hpp
100 };
101
102
103 // set specific construction
104 inline Register as_iRegister(int number) { return as_Register(RegisterImpl::ibase + number); }
105 inline Register as_lRegister(int number) { return as_Register(RegisterImpl::lbase + number); }
106 inline Register as_oRegister(int number) { return as_Register(RegisterImpl::obase + number); }
107 inline Register as_gRegister(int number) { return as_Register(RegisterImpl::gbase + number); }
108
109 // The integer registers of the SPARC architecture
110
111 CONSTANT_REGISTER_DECLARATION(Register, noreg , (-1));
112
113 CONSTANT_REGISTER_DECLARATION(Register, G0 , (RegisterImpl::gbase + 0));
114 CONSTANT_REGISTER_DECLARATION(Register, G1 , (RegisterImpl::gbase + 1));
115 CONSTANT_REGISTER_DECLARATION(Register, G2 , (RegisterImpl::gbase + 2));
116 CONSTANT_REGISTER_DECLARATION(Register, G3 , (RegisterImpl::gbase + 3));
117 CONSTANT_REGISTER_DECLARATION(Register, G4 , (RegisterImpl::gbase + 4));
118 CONSTANT_REGISTER_DECLARATION(Register, G5 , (RegisterImpl::gbase + 5));
119 CONSTANT_REGISTER_DECLARATION(Register, G6 , (RegisterImpl::gbase + 6));
120 CONSTANT_REGISTER_DECLARATION(Register, G7 , (RegisterImpl::gbase + 7));
121
122 CONSTANT_REGISTER_DECLARATION(Register, O0 , (RegisterImpl::obase + 0));
123 CONSTANT_REGISTER_DECLARATION(Register, O1 , (RegisterImpl::obase + 1));
124 CONSTANT_REGISTER_DECLARATION(Register, O2 , (RegisterImpl::obase + 2));
125 CONSTANT_REGISTER_DECLARATION(Register, O3 , (RegisterImpl::obase + 3));
126 CONSTANT_REGISTER_DECLARATION(Register, O4 , (RegisterImpl::obase + 4));
127 CONSTANT_REGISTER_DECLARATION(Register, O5 , (RegisterImpl::obase + 5));
128 CONSTANT_REGISTER_DECLARATION(Register, O6 , (RegisterImpl::obase + 6));
129 CONSTANT_REGISTER_DECLARATION(Register, O7 , (RegisterImpl::obase + 7));
130
131 CONSTANT_REGISTER_DECLARATION(Register, L0 , (RegisterImpl::lbase + 0));
132 CONSTANT_REGISTER_DECLARATION(Register, L1 , (RegisterImpl::lbase + 1));
133 CONSTANT_REGISTER_DECLARATION(Register, L2 , (RegisterImpl::lbase + 2));
134 CONSTANT_REGISTER_DECLARATION(Register, L3 , (RegisterImpl::lbase + 3));
135 CONSTANT_REGISTER_DECLARATION(Register, L4 , (RegisterImpl::lbase + 4));
136 CONSTANT_REGISTER_DECLARATION(Register, L5 , (RegisterImpl::lbase + 5));
137 CONSTANT_REGISTER_DECLARATION(Register, L6 , (RegisterImpl::lbase + 6));
138 CONSTANT_REGISTER_DECLARATION(Register, L7 , (RegisterImpl::lbase + 7));
139
140 CONSTANT_REGISTER_DECLARATION(Register, I0 , (RegisterImpl::ibase + 0));
141 CONSTANT_REGISTER_DECLARATION(Register, I1 , (RegisterImpl::ibase + 1));
142 CONSTANT_REGISTER_DECLARATION(Register, I2 , (RegisterImpl::ibase + 2));
143 CONSTANT_REGISTER_DECLARATION(Register, I3 , (RegisterImpl::ibase + 3));
144 CONSTANT_REGISTER_DECLARATION(Register, I4 , (RegisterImpl::ibase + 4));
145 CONSTANT_REGISTER_DECLARATION(Register, I5 , (RegisterImpl::ibase + 5));
146 CONSTANT_REGISTER_DECLARATION(Register, I6 , (RegisterImpl::ibase + 6));
147 CONSTANT_REGISTER_DECLARATION(Register, I7 , (RegisterImpl::ibase + 7));
148
149 CONSTANT_REGISTER_DECLARATION(Register, FP , (RegisterImpl::ibase + 6));
150 CONSTANT_REGISTER_DECLARATION(Register, SP , (RegisterImpl::obase + 6));
151
152 //
153 // Because sparc has so many registers, #define'ing values for the is
154 // beneficial in code size and the cost of some of the dangers of
155 // defines. We don't use them on Intel because win32 uses asm
156 // directives which use the same names for registers as Hotspot does,
157 // so #defines would screw up the inline assembly. If a particular
158 // file has a problem with these defines then it's possible to turn
159 // them off in that file by defining DONT_USE_REGISTER_DEFINES.
160 // register_definition_sparc.cpp does that so that it's able to
161 // provide real definitions of these registers for use in debuggers
162 // and such.
163 //
164
165 #ifndef DONT_USE_REGISTER_DEFINES
166 #define noreg ((Register)(noreg_RegisterEnumValue))
167
168 #define G0 ((Register)(G0_RegisterEnumValue))
169 #define G1 ((Register)(G1_RegisterEnumValue))
170 #define G2 ((Register)(G2_RegisterEnumValue))
171 #define G3 ((Register)(G3_RegisterEnumValue))
172 #define G4 ((Register)(G4_RegisterEnumValue))
173 #define G5 ((Register)(G5_RegisterEnumValue))
174 #define G6 ((Register)(G6_RegisterEnumValue))
175 #define G7 ((Register)(G7_RegisterEnumValue))
176
177 #define O0 ((Register)(O0_RegisterEnumValue))
178 #define O1 ((Register)(O1_RegisterEnumValue))
179 #define O2 ((Register)(O2_RegisterEnumValue))
180 #define O3 ((Register)(O3_RegisterEnumValue))
181 #define O4 ((Register)(O4_RegisterEnumValue))
182 #define O5 ((Register)(O5_RegisterEnumValue))
183 #define O6 ((Register)(O6_RegisterEnumValue))
184 #define O7 ((Register)(O7_RegisterEnumValue))
185
186 #define L0 ((Register)(L0_RegisterEnumValue))
187 #define L1 ((Register)(L1_RegisterEnumValue))
188 #define L2 ((Register)(L2_RegisterEnumValue))
189 #define L3 ((Register)(L3_RegisterEnumValue))
190 #define L4 ((Register)(L4_RegisterEnumValue))
191 #define L5 ((Register)(L5_RegisterEnumValue))
192 #define L6 ((Register)(L6_RegisterEnumValue))
193 #define L7 ((Register)(L7_RegisterEnumValue))
194
195 #define I0 ((Register)(I0_RegisterEnumValue))
196 #define I1 ((Register)(I1_RegisterEnumValue))
197 #define I2 ((Register)(I2_RegisterEnumValue))
198 #define I3 ((Register)(I3_RegisterEnumValue))
199 #define I4 ((Register)(I4_RegisterEnumValue))
200 #define I5 ((Register)(I5_RegisterEnumValue))
201 #define I6 ((Register)(I6_RegisterEnumValue))
202 #define I7 ((Register)(I7_RegisterEnumValue))
203
204 #define FP ((Register)(FP_RegisterEnumValue))
205 #define SP ((Register)(SP_RegisterEnumValue))
206 #endif // DONT_USE_REGISTER_DEFINES
207
208 // Use FloatRegister as shortcut
209 class FloatRegisterImpl;
210 typedef FloatRegisterImpl* FloatRegister;
211
212
213 // construction
214 inline FloatRegister as_FloatRegister(int encoding) {
215 return (FloatRegister)(intptr_t)encoding;
216 }
217
218 // The implementation of float registers for the SPARC architecture
219
220 class FloatRegisterImpl: public AbstractRegisterImpl {
221 public:
222 enum {
223 number_of_registers = 64
224 };
225
226 enum Width {
227 S = 1, D = 2, Q = 3
228 };
229
230 // construction
231 VMReg as_VMReg( );
232
233 // accessors
234 int encoding() const { assert(is_valid(), "invalid register"); return value(); }
235
236 public:
237 int encoding(Width w) const {
238 const int c = encoding();
239 switch (w) {
240 case S:
241 assert(c < 32, "bad single float register");
242 return c;
243
244 case D:
245 assert(c < 64 && (c & 1) == 0, "bad double float register");
246 assert(c < 32 || VM_Version::v9_instructions_work(), "V9 float work only on V9 platform");
247 return (c & 0x1e) | ((c & 0x20) >> 5);
248
249 case Q:
250 assert(c < 64 && (c & 3) == 0, "bad quad float register");
251 assert(c < 32 || VM_Version::v9_instructions_work(), "V9 float work only on V9 platform");
252 return (c & 0x1c) | ((c & 0x20) >> 5);
253 }
254 ShouldNotReachHere();
255 return -1;
256 }
257
258 bool is_valid() const { return 0 <= value() && value() < number_of_registers; }
259 const char* name() const;
260
261 FloatRegister successor() const { return as_FloatRegister(encoding() + 1); }
262 };
263
264
265 // The float registers of the SPARC architecture
266
267 CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg , (-1));
268
269 CONSTANT_REGISTER_DECLARATION(FloatRegister, F0 , ( 0));
270 CONSTANT_REGISTER_DECLARATION(FloatRegister, F1 , ( 1));
271 CONSTANT_REGISTER_DECLARATION(FloatRegister, F2 , ( 2));
272 CONSTANT_REGISTER_DECLARATION(FloatRegister, F3 , ( 3));
273 CONSTANT_REGISTER_DECLARATION(FloatRegister, F4 , ( 4));
274 CONSTANT_REGISTER_DECLARATION(FloatRegister, F5 , ( 5));
275 CONSTANT_REGISTER_DECLARATION(FloatRegister, F6 , ( 6));
276 CONSTANT_REGISTER_DECLARATION(FloatRegister, F7 , ( 7));
277 CONSTANT_REGISTER_DECLARATION(FloatRegister, F8 , ( 8));
278 CONSTANT_REGISTER_DECLARATION(FloatRegister, F9 , ( 9));
279 CONSTANT_REGISTER_DECLARATION(FloatRegister, F10 , (10));
280 CONSTANT_REGISTER_DECLARATION(FloatRegister, F11 , (11));
281 CONSTANT_REGISTER_DECLARATION(FloatRegister, F12 , (12));
282 CONSTANT_REGISTER_DECLARATION(FloatRegister, F13 , (13));
283 CONSTANT_REGISTER_DECLARATION(FloatRegister, F14 , (14));
284 CONSTANT_REGISTER_DECLARATION(FloatRegister, F15 , (15));
285 CONSTANT_REGISTER_DECLARATION(FloatRegister, F16 , (16));
286 CONSTANT_REGISTER_DECLARATION(FloatRegister, F17 , (17));
287 CONSTANT_REGISTER_DECLARATION(FloatRegister, F18 , (18));
288 CONSTANT_REGISTER_DECLARATION(FloatRegister, F19 , (19));
289 CONSTANT_REGISTER_DECLARATION(FloatRegister, F20 , (20));
290 CONSTANT_REGISTER_DECLARATION(FloatRegister, F21 , (21));
291 CONSTANT_REGISTER_DECLARATION(FloatRegister, F22 , (22));
292 CONSTANT_REGISTER_DECLARATION(FloatRegister, F23 , (23));
293 CONSTANT_REGISTER_DECLARATION(FloatRegister, F24 , (24));
294 CONSTANT_REGISTER_DECLARATION(FloatRegister, F25 , (25));
295 CONSTANT_REGISTER_DECLARATION(FloatRegister, F26 , (26));
296 CONSTANT_REGISTER_DECLARATION(FloatRegister, F27 , (27));
297 CONSTANT_REGISTER_DECLARATION(FloatRegister, F28 , (28));
298 CONSTANT_REGISTER_DECLARATION(FloatRegister, F29 , (29));
299 CONSTANT_REGISTER_DECLARATION(FloatRegister, F30 , (30));
300 CONSTANT_REGISTER_DECLARATION(FloatRegister, F31 , (31));
301
302 CONSTANT_REGISTER_DECLARATION(FloatRegister, F32 , (32));
303 CONSTANT_REGISTER_DECLARATION(FloatRegister, F34 , (34));
304 CONSTANT_REGISTER_DECLARATION(FloatRegister, F36 , (36));
305 CONSTANT_REGISTER_DECLARATION(FloatRegister, F38 , (38));
306 CONSTANT_REGISTER_DECLARATION(FloatRegister, F40 , (40));
307 CONSTANT_REGISTER_DECLARATION(FloatRegister, F42 , (42));
308 CONSTANT_REGISTER_DECLARATION(FloatRegister, F44 , (44));
309 CONSTANT_REGISTER_DECLARATION(FloatRegister, F46 , (46));
310 CONSTANT_REGISTER_DECLARATION(FloatRegister, F48 , (48));
311 CONSTANT_REGISTER_DECLARATION(FloatRegister, F50 , (50));
312 CONSTANT_REGISTER_DECLARATION(FloatRegister, F52 , (52));
313 CONSTANT_REGISTER_DECLARATION(FloatRegister, F54 , (54));
314 CONSTANT_REGISTER_DECLARATION(FloatRegister, F56 , (56));
315 CONSTANT_REGISTER_DECLARATION(FloatRegister, F58 , (58));
316 CONSTANT_REGISTER_DECLARATION(FloatRegister, F60 , (60));
317 CONSTANT_REGISTER_DECLARATION(FloatRegister, F62 , (62));
318
319
320 #ifndef DONT_USE_REGISTER_DEFINES
321 #define fnoreg ((FloatRegister)(fnoreg_FloatRegisterEnumValue))
322 #define F0 ((FloatRegister)( F0_FloatRegisterEnumValue))
323 #define F1 ((FloatRegister)( F1_FloatRegisterEnumValue))
324 #define F2 ((FloatRegister)( F2_FloatRegisterEnumValue))
325 #define F3 ((FloatRegister)( F3_FloatRegisterEnumValue))
326 #define F4 ((FloatRegister)( F4_FloatRegisterEnumValue))
327 #define F5 ((FloatRegister)( F5_FloatRegisterEnumValue))
328 #define F6 ((FloatRegister)( F6_FloatRegisterEnumValue))
329 #define F7 ((FloatRegister)( F7_FloatRegisterEnumValue))
330 #define F8 ((FloatRegister)( F8_FloatRegisterEnumValue))
331 #define F9 ((FloatRegister)( F9_FloatRegisterEnumValue))
332 #define F10 ((FloatRegister)( F10_FloatRegisterEnumValue))
333 #define F11 ((FloatRegister)( F11_FloatRegisterEnumValue))
334 #define F12 ((FloatRegister)( F12_FloatRegisterEnumValue))
335 #define F13 ((FloatRegister)( F13_FloatRegisterEnumValue))
336 #define F14 ((FloatRegister)( F14_FloatRegisterEnumValue))
337 #define F15 ((FloatRegister)( F15_FloatRegisterEnumValue))
338 #define F16 ((FloatRegister)( F16_FloatRegisterEnumValue))
339 #define F17 ((FloatRegister)( F17_FloatRegisterEnumValue))
340 #define F18 ((FloatRegister)( F18_FloatRegisterEnumValue))
341 #define F19 ((FloatRegister)( F19_FloatRegisterEnumValue))
342 #define F20 ((FloatRegister)( F20_FloatRegisterEnumValue))
343 #define F21 ((FloatRegister)( F21_FloatRegisterEnumValue))
344 #define F22 ((FloatRegister)( F22_FloatRegisterEnumValue))
345 #define F23 ((FloatRegister)( F23_FloatRegisterEnumValue))
346 #define F24 ((FloatRegister)( F24_FloatRegisterEnumValue))
347 #define F25 ((FloatRegister)( F25_FloatRegisterEnumValue))
348 #define F26 ((FloatRegister)( F26_FloatRegisterEnumValue))
349 #define F27 ((FloatRegister)( F27_FloatRegisterEnumValue))
350 #define F28 ((FloatRegister)( F28_FloatRegisterEnumValue))
351 #define F29 ((FloatRegister)( F29_FloatRegisterEnumValue))
352 #define F30 ((FloatRegister)( F30_FloatRegisterEnumValue))
353 #define F31 ((FloatRegister)( F31_FloatRegisterEnumValue))
354 #define F32 ((FloatRegister)( F32_FloatRegisterEnumValue))
355 #define F34 ((FloatRegister)( F34_FloatRegisterEnumValue))
356 #define F36 ((FloatRegister)( F36_FloatRegisterEnumValue))
357 #define F38 ((FloatRegister)( F38_FloatRegisterEnumValue))
358 #define F40 ((FloatRegister)( F40_FloatRegisterEnumValue))
359 #define F42 ((FloatRegister)( F42_FloatRegisterEnumValue))
360 #define F44 ((FloatRegister)( F44_FloatRegisterEnumValue))
361 #define F46 ((FloatRegister)( F46_FloatRegisterEnumValue))
362 #define F48 ((FloatRegister)( F48_FloatRegisterEnumValue))
363 #define F50 ((FloatRegister)( F50_FloatRegisterEnumValue))
364 #define F52 ((FloatRegister)( F52_FloatRegisterEnumValue))
365 #define F54 ((FloatRegister)( F54_FloatRegisterEnumValue))
366 #define F56 ((FloatRegister)( F56_FloatRegisterEnumValue))
367 #define F58 ((FloatRegister)( F58_FloatRegisterEnumValue))
368 #define F60 ((FloatRegister)( F60_FloatRegisterEnumValue))
369 #define F62 ((FloatRegister)( F62_FloatRegisterEnumValue))
370 #endif // DONT_USE_REGISTER_DEFINES
371
372 // Maximum number of incoming arguments that can be passed in i registers.
373 const int SPARC_ARGS_IN_REGS_NUM = 6;
374
375 class ConcreteRegisterImpl : public AbstractRegisterImpl {
376 public:
377 enum {
378 // This number must be large enough to cover REG_COUNT (defined by c2) registers.
379 // There is no requirement that any ordering here matches any ordering c2 gives
380 // it's optoregs.
381 number_of_registers = 2*RegisterImpl::number_of_registers +
382 FloatRegisterImpl::number_of_registers +
383 1 + // ccr
384 4 // fcc
385 };
386 static const int max_gpr;
387 static const int max_fpr;
388
389 };
390
391 // Single, Double and Quad fp reg classes. These exist to map the ADLC
392 // encoding for a floating point register, to the FloatRegister number
393 // desired by the macroassembler. A FloatRegister is a number between
394 // 0 and 63 passed around as a pointer. For ADLC, an fp register encoding
395 // is the actual bit encoding used by the sparc hardware. When ADLC used
396 // the macroassembler to generate an instruction that references, e.g., a
397 // double fp reg, it passed the bit encoding to the macroassembler via
398 // as_FloatRegister, which, for double regs > 30, returns an illegal
399 // register number.
400 //
401 // Therefore we provide the following classes for use by ADLC. Their
402 // sole purpose is to convert from sparc register encodings to FloatRegisters.
403 // At some future time, we might replace FloatRegister with these classes,
404 // hence the definitions of as_xxxFloatRegister as class methods rather
405 // than as external inline routines.
406
407 class SingleFloatRegisterImpl;
408 typedef SingleFloatRegisterImpl *SingleFloatRegister;
409
410 inline FloatRegister as_SingleFloatRegister(int encoding);
411 class SingleFloatRegisterImpl {
412 public:
413 friend inline FloatRegister as_SingleFloatRegister(int encoding) {
414 assert(encoding < 32, "bad single float register encoding");
415 return as_FloatRegister(encoding);
416 }
417 };
418
419
420 class DoubleFloatRegisterImpl;
421 typedef DoubleFloatRegisterImpl *DoubleFloatRegister;
422
423 inline FloatRegister as_DoubleFloatRegister(int encoding);
424 class DoubleFloatRegisterImpl {
425 public:
426 friend inline FloatRegister as_DoubleFloatRegister(int encoding) {
427 assert(encoding < 32, "bad double float register encoding");
428 return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1e) );
429 }
430 };
431
432
433 class QuadFloatRegisterImpl;
434 typedef QuadFloatRegisterImpl *QuadFloatRegister;
435
436 class QuadFloatRegisterImpl {
437 public:
438 friend FloatRegister as_QuadFloatRegister(int encoding) {
439 assert(encoding < 32 && ((encoding & 2) == 0), "bad quad float register encoding");
440 return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1c) );
441 }
442 };