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comparison src/cpu/x86/vm/assembler_x86_64.hpp @ 0:a61af66fc99e jdk7-b24

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1 /*
2 * Copyright 2003-2007 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 class BiasedLockingCounters;
26
27 // Contains all the definitions needed for amd64 assembly code generation.
28
29 #ifdef _LP64
30 // Calling convention
31 class Argument VALUE_OBJ_CLASS_SPEC {
32 public:
33 enum {
34 #ifdef _WIN64
35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
37 #else
38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
40 #endif
41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
43 };
44 };
45
46
47 // Symbolically name the register arguments used by the c calling convention.
48 // Windows is different from linux/solaris. So much for standards...
49
50 #ifdef _WIN64
51
52 REGISTER_DECLARATION(Register, c_rarg0, rcx);
53 REGISTER_DECLARATION(Register, c_rarg1, rdx);
54 REGISTER_DECLARATION(Register, c_rarg2, r8);
55 REGISTER_DECLARATION(Register, c_rarg3, r9);
56
57 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
58 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
59 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
60 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
61
62 #else
63
64 REGISTER_DECLARATION(Register, c_rarg0, rdi);
65 REGISTER_DECLARATION(Register, c_rarg1, rsi);
66 REGISTER_DECLARATION(Register, c_rarg2, rdx);
67 REGISTER_DECLARATION(Register, c_rarg3, rcx);
68 REGISTER_DECLARATION(Register, c_rarg4, r8);
69 REGISTER_DECLARATION(Register, c_rarg5, r9);
70
71 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
72 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
73 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
74 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
75 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
76 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
77 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
78 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
79
80 #endif
81
82 // Symbolically name the register arguments used by the Java calling convention.
83 // We have control over the convention for java so we can do what we please.
84 // What pleases us is to offset the java calling convention so that when
85 // we call a suitable jni method the arguments are lined up and we don't
86 // have to do little shuffling. A suitable jni method is non-static and a
87 // small number of arguments (two fewer args on windows)
88 //
89 // |-------------------------------------------------------|
90 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
91 // |-------------------------------------------------------|
92 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
93 // | rdi rsi rdx rcx r8 r9 | solaris/linux
94 // |-------------------------------------------------------|
95 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
96 // |-------------------------------------------------------|
97
98 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
99 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
100 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
101 // Windows runs out of register args here
102 #ifdef _WIN64
103 REGISTER_DECLARATION(Register, j_rarg3, rdi);
104 REGISTER_DECLARATION(Register, j_rarg4, rsi);
105 #else
106 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
107 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
108 #endif /* _WIN64 */
109 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
110
111 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
112 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
113 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
114 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
115 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
116 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
117 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
118 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
119
120 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
121 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
122
123 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
124
125 #endif // _LP64
126
127 // Address is an abstraction used to represent a memory location
128 // using any of the amd64 addressing modes with one object.
129 //
130 // Note: A register location is represented via a Register, not
131 // via an address for efficiency & simplicity reasons.
132
133 class ArrayAddress;
134
135 class Address VALUE_OBJ_CLASS_SPEC {
136 public:
137 enum ScaleFactor {
138 no_scale = -1,
139 times_1 = 0,
140 times_2 = 1,
141 times_4 = 2,
142 times_8 = 3
143 };
144
145 private:
146 Register _base;
147 Register _index;
148 ScaleFactor _scale;
149 int _disp;
150 RelocationHolder _rspec;
151
152 // Easily misused constructors make them private
153 Address(int disp, address loc, relocInfo::relocType rtype);
154 Address(int disp, address loc, RelocationHolder spec);
155
156 public:
157 // creation
158 Address()
159 : _base(noreg),
160 _index(noreg),
161 _scale(no_scale),
162 _disp(0) {
163 }
164
165 // No default displacement otherwise Register can be implicitly
166 // converted to 0(Register) which is quite a different animal.
167
168 Address(Register base, int disp)
169 : _base(base),
170 _index(noreg),
171 _scale(no_scale),
172 _disp(disp) {
173 }
174
175 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
176 : _base (base),
177 _index(index),
178 _scale(scale),
179 _disp (disp) {
180 assert(!index->is_valid() == (scale == Address::no_scale),
181 "inconsistent address");
182 }
183
184 // The following two overloads are used in connection with the
185 // ByteSize type (see sizes.hpp). They simplify the use of
186 // ByteSize'd arguments in assembly code. Note that their equivalent
187 // for the optimized build are the member functions with int disp
188 // argument since ByteSize is mapped to an int type in that case.
189 //
190 // Note: DO NOT introduce similar overloaded functions for WordSize
191 // arguments as in the optimized mode, both ByteSize and WordSize
192 // are mapped to the same type and thus the compiler cannot make a
193 // distinction anymore (=> compiler errors).
194
195 #ifdef ASSERT
196 Address(Register base, ByteSize disp)
197 : _base(base),
198 _index(noreg),
199 _scale(no_scale),
200 _disp(in_bytes(disp)) {
201 }
202
203 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
204 : _base(base),
205 _index(index),
206 _scale(scale),
207 _disp(in_bytes(disp)) {
208 assert(!index->is_valid() == (scale == Address::no_scale),
209 "inconsistent address");
210 }
211 #endif // ASSERT
212
213 // accessors
214 bool uses(Register reg) const {
215 return _base == reg || _index == reg;
216 }
217
218 // Convert the raw encoding form into the form expected by the constructor for
219 // Address. An index of 4 (rsp) corresponds to having no index, so convert
220 // that to noreg for the Address constructor.
221 static Address make_raw(int base, int index, int scale, int disp);
222
223 static Address make_array(ArrayAddress);
224
225 private:
226 bool base_needs_rex() const {
227 return _base != noreg && _base->encoding() >= 8;
228 }
229
230 bool index_needs_rex() const {
231 return _index != noreg &&_index->encoding() >= 8;
232 }
233
234 relocInfo::relocType reloc() const { return _rspec.type(); }
235
236 friend class Assembler;
237 friend class MacroAssembler;
238 friend class LIR_Assembler; // base/index/scale/disp
239 };
240
241 //
242 // AddressLiteral has been split out from Address because operands of this type
243 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
244 // the few instructions that need to deal with address literals are unique and the
245 // MacroAssembler does not have to implement every instruction in the Assembler
246 // in order to search for address literals that may need special handling depending
247 // on the instruction and the platform. As small step on the way to merging i486/amd64
248 // directories.
249 //
250 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
251 friend class ArrayAddress;
252 RelocationHolder _rspec;
253 // Typically we use AddressLiterals we want to use their rval
254 // However in some situations we want the lval (effect address) of the item.
255 // We provide a special factory for making those lvals.
256 bool _is_lval;
257
258 // If the target is far we'll need to load the ea of this to
259 // a register to reach it. Otherwise if near we can do rip
260 // relative addressing.
261
262 address _target;
263
264 protected:
265 // creation
266 AddressLiteral()
267 : _is_lval(false),
268 _target(NULL)
269 {}
270
271 public:
272
273
274 AddressLiteral(address target, relocInfo::relocType rtype);
275
276 AddressLiteral(address target, RelocationHolder const& rspec)
277 : _rspec(rspec),
278 _is_lval(false),
279 _target(target)
280 {}
281
282 AddressLiteral addr() {
283 AddressLiteral ret = *this;
284 ret._is_lval = true;
285 return ret;
286 }
287
288
289 private:
290
291 address target() { return _target; }
292 bool is_lval() { return _is_lval; }
293
294 relocInfo::relocType reloc() const { return _rspec.type(); }
295 const RelocationHolder& rspec() const { return _rspec; }
296
297 friend class Assembler;
298 friend class MacroAssembler;
299 friend class Address;
300 friend class LIR_Assembler;
301 };
302
303 // Convience classes
304 class RuntimeAddress: public AddressLiteral {
305
306 public:
307
308 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
309
310 };
311
312 class OopAddress: public AddressLiteral {
313
314 public:
315
316 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
317
318 };
319
320 class ExternalAddress: public AddressLiteral {
321
322 public:
323
324 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
325
326 };
327
328 class InternalAddress: public AddressLiteral {
329
330 public:
331
332 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
333
334 };
335
336 // x86 can do array addressing as a single operation since disp can be an absolute
337 // address but amd64 can't [e.g. array_base(rx, ry:width) ]. We create a class
338 // that expresses the concept but does extra magic on amd64 to get the final result
339
340 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
341 private:
342
343 AddressLiteral _base;
344 Address _index;
345
346 public:
347
348 ArrayAddress() {};
349 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
350 AddressLiteral base() { return _base; }
351 Address index() { return _index; }
352
353 };
354
355 // The amd64 Assembler: Pure assembler doing NO optimizations on
356 // the instruction level (e.g. mov rax, 0 is not translated into xor
357 // rax, rax!); i.e., what you write is what you get. The Assembler is
358 // generating code into a CodeBuffer.
359
360 const int FPUStateSizeInWords = 512 / wordSize;
361
362 class Assembler : public AbstractAssembler {
363 friend class AbstractAssembler; // for the non-virtual hack
364 friend class StubGenerator;
365
366
367 protected:
368 #ifdef ASSERT
369 void check_relocation(RelocationHolder const& rspec, int format);
370 #endif
371
372 inline void emit_long64(jlong x);
373
374 void emit_data(jint data, relocInfo::relocType rtype, int format /* = 1 */);
375 void emit_data(jint data, RelocationHolder const& rspec, int format /* = 1 */);
376 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
377 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
378
379 // Helper functions for groups of instructions
380 void emit_arith_b(int op1, int op2, Register dst, int imm8);
381
382 void emit_arith(int op1, int op2, Register dst, int imm32);
383 // only x86??
384 void emit_arith(int op1, int op2, Register dst, jobject obj);
385 void emit_arith(int op1, int op2, Register dst, Register src);
386
387 void emit_operand(Register reg,
388 Register base, Register index, Address::ScaleFactor scale,
389 int disp,
390 RelocationHolder const& rspec,
391 int rip_relative_correction = 0);
392 void emit_operand(Register reg, Address adr,
393 int rip_relative_correction = 0);
394 void emit_operand(XMMRegister reg,
395 Register base, Register index, Address::ScaleFactor scale,
396 int disp,
397 RelocationHolder const& rspec,
398 int rip_relative_correction = 0);
399 void emit_operand(XMMRegister reg, Address adr,
400 int rip_relative_correction = 0);
401
402 // Immediate-to-memory forms
403 void emit_arith_operand(int op1, Register rm, Address adr, int imm32);
404
405 void emit_farith(int b1, int b2, int i);
406
407 bool reachable(AddressLiteral adr);
408
409 // These are all easily abused and hence protected
410
411 // Make these disappear in 64bit mode since they would never be correct
412 #ifndef _LP64
413 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);
414 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);
415
416 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);
417 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);
418
419 void push_literal32(int32_t imm32, RelocationHolder const& rspec);
420 #endif // _LP64
421
422
423 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);
424
425 // These are unique in that we are ensured by the caller that the 32bit
426 // relative in these instructions will always be able to reach the potentially
427 // 64bit address described by entry. Since they can take a 64bit address they
428 // don't have the 32 suffix like the other instructions in this class.
429 void jmp_literal(address entry, RelocationHolder const& rspec);
430 void call_literal(address entry, RelocationHolder const& rspec);
431
432 public:
433 enum Condition { // The amd64 condition codes used for conditional jumps/moves.
434 zero = 0x4,
435 notZero = 0x5,
436 equal = 0x4,
437 notEqual = 0x5,
438 less = 0xc,
439 lessEqual = 0xe,
440 greater = 0xf,
441 greaterEqual = 0xd,
442 below = 0x2,
443 belowEqual = 0x6,
444 above = 0x7,
445 aboveEqual = 0x3,
446 overflow = 0x0,
447 noOverflow = 0x1,
448 carrySet = 0x2,
449 carryClear = 0x3,
450 negative = 0x8,
451 positive = 0x9,
452 parity = 0xa,
453 noParity = 0xb
454 };
455
456 enum Prefix {
457 // segment overrides
458 // XXX remove segment prefixes
459 CS_segment = 0x2e,
460 SS_segment = 0x36,
461 DS_segment = 0x3e,
462 ES_segment = 0x26,
463 FS_segment = 0x64,
464 GS_segment = 0x65,
465
466 REX = 0x40,
467
468 REX_B = 0x41,
469 REX_X = 0x42,
470 REX_XB = 0x43,
471 REX_R = 0x44,
472 REX_RB = 0x45,
473 REX_RX = 0x46,
474 REX_RXB = 0x47,
475
476 REX_W = 0x48,
477
478 REX_WB = 0x49,
479 REX_WX = 0x4A,
480 REX_WXB = 0x4B,
481 REX_WR = 0x4C,
482 REX_WRB = 0x4D,
483 REX_WRX = 0x4E,
484 REX_WRXB = 0x4F
485 };
486
487 enum WhichOperand {
488 // input to locate_operand, and format code for relocations
489 imm64_operand = 0, // embedded 64-bit immediate operand
490 disp32_operand = 1, // embedded 32-bit displacement
491 call32_operand = 2, // embedded 32-bit self-relative displacement
492 _WhichOperand_limit = 3
493 };
494
495 public:
496
497 // Creation
498 Assembler(CodeBuffer* code)
499 : AbstractAssembler(code) {
500 }
501
502 // Decoding
503 static address locate_operand(address inst, WhichOperand which);
504 static address locate_next_instruction(address inst);
505
506 // Utilities
507
508 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); }
509 static bool is_simm32 (int64_t x) { return x == (int64_t)(int32_t)x; }
510
511
512 // Stack
513 void pushaq();
514 void popaq();
515
516 void pushfq();
517 void popfq();
518
519 void pushq(int imm32);
520
521 void pushq(Register src);
522 void pushq(Address src);
523
524 void popq(Register dst);
525 void popq(Address dst);
526
527 // Instruction prefixes
528 void prefix(Prefix p);
529
530 int prefix_and_encode(int reg_enc, bool byteinst = false);
531 int prefixq_and_encode(int reg_enc);
532
533 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
534 int prefixq_and_encode(int dst_enc, int src_enc);
535
536 void prefix(Register reg);
537 void prefix(Address adr);
538 void prefixq(Address adr);
539
540 void prefix(Address adr, Register reg, bool byteinst = false);
541 void prefixq(Address adr, Register reg);
542
543 void prefix(Address adr, XMMRegister reg);
544
545 // Moves
546 void movb(Register dst, Address src);
547 void movb(Address dst, int imm8);
548 void movb(Address dst, Register src);
549
550 void movw(Address dst, int imm16);
551 void movw(Register dst, Address src);
552 void movw(Address dst, Register src);
553
554 void movl(Register dst, int imm32);
555 void movl(Register dst, Register src);
556 void movl(Register dst, Address src);
557 void movl(Address dst, int imm32);
558 void movl(Address dst, Register src);
559
560 void movq(Register dst, Register src);
561 void movq(Register dst, Address src);
562 void movq(Address dst, Register src);
563 // These prevent using movq from converting a zero (like NULL) into Register
564 // by giving the compiler two choices it can't resolve
565 void movq(Address dst, void* dummy);
566 void movq(Register dst, void* dummy);
567
568 void mov64(Register dst, intptr_t imm64);
569 void mov64(Address dst, intptr_t imm64);
570
571 void movsbl(Register dst, Address src);
572 void movsbl(Register dst, Register src);
573 void movswl(Register dst, Address src);
574 void movswl(Register dst, Register src);
575 void movslq(Register dst, Address src);
576 void movslq(Register dst, Register src);
577
578 void movzbl(Register dst, Address src);
579 void movzbl(Register dst, Register src);
580 void movzwl(Register dst, Address src);
581 void movzwl(Register dst, Register src);
582
583 protected: // Avoid using the next instructions directly.
584 // New cpus require use of movsd and movss to avoid partial register stall
585 // when loading from memory. But for old Opteron use movlpd instead of movsd.
586 // The selection is done in MacroAssembler::movdbl() and movflt().
587 void movss(XMMRegister dst, XMMRegister src);
588 void movss(XMMRegister dst, Address src);
589 void movss(Address dst, XMMRegister src);
590 void movsd(XMMRegister dst, XMMRegister src);
591 void movsd(Address dst, XMMRegister src);
592 void movsd(XMMRegister dst, Address src);
593 void movlpd(XMMRegister dst, Address src);
594 // New cpus require use of movaps and movapd to avoid partial register stall
595 // when moving between registers.
596 void movapd(XMMRegister dst, XMMRegister src);
597 void movaps(XMMRegister dst, XMMRegister src);
598 public:
599
600 void movdl(XMMRegister dst, Register src);
601 void movdl(Register dst, XMMRegister src);
602 void movdq(XMMRegister dst, Register src);
603 void movdq(Register dst, XMMRegister src);
604
605 void cmovl(Condition cc, Register dst, Register src);
606 void cmovl(Condition cc, Register dst, Address src);
607 void cmovq(Condition cc, Register dst, Register src);
608 void cmovq(Condition cc, Register dst, Address src);
609
610 // Prefetches
611 private:
612 void prefetch_prefix(Address src);
613 public:
614 void prefetcht0(Address src);
615 void prefetcht1(Address src);
616 void prefetcht2(Address src);
617 void prefetchnta(Address src);
618 void prefetchw(Address src);
619
620 // Arithmetics
621 void adcl(Register dst, int imm32);
622 void adcl(Register dst, Address src);
623 void adcl(Register dst, Register src);
624 void adcq(Register dst, int imm32);
625 void adcq(Register dst, Address src);
626 void adcq(Register dst, Register src);
627
628 void addl(Address dst, int imm32);
629 void addl(Address dst, Register src);
630 void addl(Register dst, int imm32);
631 void addl(Register dst, Address src);
632 void addl(Register dst, Register src);
633 void addq(Address dst, int imm32);
634 void addq(Address dst, Register src);
635 void addq(Register dst, int imm32);
636 void addq(Register dst, Address src);
637 void addq(Register dst, Register src);
638
639 void andl(Register dst, int imm32);
640 void andl(Register dst, Address src);
641 void andl(Register dst, Register src);
642 void andq(Register dst, int imm32);
643 void andq(Register dst, Address src);
644 void andq(Register dst, Register src);
645
646 void cmpb(Address dst, int imm8);
647 void cmpl(Address dst, int imm32);
648 void cmpl(Register dst, int imm32);
649 void cmpl(Register dst, Register src);
650 void cmpl(Register dst, Address src);
651 void cmpq(Address dst, int imm32);
652 void cmpq(Address dst, Register src);
653 void cmpq(Register dst, int imm32);
654 void cmpq(Register dst, Register src);
655 void cmpq(Register dst, Address src);
656
657 void ucomiss(XMMRegister dst, XMMRegister src);
658 void ucomisd(XMMRegister dst, XMMRegister src);
659
660 protected:
661 // Don't use next inc() and dec() methods directly. INC & DEC instructions
662 // could cause a partial flag stall since they don't set CF flag.
663 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
664 // which call inc() & dec() or add() & sub() in accordance with
665 // the product flag UseIncDec value.
666
667 void decl(Register dst);
668 void decl(Address dst);
669 void decq(Register dst);
670 void decq(Address dst);
671
672 void incl(Register dst);
673 void incl(Address dst);
674 void incq(Register dst);
675 void incq(Address dst);
676
677 public:
678 void idivl(Register src);
679 void idivq(Register src);
680 void cdql();
681 void cdqq();
682
683 void imull(Register dst, Register src);
684 void imull(Register dst, Register src, int value);
685 void imulq(Register dst, Register src);
686 void imulq(Register dst, Register src, int value);
687
688 void leal(Register dst, Address src);
689 void leaq(Register dst, Address src);
690
691 void mull(Address src);
692 void mull(Register src);
693
694 void negl(Register dst);
695 void negq(Register dst);
696
697 void notl(Register dst);
698 void notq(Register dst);
699
700 void orl(Address dst, int imm32);
701 void orl(Register dst, int imm32);
702 void orl(Register dst, Address src);
703 void orl(Register dst, Register src);
704 void orq(Address dst, int imm32);
705 void orq(Register dst, int imm32);
706 void orq(Register dst, Address src);
707 void orq(Register dst, Register src);
708
709 void rcll(Register dst, int imm8);
710 void rclq(Register dst, int imm8);
711
712 void sarl(Register dst, int imm8);
713 void sarl(Register dst);
714 void sarq(Register dst, int imm8);
715 void sarq(Register dst);
716
717 void sbbl(Address dst, int imm32);
718 void sbbl(Register dst, int imm32);
719 void sbbl(Register dst, Address src);
720 void sbbl(Register dst, Register src);
721 void sbbq(Address dst, int imm32);
722 void sbbq(Register dst, int imm32);
723 void sbbq(Register dst, Address src);
724 void sbbq(Register dst, Register src);
725
726 void shll(Register dst, int imm8);
727 void shll(Register dst);
728 void shlq(Register dst, int imm8);
729 void shlq(Register dst);
730
731 void shrl(Register dst, int imm8);
732 void shrl(Register dst);
733 void shrq(Register dst, int imm8);
734 void shrq(Register dst);
735
736 void subl(Address dst, int imm32);
737 void subl(Address dst, Register src);
738 void subl(Register dst, int imm32);
739 void subl(Register dst, Address src);
740 void subl(Register dst, Register src);
741 void subq(Address dst, int imm32);
742 void subq(Address dst, Register src);
743 void subq(Register dst, int imm32);
744 void subq(Register dst, Address src);
745 void subq(Register dst, Register src);
746
747 void testb(Register dst, int imm8);
748 void testl(Register dst, int imm32);
749 void testl(Register dst, Register src);
750 void testq(Register dst, int imm32);
751 void testq(Register dst, Register src);
752
753 void xaddl(Address dst, Register src);
754 void xaddq(Address dst, Register src);
755
756 void xorl(Register dst, int imm32);
757 void xorl(Register dst, Address src);
758 void xorl(Register dst, Register src);
759 void xorq(Register dst, int imm32);
760 void xorq(Register dst, Address src);
761 void xorq(Register dst, Register src);
762
763 // Miscellaneous
764 void bswapl(Register reg);
765 void bswapq(Register reg);
766 void lock();
767
768 void xchgl(Register reg, Address adr);
769 void xchgl(Register dst, Register src);
770 void xchgq(Register reg, Address adr);
771 void xchgq(Register dst, Register src);
772
773 void cmpxchgl(Register reg, Address adr);
774 void cmpxchgq(Register reg, Address adr);
775
776 void nop(int i = 1);
777 void addr_nop_4();
778 void addr_nop_5();
779 void addr_nop_7();
780 void addr_nop_8();
781
782 void hlt();
783 void ret(int imm16);
784 void smovl();
785 void rep_movl();
786 void rep_movq();
787 void rep_set();
788 void repne_scan();
789 void setb(Condition cc, Register dst);
790
791 void clflush(Address adr);
792
793 enum Membar_mask_bits {
794 StoreStore = 1 << 3,
795 LoadStore = 1 << 2,
796 StoreLoad = 1 << 1,
797 LoadLoad = 1 << 0
798 };
799
800 // Serializes memory.
801 void membar(Membar_mask_bits order_constraint) {
802 // We only have to handle StoreLoad and LoadLoad
803 if (order_constraint & StoreLoad) {
804 // MFENCE subsumes LFENCE
805 mfence();
806 } /* [jk] not needed currently: else if (order_constraint & LoadLoad) {
807 lfence();
808 } */
809 }
810
811 void lfence() {
812 emit_byte(0x0F);
813 emit_byte(0xAE);
814 emit_byte(0xE8);
815 }
816
817 void mfence() {
818 emit_byte(0x0F);
819 emit_byte(0xAE);
820 emit_byte(0xF0);
821 }
822
823 // Identify processor type and features
824 void cpuid() {
825 emit_byte(0x0F);
826 emit_byte(0xA2);
827 }
828
829 void cld() { emit_byte(0xfc);
830 }
831
832 void std() { emit_byte(0xfd);
833 }
834
835
836 // Calls
837
838 void call(Label& L, relocInfo::relocType rtype);
839 void call(Register reg);
840 void call(Address adr);
841
842 // Jumps
843
844 void jmp(Register reg);
845 void jmp(Address adr);
846
847 // Label operations & relative jumps (PPUM Appendix D)
848 // unconditional jump to L
849 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none);
850
851
852 // Unconditional 8-bit offset jump to L.
853 // WARNING: be very careful using this for forward jumps. If the label is
854 // not bound within an 8-bit offset of this instruction, a run-time error
855 // will occur.
856 void jmpb(Label& L);
857
858 // jcc is the generic conditional branch generator to run- time
859 // routines, jcc is used for branches to labels. jcc takes a branch
860 // opcode (cc) and a label (L) and generates either a backward
861 // branch or a forward branch and links it to the label fixup
862 // chain. Usage:
863 //
864 // Label L; // unbound label
865 // jcc(cc, L); // forward branch to unbound label
866 // bind(L); // bind label to the current pc
867 // jcc(cc, L); // backward branch to bound label
868 // bind(L); // illegal: a label may be bound only once
869 //
870 // Note: The same Label can be used for forward and backward branches
871 // but it may be bound only once.
872
873 void jcc(Condition cc, Label& L,
874 relocInfo::relocType rtype = relocInfo::none);
875
876 // Conditional jump to a 8-bit offset to L.
877 // WARNING: be very careful using this for forward jumps. If the label is
878 // not bound within an 8-bit offset of this instruction, a run-time error
879 // will occur.
880 void jccb(Condition cc, Label& L);
881
882 // Floating-point operations
883
884 void fxsave(Address dst);
885 void fxrstor(Address src);
886 void ldmxcsr(Address src);
887 void stmxcsr(Address dst);
888
889 void addss(XMMRegister dst, XMMRegister src);
890 void addss(XMMRegister dst, Address src);
891 void subss(XMMRegister dst, XMMRegister src);
892 void subss(XMMRegister dst, Address src);
893 void mulss(XMMRegister dst, XMMRegister src);
894 void mulss(XMMRegister dst, Address src);
895 void divss(XMMRegister dst, XMMRegister src);
896 void divss(XMMRegister dst, Address src);
897 void addsd(XMMRegister dst, XMMRegister src);
898 void addsd(XMMRegister dst, Address src);
899 void subsd(XMMRegister dst, XMMRegister src);
900 void subsd(XMMRegister dst, Address src);
901 void mulsd(XMMRegister dst, XMMRegister src);
902 void mulsd(XMMRegister dst, Address src);
903 void divsd(XMMRegister dst, XMMRegister src);
904 void divsd(XMMRegister dst, Address src);
905
906 // We only need the double form
907 void sqrtsd(XMMRegister dst, XMMRegister src);
908 void sqrtsd(XMMRegister dst, Address src);
909
910 void xorps(XMMRegister dst, XMMRegister src);
911 void xorps(XMMRegister dst, Address src);
912 void xorpd(XMMRegister dst, XMMRegister src);
913 void xorpd(XMMRegister dst, Address src);
914
915 void cvtsi2ssl(XMMRegister dst, Register src);
916 void cvtsi2ssq(XMMRegister dst, Register src);
917 void cvtsi2sdl(XMMRegister dst, Register src);
918 void cvtsi2sdq(XMMRegister dst, Register src);
919 void cvttss2sil(Register dst, XMMRegister src); // truncates
920 void cvttss2siq(Register dst, XMMRegister src); // truncates
921 void cvttsd2sil(Register dst, XMMRegister src); // truncates
922 void cvttsd2siq(Register dst, XMMRegister src); // truncates
923 void cvtss2sd(XMMRegister dst, XMMRegister src);
924 void cvtsd2ss(XMMRegister dst, XMMRegister src);
925
926 void pxor(XMMRegister dst, Address src); // Xor Packed Byte Integer Values
927 void pxor(XMMRegister dst, XMMRegister src); // Xor Packed Byte Integer Values
928
929 void movdqa(XMMRegister dst, Address src); // Move Aligned Double Quadword
930 void movdqa(XMMRegister dst, XMMRegister src);
931 void movdqa(Address dst, XMMRegister src);
932
933 void movq(XMMRegister dst, Address src);
934 void movq(Address dst, XMMRegister src);
935
936 void pshufd(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Doublewords
937 void pshufd(XMMRegister dst, Address src, int mode);
938 void pshuflw(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Low Words
939 void pshuflw(XMMRegister dst, Address src, int mode);
940
941 void psrlq(XMMRegister dst, int shift); // Shift Right Logical Quadword Immediate
942
943 void punpcklbw(XMMRegister dst, XMMRegister src); // Interleave Low Bytes
944 void punpcklbw(XMMRegister dst, Address src);
945 };
946
947
948 // MacroAssembler extends Assembler by frequently used macros.
949 //
950 // Instructions for which a 'better' code sequence exists depending
951 // on arguments should also go in here.
952
953 class MacroAssembler : public Assembler {
954 friend class LIR_Assembler;
955 protected:
956
957 Address as_Address(AddressLiteral adr);
958 Address as_Address(ArrayAddress adr);
959
960 // Support for VM calls
961 //
962 // This is the base routine called by the different versions of
963 // call_VM_leaf. The interpreter may customize this version by
964 // overriding it for its purposes (e.g., to save/restore additional
965 // registers when doing a VM call).
966
967 virtual void call_VM_leaf_base(
968 address entry_point, // the entry point
969 int number_of_arguments // the number of arguments to
970 // pop after the call
971 );
972
973 // This is the base routine called by the different versions of
974 // call_VM. The interpreter may customize this version by overriding
975 // it for its purposes (e.g., to save/restore additional registers
976 // when doing a VM call).
977 //
978 // If no java_thread register is specified (noreg) than rdi will be
979 // used instead. call_VM_base returns the register which contains
980 // the thread upon return. If a thread register has been specified,
981 // the return value will correspond to that register. If no
982 // last_java_sp is specified (noreg) than rsp will be used instead.
983 virtual void call_VM_base( // returns the register
984 // containing the thread upon
985 // return
986 Register oop_result, // where an oop-result ends up
987 // if any; use noreg otherwise
988 Register java_thread, // the thread if computed
989 // before ; use noreg otherwise
990 Register last_java_sp, // to set up last_Java_frame in
991 // stubs; use noreg otherwise
992 address entry_point, // the entry point
993 int number_of_arguments, // the number of arguments (w/o
994 // thread) to pop after the
995 // call
996 bool check_exceptions // whether to check for pending
997 // exceptions after return
998 );
999
1000 // This routines should emit JVMTI PopFrame handling and ForceEarlyReturn code.
1001 // The implementation is only non-empty for the InterpreterMacroAssembler,
1002 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1003 virtual void check_and_handle_popframe(Register java_thread);
1004 virtual void check_and_handle_earlyret(Register java_thread);
1005
1006 void call_VM_helper(Register oop_result,
1007 address entry_point,
1008 int number_of_arguments,
1009 bool check_exceptions = true);
1010
1011 public:
1012 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1013
1014 // Support for NULL-checks
1015 //
1016 // Generates code that causes a NULL OS exception if the content of
1017 // reg is NULL. If the accessed location is M[reg + offset] and the
1018 // offset is known, provide the offset. No explicit code generation
1019 // is needed if the offset is within a certain range (0 <= offset <=
1020 // page_size).
1021 void null_check(Register reg, int offset = -1);
1022 static bool needs_explicit_null_check(int offset);
1023
1024 // Required platform-specific helpers for Label::patch_instructions.
1025 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1026 void pd_patch_instruction(address branch, address target);
1027 #ifndef PRODUCT
1028 static void pd_print_patched_instruction(address branch);
1029 #endif
1030
1031
1032 // The following 4 methods return the offset of the appropriate move
1033 // instruction. Note: these are 32 bit instructions
1034
1035 // Support for fast byte/word loading with zero extension (depending
1036 // on particular CPU)
1037 int load_unsigned_byte(Register dst, Address src);
1038 int load_unsigned_word(Register dst, Address src);
1039
1040 // Support for fast byte/word loading with sign extension (depending
1041 // on particular CPU)
1042 int load_signed_byte(Register dst, Address src);
1043 int load_signed_word(Register dst, Address src);
1044
1045 // Support for inc/dec with optimal instruction selection depending
1046 // on value
1047 void incrementl(Register reg, int value = 1);
1048 void decrementl(Register reg, int value = 1);
1049 void incrementq(Register reg, int value = 1);
1050 void decrementq(Register reg, int value = 1);
1051
1052 void incrementl(Address dst, int value = 1);
1053 void decrementl(Address dst, int value = 1);
1054 void incrementq(Address dst, int value = 1);
1055 void decrementq(Address dst, int value = 1);
1056
1057 // Support optimal SSE move instructions.
1058 void movflt(XMMRegister dst, XMMRegister src) {
1059 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1060 else { movss (dst, src); return; }
1061 }
1062
1063 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1064
1065 void movflt(XMMRegister dst, AddressLiteral src);
1066
1067 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1068
1069 void movdbl(XMMRegister dst, XMMRegister src) {
1070 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1071 else { movsd (dst, src); return; }
1072 }
1073
1074 void movdbl(XMMRegister dst, AddressLiteral src);
1075
1076 void movdbl(XMMRegister dst, Address src) {
1077 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1078 else { movlpd(dst, src); return; }
1079 }
1080
1081 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1082
1083 void incrementl(AddressLiteral dst);
1084 void incrementl(ArrayAddress dst);
1085
1086 // Alignment
1087 void align(int modulus);
1088
1089 // Misc
1090 void fat_nop(); // 5 byte nop
1091
1092
1093 // C++ bool manipulation
1094
1095 void movbool(Register dst, Address src);
1096 void movbool(Address dst, bool boolconst);
1097 void movbool(Address dst, Register src);
1098 void testbool(Register dst);
1099
1100 // Stack frame creation/removal
1101 void enter();
1102 void leave();
1103
1104 // Support for getting the JavaThread pointer (i.e.; a reference to
1105 // thread-local information) The pointer will be loaded into the
1106 // thread register.
1107 void get_thread(Register thread);
1108
1109 void int3();
1110
1111 // Support for VM calls
1112 //
1113 // It is imperative that all calls into the VM are handled via the
1114 // call_VM macros. They make sure that the stack linkage is setup
1115 // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points
1116 // while call_VM_leaf's correspond to LEAF entry points.
1117 void call_VM(Register oop_result,
1118 address entry_point,
1119 bool check_exceptions = true);
1120 void call_VM(Register oop_result,
1121 address entry_point,
1122 Register arg_1,
1123 bool check_exceptions = true);
1124 void call_VM(Register oop_result,
1125 address entry_point,
1126 Register arg_1, Register arg_2,
1127 bool check_exceptions = true);
1128 void call_VM(Register oop_result,
1129 address entry_point,
1130 Register arg_1, Register arg_2, Register arg_3,
1131 bool check_exceptions = true);
1132
1133 // Overloadings with last_Java_sp
1134 void call_VM(Register oop_result,
1135 Register last_java_sp,
1136 address entry_point,
1137 int number_of_arguments = 0,
1138 bool check_exceptions = true);
1139 void call_VM(Register oop_result,
1140 Register last_java_sp,
1141 address entry_point,
1142 Register arg_1, bool
1143 check_exceptions = true);
1144 void call_VM(Register oop_result,
1145 Register last_java_sp,
1146 address entry_point,
1147 Register arg_1, Register arg_2,
1148 bool check_exceptions = true);
1149 void call_VM(Register oop_result,
1150 Register last_java_sp,
1151 address entry_point,
1152 Register arg_1, Register arg_2, Register arg_3,
1153 bool check_exceptions = true);
1154
1155 void call_VM_leaf(address entry_point,
1156 int number_of_arguments = 0);
1157 void call_VM_leaf(address entry_point,
1158 Register arg_1);
1159 void call_VM_leaf(address entry_point,
1160 Register arg_1, Register arg_2);
1161 void call_VM_leaf(address entry_point,
1162 Register arg_1, Register arg_2, Register arg_3);
1163
1164 // last Java Frame (fills frame anchor)
1165 void set_last_Java_frame(Register last_java_sp,
1166 Register last_java_fp,
1167 address last_java_pc);
1168 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1169
1170 // Stores
1171 void store_check(Register obj); // store check for
1172 // obj - register is
1173 // destroyed
1174 // afterwards
1175 void store_check(Register obj, Address dst); // same as above, dst
1176 // is exact store
1177 // location (reg. is
1178 // destroyed)
1179
1180 // split store_check(Register obj) to enhance instruction interleaving
1181 void store_check_part_1(Register obj);
1182 void store_check_part_2(Register obj);
1183
1184 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1185 void c2bool(Register x);
1186
1187 // Int division/reminder for Java
1188 // (as idivl, but checks for special case as described in JVM spec.)
1189 // returns idivl instruction offset for implicit exception handling
1190 int corrected_idivl(Register reg);
1191 // Long division/reminder for Java
1192 // (as idivq, but checks for special case as described in JVM spec.)
1193 // returns idivq instruction offset for implicit exception handling
1194 int corrected_idivq(Register reg);
1195
1196 // Push and pop integer/fpu/cpu state
1197 void push_IU_state();
1198 void pop_IU_state();
1199
1200 void push_FPU_state();
1201 void pop_FPU_state();
1202
1203 void push_CPU_state();
1204 void pop_CPU_state();
1205
1206 // Sign extension
1207 void sign_extend_short(Register reg);
1208 void sign_extend_byte(Register reg);
1209
1210 // Division by power of 2, rounding towards 0
1211 void division_with_shift(Register reg, int shift_value);
1212
1213 // Round up to a power of two
1214 void round_to_l(Register reg, int modulus);
1215 void round_to_q(Register reg, int modulus);
1216
1217 // allocation
1218 void eden_allocate(
1219 Register obj, // result: pointer to object after
1220 // successful allocation
1221 Register var_size_in_bytes, // object size in bytes if unknown at
1222 // compile time; invalid otherwise
1223 int con_size_in_bytes, // object size in bytes if known at
1224 // compile time
1225 Register t1, // temp register
1226 Label& slow_case // continuation point if fast
1227 // allocation fails
1228 );
1229 void tlab_allocate(
1230 Register obj, // result: pointer to object after
1231 // successful allocation
1232 Register var_size_in_bytes, // object size in bytes if unknown at
1233 // compile time; invalid otherwise
1234 int con_size_in_bytes, // object size in bytes if known at
1235 // compile time
1236 Register t1, // temp register
1237 Register t2, // temp register
1238 Label& slow_case // continuation point if fast
1239 // allocation fails
1240 );
1241 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
1242
1243 //----
1244
1245 // Debugging
1246
1247 // only if +VerifyOops
1248 void verify_oop(Register reg, const char* s = "broken oop");
1249 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1250
1251 // only if +VerifyFPU
1252 void verify_FPU(int stack_depth, const char* s = "illegal FPU state") {}
1253
1254 // prints msg, dumps registers and stops execution
1255 void stop(const char* msg);
1256
1257 // prints message and continues
1258 void warn(const char* msg);
1259
1260 static void debug(char* msg, int64_t pc, int64_t regs[]);
1261
1262 void os_breakpoint();
1263
1264 void untested()
1265 {
1266 stop("untested");
1267 }
1268
1269 void unimplemented(const char* what = "")
1270 {
1271 char* b = new char[1024];
1272 sprintf(b, "unimplemented: %s", what);
1273 stop(b);
1274 }
1275
1276 void should_not_reach_here()
1277 {
1278 stop("should not reach here");
1279 }
1280
1281 // Stack overflow checking
1282 void bang_stack_with_offset(int offset)
1283 {
1284 // stack grows down, caller passes positive offset
1285 assert(offset > 0, "must bang with negative offset");
1286 movl(Address(rsp, (-offset)), rax);
1287 }
1288
1289 // Writes to stack successive pages until offset reached to check for
1290 // stack overflow + shadow pages. Also, clobbers tmp
1291 void bang_stack_size(Register offset, Register tmp);
1292
1293 // Support for serializing memory accesses between threads.
1294 void serialize_memory(Register thread, Register tmp);
1295
1296 void verify_tlab();
1297
1298 // Biased locking support
1299 // lock_reg and obj_reg must be loaded up with the appropriate values.
1300 // swap_reg must be rax and is killed.
1301 // tmp_reg must be supplied and is killed.
1302 // If swap_reg_contains_mark is true then the code assumes that the
1303 // mark word of the object has already been loaded into swap_reg.
1304 // Optional slow case is for implementations (interpreter and C1) which branch to
1305 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
1306 // Returns offset of first potentially-faulting instruction for null
1307 // check info (currently consumed only by C1). If
1308 // swap_reg_contains_mark is true then returns -1 as it is assumed
1309 // the calling code has already passed any potential faults.
1310 int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
1311 bool swap_reg_contains_mark,
1312 Label& done, Label* slow_case = NULL,
1313 BiasedLockingCounters* counters = NULL);
1314 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
1315
1316 Condition negate_condition(Condition cond);
1317
1318 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
1319 // operands. In general the names are modified to avoid hiding the instruction in Assembler
1320 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
1321 // here in MacroAssembler. The major exception to this rule is call
1322
1323 // Arithmetics
1324
1325 void cmp8(AddressLiteral src1, int8_t imm32);
1326
1327 void cmp32(AddressLiteral src1, int32_t src2);
1328 // compare reg - mem, or reg - &mem
1329 void cmp32(Register src1, AddressLiteral src2);
1330
1331 void cmp32(Register src1, Address src2);
1332
1333 #ifndef _LP64
1334 void cmpoop(Address dst, jobject obj);
1335 void cmpoop(Register dst, jobject obj);
1336 #endif // _LP64
1337
1338 // NOTE src2 must be the lval. This is NOT an mem-mem compare
1339 void cmpptr(Address src1, AddressLiteral src2);
1340
1341 void cmpptr(Register src1, AddressLiteral src);
1342
1343 // will be cmpreg(?)
1344 void cmp64(Register src1, AddressLiteral src);
1345
1346 void cmpxchgptr(Register reg, Address adr);
1347 void cmpxchgptr(Register reg, AddressLiteral adr);
1348
1349 // Helper functions for statistics gathering.
1350 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
1351 void cond_inc32(Condition cond, AddressLiteral counter_addr);
1352 // Unconditional atomic increment.
1353 void atomic_incl(AddressLiteral counter_addr);
1354
1355
1356 void lea(Register dst, AddressLiteral src);
1357 void lea(Register dst, Address src);
1358
1359
1360 // Calls
1361 void call(Label& L, relocInfo::relocType rtype);
1362 void call(Register entry);
1363 void call(AddressLiteral entry);
1364
1365 // Jumps
1366
1367 // 32bit can do a case table jump in one instruction but we no longer allow the base
1368 // to be installed in the Address class
1369 void jump(ArrayAddress entry);
1370
1371 void jump(AddressLiteral entry);
1372 void jump_cc(Condition cc, AddressLiteral dst);
1373
1374 // Floating
1375
1376 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
1377 void ldmxcsr(AddressLiteral src);
1378
1379 private:
1380 // these are private because users should be doing movflt/movdbl
1381
1382 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1383 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1384 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1385 void movss(XMMRegister dst, AddressLiteral src);
1386
1387 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1388 void movlpd(XMMRegister dst, AddressLiteral src);
1389
1390 public:
1391
1392
1393 void xorpd(XMMRegister dst, XMMRegister src) {Assembler::xorpd(dst, src); }
1394 void xorpd(XMMRegister dst, Address src) {Assembler::xorpd(dst, src); }
1395 void xorpd(XMMRegister dst, AddressLiteral src);
1396
1397 void xorps(XMMRegister dst, XMMRegister src) {Assembler::xorps(dst, src); }
1398 void xorps(XMMRegister dst, Address src) {Assembler::xorps(dst, src); }
1399 void xorps(XMMRegister dst, AddressLiteral src);
1400
1401
1402 // Data
1403
1404 void movoop(Register dst, jobject obj);
1405 void movoop(Address dst, jobject obj);
1406
1407 void movptr(ArrayAddress dst, Register src);
1408 void movptr(Register dst, AddressLiteral src);
1409
1410 void movptr(Register dst, intptr_t src);
1411 void movptr(Address dst, intptr_t src);
1412
1413 void movptr(Register dst, ArrayAddress src);
1414
1415 // to avoid hiding movl
1416 void mov32(AddressLiteral dst, Register src);
1417 void mov32(Register dst, AddressLiteral src);
1418
1419 void pushoop(jobject obj);
1420
1421 // Can push value or effective address
1422 void pushptr(AddressLiteral src);
1423
1424 };
1425
1426 /**
1427 * class SkipIfEqual:
1428 *
1429 * Instantiating this class will result in assembly code being output that will
1430 * jump around any code emitted between the creation of the instance and it's
1431 * automatic destruction at the end of a scope block, depending on the value of
1432 * the flag passed to the constructor, which will be checked at run-time.
1433 */
1434 class SkipIfEqual {
1435 private:
1436 MacroAssembler* _masm;
1437 Label _label;
1438
1439 public:
1440 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1441 ~SkipIfEqual();
1442 };
1443
1444
1445 #ifdef ASSERT
1446 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
1447 #endif