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comparison src/cpu/x86/vm/c1_LinearScan_x86.hpp @ 0:a61af66fc99e jdk7-b24

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author duke
date Sat, 01 Dec 2007 00:00:00 +0000
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1 /*
2 * Copyright 2005-2006 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 inline bool LinearScan::is_processed_reg_num(int reg_num) {
26 // rsp and rbp (numbers 6 ancd 7) are ignored
27 assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below");
28 assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below");
29 assert(reg_num >= 0, "invalid reg_num");
30
31 return reg_num < 6 || reg_num > 7;
32 }
33
34 inline int LinearScan::num_physical_regs(BasicType type) {
35 // Intel requires two cpu registers for long,
36 // but requires only one fpu register for double
37 if (type == T_LONG) {
38 return 2;
39 }
40 return 1;
41 }
42
43
44 inline bool LinearScan::requires_adjacent_regs(BasicType type) {
45 return false;
46 }
47
48 inline bool LinearScan::is_caller_save(int assigned_reg) {
49 assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers");
50 return true; // no callee-saved registers on Intel
51
52 }
53
54
55 inline void LinearScan::pd_add_temps(LIR_Op* op) {
56 switch (op->code()) {
57 case lir_tan:
58 case lir_sin:
59 case lir_cos: {
60 // The slow path for these functions may need to save and
61 // restore all live registers but we don't want to save and
62 // restore everything all the time, so mark the xmms as being
63 // killed. If the slow path were explicit or we could propagate
64 // live register masks down to the assembly we could do better
65 // but we don't have any easy way to do that right now. We
66 // could also consider not killing all xmm registers if we
67 // assume that slow paths are uncommon but it's not clear that
68 // would be a good idea.
69 if (UseSSE > 0) {
70 #ifndef PRODUCT
71 if (TraceLinearScanLevel >= 2) {
72 tty->print_cr("killing XMMs for trig");
73 }
74 #endif
75 int op_id = op->id();
76 for (int xmm = 0; xmm < FrameMap::nof_caller_save_xmm_regs; xmm++) {
77 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(xmm);
78 add_temp(reg_num(opr), op_id, noUse, T_ILLEGAL);
79 }
80 }
81 break;
82 }
83 }
84 }
85
86
87 // Implementation of LinearScanWalker
88
89 inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) {
90 if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::byte_reg)) {
91 assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only");
92 _first_reg = pd_first_byte_reg;
93 _last_reg = pd_last_byte_reg;
94 return true;
95 } else if ((UseSSE >= 1 && cur->type() == T_FLOAT) || (UseSSE >= 2 && cur->type() == T_DOUBLE)) {
96 _first_reg = pd_first_xmm_reg;
97 _last_reg = pd_last_xmm_reg;
98 return true;
99 }
100
101 return false;
102 }
103
104
105 class FpuStackAllocator VALUE_OBJ_CLASS_SPEC {
106 private:
107 Compilation* _compilation;
108 LinearScan* _allocator;
109
110 LIR_OpVisitState visitor;
111
112 LIR_List* _lir;
113 int _pos;
114 FpuStackSim _sim;
115 FpuStackSim _temp_sim;
116
117 bool _debug_information_computed;
118
119 LinearScan* allocator() { return _allocator; }
120 Compilation* compilation() const { return _compilation; }
121
122 // unified bailout support
123 void bailout(const char* msg) const { compilation()->bailout(msg); }
124 bool bailed_out() const { return compilation()->bailed_out(); }
125
126 int pos() { return _pos; }
127 void set_pos(int pos) { _pos = pos; }
128 LIR_Op* cur_op() { return lir()->instructions_list()->at(pos()); }
129 LIR_List* lir() { return _lir; }
130 void set_lir(LIR_List* lir) { _lir = lir; }
131 FpuStackSim* sim() { return &_sim; }
132 FpuStackSim* temp_sim() { return &_temp_sim; }
133
134 int fpu_num(LIR_Opr opr);
135 int tos_offset(LIR_Opr opr);
136 LIR_Opr to_fpu_stack_top(LIR_Opr opr, bool dont_check_offset = false);
137
138 // Helper functions for handling operations
139 void insert_op(LIR_Op* op);
140 void insert_exchange(int offset);
141 void insert_exchange(LIR_Opr opr);
142 void insert_free(int offset);
143 void insert_free_if_dead(LIR_Opr opr);
144 void insert_free_if_dead(LIR_Opr opr, LIR_Opr ignore);
145 void insert_copy(LIR_Opr from, LIR_Opr to);
146 void do_rename(LIR_Opr from, LIR_Opr to);
147 void do_push(LIR_Opr opr);
148 void pop_if_last_use(LIR_Op* op, LIR_Opr opr);
149 void pop_always(LIR_Op* op, LIR_Opr opr);
150 void clear_fpu_stack(LIR_Opr preserve);
151 void handle_op1(LIR_Op1* op1);
152 void handle_op2(LIR_Op2* op2);
153 void handle_opCall(LIR_OpCall* opCall);
154 void compute_debug_information(LIR_Op* op);
155 void allocate_exception_handler(XHandler* xhandler);
156 void allocate_block(BlockBegin* block);
157
158 #ifndef PRODUCT
159 void check_invalid_lir_op(LIR_Op* op);
160 #endif
161
162 // Helper functions for merging of fpu stacks
163 void merge_insert_add(LIR_List* instrs, FpuStackSim* cur_sim, int reg);
164 void merge_insert_xchg(LIR_List* instrs, FpuStackSim* cur_sim, int slot);
165 void merge_insert_pop(LIR_List* instrs, FpuStackSim* cur_sim);
166 bool merge_rename(FpuStackSim* cur_sim, FpuStackSim* sux_sim, int start_slot, int change_slot);
167 void merge_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, FpuStackSim* sux_sim);
168 void merge_cleanup_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, BitMap& live_fpu_regs);
169 bool merge_fpu_stack_with_successors(BlockBegin* block);
170
171 public:
172 LIR_Opr to_fpu_stack(LIR_Opr opr); // used by LinearScan for creation of debug information
173
174 FpuStackAllocator(Compilation* compilation, LinearScan* allocator);
175 void allocate();
176 };