truffle: src/share/vm/opto/machnode.hpp comparison

comparison src/share/vm/opto/machnode.hpp @ 17812:a7d4d4655766

Merge

author	kvn
date	Wed, 26 Mar 2014 18:21:05 -0700
parents	62c54fcc0a35
children	17b2fbdb6637

comparison

equal deleted inserted replaced

-:6b207d038106
+:a7d4d4655766
 #include "opto/matcher.hpp"
 #include "opto/multnode.hpp"
 #include "opto/node.hpp"
 #include "opto/regmask.hpp"
+class BiasedLockingCounters;
 class BufferBlob;
 class CodeBuffer;
 class JVMState;
 class MachCallDynamicJavaNode;
 class MachCallJavaNode;
 }
 XMMRegister  as_XMMRegister(PhaseRegAlloc *ra_, const Node *node, int idx)   const {
 return ::as_XMMRegister(reg(ra_, node, idx));
 }
 #endif
+// CondRegister reg converter
+#if defined(PPC64)
+ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node) const {
+return ::as_ConditionRegister(reg(ra_, node));
+}
+ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
+return ::as_ConditionRegister(reg(ra_, node, idx));
+}
+#endif
 virtual intptr_t  constant() const;
 virtual relocInfo::relocType constant_reloc() const;
 virtual jdouble constantD() const;
 virtual jfloat  constantF() const;
 // Methods to output the text version of the operand
 virtual void int_format(PhaseRegAlloc *,const MachNode *node, outputStream *st) const = 0;
 virtual void ext_format(PhaseRegAlloc *,const MachNode *node,int idx, outputStream *st) const=0;
 virtual void dump_spec(outputStream *st) const; // Print per-operand info
-#endif
+// Check whether o is a valid oper.
+static bool notAnOper(const MachOper *o) {
+if (o == NULL)                   return true;
+if (((intptr_t)o & 1) != 0)      return true;
+if (*(address*)o == badAddress)  return true;  // kill by Node::destruct
+return false;
+}
+#endif // !PRODUCT
 };
 //------------------------------MachNode---------------------------------------
 // Base type for all machine specific nodes.  All node classes generated by the
 // ADLC inherit from this class.
 virtual int  Opcode() const;          // Always equal to MachNode
 virtual uint rule() const = 0;        // Machine-specific opcode
 // Number of inputs which come before the first operand.
 // Generally at least 1, to skip the Control input
 virtual uint oper_input_base() const { return 1; }
+// Position of constant base node in node's inputs. -1 if
+// no constant base node input.
+virtual uint mach_constant_base_node_input() const { return (uint)-1; }
 // Copy inputs and operands to new node of instruction.
 // Called from cisc_version() and short_branch_version().
 // !!!! The method's body is defined in ad_<arch>.cpp file.
 void fill_new_machnode(MachNode *n, Compile* C) const;
 // instruction implemented with a call
 bool has_call() const { return (flags() & Flag_has_call) != 0; }
 // First index in _in[] corresponding to operand, or -1 if there is none
 int  operand_index(uint operand) const;
+int  operand_index(const MachOper *oper) const;
 // Register class input is expected in
 virtual const RegMask &in_RegMask(uint) const;
 // cisc-spillable instructions redefine for use by in_RegMask
 MachOper **_opnds;
 uint  num_opnds() const { return _num_opnds; }
 // Emit bytes into cbuf
 virtual void  emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
+// Expand node after register allocation.
+// Node is replaced by several nodes in the postalloc expand phase.
+// Corresponding methods are generated for nodes if they specify
+// postalloc_expand. See block.cpp for more documentation.
+virtual bool requires_postalloc_expand() const { return false; }
+virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
 // Size of instruction in bytes
 virtual uint  size(PhaseRegAlloc *ra_) const;
 // Helper function that computes size by emitting code
 virtual uint  emit_size(PhaseRegAlloc *ra_) const;
 // instruction to properly align it.
 virtual int   compute_padding(int current_offset) const { return 0; }
 // Return number of relocatable values contained in this instruction
 virtual int   reloc() const { return 0; }
+// Return number of words used for double constants in this instruction
+virtual int   ins_num_consts() const { return 0; }
 // Hash and compare over operands.  Used to do GVN on machine Nodes.
 virtual uint  hash() const;
 virtual uint  cmp( const Node &n ) const;
 // Get the pipeline info
 static const Pipeline *pipeline_class();
 virtual const Pipeline *pipeline() const;
+// Returns true if this node is a check that can be implemented with a trap.
+virtual bool is_TrapBasedCheckNode() const { return false; }
 #ifndef PRODUCT
 virtual const char *Name() const = 0; // Machine-specific name
 virtual void dump_spec(outputStream *st) const; // Print per-node info
 void         dump_format(PhaseRegAlloc *ra, outputStream *st) const; // access to virtual
 #endif
 }
 virtual const class Type* bottom_type() const { return TypeRawPtr::NOTNULL; }
 virtual uint ideal_reg() const { return Op_RegP; }
 virtual uint oper_input_base() const { return 1; }
+virtual bool requires_postalloc_expand() const;
+virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
 virtual void emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const;
 virtual uint size(PhaseRegAlloc* ra_) const;
 virtual bool pinned() const { return UseRDPCForConstantTableBase; }
 static const RegMask& static_out_RegMask() { return _out_RegMask; }
 return MachConstantBaseNode::static_out_RegMask();
 return MachNode::in_RegMask(idx);
 }
 // Input edge of MachConstantBaseNode.
-uint mach_constant_base_node_input() const { return req() - 1; }
+virtual uint mach_constant_base_node_input() const { return req() - 1; }
 int  constant_offset();
 int  constant_offset() const { return ((MachConstantNode*) this)->constant_offset(); }
+// Unchecked version to avoid assertions in debug output.
+int  constant_offset_unchecked() const;
 };
 //------------------------------MachUEPNode-----------------------------------
 // Machine Unvalidated Entry Point Node
 class MachUEPNode : public MachIdealNode {

Mercurial > hg > truffle

comparison src/share/vm/opto/machnode.hpp @ 17812:a7d4d4655766