Mercurial > hg > truffle
comparison src/cpu/x86/vm/x86_32.ad @ 219:ab65a4c9b2e8
6708714: Optimize long LShift on 32-bits x86
Summary: For small (1-3 bits) left long shifts in 32-bits VM use sets of add+addc instructions instead of shld+shl on new AMD cpus.
Reviewed-by: never
Contributed-by: shrinivas.joshi@amd.com
author | kvn |
---|---|
date | Mon, 23 Jun 2008 14:11:12 -0700 |
parents | 9148c65abefc |
children | 9c2ecc2ffb12 |
comparison
equal
deleted
inserted
replaced
217:411c61adc994 | 219:ab65a4c9b2e8 |
---|---|
4752 | 4752 |
4753 format %{ %} | 4753 format %{ %} |
4754 interface(CONST_INTER); | 4754 interface(CONST_INTER); |
4755 %} | 4755 %} |
4756 | 4756 |
4757 operand immI_1() %{ | |
4758 predicate( n->get_int() == 1 ); | |
4759 match(ConI); | |
4760 | |
4761 op_cost(0); | |
4762 format %{ %} | |
4763 interface(CONST_INTER); | |
4764 %} | |
4765 | |
4766 operand immI_2() %{ | |
4767 predicate( n->get_int() == 2 ); | |
4768 match(ConI); | |
4769 | |
4770 op_cost(0); | |
4771 format %{ %} | |
4772 interface(CONST_INTER); | |
4773 %} | |
4774 | |
4775 operand immI_3() %{ | |
4776 predicate( n->get_int() == 3 ); | |
4777 match(ConI); | |
4778 | |
4779 op_cost(0); | |
4780 format %{ %} | |
4781 interface(CONST_INTER); | |
4782 %} | |
4783 | |
4757 // Pointer Immediate | 4784 // Pointer Immediate |
4758 operand immP() %{ | 4785 operand immP() %{ |
4759 match(ConP); | 4786 match(ConP); |
4760 | 4787 |
4761 op_cost(10); | 4788 op_cost(10); |
8939 format %{ "XOR $dst.lo,$mem\n\t" | 8966 format %{ "XOR $dst.lo,$mem\n\t" |
8940 "XOR $dst.hi,$mem+4" %} | 8967 "XOR $dst.hi,$mem+4" %} |
8941 opcode(0x33,0x33); | 8968 opcode(0x33,0x33); |
8942 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | 8969 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); |
8943 ins_pipe( ialu_reg_long_mem ); | 8970 ins_pipe( ialu_reg_long_mem ); |
8971 %} | |
8972 | |
8973 // Shift Left Long by 1 | |
8974 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ | |
8975 predicate(UseNewLongLShift); | |
8976 match(Set dst (LShiftL dst cnt)); | |
8977 effect(KILL cr); | |
8978 ins_cost(100); | |
8979 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
8980 "ADC $dst.hi,$dst.hi" %} | |
8981 ins_encode %{ | |
8982 __ addl($dst$$Register,$dst$$Register); | |
8983 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
8984 %} | |
8985 ins_pipe( ialu_reg_long ); | |
8986 %} | |
8987 | |
8988 // Shift Left Long by 2 | |
8989 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ | |
8990 predicate(UseNewLongLShift); | |
8991 match(Set dst (LShiftL dst cnt)); | |
8992 effect(KILL cr); | |
8993 ins_cost(100); | |
8994 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
8995 "ADC $dst.hi,$dst.hi\n\t" | |
8996 "ADD $dst.lo,$dst.lo\n\t" | |
8997 "ADC $dst.hi,$dst.hi" %} | |
8998 ins_encode %{ | |
8999 __ addl($dst$$Register,$dst$$Register); | |
9000 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
9001 __ addl($dst$$Register,$dst$$Register); | |
9002 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
9003 %} | |
9004 ins_pipe( ialu_reg_long ); | |
9005 %} | |
9006 | |
9007 // Shift Left Long by 3 | |
9008 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ | |
9009 predicate(UseNewLongLShift); | |
9010 match(Set dst (LShiftL dst cnt)); | |
9011 effect(KILL cr); | |
9012 ins_cost(100); | |
9013 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
9014 "ADC $dst.hi,$dst.hi\n\t" | |
9015 "ADD $dst.lo,$dst.lo\n\t" | |
9016 "ADC $dst.hi,$dst.hi\n\t" | |
9017 "ADD $dst.lo,$dst.lo\n\t" | |
9018 "ADC $dst.hi,$dst.hi" %} | |
9019 ins_encode %{ | |
9020 __ addl($dst$$Register,$dst$$Register); | |
9021 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
9022 __ addl($dst$$Register,$dst$$Register); | |
9023 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
9024 __ addl($dst$$Register,$dst$$Register); | |
9025 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
9026 %} | |
9027 ins_pipe( ialu_reg_long ); | |
8944 %} | 9028 %} |
8945 | 9029 |
8946 // Shift Left Long by 1-31 | 9030 // Shift Left Long by 1-31 |
8947 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | 9031 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ |
8948 match(Set dst (LShiftL dst cnt)); | 9032 match(Set dst (LShiftL dst cnt)); |