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comparison src/cpu/sparc/vm/assembler_sparc.hpp @ 2002:ac637b7220d1

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6985015: C1 needs to support compressed oops Summary: This change implements compressed oops for C1 for x64 and sparc. The changes are mostly on the codegen level, with a few exceptions when we do access things outside of the heap that are uncompressed from the IR. Compressed oops are now also enabled with tiered. Reviewed-by: twisti, kvn, never, phh
author iveresov
date Tue, 30 Nov 2010 23:23:40 -0800
parents f95d63e2154a
children 2f644f85485d
comparison
equal deleted inserted replaced
1972:f95d63e2154a 2002:ac637b7220d1
1796 MacroAssembler* delayed() { Assembler::delayed(); return this; } 1796 MacroAssembler* delayed() { Assembler::delayed(); return this; }
1797 1797
1798 // branches that use right instruction for v8 vs. v9 1798 // branches that use right instruction for v8 vs. v9
1799 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 1799 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1800 inline void br( Condition c, bool a, Predict p, Label& L ); 1800 inline void br( Condition c, bool a, Predict p, Label& L );
1801
1801 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 1802 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1802 inline void fb( Condition c, bool a, Predict p, Label& L ); 1803 inline void fb( Condition c, bool a, Predict p, Label& L );
1803 1804
1804 // compares register with zero and branches (V9 and V8 instructions) 1805 // compares register with zero and branches (V9 and V8 instructions)
1805 void br_zero( Condition c, bool a, Predict p, Register s1, Label& L); 1806 void br_zero( Condition c, bool a, Predict p, Register s1, Label& L);