Mercurial > hg > truffle
comparison src/cpu/x86/vm/c1_LinearScan_x86.hpp @ 2002:ac637b7220d1
6985015: C1 needs to support compressed oops
Summary: This change implements compressed oops for C1 for x64 and sparc. The changes are mostly on the codegen level, with a few exceptions when we do access things outside of the heap that are uncompressed from the IR. Compressed oops are now also enabled with tiered.
Reviewed-by: twisti, kvn, never, phh
author | iveresov |
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date | Tue, 30 Nov 2010 23:23:40 -0800 |
parents | f95d63e2154a |
children |
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1972:f95d63e2154a | 2002:ac637b7220d1 |
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29 #ifndef _LP64 | 29 #ifndef _LP64 |
30 // rsp and rbp (numbers 6 ancd 7) are ignored | 30 // rsp and rbp (numbers 6 ancd 7) are ignored |
31 assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below"); | 31 assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below"); |
32 assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below"); | 32 assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below"); |
33 assert(reg_num >= 0, "invalid reg_num"); | 33 assert(reg_num >= 0, "invalid reg_num"); |
34 | |
35 return reg_num < 6 || reg_num > 7; | |
36 #else | 34 #else |
37 // rsp and rbp, r10, r15 (numbers 6 ancd 7) are ignored | 35 // rsp and rbp, r10, r15 (numbers [12,15]) are ignored |
36 // r12 (number 11) is conditional on compressed oops. | |
37 assert(FrameMap::r12_opr->cpu_regnr() == 11, "wrong assumption below"); | |
38 assert(FrameMap::r10_opr->cpu_regnr() == 12, "wrong assumption below"); | 38 assert(FrameMap::r10_opr->cpu_regnr() == 12, "wrong assumption below"); |
39 assert(FrameMap::r15_opr->cpu_regnr() == 13, "wrong assumption below"); | 39 assert(FrameMap::r15_opr->cpu_regnr() == 13, "wrong assumption below"); |
40 assert(FrameMap::rsp_opr->cpu_regnrLo() == 14, "wrong assumption below"); | 40 assert(FrameMap::rsp_opr->cpu_regnrLo() == 14, "wrong assumption below"); |
41 assert(FrameMap::rbp_opr->cpu_regnrLo() == 15, "wrong assumption below"); | 41 assert(FrameMap::rbp_opr->cpu_regnrLo() == 15, "wrong assumption below"); |
42 assert(reg_num >= 0, "invalid reg_num"); | 42 assert(reg_num >= 0, "invalid reg_num"); |
43 | |
44 return reg_num < 12 || reg_num > 15; | |
45 #endif // _LP64 | 43 #endif // _LP64 |
44 return reg_num <= FrameMap::last_cpu_reg() || reg_num >= pd_nof_cpu_regs_frame_map; | |
46 } | 45 } |
47 | 46 |
48 inline int LinearScan::num_physical_regs(BasicType type) { | 47 inline int LinearScan::num_physical_regs(BasicType type) { |
49 // Intel requires two cpu registers for long, | 48 // Intel requires two cpu registers for long, |
50 // but requires only one fpu register for double | 49 // but requires only one fpu register for double |
102 | 101 |
103 inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) { | 102 inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) { |
104 if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::byte_reg)) { | 103 if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::byte_reg)) { |
105 assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only"); | 104 assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only"); |
106 _first_reg = pd_first_byte_reg; | 105 _first_reg = pd_first_byte_reg; |
107 _last_reg = pd_last_byte_reg; | 106 _last_reg = FrameMap::last_byte_reg(); |
108 return true; | 107 return true; |
109 } else if ((UseSSE >= 1 && cur->type() == T_FLOAT) || (UseSSE >= 2 && cur->type() == T_DOUBLE)) { | 108 } else if ((UseSSE >= 1 && cur->type() == T_FLOAT) || (UseSSE >= 2 && cur->type() == T_DOUBLE)) { |
110 _first_reg = pd_first_xmm_reg; | 109 _first_reg = pd_first_xmm_reg; |
111 _last_reg = pd_last_xmm_reg; | 110 _last_reg = pd_last_xmm_reg; |
112 return true; | 111 return true; |