Mercurial > hg > truffle
comparison src/cpu/sparc/vm/vm_version_sparc.hpp @ 1914:ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
Summary: Use hardware DIV instruction for long division by constant when it is faster than code with multiply.
Reviewed-by: never
author | kvn |
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date | Tue, 02 Nov 2010 09:00:37 -0700 |
parents | c18cbe5936b8 |
children | f95d63e2154a |
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1913:3b2dea75431e | 1914:ae065c367d93 |
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1 /* | 1 /* |
2 * Copyright (c) 1997, 2009, Oracle and/or its affiliates. All rights reserved. | 2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | 4 * |
5 * This code is free software; you can redistribute it and/or modify it | 5 * This code is free software; you can redistribute it and/or modify it |
6 * under the terms of the GNU General Public License version 2 only, as | 6 * under the terms of the GNU General Public License version 2 only, as |
7 * published by the Free Software Foundation. | 7 * published by the Free Software Foundation. |
31 hardware_fsmuld = 3, | 31 hardware_fsmuld = 3, |
32 hardware_popc = 4, | 32 hardware_popc = 4, |
33 v9_instructions = 5, | 33 v9_instructions = 5, |
34 vis1_instructions = 6, | 34 vis1_instructions = 6, |
35 vis2_instructions = 7, | 35 vis2_instructions = 7, |
36 sun4v_instructions = 8 | 36 sun4v_instructions = 8, |
37 blk_init_instructions = 9, | |
38 fmaf_instructions = 10 | |
37 }; | 39 }; |
38 | 40 |
39 enum Feature_Flag_Set { | 41 enum Feature_Flag_Set { |
40 unknown_m = 0, | 42 unknown_m = 0, |
41 all_features_m = -1, | 43 all_features_m = -1, |
47 hardware_popc_m = 1 << hardware_popc, | 49 hardware_popc_m = 1 << hardware_popc, |
48 v9_instructions_m = 1 << v9_instructions, | 50 v9_instructions_m = 1 << v9_instructions, |
49 vis1_instructions_m = 1 << vis1_instructions, | 51 vis1_instructions_m = 1 << vis1_instructions, |
50 vis2_instructions_m = 1 << vis2_instructions, | 52 vis2_instructions_m = 1 << vis2_instructions, |
51 sun4v_m = 1 << sun4v_instructions, | 53 sun4v_m = 1 << sun4v_instructions, |
54 blk_init_instructions_m = 1 << blk_init_instructions, | |
55 fmaf_instructions_m = 1 << fmaf_instructions, | |
52 | 56 |
53 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, | 57 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, |
54 generic_v9_m = generic_v8_m | v9_instructions_m, | 58 generic_v9_m = generic_v8_m | v9_instructions_m, |
55 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m, | 59 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m, |
56 | 60 |
65 static void print_features(); | 69 static void print_features(); |
66 static int determine_features(); | 70 static int determine_features(); |
67 static int platform_features(int features); | 71 static int platform_features(int features); |
68 | 72 |
69 static bool is_niagara1(int features) { return (features & sun4v_m) != 0; } | 73 static bool is_niagara1(int features) { return (features & sun4v_m) != 0; } |
74 static bool is_sparc64(int features) { return (features & fmaf_instructions_m) != 0; } | |
70 | 75 |
71 static int maximum_niagara1_processor_count() { return 32; } | 76 static int maximum_niagara1_processor_count() { return 32; } |
72 // Returns true if the platform is in the niagara line and | 77 // Returns true if the platform is in the niagara line and |
73 // newer than the niagara1. | 78 // newer than the niagara1. |
74 static bool is_niagara1_plus(); | 79 static bool is_niagara1_plus(); |
84 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; } | 89 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; } |
85 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; } | 90 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; } |
86 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; } | 91 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; } |
87 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; } | 92 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; } |
88 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; } | 93 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; } |
94 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; } | |
89 | 95 |
90 static bool supports_compare_and_exchange() | 96 static bool supports_compare_and_exchange() |
91 { return has_v9(); } | 97 { return has_v9(); } |
92 | 98 |
93 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m; } | 99 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m; } |
94 static bool is_sun4v() { return (_features & sun4v_m) != 0; } | 100 static bool is_sun4v() { return (_features & sun4v_m) != 0; } |
95 static bool is_niagara1() { return is_niagara1(_features); } | 101 static bool is_niagara1() { return is_niagara1(_features); } |
102 static bool is_sparc64() { return is_sparc64(_features); } | |
96 | 103 |
97 static bool has_fast_fxtof() { return has_v9() && !is_ultra3(); } | 104 static bool has_fast_fxtof() { return has_v9() && !is_ultra3(); } |
105 static bool has_fast_idiv() { return is_niagara1_plus() || is_sparc64(); } | |
98 | 106 |
99 static const char* cpu_features() { return _features_str; } | 107 static const char* cpu_features() { return _features_str; } |
100 | 108 |
101 static intx L1_data_cache_line_size() { | 109 static intx L1_data_cache_line_size() { |
102 return 64; // default prefetch block size on sparc | 110 return 64; // default prefetch block size on sparc |