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comparison src/cpu/sparc/vm/vm_version_sparc.hpp @ 20313:b20a35eae442

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8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC Summary: Add C2 SHA intrinsics on SPARC Reviewed-by: kvn, roland Contributed-by: james.cheng@oracle.com
author kvn
date Wed, 11 Jun 2014 11:05:10 -0700
parents 031b06eac1a9
children d635fd1ac81c
comparison
equal deleted inserted replaced
20312:922c87c9aed4 20313:b20a35eae442
1 /* 1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 * 4 *
5 * This code is free software; you can redistribute it and/or modify it 5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as 6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
48 sparc64_family = 14, 48 sparc64_family = 14,
49 M_family = 15, 49 M_family = 15,
50 T_family = 16, 50 T_family = 16,
51 T1_model = 17, 51 T1_model = 17,
52 sparc5_instructions = 18, 52 sparc5_instructions = 18,
53 aes_instructions = 19 53 aes_instructions = 19,
54 sha1_instruction = 20,
55 sha256_instruction = 21,
56 sha512_instruction = 22
54 }; 57 };
55 58
56 enum Feature_Flag_Set { 59 enum Feature_Flag_Set {
57 unknown_m = 0, 60 unknown_m = 0,
58 all_features_m = -1, 61 all_features_m = -1,
75 M_family_m = 1 << M_family, 78 M_family_m = 1 << M_family,
76 T_family_m = 1 << T_family, 79 T_family_m = 1 << T_family,
77 T1_model_m = 1 << T1_model, 80 T1_model_m = 1 << T1_model,
78 sparc5_instructions_m = 1 << sparc5_instructions, 81 sparc5_instructions_m = 1 << sparc5_instructions,
79 aes_instructions_m = 1 << aes_instructions, 82 aes_instructions_m = 1 << aes_instructions,
83 sha1_instruction_m = 1 << sha1_instruction,
84 sha256_instruction_m = 1 << sha256_instruction,
85 sha512_instruction_m = 1 << sha512_instruction,
80 86
81 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, 87 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
82 generic_v9_m = generic_v8_m | v9_instructions_m, 88 generic_v9_m = generic_v8_m | v9_instructions_m,
83 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m, 89 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
84 90
127 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; } 133 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; }
128 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; } 134 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; }
129 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; } 135 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; }
130 static bool has_sparc5_instr() { return (_features & sparc5_instructions_m) != 0; } 136 static bool has_sparc5_instr() { return (_features & sparc5_instructions_m) != 0; }
131 static bool has_aes() { return (_features & aes_instructions_m) != 0; } 137 static bool has_aes() { return (_features & aes_instructions_m) != 0; }
138 static bool has_sha1() { return (_features & sha1_instruction_m) != 0; }
139 static bool has_sha256() { return (_features & sha256_instruction_m) != 0; }
140 static bool has_sha512() { return (_features & sha512_instruction_m) != 0; }
132 141
133 static bool supports_compare_and_exchange() 142 static bool supports_compare_and_exchange()
134 { return has_v9(); } 143 { return has_v9(); }
135 144
136 // Returns true if the platform is in the niagara line (T series) 145 // Returns true if the platform is in the niagara line (T series)