Mercurial > hg > truffle

comparison src/cpu/x86/vm/assembler_x86.cpp @ 14704:b51e29501f30

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Merged with jdk9/dev/hotspot changeset 9486a41de3b7
author twisti
date Tue, 18 Mar 2014 20:19:10 -0700
parents d49f00604347 9e9af3aa4278
children 92aa6797d639
comparison
equal deleted inserted replaced
14647:8f483e200405 14704:b51e29501f30
1087 void Assembler::andl(Register dst, Register src) { 1087 void Assembler::andl(Register dst, Register src) {
1088 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1088 (void) prefix_and_encode(dst->encoding(), src->encoding());
1089 emit_arith(0x23, 0xC0, dst, src); 1089 emit_arith(0x23, 0xC0, dst, src);
1090 } 1090 }
1091 1091
1092 void Assembler::andnl(Register dst, Register src1, Register src2) {
1093 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1094 int encode = vex_prefix_0F38_and_encode(dst, src1, src2);
1095 emit_int8((unsigned char)0xF2);
1096 emit_int8((unsigned char)(0xC0 | encode));
1097 }
1098
1099 void Assembler::andnl(Register dst, Register src1, Address src2) {
1100 InstructionMark im(this);
1101 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1102 vex_prefix_0F38(dst, src1, src2);
1103 emit_int8((unsigned char)0xF2);
1104 emit_operand(dst, src2);
1105 }
1106
1092 void Assembler::bsfl(Register dst, Register src) { 1107 void Assembler::bsfl(Register dst, Register src) {
1093 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1108 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1094 emit_int8(0x0F); 1109 emit_int8(0x0F);
1095 emit_int8((unsigned char)0xBC); 1110 emit_int8((unsigned char)0xBC);
1096 emit_int8((unsigned char)(0xC0 | encode)); 1111 emit_int8((unsigned char)(0xC0 | encode));
1106 1121
1107 void Assembler::bswapl(Register reg) { // bswap 1122 void Assembler::bswapl(Register reg) { // bswap
1108 int encode = prefix_and_encode(reg->encoding()); 1123 int encode = prefix_and_encode(reg->encoding());
1109 emit_int8(0x0F); 1124 emit_int8(0x0F);
1110 emit_int8((unsigned char)(0xC8 | encode)); 1125 emit_int8((unsigned char)(0xC8 | encode));
1126 }
1127
1128 void Assembler::blsil(Register dst, Register src) {
1129 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1130 int encode = vex_prefix_0F38_and_encode(rbx, dst, src);
1131 emit_int8((unsigned char)0xF3);
1132 emit_int8((unsigned char)(0xC0 | encode));
1133 }
1134
1135 void Assembler::blsil(Register dst, Address src) {
1136 InstructionMark im(this);
1137 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1138 vex_prefix_0F38(rbx, dst, src);
1139 emit_int8((unsigned char)0xF3);
1140 emit_operand(rbx, src);
1141 }
1142
1143 void Assembler::blsmskl(Register dst, Register src) {
1144 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1145 int encode = vex_prefix_0F38_and_encode(rdx, dst, src);
1146 emit_int8((unsigned char)0xF3);
1147 emit_int8((unsigned char)(0xC0 | encode));
1148 }
1149
1150 void Assembler::blsmskl(Register dst, Address src) {
1151 InstructionMark im(this);
1152 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1153 vex_prefix_0F38(rdx, dst, src);
1154 emit_int8((unsigned char)0xF3);
1155 emit_operand(rdx, src);
1156 }
1157
1158 void Assembler::blsrl(Register dst, Register src) {
1159 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1160 int encode = vex_prefix_0F38_and_encode(rcx, dst, src);
1161 emit_int8((unsigned char)0xF3);
1162 emit_int8((unsigned char)(0xC0 | encode));
1163 }
1164
1165 void Assembler::blsrl(Register dst, Address src) {
1166 InstructionMark im(this);
1167 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1168 vex_prefix_0F38(rcx, dst, src);
1169 emit_int8((unsigned char)0xF3);
1170 emit_operand(rcx, src);
1111 } 1171 }
1112 1172
1113 void Assembler::call(Label& L, relocInfo::relocType rtype) { 1173 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1114 // suspect disp32 is always good 1174 // suspect disp32 is always good
1115 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); 1175 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
2876 prefix(src, dst); 2936 prefix(src, dst);
2877 emit_int8((unsigned char)0x85); 2937 emit_int8((unsigned char)0x85);
2878 emit_operand(dst, src); 2938 emit_operand(dst, src);
2879 } 2939 }
2880 2940
2941 void Assembler::tzcntl(Register dst, Register src) {
2942 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2943 emit_int8((unsigned char)0xF3);
2944 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2945 emit_int8(0x0F);
2946 emit_int8((unsigned char)0xBC);
2947 emit_int8((unsigned char)0xC0 | encode);
2948 }
2949
2950 void Assembler::tzcntq(Register dst, Register src) {
2951 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2952 emit_int8((unsigned char)0xF3);
2953 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2954 emit_int8(0x0F);
2955 emit_int8((unsigned char)0xBC);
2956 emit_int8((unsigned char)(0xC0 | encode));
2957 }
2958
2881 void Assembler::ucomisd(XMMRegister dst, Address src) { 2959 void Assembler::ucomisd(XMMRegister dst, Address src) {
2882 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2960 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2883 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); 2961 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2884 } 2962 }
2885 2963
4835 void Assembler::andq(Register dst, Register src) { 4913 void Assembler::andq(Register dst, Register src) {
4836 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 4914 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4837 emit_arith(0x23, 0xC0, dst, src); 4915 emit_arith(0x23, 0xC0, dst, src);
4838 } 4916 }
4839 4917
4918 void Assembler::andnq(Register dst, Register src1, Register src2) {
4919 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4920 int encode = vex_prefix_0F38_and_encode_q(dst, src1, src2);
4921 emit_int8((unsigned char)0xF2);
4922 emit_int8((unsigned char)(0xC0 | encode));
4923 }
4924
4925 void Assembler::andnq(Register dst, Register src1, Address src2) {
4926 InstructionMark im(this);
4927 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4928 vex_prefix_0F38_q(dst, src1, src2);
4929 emit_int8((unsigned char)0xF2);
4930 emit_operand(dst, src2);
4931 }
4932
4840 void Assembler::bsfq(Register dst, Register src) { 4933 void Assembler::bsfq(Register dst, Register src) {
4841 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4934 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4842 emit_int8(0x0F); 4935 emit_int8(0x0F);
4843 emit_int8((unsigned char)0xBC); 4936 emit_int8((unsigned char)0xBC);
4844 emit_int8((unsigned char)(0xC0 | encode)); 4937 emit_int8((unsigned char)(0xC0 | encode));
4854 4947
4855 void Assembler::bswapq(Register reg) { 4948 void Assembler::bswapq(Register reg) {
4856 int encode = prefixq_and_encode(reg->encoding()); 4949 int encode = prefixq_and_encode(reg->encoding());
4857 emit_int8(0x0F); 4950 emit_int8(0x0F);
4858 emit_int8((unsigned char)(0xC8 | encode)); 4951 emit_int8((unsigned char)(0xC8 | encode));
4952 }
4953
4954 void Assembler::blsiq(Register dst, Register src) {
4955 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4956 int encode = vex_prefix_0F38_and_encode_q(rbx, dst, src);
4957 emit_int8((unsigned char)0xF3);
4958 emit_int8((unsigned char)(0xC0 | encode));
4959 }
4960
4961 void Assembler::blsiq(Register dst, Address src) {
4962 InstructionMark im(this);
4963 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4964 vex_prefix_0F38_q(rbx, dst, src);
4965 emit_int8((unsigned char)0xF3);
4966 emit_operand(rbx, src);
4967 }
4968
4969 void Assembler::blsmskq(Register dst, Register src) {
4970 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4971 int encode = vex_prefix_0F38_and_encode_q(rdx, dst, src);
4972 emit_int8((unsigned char)0xF3);
4973 emit_int8((unsigned char)(0xC0 | encode));
4974 }
4975
4976 void Assembler::blsmskq(Register dst, Address src) {
4977 InstructionMark im(this);
4978 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4979 vex_prefix_0F38_q(rdx, dst, src);
4980 emit_int8((unsigned char)0xF3);
4981 emit_operand(rdx, src);
4982 }
4983
4984 void Assembler::blsrq(Register dst, Register src) {
4985 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4986 int encode = vex_prefix_0F38_and_encode_q(rcx, dst, src);
4987 emit_int8((unsigned char)0xF3);
4988 emit_int8((unsigned char)(0xC0 | encode));
4989 }
4990
4991 void Assembler::blsrq(Register dst, Address src) {
4992 InstructionMark im(this);
4993 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4994 vex_prefix_0F38_q(rcx, dst, src);
4995 emit_int8((unsigned char)0xF3);
4996 emit_operand(rcx, src);
4859 } 4997 }
4860 4998
4861 void Assembler::cdqq() { 4999 void Assembler::cdqq() {
4862 prefix(REX_W); 5000 prefix(REX_W);
4863 emit_int8((unsigned char)0x99); 5001 emit_int8((unsigned char)0x99);