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comparison graal/com.oracle.max.asm/src/com/oracle/max/asm/target/amd64/AMD64Assembler.java @ 5547:b6617d13ea44

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Dropping Ci* prefixes. Some additional renamings in the api.code interface.
author Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
date Sat, 09 Jun 2012 20:10:05 +0200
parents a891c53a295b
children 69a8969dbf40
comparison
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5546:e42c0df7212a 5547:b6617d13ea44
20 * or visit www.oracle.com if you need additional information or have any 20 * or visit www.oracle.com if you need additional information or have any
21 * questions. 21 * questions.
22 */ 22 */
23 package com.oracle.max.asm.target.amd64; 23 package com.oracle.max.asm.target.amd64;
24 24
25 import static com.oracle.graal.api.code.CiValueUtil.*; 25 import static com.oracle.graal.api.code.ValueUtil.*;
26 import static com.oracle.max.asm.NumUtil.*; 26 import static com.oracle.max.asm.NumUtil.*;
27 import static com.oracle.max.asm.target.amd64.AMD64.*; 27 import static com.oracle.max.asm.target.amd64.AMD64.*;
28 import static com.oracle.max.cri.util.MemoryBarriers.*; 28 import static com.oracle.max.cri.util.MemoryBarriers.*;
29 29
30 import com.oracle.graal.api.code.*; 30 import com.oracle.graal.api.code.*;
123 private static final int REXWRX = 0x4E; 123 private static final int REXWRX = 0x4E;
124 private static final int REXWRXB = 0x4F; 124 private static final int REXWRXB = 0x4F;
125 } 125 }
126 126
127 /** 127 /**
128 * The register to which {@link CiRegister#Frame} and {@link CiRegister#CallerFrame} are bound. 128 * The register to which {@link Register#Frame} and {@link Register#CallerFrame} are bound.
129 */ 129 */
130 public final CiRegister frameRegister; 130 public final Register frameRegister;
131 131
132 /** 132 /**
133 * Constructs an assembler for the AMD64 architecture. 133 * Constructs an assembler for the AMD64 architecture.
134 * 134 *
135 * @param registerConfig the register configuration used to bind {@link CiRegister#Frame} and 135 * @param registerConfig the register configuration used to bind {@link Register#Frame} and
136 * {@link CiRegister#CallerFrame} to physical registers. This value can be null if this assembler 136 * {@link Register#CallerFrame} to physical registers. This value can be null if this assembler
137 * instance will not be used to assemble instructions using these logical registers. 137 * instance will not be used to assemble instructions using these logical registers.
138 */ 138 */
139 public AMD64Assembler(CiTarget target, CiRegisterConfig registerConfig) { 139 public AMD64Assembler(TargetDescription target, RegisterConfig registerConfig) {
140 super(target); 140 super(target);
141 this.frameRegister = registerConfig == null ? null : registerConfig.getFrameRegister(); 141 this.frameRegister = registerConfig == null ? null : registerConfig.getFrameRegister();
142 } 142 }
143 143
144 private static int encode(CiRegister r) { 144 private static int encode(Register r) {
145 assert r.encoding < 16 && r.encoding >= 0 : "encoding out of range: " + r.encoding; 145 assert r.encoding < 16 && r.encoding >= 0 : "encoding out of range: " + r.encoding;
146 return r.encoding & 0x7; 146 return r.encoding & 0x7;
147 } 147 }
148 148
149 private void emitArithB(int op1, int op2, CiRegister dst, int imm8) { 149 private void emitArithB(int op1, int op2, Register dst, int imm8) {
150 assert dst.isByte() : "must have byte register"; 150 assert dst.isByte() : "must have byte register";
151 assert isUByte(op1) && isUByte(op2) : "wrong opcode"; 151 assert isUByte(op1) && isUByte(op2) : "wrong opcode";
152 assert isUByte(imm8) : "not a byte"; 152 assert isUByte(imm8) : "not a byte";
153 assert (op1 & 0x01) == 0 : "should be 8bit operation"; 153 assert (op1 & 0x01) == 0 : "should be 8bit operation";
154 emitByte(op1); 154 emitByte(op1);
155 emitByte(op2 | encode(dst)); 155 emitByte(op2 | encode(dst));
156 emitByte(imm8); 156 emitByte(imm8);
157 } 157 }
158 158
159 private void emitArith(int op1, int op2, CiRegister dst, int imm32) { 159 private void emitArith(int op1, int op2, Register dst, int imm32) {
160 assert isUByte(op1) && isUByte(op2) : "wrong opcode"; 160 assert isUByte(op1) && isUByte(op2) : "wrong opcode";
161 assert (op1 & 0x01) == 1 : "should be 32bit operation"; 161 assert (op1 & 0x01) == 1 : "should be 32bit operation";
162 assert (op1 & 0x02) == 0 : "sign-extension bit should not be set"; 162 assert (op1 & 0x02) == 0 : "sign-extension bit should not be set";
163 if (isByte(imm32)) { 163 if (isByte(imm32)) {
164 emitByte(op1 | 0x02); // set sign bit 164 emitByte(op1 | 0x02); // set sign bit
170 emitInt(imm32); 170 emitInt(imm32);
171 } 171 }
172 } 172 }
173 173
174 // immediate-to-memory forms 174 // immediate-to-memory forms
175 private void emitArithOperand(int op1, CiRegister rm, CiAddress adr, int imm32) { 175 private void emitArithOperand(int op1, Register rm, Address adr, int imm32) {
176 assert (op1 & 0x01) == 1 : "should be 32bit operation"; 176 assert (op1 & 0x01) == 1 : "should be 32bit operation";
177 assert (op1 & 0x02) == 0 : "sign-extension bit should not be set"; 177 assert (op1 & 0x02) == 0 : "sign-extension bit should not be set";
178 if (isByte(imm32)) { 178 if (isByte(imm32)) {
179 emitByte(op1 | 0x02); // set sign bit 179 emitByte(op1 | 0x02); // set sign bit
180 emitOperandHelper(rm, adr); 180 emitOperandHelper(rm, adr);
184 emitOperandHelper(rm, adr); 184 emitOperandHelper(rm, adr);
185 emitInt(imm32); 185 emitInt(imm32);
186 } 186 }
187 } 187 }
188 188
189 private void emitArith(int op1, int op2, CiRegister dst, CiRegister src) { 189 private void emitArith(int op1, int op2, Register dst, Register src) {
190 assert isUByte(op1) && isUByte(op2) : "wrong opcode"; 190 assert isUByte(op1) && isUByte(op2) : "wrong opcode";
191 emitByte(op1); 191 emitByte(op1);
192 emitByte(op2 | encode(dst) << 3 | encode(src)); 192 emitByte(op2 | encode(dst) << 3 | encode(src));
193 } 193 }
194 194
195 private void emitOperandHelper(CiRegister reg, CiAddress addr) { 195 private void emitOperandHelper(Register reg, Address addr) {
196 CiRegister base = isLegal(addr.base) ? asRegister(addr.base) : CiRegister.None; 196 Register base = isLegal(addr.base) ? asRegister(addr.base) : Register.None;
197 CiRegister index = isLegal(addr.index) ? asRegister(addr.index) : CiRegister.None; 197 Register index = isLegal(addr.index) ? asRegister(addr.index) : Register.None;
198 198
199 CiAddress.Scale scale = addr.scale; 199 Address.Scale scale = addr.scale;
200 int disp = addr.displacement; 200 int disp = addr.displacement;
201 201
202 if (base == CiRegister.Frame) { 202 if (base == Register.Frame) {
203 assert frameRegister != null : "cannot use register " + CiRegister.Frame + " in assembler with null register configuration"; 203 assert frameRegister != null : "cannot use register " + Register.Frame + " in assembler with null register configuration";
204 base = frameRegister; 204 base = frameRegister;
205 // } else if (base == CiRegister.CallerFrame) { 205 // } else if (base == CiRegister.CallerFrame) {
206 // assert frameRegister != null : "cannot use register " + CiRegister.Frame + " in assembler with null register configuration"; 206 // assert frameRegister != null : "cannot use register " + CiRegister.Frame + " in assembler with null register configuration";
207 // base = frameRegister; 207 // base = frameRegister;
208 // disp += targetMethod.frameSize() + 8; 208 // disp += targetMethod.frameSize() + 8;
209 } 209 }
210 210
211 // Encode the registers as needed in the fields they are used in 211 // Encode the registers as needed in the fields they are used in
212 212
213 assert reg != CiRegister.None; 213 assert reg != Register.None;
214 int regenc = encode(reg) << 3; 214 int regenc = encode(reg) << 3;
215 215
216 if (base == AMD64.rip) { 216 if (base == AMD64.rip) {
217 // [00 000 101] disp32 217 // [00 000 101] disp32
218 emitByte(0x05 | regenc); 218 emitByte(0x05 | regenc);
219 emitInt(disp); 219 emitInt(disp);
220 } else if (addr == CiAddress.Placeholder) { 220 } else if (addr == Address.Placeholder) {
221 // [00 000 101] disp32 221 // [00 000 101] disp32
222 emitByte(0x05 | regenc); 222 emitByte(0x05 | regenc);
223 emitInt(0); 223 emitInt(0);
224 224
225 } else if (base.isValid()) { 225 } else if (base.isValid()) {
304 emitInt(disp); 304 emitInt(disp);
305 } 305 }
306 } 306 }
307 } 307 }
308 308
309 public final void addl(CiAddress dst, int imm32) { 309 public final void addl(Address dst, int imm32) {
310 prefix(dst); 310 prefix(dst);
311 emitArithOperand(0x81, rax, dst, imm32); 311 emitArithOperand(0x81, rax, dst, imm32);
312 } 312 }
313 313
314 public final void addl(CiAddress dst, CiRegister src) { 314 public final void addl(Address dst, Register src) {
315 prefix(dst, src); 315 prefix(dst, src);
316 emitByte(0x01); 316 emitByte(0x01);
317 emitOperandHelper(src, dst); 317 emitOperandHelper(src, dst);
318 } 318 }
319 319
320 public final void addl(CiRegister dst, int imm32) { 320 public final void addl(Register dst, int imm32) {
321 prefix(dst); 321 prefix(dst);
322 emitArith(0x81, 0xC0, dst, imm32); 322 emitArith(0x81, 0xC0, dst, imm32);
323 } 323 }
324 324
325 public final void addl(CiRegister dst, CiAddress src) { 325 public final void addl(Register dst, Address src) {
326 prefix(src, dst); 326 prefix(src, dst);
327 emitByte(0x03); 327 emitByte(0x03);
328 emitOperandHelper(dst, src); 328 emitOperandHelper(dst, src);
329 } 329 }
330 330
331 public final void addl(CiRegister dst, CiRegister src) { 331 public final void addl(Register dst, Register src) {
332 prefixAndEncode(dst.encoding, src.encoding); 332 prefixAndEncode(dst.encoding, src.encoding);
333 emitArith(0x03, 0xC0, dst, src); 333 emitArith(0x03, 0xC0, dst, src);
334 } 334 }
335 335
336 private void addrNop4() { 336 private void addrNop4() {
365 emitByte(0x84); // emitRm(cbuf, 0x2, EAXEnc, 0x4); 365 emitByte(0x84); // emitRm(cbuf, 0x2, EAXEnc, 0x4);
366 emitByte(0x00); // emitRm(cbuf, 0x0, EAXEnc, EAXEnc); 366 emitByte(0x00); // emitRm(cbuf, 0x0, EAXEnc, EAXEnc);
367 emitInt(0); // 32-bits offset (4 bytes) 367 emitInt(0); // 32-bits offset (4 bytes)
368 } 368 }
369 369
370 public final void addsd(CiRegister dst, CiRegister src) { 370 public final void addsd(Register dst, Register src) {
371 assert dst.isFpu() && src.isFpu(); 371 assert dst.isFpu() && src.isFpu();
372 emitByte(0xF2); 372 emitByte(0xF2);
373 int encode = prefixAndEncode(dst.encoding, src.encoding); 373 int encode = prefixAndEncode(dst.encoding, src.encoding);
374 emitByte(0x0F); 374 emitByte(0x0F);
375 emitByte(0x58); 375 emitByte(0x58);
376 emitByte(0xC0 | encode); 376 emitByte(0xC0 | encode);
377 } 377 }
378 378
379 public final void addsd(CiRegister dst, CiAddress src) { 379 public final void addsd(Register dst, Address src) {
380 assert dst.isFpu(); 380 assert dst.isFpu();
381 emitByte(0xF2); 381 emitByte(0xF2);
382 prefix(src, dst); 382 prefix(src, dst);
383 emitByte(0x0F); 383 emitByte(0x0F);
384 emitByte(0x58); 384 emitByte(0x58);
385 emitOperandHelper(dst, src); 385 emitOperandHelper(dst, src);
386 } 386 }
387 387
388 public final void addss(CiRegister dst, CiRegister src) { 388 public final void addss(Register dst, Register src) {
389 assert dst.isFpu() && src.isFpu(); 389 assert dst.isFpu() && src.isFpu();
390 emitByte(0xF3); 390 emitByte(0xF3);
391 int encode = prefixAndEncode(dst.encoding, src.encoding); 391 int encode = prefixAndEncode(dst.encoding, src.encoding);
392 emitByte(0x0F); 392 emitByte(0x0F);
393 emitByte(0x58); 393 emitByte(0x58);
394 emitByte(0xC0 | encode); 394 emitByte(0xC0 | encode);
395 } 395 }
396 396
397 public final void addss(CiRegister dst, CiAddress src) { 397 public final void addss(Register dst, Address src) {
398 assert dst.isFpu(); 398 assert dst.isFpu();
399 emitByte(0xF3); 399 emitByte(0xF3);
400 prefix(src, dst); 400 prefix(src, dst);
401 emitByte(0x0F); 401 emitByte(0x0F);
402 emitByte(0x58); 402 emitByte(0x58);
403 emitOperandHelper(dst, src); 403 emitOperandHelper(dst, src);
404 } 404 }
405 405
406 public final void andl(CiRegister dst, int imm32) { 406 public final void andl(Register dst, int imm32) {
407 prefix(dst); 407 prefix(dst);
408 emitArith(0x81, 0xE0, dst, imm32); 408 emitArith(0x81, 0xE0, dst, imm32);
409 } 409 }
410 410
411 public final void andl(CiRegister dst, CiAddress src) { 411 public final void andl(Register dst, Address src) {
412 prefix(src, dst); 412 prefix(src, dst);
413 emitByte(0x23); 413 emitByte(0x23);
414 emitOperandHelper(dst, src); 414 emitOperandHelper(dst, src);
415 } 415 }
416 416
417 public final void andl(CiRegister dst, CiRegister src) { 417 public final void andl(Register dst, Register src) {
418 prefixAndEncode(dst.encoding, src.encoding); 418 prefixAndEncode(dst.encoding, src.encoding);
419 emitArith(0x23, 0xC0, dst, src); 419 emitArith(0x23, 0xC0, dst, src);
420 } 420 }
421 421
422 public final void bsfq(CiRegister dst, CiRegister src) { 422 public final void bsfq(Register dst, Register src) {
423 int encode = prefixqAndEncode(dst.encoding, src.encoding); 423 int encode = prefixqAndEncode(dst.encoding, src.encoding);
424 emitByte(0x0F); 424 emitByte(0x0F);
425 emitByte(0xBC); 425 emitByte(0xBC);
426 emitByte(0xC0 | encode); 426 emitByte(0xC0 | encode);
427 } 427 }
428 428
429 public final void bsfq(CiRegister dst, CiAddress src) { 429 public final void bsfq(Register dst, Address src) {
430 prefixq(src, dst); 430 prefixq(src, dst);
431 emitByte(0xBC); 431 emitByte(0xBC);
432 emitOperandHelper(dst, src); 432 emitOperandHelper(dst, src);
433 } 433 }
434 434
435 public final void bsrq(CiRegister dst, CiRegister src) { 435 public final void bsrq(Register dst, Register src) {
436 int encode = prefixqAndEncode(dst.encoding, src.encoding); 436 int encode = prefixqAndEncode(dst.encoding, src.encoding);
437 emitByte(0x0F); 437 emitByte(0x0F);
438 emitByte(0xBD); 438 emitByte(0xBD);
439 emitByte(0xC0 | encode); 439 emitByte(0xC0 | encode);
440 } 440 }
441 441
442 442
443 public final void bsrq(CiRegister dst, CiAddress src) { 443 public final void bsrq(Register dst, Address src) {
444 prefixq(src, dst); 444 prefixq(src, dst);
445 emitByte(0xBD); 445 emitByte(0xBD);
446 emitOperandHelper(dst, src); 446 emitOperandHelper(dst, src);
447 } 447 }
448 448
449 public final void bswapl(CiRegister reg) { // bswap 449 public final void bswapl(Register reg) { // bswap
450 int encode = prefixAndEncode(reg.encoding); 450 int encode = prefixAndEncode(reg.encoding);
451 emitByte(0x0F); 451 emitByte(0x0F);
452 emitByte(0xC8 | encode); 452 emitByte(0xC8 | encode);
453 } 453 }
454 454
455 public final void btli(CiAddress src, int imm8) { 455 public final void btli(Address src, int imm8) {
456 prefixq(src); 456 prefixq(src);
457 emitByte(0x0F); 457 emitByte(0x0F);
458 emitByte(0xBA); 458 emitByte(0xBA);
459 emitOperandHelper(rsp, src); 459 emitOperandHelper(rsp, src);
460 emitByte(imm8); 460 emitByte(imm8);
462 462
463 public final void cdql() { 463 public final void cdql() {
464 emitByte(0x99); 464 emitByte(0x99);
465 } 465 }
466 466
467 public final void cmovl(ConditionFlag cc, CiRegister dst, CiRegister src) { 467 public final void cmovl(ConditionFlag cc, Register dst, Register src) {
468 int encode = prefixAndEncode(dst.encoding, src.encoding); 468 int encode = prefixAndEncode(dst.encoding, src.encoding);
469 emitByte(0x0F); 469 emitByte(0x0F);
470 emitByte(0x40 | cc.value); 470 emitByte(0x40 | cc.value);
471 emitByte(0xC0 | encode); 471 emitByte(0xC0 | encode);
472 } 472 }
473 473
474 public final void cmovl(ConditionFlag cc, CiRegister dst, CiAddress src) { 474 public final void cmovl(ConditionFlag cc, Register dst, Address src) {
475 prefix(src, dst); 475 prefix(src, dst);
476 emitByte(0x0F); 476 emitByte(0x0F);
477 emitByte(0x40 | cc.value); 477 emitByte(0x40 | cc.value);
478 emitOperandHelper(dst, src); 478 emitOperandHelper(dst, src);
479 } 479 }
480 480
481 public final void cmpb(CiAddress dst, int imm8) { 481 public final void cmpb(Address dst, int imm8) {
482 prefix(dst); 482 prefix(dst);
483 emitByte(0x80); 483 emitByte(0x80);
484 emitOperandHelper(rdi, dst); 484 emitOperandHelper(rdi, dst);
485 emitByte(imm8); 485 emitByte(imm8);
486 } 486 }
487 487
488 public final void cmpl(CiAddress dst, int imm32) { 488 public final void cmpl(Address dst, int imm32) {
489 prefix(dst); 489 prefix(dst);
490 emitByte(0x81); 490 emitByte(0x81);
491 emitOperandHelper(rdi, dst); 491 emitOperandHelper(rdi, dst);
492 emitInt(imm32); 492 emitInt(imm32);
493 } 493 }
494 494
495 public final void cmpl(CiRegister dst, int imm32) { 495 public final void cmpl(Register dst, int imm32) {
496 prefix(dst); 496 prefix(dst);
497 emitArith(0x81, 0xF8, dst, imm32); 497 emitArith(0x81, 0xF8, dst, imm32);
498 } 498 }
499 499
500 public final void cmpl(CiRegister dst, CiRegister src) { 500 public final void cmpl(Register dst, Register src) {
501 prefixAndEncode(dst.encoding, src.encoding); 501 prefixAndEncode(dst.encoding, src.encoding);
502 emitArith(0x3B, 0xC0, dst, src); 502 emitArith(0x3B, 0xC0, dst, src);
503 } 503 }
504 504
505 public final void cmpl(CiRegister dst, CiAddress src) { 505 public final void cmpl(Register dst, Address src) {
506 prefix(src, dst); 506 prefix(src, dst);
507 emitByte(0x3B); 507 emitByte(0x3B);
508 emitOperandHelper(dst, src); 508 emitOperandHelper(dst, src);
509 } 509 }
510 510
511 // The 32-bit cmpxchg compares the value at adr with the contents of X86.rax, 511 // The 32-bit cmpxchg compares the value at adr with the contents of X86.rax,
512 // and stores reg into adr if so; otherwise, the value at adr is loaded into X86.rax,. 512 // and stores reg into adr if so; otherwise, the value at adr is loaded into X86.rax,.
513 // The ZF is set if the compared values were equal, and cleared otherwise. 513 // The ZF is set if the compared values were equal, and cleared otherwise.
514 public final void cmpxchgl(CiRegister reg, CiAddress adr) { // cmpxchg 514 public final void cmpxchgl(Register reg, Address adr) { // cmpxchg
515 if ((AsmOptions.Atomics & 2) != 0) { 515 if ((AsmOptions.Atomics & 2) != 0) {
516 // caveat: no instructionmark, so this isn't relocatable. 516 // caveat: no instructionmark, so this isn't relocatable.
517 // Emit a synthetic, non-atomic, CAS equivalent. 517 // Emit a synthetic, non-atomic, CAS equivalent.
518 // Beware. The synthetic form sets all ICCs, not just ZF. 518 // Beware. The synthetic form sets all ICCs, not just ZF.
519 // cmpxchg r,[m] is equivalent to X86.rax, = CAS (m, X86.rax, r) 519 // cmpxchg r,[m] is equivalent to X86.rax, = CAS (m, X86.rax, r)
532 emitByte(0xB1); 532 emitByte(0xB1);
533 emitOperandHelper(reg, adr); 533 emitOperandHelper(reg, adr);
534 } 534 }
535 } 535 }
536 536
537 public final void comisd(CiRegister dst, CiAddress src) { 537 public final void comisd(Register dst, Address src) {
538 assert dst.isFpu(); 538 assert dst.isFpu();
539 // NOTE: dbx seems to decode this as comiss even though the 539 // NOTE: dbx seems to decode this as comiss even though the
540 // 0x66 is there. Strangly ucomisd comes out correct 540 // 0x66 is there. Strangly ucomisd comes out correct
541 emitByte(0x66); 541 emitByte(0x66);
542 comiss(dst, src); 542 comiss(dst, src);
543 } 543 }
544 544
545 public final void comiss(CiRegister dst, CiAddress src) { 545 public final void comiss(Register dst, Address src) {
546 assert dst.isFpu(); 546 assert dst.isFpu();
547 547
548 prefix(src, dst); 548 prefix(src, dst);
549 emitByte(0x0F); 549 emitByte(0x0F);
550 emitByte(0x2F); 550 emitByte(0x2F);
551 emitOperandHelper(dst, src); 551 emitOperandHelper(dst, src);
552 } 552 }
553 553
554 public final void cvtdq2pd(CiRegister dst, CiRegister src) { 554 public final void cvtdq2pd(Register dst, Register src) {
555 assert dst.isFpu(); 555 assert dst.isFpu();
556 assert src.isFpu(); 556 assert src.isFpu();
557 557
558 emitByte(0xF3); 558 emitByte(0xF3);
559 int encode = prefixAndEncode(dst.encoding, src.encoding); 559 int encode = prefixAndEncode(dst.encoding, src.encoding);
560 emitByte(0x0F); 560 emitByte(0x0F);
561 emitByte(0xE6); 561 emitByte(0xE6);
562 emitByte(0xC0 | encode); 562 emitByte(0xC0 | encode);
563 } 563 }
564 564
565 public final void cvtdq2ps(CiRegister dst, CiRegister src) { 565 public final void cvtdq2ps(Register dst, Register src) {
566 assert dst.isFpu(); 566 assert dst.isFpu();
567 assert src.isFpu(); 567 assert src.isFpu();
568 int encode = prefixAndEncode(dst.encoding, src.encoding); 568 int encode = prefixAndEncode(dst.encoding, src.encoding);
569 emitByte(0x0F); 569 emitByte(0x0F);
570 emitByte(0x5B); 570 emitByte(0x5B);
571 emitByte(0xC0 | encode); 571 emitByte(0xC0 | encode);
572 } 572 }
573 573
574 public final void cvtsd2ss(CiRegister dst, CiRegister src) { 574 public final void cvtsd2ss(Register dst, Register src) {
575 assert dst.isFpu(); 575 assert dst.isFpu();
576 assert src.isFpu(); 576 assert src.isFpu();
577 emitByte(0xF2); 577 emitByte(0xF2);
578 int encode = prefixAndEncode(dst.encoding, src.encoding); 578 int encode = prefixAndEncode(dst.encoding, src.encoding);
579 emitByte(0x0F); 579 emitByte(0x0F);
580 emitByte(0x5A); 580 emitByte(0x5A);
581 emitByte(0xC0 | encode); 581 emitByte(0xC0 | encode);
582 } 582 }
583 583
584 public final void cvtsi2sdl(CiRegister dst, CiRegister src) { 584 public final void cvtsi2sdl(Register dst, Register src) {
585 assert dst.isFpu(); 585 assert dst.isFpu();
586 emitByte(0xF2); 586 emitByte(0xF2);
587 int encode = prefixAndEncode(dst.encoding, src.encoding); 587 int encode = prefixAndEncode(dst.encoding, src.encoding);
588 emitByte(0x0F); 588 emitByte(0x0F);
589 emitByte(0x2A); 589 emitByte(0x2A);
590 emitByte(0xC0 | encode); 590 emitByte(0xC0 | encode);
591 } 591 }
592 592
593 public final void cvtsi2ssl(CiRegister dst, CiRegister src) { 593 public final void cvtsi2ssl(Register dst, Register src) {
594 assert dst.isFpu(); 594 assert dst.isFpu();
595 emitByte(0xF3); 595 emitByte(0xF3);
596 int encode = prefixAndEncode(dst.encoding, src.encoding); 596 int encode = prefixAndEncode(dst.encoding, src.encoding);
597 emitByte(0x0F); 597 emitByte(0x0F);
598 emitByte(0x2A); 598 emitByte(0x2A);
599 emitByte(0xC0 | encode); 599 emitByte(0xC0 | encode);
600 } 600 }
601 601
602 public final void cvtss2sd(CiRegister dst, CiRegister src) { 602 public final void cvtss2sd(Register dst, Register src) {
603 assert dst.isFpu(); 603 assert dst.isFpu();
604 assert src.isFpu(); 604 assert src.isFpu();
605 emitByte(0xF3); 605 emitByte(0xF3);
606 int encode = prefixAndEncode(dst.encoding, src.encoding); 606 int encode = prefixAndEncode(dst.encoding, src.encoding);
607 emitByte(0x0F); 607 emitByte(0x0F);
608 emitByte(0x5A); 608 emitByte(0x5A);
609 emitByte(0xC0 | encode); 609 emitByte(0xC0 | encode);
610 } 610 }
611 611
612 public final void cvttsd2sil(CiRegister dst, CiRegister src) { 612 public final void cvttsd2sil(Register dst, Register src) {
613 assert src.isFpu(); 613 assert src.isFpu();
614 emitByte(0xF2); 614 emitByte(0xF2);
615 int encode = prefixAndEncode(dst.encoding, src.encoding); 615 int encode = prefixAndEncode(dst.encoding, src.encoding);
616 emitByte(0x0F); 616 emitByte(0x0F);
617 emitByte(0x2C); 617 emitByte(0x2C);
618 emitByte(0xC0 | encode); 618 emitByte(0xC0 | encode);
619 } 619 }
620 620
621 public final void cvttss2sil(CiRegister dst, CiRegister src) { 621 public final void cvttss2sil(Register dst, Register src) {
622 assert src.isFpu(); 622 assert src.isFpu();
623 emitByte(0xF3); 623 emitByte(0xF3);
624 int encode = prefixAndEncode(dst.encoding, src.encoding); 624 int encode = prefixAndEncode(dst.encoding, src.encoding);
625 emitByte(0x0F); 625 emitByte(0x0F);
626 emitByte(0x2C); 626 emitByte(0x2C);
627 emitByte(0xC0 | encode); 627 emitByte(0xC0 | encode);
628 } 628 }
629 629
630 public final void decl(CiAddress dst) { 630 public final void decl(Address dst) {
631 // Don't use it directly. Use Macrodecrement() instead. 631 // Don't use it directly. Use Macrodecrement() instead.
632 prefix(dst); 632 prefix(dst);
633 emitByte(0xFF); 633 emitByte(0xFF);
634 emitOperandHelper(rcx, dst); 634 emitOperandHelper(rcx, dst);
635 } 635 }
636 636
637 public final void divsd(CiRegister dst, CiAddress src) { 637 public final void divsd(Register dst, Address src) {
638 assert dst.isFpu(); 638 assert dst.isFpu();
639 emitByte(0xF2); 639 emitByte(0xF2);
640 prefix(src, dst); 640 prefix(src, dst);
641 emitByte(0x0F); 641 emitByte(0x0F);
642 emitByte(0x5E); 642 emitByte(0x5E);
643 emitOperandHelper(dst, src); 643 emitOperandHelper(dst, src);
644 } 644 }
645 645
646 public final void divsd(CiRegister dst, CiRegister src) { 646 public final void divsd(Register dst, Register src) {
647 assert dst.isFpu(); 647 assert dst.isFpu();
648 assert src.isFpu(); 648 assert src.isFpu();
649 emitByte(0xF2); 649 emitByte(0xF2);
650 int encode = prefixAndEncode(dst.encoding, src.encoding); 650 int encode = prefixAndEncode(dst.encoding, src.encoding);
651 emitByte(0x0F); 651 emitByte(0x0F);
652 emitByte(0x5E); 652 emitByte(0x5E);
653 emitByte(0xC0 | encode); 653 emitByte(0xC0 | encode);
654 } 654 }
655 655
656 public final void divss(CiRegister dst, CiAddress src) { 656 public final void divss(Register dst, Address src) {
657 assert dst.isFpu(); 657 assert dst.isFpu();
658 emitByte(0xF3); 658 emitByte(0xF3);
659 prefix(src, dst); 659 prefix(src, dst);
660 emitByte(0x0F); 660 emitByte(0x0F);
661 emitByte(0x5E); 661 emitByte(0x5E);
662 emitOperandHelper(dst, src); 662 emitOperandHelper(dst, src);
663 } 663 }
664 664
665 public final void divss(CiRegister dst, CiRegister src) { 665 public final void divss(Register dst, Register src) {
666 assert dst.isFpu(); 666 assert dst.isFpu();
667 assert src.isFpu(); 667 assert src.isFpu();
668 emitByte(0xF3); 668 emitByte(0xF3);
669 int encode = prefixAndEncode(dst.encoding, src.encoding); 669 int encode = prefixAndEncode(dst.encoding, src.encoding);
670 emitByte(0x0F); 670 emitByte(0x0F);
674 674
675 public final void hlt() { 675 public final void hlt() {
676 emitByte(0xF4); 676 emitByte(0xF4);
677 } 677 }
678 678
679 public final void idivl(CiRegister src) { 679 public final void idivl(Register src) {
680 int encode = prefixAndEncode(src.encoding); 680 int encode = prefixAndEncode(src.encoding);
681 emitByte(0xF7); 681 emitByte(0xF7);
682 emitByte(0xF8 | encode); 682 emitByte(0xF8 | encode);
683 } 683 }
684 684
685 public final void divl(CiRegister src) { 685 public final void divl(Register src) {
686 int encode = prefixAndEncode(src.encoding); 686 int encode = prefixAndEncode(src.encoding);
687 emitByte(0xF7); 687 emitByte(0xF7);
688 emitByte(0xF0 | encode); 688 emitByte(0xF0 | encode);
689 } 689 }
690 690
691 public final void imull(CiRegister dst, CiRegister src) { 691 public final void imull(Register dst, Register src) {
692 int encode = prefixAndEncode(dst.encoding, src.encoding); 692 int encode = prefixAndEncode(dst.encoding, src.encoding);
693 emitByte(0x0F); 693 emitByte(0x0F);
694 emitByte(0xAF); 694 emitByte(0xAF);
695 emitByte(0xC0 | encode); 695 emitByte(0xC0 | encode);
696 } 696 }
697 697
698 public final void imull(CiRegister dst, CiRegister src, int value) { 698 public final void imull(Register dst, Register src, int value) {
699 int encode = prefixAndEncode(dst.encoding, src.encoding); 699 int encode = prefixAndEncode(dst.encoding, src.encoding);
700 if (isByte(value)) { 700 if (isByte(value)) {
701 emitByte(0x6B); 701 emitByte(0x6B);
702 emitByte(0xC0 | encode); 702 emitByte(0xC0 | encode);
703 emitByte(value & 0xFF); 703 emitByte(value & 0xFF);
706 emitByte(0xC0 | encode); 706 emitByte(0xC0 | encode);
707 emitInt(value); 707 emitInt(value);
708 } 708 }
709 } 709 }
710 710
711 public final void incl(CiAddress dst) { 711 public final void incl(Address dst) {
712 // Don't use it directly. Use Macroincrement() instead. 712 // Don't use it directly. Use Macroincrement() instead.
713 prefix(dst); 713 prefix(dst);
714 emitByte(0xFF); 714 emitByte(0xFF);
715 emitOperandHelper(rax, dst); 715 emitOperandHelper(rax, dst);
716 } 716 }
764 emitByte(0x70 | cc.value); 764 emitByte(0x70 | cc.value);
765 emitByte(0); 765 emitByte(0);
766 } 766 }
767 } 767 }
768 768
769 public final void jmp(CiAddress adr) { 769 public final void jmp(Address adr) {
770 prefix(adr); 770 prefix(adr);
771 emitByte(0xFF); 771 emitByte(0xFF);
772 emitOperandHelper(rsp, adr); 772 emitOperandHelper(rsp, adr);
773 } 773 }
774 774
799 emitByte(0xE9); 799 emitByte(0xE9);
800 emitInt(0); 800 emitInt(0);
801 } 801 }
802 } 802 }
803 803
804 public final void jmp(CiRegister entry) { 804 public final void jmp(Register entry) {
805 int encode = prefixAndEncode(entry.encoding); 805 int encode = prefixAndEncode(entry.encoding);
806 emitByte(0xFF); 806 emitByte(0xFF);
807 emitByte(0xE0 | encode); 807 emitByte(0xE0 | encode);
808 } 808 }
809 809
821 emitByte(0xEB); 821 emitByte(0xEB);
822 emitByte(0); 822 emitByte(0);
823 } 823 }
824 } 824 }
825 825
826 public final void leaq(CiRegister dst, CiAddress src) { 826 public final void leaq(Register dst, Address src) {
827 prefixq(src, dst); 827 prefixq(src, dst);
828 emitByte(0x8D); 828 emitByte(0x8D);
829 emitOperandHelper(dst, src); 829 emitOperandHelper(dst, src);
830 } 830 }
831 831
853 emitByte(0x0F); 853 emitByte(0x0F);
854 emitByte(0xAE); 854 emitByte(0xAE);
855 emitByte(0xF0); 855 emitByte(0xF0);
856 } 856 }
857 857
858 public final void mov(CiRegister dst, CiRegister src) { 858 public final void mov(Register dst, Register src) {
859 movq(dst, src); 859 movq(dst, src);
860 } 860 }
861 861
862 public final void movapd(CiRegister dst, CiRegister src) { 862 public final void movapd(Register dst, Register src) {
863 assert dst.isFpu(); 863 assert dst.isFpu();
864 assert src.isFpu(); 864 assert src.isFpu();
865 int dstenc = dst.encoding; 865 int dstenc = dst.encoding;
866 int srcenc = src.encoding; 866 int srcenc = src.encoding;
867 emitByte(0x66); 867 emitByte(0x66);
882 emitByte(0x0F); 882 emitByte(0x0F);
883 emitByte(0x28); 883 emitByte(0x28);
884 emitByte(0xC0 | dstenc << 3 | srcenc); 884 emitByte(0xC0 | dstenc << 3 | srcenc);
885 } 885 }
886 886
887 public final void movaps(CiRegister dst, CiRegister src) { 887 public final void movaps(Register dst, Register src) {
888 assert dst.isFpu(); 888 assert dst.isFpu();
889 assert src.isFpu(); 889 assert src.isFpu();
890 int dstenc = dst.encoding; 890 int dstenc = dst.encoding;
891 int srcenc = src.encoding; 891 int srcenc = src.encoding;
892 if (dstenc < 8) { 892 if (dstenc < 8) {
906 emitByte(0x0F); 906 emitByte(0x0F);
907 emitByte(0x28); 907 emitByte(0x28);
908 emitByte(0xC0 | dstenc << 3 | srcenc); 908 emitByte(0xC0 | dstenc << 3 | srcenc);
909 } 909 }
910 910
911 public final void movb(CiRegister dst, CiAddress src) { 911 public final void movb(Register dst, Address src) {
912 prefix(src, dst); // , true) 912 prefix(src, dst); // , true)
913 emitByte(0x8A); 913 emitByte(0x8A);
914 emitOperandHelper(dst, src); 914 emitOperandHelper(dst, src);
915 } 915 }
916 916
917 public final void movb(CiAddress dst, int imm8) { 917 public final void movb(Address dst, int imm8) {
918 prefix(dst); 918 prefix(dst);
919 emitByte(0xC6); 919 emitByte(0xC6);
920 emitOperandHelper(rax, dst); 920 emitOperandHelper(rax, dst);
921 emitByte(imm8); 921 emitByte(imm8);
922 } 922 }
923 923
924 public final void movb(CiAddress dst, CiRegister src) { 924 public final void movb(Address dst, Register src) {
925 assert src.isByte() : "must have byte register"; 925 assert src.isByte() : "must have byte register";
926 prefix(dst, src); // , true) 926 prefix(dst, src); // , true)
927 emitByte(0x88); 927 emitByte(0x88);
928 emitOperandHelper(src, dst); 928 emitOperandHelper(src, dst);
929 } 929 }
930 930
931 public final void movdl(CiRegister dst, CiRegister src) { 931 public final void movdl(Register dst, Register src) {
932 if (dst.isFpu()) { 932 if (dst.isFpu()) {
933 assert !src.isFpu() : "does this hold?"; 933 assert !src.isFpu() : "does this hold?";
934 emitByte(0x66); 934 emitByte(0x66);
935 int encode = prefixAndEncode(dst.encoding, src.encoding); 935 int encode = prefixAndEncode(dst.encoding, src.encoding);
936 emitByte(0x0F); 936 emitByte(0x0F);
945 emitByte(0x7E); 945 emitByte(0x7E);
946 emitByte(0xC0 | encode); 946 emitByte(0xC0 | encode);
947 } 947 }
948 } 948 }
949 949
950 public final void movdqa(CiRegister dst, CiAddress src) { 950 public final void movdqa(Register dst, Address src) {
951 assert dst.isFpu(); 951 assert dst.isFpu();
952 emitByte(0x66); 952 emitByte(0x66);
953 prefix(src, dst); 953 prefix(src, dst);
954 emitByte(0x0F); 954 emitByte(0x0F);
955 emitByte(0x6F); 955 emitByte(0x6F);
956 emitOperandHelper(dst, src); 956 emitOperandHelper(dst, src);
957 } 957 }
958 958
959 public final void movdqa(CiRegister dst, CiRegister src) { 959 public final void movdqa(Register dst, Register src) {
960 assert dst.isFpu(); 960 assert dst.isFpu();
961 emitByte(0x66); 961 emitByte(0x66);
962 int encode = prefixqAndEncode(dst.encoding, src.encoding); 962 int encode = prefixqAndEncode(dst.encoding, src.encoding);
963 emitByte(0x0F); 963 emitByte(0x0F);
964 emitByte(0x6F); 964 emitByte(0x6F);
965 emitByte(0xC0 | encode); 965 emitByte(0xC0 | encode);
966 } 966 }
967 967
968 public final void movdqa(CiAddress dst, CiRegister src) { 968 public final void movdqa(Address dst, Register src) {
969 assert src.isFpu(); 969 assert src.isFpu();
970 emitByte(0x66); 970 emitByte(0x66);
971 prefix(dst, src); 971 prefix(dst, src);
972 emitByte(0x0F); 972 emitByte(0x0F);
973 emitByte(0x7F); 973 emitByte(0x7F);
974 emitOperandHelper(src, dst); 974 emitOperandHelper(src, dst);
975 } 975 }
976 976
977 public final void movdqu(CiRegister dst, CiAddress src) { 977 public final void movdqu(Register dst, Address src) {
978 assert dst.isFpu(); 978 assert dst.isFpu();
979 emitByte(0xF3); 979 emitByte(0xF3);
980 prefix(src, dst); 980 prefix(src, dst);
981 emitByte(0x0F); 981 emitByte(0x0F);
982 emitByte(0x6F); 982 emitByte(0x6F);
983 emitOperandHelper(dst, src); 983 emitOperandHelper(dst, src);
984 } 984 }
985 985
986 public final void movdqu(CiRegister dst, CiRegister src) { 986 public final void movdqu(Register dst, Register src) {
987 assert dst.isFpu(); 987 assert dst.isFpu();
988 assert src.isFpu(); 988 assert src.isFpu();
989 989
990 emitByte(0xF3); 990 emitByte(0xF3);
991 int encode = prefixqAndEncode(dst.encoding, src.encoding); 991 int encode = prefixqAndEncode(dst.encoding, src.encoding);
992 emitByte(0x0F); 992 emitByte(0x0F);
993 emitByte(0x6F); 993 emitByte(0x6F);
994 emitByte(0xC0 | encode); 994 emitByte(0xC0 | encode);
995 } 995 }
996 996
997 public final void movdqu(CiAddress dst, CiRegister src) { 997 public final void movdqu(Address dst, Register src) {
998 assert src.isFpu(); 998 assert src.isFpu();
999 999
1000 emitByte(0xF3); 1000 emitByte(0xF3);
1001 prefix(dst, src); 1001 prefix(dst, src);
1002 emitByte(0x0F); 1002 emitByte(0x0F);
1003 emitByte(0x7F); 1003 emitByte(0x7F);
1004 emitOperandHelper(src, dst); 1004 emitOperandHelper(src, dst);
1005 } 1005 }
1006 1006
1007 public final void movl(CiRegister dst, int imm32) { 1007 public final void movl(Register dst, int imm32) {
1008 int encode = prefixAndEncode(dst.encoding); 1008 int encode = prefixAndEncode(dst.encoding);
1009 emitByte(0xB8 | encode); 1009 emitByte(0xB8 | encode);
1010 emitInt(imm32); 1010 emitInt(imm32);
1011 } 1011 }
1012 1012
1013 public final void movl(CiRegister dst, CiRegister src) { 1013 public final void movl(Register dst, Register src) {
1014 int encode = prefixAndEncode(dst.encoding, src.encoding); 1014 int encode = prefixAndEncode(dst.encoding, src.encoding);
1015 emitByte(0x8B); 1015 emitByte(0x8B);
1016 emitByte(0xC0 | encode); 1016 emitByte(0xC0 | encode);
1017 } 1017 }
1018 1018
1019 public final void movl(CiRegister dst, CiAddress src) { 1019 public final void movl(Register dst, Address src) {
1020 prefix(src, dst); 1020 prefix(src, dst);
1021 emitByte(0x8B); 1021 emitByte(0x8B);
1022 emitOperandHelper(dst, src); 1022 emitOperandHelper(dst, src);
1023 } 1023 }
1024 1024
1025 public final void movl(CiAddress dst, int imm32) { 1025 public final void movl(Address dst, int imm32) {
1026 prefix(dst); 1026 prefix(dst);
1027 emitByte(0xC7); 1027 emitByte(0xC7);
1028 emitOperandHelper(rax, dst); 1028 emitOperandHelper(rax, dst);
1029 emitInt(imm32); 1029 emitInt(imm32);
1030 } 1030 }
1031 1031
1032 public final void movl(CiAddress dst, CiRegister src) { 1032 public final void movl(Address dst, Register src) {
1033 prefix(dst, src); 1033 prefix(dst, src);
1034 emitByte(0x89); 1034 emitByte(0x89);
1035 emitOperandHelper(src, dst); 1035 emitOperandHelper(src, dst);
1036 } 1036 }
1037 1037
1038 /** 1038 /**
1039 * New CPUs require use of movsd and movss to avoid partial register stall 1039 * New CPUs require use of movsd and movss to avoid partial register stall
1040 * when loading from memory. But for old Opteron use movlpd instead of movsd. 1040 * when loading from memory. But for old Opteron use movlpd instead of movsd.
1041 * The selection is done in {@link AMD64MacroAssembler#movdbl(CiRegister, CiAddress)} 1041 * The selection is done in {@link AMD64MacroAssembler#movdbl(Register, Address)}
1042 * and {@link AMD64MacroAssembler#movflt(CiRegister, CiRegister)}. 1042 * and {@link AMD64MacroAssembler#movflt(Register, Register)}.
1043 */ 1043 */
1044 public final void movlpd(CiRegister dst, CiAddress src) { 1044 public final void movlpd(Register dst, Address src) {
1045 assert dst.isFpu(); 1045 assert dst.isFpu();
1046 emitByte(0x66); 1046 emitByte(0x66);
1047 prefix(src, dst); 1047 prefix(src, dst);
1048 emitByte(0x0F); 1048 emitByte(0x0F);
1049 emitByte(0x12); 1049 emitByte(0x12);
1050 emitOperandHelper(dst, src); 1050 emitOperandHelper(dst, src);
1051 } 1051 }
1052 1052
1053 public final void movlpd(CiAddress dst, CiRegister src) { 1053 public final void movlpd(Address dst, Register src) {
1054 assert src.isFpu(); 1054 assert src.isFpu();
1055 emitByte(0x66); 1055 emitByte(0x66);
1056 prefix(dst, src); 1056 prefix(dst, src);
1057 emitByte(0x0F); 1057 emitByte(0x0F);
1058 emitByte(0x13); 1058 emitByte(0x13);
1059 emitOperandHelper(src, dst); 1059 emitOperandHelper(src, dst);
1060 } 1060 }
1061 1061
1062 public final void movq(CiRegister dst, CiAddress src) { 1062 public final void movq(Register dst, Address src) {
1063 if (dst.isFpu()) { 1063 if (dst.isFpu()) {
1064 emitByte(0xF3); 1064 emitByte(0xF3);
1065 prefixq(src, dst); 1065 prefixq(src, dst);
1066 emitByte(0x0F); 1066 emitByte(0x0F);
1067 emitByte(0x7E); 1067 emitByte(0x7E);
1071 emitByte(0x8B); 1071 emitByte(0x8B);
1072 emitOperandHelper(dst, src); 1072 emitOperandHelper(dst, src);
1073 } 1073 }
1074 } 1074 }
1075 1075
1076 public final void movq(CiRegister dst, CiRegister src) { 1076 public final void movq(Register dst, Register src) {
1077 int encode = prefixqAndEncode(dst.encoding, src.encoding); 1077 int encode = prefixqAndEncode(dst.encoding, src.encoding);
1078 emitByte(0x8B); 1078 emitByte(0x8B);
1079 emitByte(0xC0 | encode); 1079 emitByte(0xC0 | encode);
1080 } 1080 }
1081 1081
1082 public final void movq(CiAddress dst, CiRegister src) { 1082 public final void movq(Address dst, Register src) {
1083 if (src.isFpu()) { 1083 if (src.isFpu()) {
1084 emitByte(0x66); 1084 emitByte(0x66);
1085 prefixq(dst, src); 1085 prefixq(dst, src);
1086 emitByte(0x0F); 1086 emitByte(0x0F);
1087 emitByte(0xD6); 1087 emitByte(0xD6);
1091 emitByte(0x89); 1091 emitByte(0x89);
1092 emitOperandHelper(src, dst); 1092 emitOperandHelper(src, dst);
1093 } 1093 }
1094 } 1094 }
1095 1095
1096 public final void movsxb(CiRegister dst, CiAddress src) { // movsxb 1096 public final void movsxb(Register dst, Address src) { // movsxb
1097 prefix(src, dst); 1097 prefix(src, dst);
1098 emitByte(0x0F); 1098 emitByte(0x0F);
1099 emitByte(0xBE); 1099 emitByte(0xBE);
1100 emitOperandHelper(dst, src); 1100 emitOperandHelper(dst, src);
1101 } 1101 }
1102 1102
1103 public final void movsxb(CiRegister dst, CiRegister src) { // movsxb 1103 public final void movsxb(Register dst, Register src) { // movsxb
1104 int encode = prefixAndEncode(dst.encoding, src.encoding, true); 1104 int encode = prefixAndEncode(dst.encoding, src.encoding, true);
1105 emitByte(0x0F); 1105 emitByte(0x0F);
1106 emitByte(0xBE); 1106 emitByte(0xBE);
1107 emitByte(0xC0 | encode); 1107 emitByte(0xC0 | encode);
1108 } 1108 }
1109 1109
1110 public final void movsd(CiRegister dst, CiRegister src) { 1110 public final void movsd(Register dst, Register src) {
1111 assert dst.isFpu(); 1111 assert dst.isFpu();
1112 assert src.isFpu(); 1112 assert src.isFpu();
1113 emitByte(0xF2); 1113 emitByte(0xF2);
1114 int encode = prefixAndEncode(dst.encoding, src.encoding); 1114 int encode = prefixAndEncode(dst.encoding, src.encoding);
1115 emitByte(0x0F); 1115 emitByte(0x0F);
1116 emitByte(0x10); 1116 emitByte(0x10);
1117 emitByte(0xC0 | encode); 1117 emitByte(0xC0 | encode);
1118 } 1118 }
1119 1119
1120 public final void movsd(CiRegister dst, CiAddress src) { 1120 public final void movsd(Register dst, Address src) {
1121 assert dst.isFpu(); 1121 assert dst.isFpu();
1122 emitByte(0xF2); 1122 emitByte(0xF2);
1123 prefix(src, dst); 1123 prefix(src, dst);
1124 emitByte(0x0F); 1124 emitByte(0x0F);
1125 emitByte(0x10); 1125 emitByte(0x10);
1126 emitOperandHelper(dst, src); 1126 emitOperandHelper(dst, src);
1127 } 1127 }
1128 1128
1129 public final void movsd(CiAddress dst, CiRegister src) { 1129 public final void movsd(Address dst, Register src) {
1130 assert src.isFpu(); 1130 assert src.isFpu();
1131 emitByte(0xF2); 1131 emitByte(0xF2);
1132 prefix(dst, src); 1132 prefix(dst, src);
1133 emitByte(0x0F); 1133 emitByte(0x0F);
1134 emitByte(0x11); 1134 emitByte(0x11);
1135 emitOperandHelper(src, dst); 1135 emitOperandHelper(src, dst);
1136 } 1136 }
1137 1137
1138 public final void movss(CiRegister dst, CiRegister src) { 1138 public final void movss(Register dst, Register src) {
1139 assert dst.isFpu(); 1139 assert dst.isFpu();
1140 assert src.isFpu(); 1140 assert src.isFpu();
1141 emitByte(0xF3); 1141 emitByte(0xF3);
1142 int encode = prefixAndEncode(dst.encoding, src.encoding); 1142 int encode = prefixAndEncode(dst.encoding, src.encoding);
1143 emitByte(0x0F); 1143 emitByte(0x0F);
1144 emitByte(0x10); 1144 emitByte(0x10);
1145 emitByte(0xC0 | encode); 1145 emitByte(0xC0 | encode);
1146 } 1146 }
1147 1147
1148 public final void movss(CiRegister dst, CiAddress src) { 1148 public final void movss(Register dst, Address src) {
1149 assert dst.isFpu(); 1149 assert dst.isFpu();
1150 emitByte(0xF3); 1150 emitByte(0xF3);
1151 prefix(src, dst); 1151 prefix(src, dst);
1152 emitByte(0x0F); 1152 emitByte(0x0F);
1153 emitByte(0x10); 1153 emitByte(0x10);
1154 emitOperandHelper(dst, src); 1154 emitOperandHelper(dst, src);
1155 } 1155 }
1156 1156
1157 public final void movss(CiAddress dst, CiRegister src) { 1157 public final void movss(Address dst, Register src) {
1158 assert src.isFpu(); 1158 assert src.isFpu();
1159 emitByte(0xF3); 1159 emitByte(0xF3);
1160 prefix(dst, src); 1160 prefix(dst, src);
1161 emitByte(0x0F); 1161 emitByte(0x0F);
1162 emitByte(0x11); 1162 emitByte(0x11);
1163 emitOperandHelper(src, dst); 1163 emitOperandHelper(src, dst);
1164 } 1164 }
1165 1165
1166 public final void movswl(CiRegister dst, CiAddress src) { 1166 public final void movswl(Register dst, Address src) {
1167 prefix(src, dst); 1167 prefix(src, dst);
1168 emitByte(0x0F); 1168 emitByte(0x0F);
1169 emitByte(0xBF); 1169 emitByte(0xBF);
1170 emitOperandHelper(dst, src); 1170 emitOperandHelper(dst, src);
1171 } 1171 }
1172 1172
1173 public final void movsxw(CiRegister dst, CiRegister src) { // movsxw 1173 public final void movsxw(Register dst, Register src) { // movsxw
1174 int encode = prefixAndEncode(dst.encoding, src.encoding); 1174 int encode = prefixAndEncode(dst.encoding, src.encoding);
1175 emitByte(0x0F); 1175 emitByte(0x0F);
1176 emitByte(0xBF); 1176 emitByte(0xBF);
1177 emitByte(0xC0 | encode); 1177 emitByte(0xC0 | encode);
1178 } 1178 }
1179 1179
1180 public final void movsxw(CiRegister dst, CiAddress src) { // movsxw 1180 public final void movsxw(Register dst, Address src) { // movsxw
1181 prefix(src, dst); 1181 prefix(src, dst);
1182 emitByte(0x0F); 1182 emitByte(0x0F);
1183 emitByte(0xBF); 1183 emitByte(0xBF);
1184 emitOperandHelper(dst, src); 1184 emitOperandHelper(dst, src);
1185 } 1185 }
1186 1186
1187 public final void movzxd(CiRegister dst, CiRegister src) { // movzxd 1187 public final void movzxd(Register dst, Register src) { // movzxd
1188 int encode = prefixAndEncode(dst.encoding, src.encoding); 1188 int encode = prefixAndEncode(dst.encoding, src.encoding);
1189 emitByte(0x63); 1189 emitByte(0x63);
1190 emitByte(0xC0 | encode); 1190 emitByte(0xC0 | encode);
1191 } 1191 }
1192 1192
1193 public final void movzxd(CiRegister dst, CiAddress src) { // movzxd 1193 public final void movzxd(Register dst, Address src) { // movzxd
1194 prefix(src, dst); 1194 prefix(src, dst);
1195 emitByte(0x63); 1195 emitByte(0x63);
1196 emitOperandHelper(dst, src); 1196 emitOperandHelper(dst, src);
1197 } 1197 }
1198 1198
1199 public final void movw(CiAddress dst, int imm16) { 1199 public final void movw(Address dst, int imm16) {
1200 emitByte(0x66); // switch to 16-bit mode 1200 emitByte(0x66); // switch to 16-bit mode
1201 prefix(dst); 1201 prefix(dst);
1202 emitByte(0xC7); 1202 emitByte(0xC7);
1203 emitOperandHelper(rax, dst); 1203 emitOperandHelper(rax, dst);
1204 emitShort(imm16); 1204 emitShort(imm16);
1205 } 1205 }
1206 1206
1207 public final void movw(CiRegister dst, CiAddress src) { 1207 public final void movw(Register dst, Address src) {
1208 emitByte(0x66); 1208 emitByte(0x66);
1209 prefix(src, dst); 1209 prefix(src, dst);
1210 emitByte(0x8B); 1210 emitByte(0x8B);
1211 emitOperandHelper(dst, src); 1211 emitOperandHelper(dst, src);
1212 } 1212 }
1213 1213
1214 public final void movw(CiAddress dst, CiRegister src) { 1214 public final void movw(Address dst, Register src) {
1215 emitByte(0x66); 1215 emitByte(0x66);
1216 prefix(dst, src); 1216 prefix(dst, src);
1217 emitByte(0x89); 1217 emitByte(0x89);
1218 emitOperandHelper(src, dst); 1218 emitOperandHelper(src, dst);
1219 } 1219 }
1220 1220
1221 public final void movzxb(CiRegister dst, CiAddress src) { // movzxb 1221 public final void movzxb(Register dst, Address src) { // movzxb
1222 prefix(src, dst); 1222 prefix(src, dst);
1223 emitByte(0x0F); 1223 emitByte(0x0F);
1224 emitByte(0xB6); 1224 emitByte(0xB6);
1225 emitOperandHelper(dst, src); 1225 emitOperandHelper(dst, src);
1226 } 1226 }
1227 1227
1228 public final void movzxb(CiRegister dst, CiRegister src) { // movzxb 1228 public final void movzxb(Register dst, Register src) { // movzxb
1229 int encode = prefixAndEncode(dst.encoding, src.encoding, true); 1229 int encode = prefixAndEncode(dst.encoding, src.encoding, true);
1230 emitByte(0x0F); 1230 emitByte(0x0F);
1231 emitByte(0xB6); 1231 emitByte(0xB6);
1232 emitByte(0xC0 | encode); 1232 emitByte(0xC0 | encode);
1233 } 1233 }
1234 1234
1235 public final void movzxl(CiRegister dst, CiAddress src) { // movzxw 1235 public final void movzxl(Register dst, Address src) { // movzxw
1236 prefix(src, dst); 1236 prefix(src, dst);
1237 emitByte(0x0F); 1237 emitByte(0x0F);
1238 emitByte(0xB7); 1238 emitByte(0xB7);
1239 emitOperandHelper(dst, src); 1239 emitOperandHelper(dst, src);
1240 } 1240 }
1241 1241
1242 public final void movzxl(CiRegister dst, CiRegister src) { // movzxw 1242 public final void movzxl(Register dst, Register src) { // movzxw
1243 int encode = prefixAndEncode(dst.encoding, src.encoding); 1243 int encode = prefixAndEncode(dst.encoding, src.encoding);
1244 emitByte(0x0F); 1244 emitByte(0x0F);
1245 emitByte(0xB7); 1245 emitByte(0xB7);
1246 emitByte(0xC0 | encode); 1246 emitByte(0xC0 | encode);
1247 } 1247 }
1248 1248
1249 public final void mull(CiAddress src) { 1249 public final void mull(Address src) {
1250 prefix(src); 1250 prefix(src);
1251 emitByte(0xF7); 1251 emitByte(0xF7);
1252 emitOperandHelper(rsp, src); 1252 emitOperandHelper(rsp, src);
1253 } 1253 }
1254 1254
1255 public final void mulsd(CiRegister dst, CiAddress src) { 1255 public final void mulsd(Register dst, Address src) {
1256 assert dst.isFpu(); 1256 assert dst.isFpu();
1257 emitByte(0xF2); 1257 emitByte(0xF2);
1258 prefix(src, dst); 1258 prefix(src, dst);
1259 emitByte(0x0F); 1259 emitByte(0x0F);
1260 emitByte(0x59); 1260 emitByte(0x59);
1261 emitOperandHelper(dst, src); 1261 emitOperandHelper(dst, src);
1262 } 1262 }
1263 1263
1264 public final void mulsd(CiRegister dst, CiRegister src) { 1264 public final void mulsd(Register dst, Register src) {
1265 assert dst.isFpu(); 1265 assert dst.isFpu();
1266 assert src.isFpu(); 1266 assert src.isFpu();
1267 1267
1268 emitByte(0xF2); 1268 emitByte(0xF2);
1269 int encode = prefixAndEncode(dst.encoding, src.encoding); 1269 int encode = prefixAndEncode(dst.encoding, src.encoding);
1270 emitByte(0x0F); 1270 emitByte(0x0F);
1271 emitByte(0x59); 1271 emitByte(0x59);
1272 emitByte(0xC0 | encode); 1272 emitByte(0xC0 | encode);
1273 } 1273 }
1274 1274
1275 public final void mulss(CiRegister dst, CiAddress src) { 1275 public final void mulss(Register dst, Address src) {
1276 assert dst.isFpu(); 1276 assert dst.isFpu();
1277 1277
1278 emitByte(0xF3); 1278 emitByte(0xF3);
1279 prefix(src, dst); 1279 prefix(src, dst);
1280 emitByte(0x0F); 1280 emitByte(0x0F);
1281 emitByte(0x59); 1281 emitByte(0x59);
1282 emitOperandHelper(dst, src); 1282 emitOperandHelper(dst, src);
1283 } 1283 }
1284 1284
1285 public final void mulss(CiRegister dst, CiRegister src) { 1285 public final void mulss(Register dst, Register src) {
1286 assert dst.isFpu(); 1286 assert dst.isFpu();
1287 assert src.isFpu(); 1287 assert src.isFpu();
1288 emitByte(0xF3); 1288 emitByte(0xF3);
1289 int encode = prefixAndEncode(dst.encoding, src.encoding); 1289 int encode = prefixAndEncode(dst.encoding, src.encoding);
1290 emitByte(0x0F); 1290 emitByte(0x0F);
1291 emitByte(0x59); 1291 emitByte(0x59);
1292 emitByte(0xC0 | encode); 1292 emitByte(0xC0 | encode);
1293 } 1293 }
1294 1294
1295 public final void negl(CiRegister dst) { 1295 public final void negl(Register dst) {
1296 int encode = prefixAndEncode(dst.encoding); 1296 int encode = prefixAndEncode(dst.encoding);
1297 emitByte(0xF7); 1297 emitByte(0xF7);
1298 emitByte(0xD8 | encode); 1298 emitByte(0xD8 | encode);
1299 } 1299 }
1300 1300
1506 default: 1506 default:
1507 assert i == 0; 1507 assert i == 0;
1508 } 1508 }
1509 } 1509 }
1510 1510
1511 public final void notl(CiRegister dst) { 1511 public final void notl(Register dst) {
1512 int encode = prefixAndEncode(dst.encoding); 1512 int encode = prefixAndEncode(dst.encoding);
1513 emitByte(0xF7); 1513 emitByte(0xF7);
1514 emitByte(0xD0 | encode); 1514 emitByte(0xD0 | encode);
1515 } 1515 }
1516 1516
1517 public final void orl(CiAddress dst, int imm32) { 1517 public final void orl(Address dst, int imm32) {
1518 prefix(dst); 1518 prefix(dst);
1519 emitByte(0x81); 1519 emitByte(0x81);
1520 emitOperandHelper(rcx, dst); 1520 emitOperandHelper(rcx, dst);
1521 emitInt(imm32); 1521 emitInt(imm32);
1522 } 1522 }
1523 1523
1524 public final void orl(CiRegister dst, int imm32) { 1524 public final void orl(Register dst, int imm32) {
1525 prefix(dst); 1525 prefix(dst);
1526 emitArith(0x81, 0xC8, dst, imm32); 1526 emitArith(0x81, 0xC8, dst, imm32);
1527 } 1527 }
1528 1528
1529 public final void orl(CiRegister dst, CiAddress src) { 1529 public final void orl(Register dst, Address src) {
1530 prefix(src, dst); 1530 prefix(src, dst);
1531 emitByte(0x0B); 1531 emitByte(0x0B);
1532 emitOperandHelper(dst, src); 1532 emitOperandHelper(dst, src);
1533 } 1533 }
1534 1534
1535 public final void orl(CiRegister dst, CiRegister src) { 1535 public final void orl(Register dst, Register src) {
1536 prefixAndEncode(dst.encoding, src.encoding); 1536 prefixAndEncode(dst.encoding, src.encoding);
1537 emitArith(0x0B, 0xC0, dst, src); 1537 emitArith(0x0B, 0xC0, dst, src);
1538 } 1538 }
1539 1539
1540 // generic 1540 // generic
1541 public final void pop(CiRegister dst) { 1541 public final void pop(Register dst) {
1542 int encode = prefixAndEncode(dst.encoding); 1542 int encode = prefixAndEncode(dst.encoding);
1543 emitByte(0x58 | encode); 1543 emitByte(0x58 | encode);
1544 } 1544 }
1545 1545
1546 public final void prefetchPrefix(CiAddress src) { 1546 public final void prefetchPrefix(Address src) {
1547 prefix(src); 1547 prefix(src);
1548 emitByte(0x0F); 1548 emitByte(0x0F);
1549 } 1549 }
1550 1550
1551 public final void prefetchnta(CiAddress src) { 1551 public final void prefetchnta(Address src) {
1552 prefetchPrefix(src); 1552 prefetchPrefix(src);
1553 emitByte(0x18); 1553 emitByte(0x18);
1554 emitOperandHelper(rax, src); // 0, src 1554 emitOperandHelper(rax, src); // 0, src
1555 } 1555 }
1556 1556
1557 public final void prefetchr(CiAddress src) { 1557 public final void prefetchr(Address src) {
1558 prefetchPrefix(src); 1558 prefetchPrefix(src);
1559 emitByte(0x0D); 1559 emitByte(0x0D);
1560 emitOperandHelper(rax, src); // 0, src 1560 emitOperandHelper(rax, src); // 0, src
1561 } 1561 }
1562 1562
1563 public final void prefetcht0(CiAddress src) { 1563 public final void prefetcht0(Address src) {
1564 prefetchPrefix(src); 1564 prefetchPrefix(src);
1565 emitByte(0x18); 1565 emitByte(0x18);
1566 emitOperandHelper(rcx, src); // 1, src 1566 emitOperandHelper(rcx, src); // 1, src
1567 1567
1568 } 1568 }
1569 1569
1570 public final void prefetcht1(CiAddress src) { 1570 public final void prefetcht1(Address src) {
1571 prefetchPrefix(src); 1571 prefetchPrefix(src);
1572 emitByte(0x18); 1572 emitByte(0x18);
1573 emitOperandHelper(rdx, src); // 2, src 1573 emitOperandHelper(rdx, src); // 2, src
1574 } 1574 }
1575 1575
1576 public final void prefetcht2(CiAddress src) { 1576 public final void prefetcht2(Address src) {
1577 prefetchPrefix(src); 1577 prefetchPrefix(src);
1578 emitByte(0x18); 1578 emitByte(0x18);
1579 emitOperandHelper(rbx, src); // 3, src 1579 emitOperandHelper(rbx, src); // 3, src
1580 } 1580 }
1581 1581
1582 public final void prefetchw(CiAddress src) { 1582 public final void prefetchw(Address src) {
1583 prefetchPrefix(src); 1583 prefetchPrefix(src);
1584 emitByte(0x0D); 1584 emitByte(0x0D);
1585 emitOperandHelper(rcx, src); // 1, src 1585 emitOperandHelper(rcx, src); // 1, src
1586 } 1586 }
1587 1587
1588 public final void pshufd(CiRegister dst, CiRegister src, int mode) { 1588 public final void pshufd(Register dst, Register src, int mode) {
1589 assert dst.isFpu(); 1589 assert dst.isFpu();
1590 assert src.isFpu(); 1590 assert src.isFpu();
1591 assert isUByte(mode) : "invalid value"; 1591 assert isUByte(mode) : "invalid value";
1592 1592
1593 emitByte(0x66); 1593 emitByte(0x66);
1596 emitByte(0x70); 1596 emitByte(0x70);
1597 emitByte(0xC0 | encode); 1597 emitByte(0xC0 | encode);
1598 emitByte(mode & 0xFF); 1598 emitByte(mode & 0xFF);
1599 } 1599 }
1600 1600
1601 public final void pshufd(CiRegister dst, CiAddress src, int mode) { 1601 public final void pshufd(Register dst, Address src, int mode) {
1602 assert dst.isFpu(); 1602 assert dst.isFpu();
1603 assert isUByte(mode) : "invalid value"; 1603 assert isUByte(mode) : "invalid value";
1604 1604
1605 emitByte(0x66); 1605 emitByte(0x66);
1606 prefix(src, dst); 1606 prefix(src, dst);
1609 emitOperandHelper(dst, src); 1609 emitOperandHelper(dst, src);
1610 emitByte(mode & 0xFF); 1610 emitByte(mode & 0xFF);
1611 1611
1612 } 1612 }
1613 1613
1614 public final void pshuflw(CiRegister dst, CiRegister src, int mode) { 1614 public final void pshuflw(Register dst, Register src, int mode) {
1615 assert dst.isFpu(); 1615 assert dst.isFpu();
1616 assert src.isFpu(); 1616 assert src.isFpu();
1617 assert isUByte(mode) : "invalid value"; 1617 assert isUByte(mode) : "invalid value";
1618 1618
1619 emitByte(0xF2); 1619 emitByte(0xF2);
1622 emitByte(0x70); 1622 emitByte(0x70);
1623 emitByte(0xC0 | encode); 1623 emitByte(0xC0 | encode);
1624 emitByte(mode & 0xFF); 1624 emitByte(mode & 0xFF);
1625 } 1625 }
1626 1626
1627 public final void pshuflw(CiRegister dst, CiAddress src, int mode) { 1627 public final void pshuflw(Register dst, Address src, int mode) {
1628 assert dst.isFpu(); 1628 assert dst.isFpu();
1629 assert isUByte(mode) : "invalid value"; 1629 assert isUByte(mode) : "invalid value";
1630 1630
1631 emitByte(0xF2); 1631 emitByte(0xF2);
1632 prefix(src, dst); // QQ new 1632 prefix(src, dst); // QQ new
1634 emitByte(0x70); 1634 emitByte(0x70);
1635 emitOperandHelper(dst, src); 1635 emitOperandHelper(dst, src);
1636 emitByte(mode & 0xFF); 1636 emitByte(mode & 0xFF);
1637 } 1637 }
1638 1638
1639 public final void psrlq(CiRegister dst, int shift) { 1639 public final void psrlq(Register dst, int shift) {
1640 assert dst.isFpu(); 1640 assert dst.isFpu();
1641 // HMM Table D-1 says sse2 or mmx 1641 // HMM Table D-1 says sse2 or mmx
1642 1642
1643 int encode = prefixqAndEncode(xmm2.encoding, dst.encoding); 1643 int encode = prefixqAndEncode(xmm2.encoding, dst.encoding);
1644 emitByte(0x66); 1644 emitByte(0x66);
1646 emitByte(0x73); 1646 emitByte(0x73);
1647 emitByte(0xC0 | encode); 1647 emitByte(0xC0 | encode);
1648 emitByte(shift); 1648 emitByte(shift);
1649 } 1649 }
1650 1650
1651 public final void punpcklbw(CiRegister dst, CiRegister src) { 1651 public final void punpcklbw(Register dst, Register src) {
1652 assert dst.isFpu(); 1652 assert dst.isFpu();
1653 assert src.isFpu(); 1653 assert src.isFpu();
1654 emitByte(0x66); 1654 emitByte(0x66);
1655 int encode = prefixAndEncode(dst.encoding, src.encoding); 1655 int encode = prefixAndEncode(dst.encoding, src.encoding);
1656 emitByte(0x0F); 1656 emitByte(0x0F);
1663 // take a 32bit immediate 1663 // take a 32bit immediate
1664 emitByte(0x68); 1664 emitByte(0x68);
1665 emitInt(imm32); 1665 emitInt(imm32);
1666 } 1666 }
1667 1667
1668 public final void push(CiRegister src) { 1668 public final void push(Register src) {
1669 int encode = prefixAndEncode(src.encoding); 1669 int encode = prefixAndEncode(src.encoding);
1670 emitByte(0x50 | encode); 1670 emitByte(0x50 | encode);
1671 } 1671 }
1672 1672
1673 public final void pushf() { 1673 public final void pushf() {
1674 emitByte(0x9C); 1674 emitByte(0x9C);
1675 } 1675 }
1676 1676
1677 public final void pxor(CiRegister dst, CiAddress src) { 1677 public final void pxor(Register dst, Address src) {
1678 assert dst.isFpu(); 1678 assert dst.isFpu();
1679 1679
1680 emitByte(0x66); 1680 emitByte(0x66);
1681 prefix(src, dst); 1681 prefix(src, dst);
1682 emitByte(0x0F); 1682 emitByte(0x0F);
1683 emitByte(0xEF); 1683 emitByte(0xEF);
1684 emitOperandHelper(dst, src); 1684 emitOperandHelper(dst, src);
1685 } 1685 }
1686 1686
1687 public final void pxor(CiRegister dst, CiRegister src) { 1687 public final void pxor(Register dst, Register src) {
1688 assert dst.isFpu(); 1688 assert dst.isFpu();
1689 assert src.isFpu(); 1689 assert src.isFpu();
1690 1690
1691 emitByte(0x66); 1691 emitByte(0x66);
1692 int encode = prefixAndEncode(dst.encoding, src.encoding); 1692 int encode = prefixAndEncode(dst.encoding, src.encoding);
1694 emitByte(0xEF); 1694 emitByte(0xEF);
1695 emitByte(0xC0 | encode); 1695 emitByte(0xC0 | encode);
1696 1696
1697 } 1697 }
1698 1698
1699 public final void rcll(CiRegister dst, int imm8) { 1699 public final void rcll(Register dst, int imm8) {
1700 assert isShiftCount(imm8) : "illegal shift count"; 1700 assert isShiftCount(imm8) : "illegal shift count";
1701 int encode = prefixAndEncode(dst.encoding); 1701 int encode = prefixAndEncode(dst.encoding);
1702 if (imm8 == 1) { 1702 if (imm8 == 1) {
1703 emitByte(0xD1); 1703 emitByte(0xD1);
1704 emitByte(0xD0 | encode); 1704 emitByte(0xD0 | encode);
1761 emitByte(0xC2); 1761 emitByte(0xC2);
1762 emitShort(imm16); 1762 emitShort(imm16);
1763 } 1763 }
1764 } 1764 }
1765 1765
1766 public final void sarl(CiRegister dst, int imm8) { 1766 public final void sarl(Register dst, int imm8) {
1767 int encode = prefixAndEncode(dst.encoding); 1767 int encode = prefixAndEncode(dst.encoding);
1768 assert isShiftCount(imm8) : "illegal shift count"; 1768 assert isShiftCount(imm8) : "illegal shift count";
1769 if (imm8 == 1) { 1769 if (imm8 == 1) {
1770 emitByte(0xD1); 1770 emitByte(0xD1);
1771 emitByte(0xF8 | encode); 1771 emitByte(0xF8 | encode);
1774 emitByte(0xF8 | encode); 1774 emitByte(0xF8 | encode);
1775 emitByte(imm8); 1775 emitByte(imm8);
1776 } 1776 }
1777 } 1777 }
1778 1778
1779 public final void sarl(CiRegister dst) { 1779 public final void sarl(Register dst) {
1780 int encode = prefixAndEncode(dst.encoding); 1780 int encode = prefixAndEncode(dst.encoding);
1781 emitByte(0xD3); 1781 emitByte(0xD3);
1782 emitByte(0xF8 | encode); 1782 emitByte(0xF8 | encode);
1783 } 1783 }
1784 1784
1785 public final void sbbl(CiAddress dst, int imm32) { 1785 public final void sbbl(Address dst, int imm32) {
1786 prefix(dst); 1786 prefix(dst);
1787 emitArithOperand(0x81, rbx, dst, imm32); 1787 emitArithOperand(0x81, rbx, dst, imm32);
1788 } 1788 }
1789 1789
1790 public final void sbbl(CiRegister dst, int imm32) { 1790 public final void sbbl(Register dst, int imm32) {
1791 prefix(dst); 1791 prefix(dst);
1792 emitArith(0x81, 0xD8, dst, imm32); 1792 emitArith(0x81, 0xD8, dst, imm32);
1793 } 1793 }
1794 1794
1795 public final void sbbl(CiRegister dst, CiAddress src) { 1795 public final void sbbl(Register dst, Address src) {
1796 prefix(src, dst); 1796 prefix(src, dst);
1797 emitByte(0x1B); 1797 emitByte(0x1B);
1798 emitOperandHelper(dst, src); 1798 emitOperandHelper(dst, src);
1799 } 1799 }
1800 1800
1801 public final void sbbl(CiRegister dst, CiRegister src) { 1801 public final void sbbl(Register dst, Register src) {
1802 prefixAndEncode(dst.encoding, src.encoding); 1802 prefixAndEncode(dst.encoding, src.encoding);
1803 emitArith(0x1B, 0xC0, dst, src); 1803 emitArith(0x1B, 0xC0, dst, src);
1804 } 1804 }
1805 1805
1806 public final void setb(ConditionFlag cc, CiRegister dst) { 1806 public final void setb(ConditionFlag cc, Register dst) {
1807 assert 0 <= cc.value && cc.value < 16 : "illegal cc"; 1807 assert 0 <= cc.value && cc.value < 16 : "illegal cc";
1808 int encode = prefixAndEncode(dst.encoding, true); 1808 int encode = prefixAndEncode(dst.encoding, true);
1809 emitByte(0x0F); 1809 emitByte(0x0F);
1810 emitByte(0x90 | cc.value); 1810 emitByte(0x90 | cc.value);
1811 emitByte(0xC0 | encode); 1811 emitByte(0xC0 | encode);
1812 } 1812 }
1813 1813
1814 public final void shll(CiRegister dst, int imm8) { 1814 public final void shll(Register dst, int imm8) {
1815 assert isShiftCount(imm8) : "illegal shift count"; 1815 assert isShiftCount(imm8) : "illegal shift count";
1816 int encode = prefixAndEncode(dst.encoding); 1816 int encode = prefixAndEncode(dst.encoding);
1817 if (imm8 == 1) { 1817 if (imm8 == 1) {
1818 emitByte(0xD1); 1818 emitByte(0xD1);
1819 emitByte(0xE0 | encode); 1819 emitByte(0xE0 | encode);
1822 emitByte(0xE0 | encode); 1822 emitByte(0xE0 | encode);
1823 emitByte(imm8); 1823 emitByte(imm8);
1824 } 1824 }
1825 } 1825 }
1826 1826
1827 public final void shll(CiRegister dst) { 1827 public final void shll(Register dst) {
1828 int encode = prefixAndEncode(dst.encoding); 1828 int encode = prefixAndEncode(dst.encoding);
1829 emitByte(0xD3); 1829 emitByte(0xD3);
1830 emitByte(0xE0 | encode); 1830 emitByte(0xE0 | encode);
1831 } 1831 }
1832 1832
1833 public final void shrl(CiRegister dst, int imm8) { 1833 public final void shrl(Register dst, int imm8) {
1834 assert isShiftCount(imm8) : "illegal shift count"; 1834 assert isShiftCount(imm8) : "illegal shift count";
1835 int encode = prefixAndEncode(dst.encoding); 1835 int encode = prefixAndEncode(dst.encoding);
1836 emitByte(0xC1); 1836 emitByte(0xC1);
1837 emitByte(0xE8 | encode); 1837 emitByte(0xE8 | encode);
1838 emitByte(imm8); 1838 emitByte(imm8);
1839 } 1839 }
1840 1840
1841 public final void shrl(CiRegister dst) { 1841 public final void shrl(Register dst) {
1842 int encode = prefixAndEncode(dst.encoding); 1842 int encode = prefixAndEncode(dst.encoding);
1843 emitByte(0xD3); 1843 emitByte(0xD3);
1844 emitByte(0xE8 | encode); 1844 emitByte(0xE8 | encode);
1845 } 1845 }
1846 1846
1847 // copies a single word from [esi] to [edi] 1847 // copies a single word from [esi] to [edi]
1848 public final void smovl() { 1848 public final void smovl() {
1849 emitByte(0xA5); 1849 emitByte(0xA5);
1850 } 1850 }
1851 1851
1852 public final void sqrtsd(CiRegister dst, CiRegister src) { 1852 public final void sqrtsd(Register dst, Register src) {
1853 assert dst.isFpu(); 1853 assert dst.isFpu();
1854 assert src.isFpu(); 1854 assert src.isFpu();
1855 // HMM Table D-1 says sse2 1855 // HMM Table D-1 says sse2
1856 // assert is64 || target.supportsSSE(); 1856 // assert is64 || target.supportsSSE();
1857 emitByte(0xF2); 1857 emitByte(0xF2);
1859 emitByte(0x0F); 1859 emitByte(0x0F);
1860 emitByte(0x51); 1860 emitByte(0x51);
1861 emitByte(0xC0 | encode); 1861 emitByte(0xC0 | encode);
1862 } 1862 }
1863 1863
1864 public final void subl(CiAddress dst, int imm32) { 1864 public final void subl(Address dst, int imm32) {
1865 prefix(dst); 1865 prefix(dst);
1866 if (isByte(imm32)) { 1866 if (isByte(imm32)) {
1867 emitByte(0x83); 1867 emitByte(0x83);
1868 emitOperandHelper(rbp, dst); 1868 emitOperandHelper(rbp, dst);
1869 emitByte(imm32 & 0xFF); 1869 emitByte(imm32 & 0xFF);
1872 emitOperandHelper(rbp, dst); 1872 emitOperandHelper(rbp, dst);
1873 emitInt(imm32); 1873 emitInt(imm32);
1874 } 1874 }
1875 } 1875 }
1876 1876
1877 public final void subl(CiRegister dst, int imm32) { 1877 public final void subl(Register dst, int imm32) {
1878 prefix(dst); 1878 prefix(dst);
1879 emitArith(0x81, 0xE8, dst, imm32); 1879 emitArith(0x81, 0xE8, dst, imm32);
1880 } 1880 }
1881 1881
1882 public final void subl(CiAddress dst, CiRegister src) { 1882 public final void subl(Address dst, Register src) {
1883 prefix(dst, src); 1883 prefix(dst, src);
1884 emitByte(0x29); 1884 emitByte(0x29);
1885 emitOperandHelper(src, dst); 1885 emitOperandHelper(src, dst);
1886 } 1886 }
1887 1887
1888 public final void subl(CiRegister dst, CiAddress src) { 1888 public final void subl(Register dst, Address src) {
1889 prefix(src, dst); 1889 prefix(src, dst);
1890 emitByte(0x2B); 1890 emitByte(0x2B);
1891 emitOperandHelper(dst, src); 1891 emitOperandHelper(dst, src);
1892 } 1892 }
1893 1893
1894 public final void subl(CiRegister dst, CiRegister src) { 1894 public final void subl(Register dst, Register src) {
1895 prefixAndEncode(dst.encoding, src.encoding); 1895 prefixAndEncode(dst.encoding, src.encoding);
1896 emitArith(0x2B, 0xC0, dst, src); 1896 emitArith(0x2B, 0xC0, dst, src);
1897 } 1897 }
1898 1898
1899 public final void subsd(CiRegister dst, CiRegister src) { 1899 public final void subsd(Register dst, Register src) {
1900 assert dst.isFpu(); 1900 assert dst.isFpu();
1901 assert src.isFpu(); 1901 assert src.isFpu();
1902 emitByte(0xF2); 1902 emitByte(0xF2);
1903 int encode = prefixAndEncode(dst.encoding, src.encoding); 1903 int encode = prefixAndEncode(dst.encoding, src.encoding);
1904 emitByte(0x0F); 1904 emitByte(0x0F);
1905 emitByte(0x5C); 1905 emitByte(0x5C);
1906 emitByte(0xC0 | encode); 1906 emitByte(0xC0 | encode);
1907 } 1907 }
1908 1908
1909 public final void subsd(CiRegister dst, CiAddress src) { 1909 public final void subsd(Register dst, Address src) {
1910 assert dst.isFpu(); 1910 assert dst.isFpu();
1911 1911
1912 emitByte(0xF2); 1912 emitByte(0xF2);
1913 prefix(src, dst); 1913 prefix(src, dst);
1914 emitByte(0x0F); 1914 emitByte(0x0F);
1915 emitByte(0x5C); 1915 emitByte(0x5C);
1916 emitOperandHelper(dst, src); 1916 emitOperandHelper(dst, src);
1917 } 1917 }
1918 1918
1919 public final void subss(CiRegister dst, CiRegister src) { 1919 public final void subss(Register dst, Register src) {
1920 assert dst.isFpu(); 1920 assert dst.isFpu();
1921 assert src.isFpu(); 1921 assert src.isFpu();
1922 emitByte(0xF3); 1922 emitByte(0xF3);
1923 int encode = prefixAndEncode(dst.encoding, src.encoding); 1923 int encode = prefixAndEncode(dst.encoding, src.encoding);
1924 emitByte(0x0F); 1924 emitByte(0x0F);
1925 emitByte(0x5C); 1925 emitByte(0x5C);
1926 emitByte(0xC0 | encode); 1926 emitByte(0xC0 | encode);
1927 } 1927 }
1928 1928
1929 public final void subss(CiRegister dst, CiAddress src) { 1929 public final void subss(Register dst, Address src) {
1930 assert dst.isFpu(); 1930 assert dst.isFpu();
1931 1931
1932 emitByte(0xF3); 1932 emitByte(0xF3);
1933 prefix(src, dst); 1933 prefix(src, dst);
1934 emitByte(0x0F); 1934 emitByte(0x0F);
1935 emitByte(0x5C); 1935 emitByte(0x5C);
1936 emitOperandHelper(dst, src); 1936 emitOperandHelper(dst, src);
1937 } 1937 }
1938 1938
1939 public final void testb(CiRegister dst, int imm8) { 1939 public final void testb(Register dst, int imm8) {
1940 prefixAndEncode(dst.encoding, true); 1940 prefixAndEncode(dst.encoding, true);
1941 emitArithB(0xF6, 0xC0, dst, imm8); 1941 emitArithB(0xF6, 0xC0, dst, imm8);
1942 } 1942 }
1943 1943
1944 public final void testl(CiRegister dst, int imm32) { 1944 public final void testl(Register dst, int imm32) {
1945 // not using emitArith because test 1945 // not using emitArith because test
1946 // doesn't support sign-extension of 1946 // doesn't support sign-extension of
1947 // 8bit operands 1947 // 8bit operands
1948 int encode = dst.encoding; 1948 int encode = dst.encoding;
1949 if (encode == 0) { 1949 if (encode == 0) {
1954 emitByte(0xC0 | encode); 1954 emitByte(0xC0 | encode);
1955 } 1955 }
1956 emitInt(imm32); 1956 emitInt(imm32);
1957 } 1957 }
1958 1958
1959 public final void testl(CiRegister dst, CiRegister src) { 1959 public final void testl(Register dst, Register src) {
1960 prefixAndEncode(dst.encoding, src.encoding); 1960 prefixAndEncode(dst.encoding, src.encoding);
1961 emitArith(0x85, 0xC0, dst, src); 1961 emitArith(0x85, 0xC0, dst, src);
1962 } 1962 }
1963 1963
1964 public final void testl(CiRegister dst, CiAddress src) { 1964 public final void testl(Register dst, Address src) {
1965 prefix(src, dst); 1965 prefix(src, dst);
1966 emitByte(0x85); 1966 emitByte(0x85);
1967 emitOperandHelper(dst, src); 1967 emitOperandHelper(dst, src);
1968 } 1968 }
1969 1969
1970 public final void ucomisd(CiRegister dst, CiAddress src) { 1970 public final void ucomisd(Register dst, Address src) {
1971 assert dst.isFpu(); 1971 assert dst.isFpu();
1972 emitByte(0x66); 1972 emitByte(0x66);
1973 ucomiss(dst, src); 1973 ucomiss(dst, src);
1974 } 1974 }
1975 1975
1976 public final void ucomisd(CiRegister dst, CiRegister src) { 1976 public final void ucomisd(Register dst, Register src) {
1977 assert dst.isFpu(); 1977 assert dst.isFpu();
1978 assert src.isFpu(); 1978 assert src.isFpu();
1979 emitByte(0x66); 1979 emitByte(0x66);
1980 ucomiss(dst, src); 1980 ucomiss(dst, src);
1981 } 1981 }
1982 1982
1983 public final void ucomiss(CiRegister dst, CiAddress src) { 1983 public final void ucomiss(Register dst, Address src) {
1984 assert dst.isFpu(); 1984 assert dst.isFpu();
1985 1985
1986 prefix(src, dst); 1986 prefix(src, dst);
1987 emitByte(0x0F); 1987 emitByte(0x0F);
1988 emitByte(0x2E); 1988 emitByte(0x2E);
1989 emitOperandHelper(dst, src); 1989 emitOperandHelper(dst, src);
1990 } 1990 }
1991 1991
1992 public final void ucomiss(CiRegister dst, CiRegister src) { 1992 public final void ucomiss(Register dst, Register src) {
1993 assert dst.isFpu(); 1993 assert dst.isFpu();
1994 assert src.isFpu(); 1994 assert src.isFpu();
1995 int encode = prefixAndEncode(dst.encoding, src.encoding); 1995 int encode = prefixAndEncode(dst.encoding, src.encoding);
1996 emitByte(0x0F); 1996 emitByte(0x0F);
1997 emitByte(0x2E); 1997 emitByte(0x2E);
1998 emitByte(0xC0 | encode); 1998 emitByte(0xC0 | encode);
1999 } 1999 }
2000 2000
2001 public final void xaddl(CiAddress dst, CiRegister src) { 2001 public final void xaddl(Address dst, Register src) {
2002 assert src.isFpu(); 2002 assert src.isFpu();
2003 2003
2004 prefix(dst, src); 2004 prefix(dst, src);
2005 emitByte(0x0F); 2005 emitByte(0x0F);
2006 emitByte(0xC1); 2006 emitByte(0xC1);
2007 emitOperandHelper(src, dst); 2007 emitOperandHelper(src, dst);
2008 } 2008 }
2009 2009
2010 public final void xchgl(CiRegister dst, CiAddress src) { // xchg 2010 public final void xchgl(Register dst, Address src) { // xchg
2011 prefix(src, dst); 2011 prefix(src, dst);
2012 emitByte(0x87); 2012 emitByte(0x87);
2013 emitOperandHelper(dst, src); 2013 emitOperandHelper(dst, src);
2014 } 2014 }
2015 2015
2016 public final void xchgl(CiRegister dst, CiRegister src) { 2016 public final void xchgl(Register dst, Register src) {
2017 int encode = prefixAndEncode(dst.encoding, src.encoding); 2017 int encode = prefixAndEncode(dst.encoding, src.encoding);
2018 emitByte(0x87); 2018 emitByte(0x87);
2019 emitByte(0xc0 | encode); 2019 emitByte(0xc0 | encode);
2020 } 2020 }
2021 2021
2022 public final void xorl(CiRegister dst, int imm32) { 2022 public final void xorl(Register dst, int imm32) {
2023 prefix(dst); 2023 prefix(dst);
2024 emitArith(0x81, 0xF0, dst, imm32); 2024 emitArith(0x81, 0xF0, dst, imm32);
2025 } 2025 }
2026 2026
2027 public final void xorl(CiRegister dst, CiAddress src) { 2027 public final void xorl(Register dst, Address src) {
2028 prefix(src, dst); 2028 prefix(src, dst);
2029 emitByte(0x33); 2029 emitByte(0x33);
2030 emitOperandHelper(dst, src); 2030 emitOperandHelper(dst, src);
2031 } 2031 }
2032 2032
2033 public final void xorl(CiRegister dst, CiRegister src) { 2033 public final void xorl(Register dst, Register src) {
2034 prefixAndEncode(dst.encoding, src.encoding); 2034 prefixAndEncode(dst.encoding, src.encoding);
2035 emitArith(0x33, 0xC0, dst, src); 2035 emitArith(0x33, 0xC0, dst, src);
2036 } 2036 }
2037 2037
2038 public final void andpd(CiRegister dst, CiRegister src) { 2038 public final void andpd(Register dst, Register src) {
2039 emitByte(0x66); 2039 emitByte(0x66);
2040 andps(dst, src); 2040 andps(dst, src);
2041 } 2041 }
2042 2042
2043 public final void andpd(CiRegister dst, CiAddress src) { 2043 public final void andpd(Register dst, Address src) {
2044 emitByte(0x66); 2044 emitByte(0x66);
2045 andps(dst, src); 2045 andps(dst, src);
2046 } 2046 }
2047 2047
2048 public final void andps(CiRegister dst, CiRegister src) { 2048 public final void andps(Register dst, Register src) {
2049 assert dst.isFpu() && src.isFpu(); 2049 assert dst.isFpu() && src.isFpu();
2050 int encode = prefixAndEncode(dst.encoding, src.encoding); 2050 int encode = prefixAndEncode(dst.encoding, src.encoding);
2051 emitByte(0x0F); 2051 emitByte(0x0F);
2052 emitByte(0x54); 2052 emitByte(0x54);
2053 emitByte(0xC0 | encode); 2053 emitByte(0xC0 | encode);
2054 } 2054 }
2055 2055
2056 public final void andps(CiRegister dst, CiAddress src) { 2056 public final void andps(Register dst, Address src) {
2057 assert dst.isFpu(); 2057 assert dst.isFpu();
2058 prefix(src, dst); 2058 prefix(src, dst);
2059 emitByte(0x0F); 2059 emitByte(0x0F);
2060 emitByte(0x54); 2060 emitByte(0x54);
2061 emitOperandHelper(dst, src); 2061 emitOperandHelper(dst, src);
2062 } 2062 }
2063 2063
2064 public final void orpd(CiRegister dst, CiRegister src) { 2064 public final void orpd(Register dst, Register src) {
2065 emitByte(0x66); 2065 emitByte(0x66);
2066 orps(dst, src); 2066 orps(dst, src);
2067 } 2067 }
2068 2068
2069 public final void orpd(CiRegister dst, CiAddress src) { 2069 public final void orpd(Register dst, Address src) {
2070 emitByte(0x66); 2070 emitByte(0x66);
2071 orps(dst, src); 2071 orps(dst, src);
2072 } 2072 }
2073 2073
2074 public final void orps(CiRegister dst, CiRegister src) { 2074 public final void orps(Register dst, Register src) {
2075 assert dst.isFpu() && src.isFpu(); 2075 assert dst.isFpu() && src.isFpu();
2076 int encode = prefixAndEncode(dst.encoding, src.encoding); 2076 int encode = prefixAndEncode(dst.encoding, src.encoding);
2077 emitByte(0x0F); 2077 emitByte(0x0F);
2078 emitByte(0x56); 2078 emitByte(0x56);
2079 emitByte(0xC0 | encode); 2079 emitByte(0xC0 | encode);
2080 } 2080 }
2081 2081
2082 public final void orps(CiRegister dst, CiAddress src) { 2082 public final void orps(Register dst, Address src) {
2083 assert dst.isFpu(); 2083 assert dst.isFpu();
2084 prefix(src, dst); 2084 prefix(src, dst);
2085 emitByte(0x0F); 2085 emitByte(0x0F);
2086 emitByte(0x56); 2086 emitByte(0x56);
2087 emitOperandHelper(dst, src); 2087 emitOperandHelper(dst, src);
2088 } 2088 }
2089 2089
2090 public final void xorpd(CiRegister dst, CiRegister src) { 2090 public final void xorpd(Register dst, Register src) {
2091 emitByte(0x66); 2091 emitByte(0x66);
2092 xorps(dst, src); 2092 xorps(dst, src);
2093 } 2093 }
2094 2094
2095 public final void xorpd(CiRegister dst, CiAddress src) { 2095 public final void xorpd(Register dst, Address src) {
2096 emitByte(0x66); 2096 emitByte(0x66);
2097 xorps(dst, src); 2097 xorps(dst, src);
2098 } 2098 }
2099 2099
2100 public final void xorps(CiRegister dst, CiRegister src) { 2100 public final void xorps(Register dst, Register src) {
2101 assert dst.isFpu() && src.isFpu(); 2101 assert dst.isFpu() && src.isFpu();
2102 int encode = prefixAndEncode(dst.encoding, src.encoding); 2102 int encode = prefixAndEncode(dst.encoding, src.encoding);
2103 emitByte(0x0F); 2103 emitByte(0x0F);
2104 emitByte(0x57); 2104 emitByte(0x57);
2105 emitByte(0xC0 | encode); 2105 emitByte(0xC0 | encode);
2106 } 2106 }
2107 2107
2108 public final void xorps(CiRegister dst, CiAddress src) { 2108 public final void xorps(Register dst, Address src) {
2109 assert dst.isFpu(); 2109 assert dst.isFpu();
2110 prefix(src, dst); 2110 prefix(src, dst);
2111 emitByte(0x0F); 2111 emitByte(0x0F);
2112 emitByte(0x57); 2112 emitByte(0x57);
2113 emitOperandHelper(dst, src); 2113 emitOperandHelper(dst, src);
2114 } 2114 }
2115 2115
2116 // 32bit only pieces of the assembler 2116 // 32bit only pieces of the assembler
2117 2117
2118 public final void decl(CiRegister dst) { 2118 public final void decl(Register dst) {
2119 // Don't use it directly. Use Macrodecrementl() instead. 2119 // Don't use it directly. Use Macrodecrementl() instead.
2120 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) 2120 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
2121 int encode = prefixAndEncode(dst.encoding); 2121 int encode = prefixAndEncode(dst.encoding);
2122 emitByte(0xFF); 2122 emitByte(0xFF);
2123 emitByte(0xC8 | encode); 2123 emitByte(0xC8 | encode);
2124 } 2124 }
2125 2125
2126 public final void incl(CiRegister dst) { 2126 public final void incl(Register dst) {
2127 // Don't use it directly. Use Macroincrementl() instead. 2127 // Don't use it directly. Use Macroincrementl() instead.
2128 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 2128 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
2129 int encode = prefixAndEncode(dst.encoding); 2129 int encode = prefixAndEncode(dst.encoding);
2130 emitByte(0xFF); 2130 emitByte(0xFF);
2131 emitByte(0xC0 | encode); 2131 emitByte(0xC0 | encode);
2209 regEnc -= 8; 2209 regEnc -= 8;
2210 } 2210 }
2211 return regEnc << 3 | rmEnc; 2211 return regEnc << 3 | rmEnc;
2212 } 2212 }
2213 2213
2214 private void prefix(CiRegister reg) { 2214 private void prefix(Register reg) {
2215 if (reg.encoding >= 8) { 2215 if (reg.encoding >= 8) {
2216 emitByte(Prefix.REXB); 2216 emitByte(Prefix.REXB);
2217 } 2217 }
2218 } 2218 }
2219 2219
2220 private static boolean needsRex(Value value) { 2220 private static boolean needsRex(Value value) {
2221 return isRegister(value) && asRegister(value).encoding >= MinEncodingNeedsRex; 2221 return isRegister(value) && asRegister(value).encoding >= MinEncodingNeedsRex;
2222 } 2222 }
2223 2223
2224 2224
2225 private void prefix(CiAddress adr) { 2225 private void prefix(Address adr) {
2226 if (needsRex(adr.base)) { 2226 if (needsRex(adr.base)) {
2227 if (needsRex(adr.index)) { 2227 if (needsRex(adr.index)) {
2228 emitByte(Prefix.REXXB); 2228 emitByte(Prefix.REXXB);
2229 } else { 2229 } else {
2230 emitByte(Prefix.REXB); 2230 emitByte(Prefix.REXB);
2234 emitByte(Prefix.REXX); 2234 emitByte(Prefix.REXX);
2235 } 2235 }
2236 } 2236 }
2237 } 2237 }
2238 2238
2239 private void prefixq(CiAddress adr) { 2239 private void prefixq(Address adr) {
2240 if (needsRex(adr.base)) { 2240 if (needsRex(adr.base)) {
2241 if (needsRex(adr.index)) { 2241 if (needsRex(adr.index)) {
2242 emitByte(Prefix.REXWXB); 2242 emitByte(Prefix.REXWXB);
2243 } else { 2243 } else {
2244 emitByte(Prefix.REXWB); 2244 emitByte(Prefix.REXWB);
2250 emitByte(Prefix.REXW); 2250 emitByte(Prefix.REXW);
2251 } 2251 }
2252 } 2252 }
2253 } 2253 }
2254 2254
2255 private void prefix(CiAddress adr, CiRegister reg) { 2255 private void prefix(Address adr, Register reg) {
2256 if (reg.encoding < 8) { 2256 if (reg.encoding < 8) {
2257 if (needsRex(adr.base)) { 2257 if (needsRex(adr.base)) {
2258 if (needsRex(adr.index)) { 2258 if (needsRex(adr.index)) {
2259 emitByte(Prefix.REXXB); 2259 emitByte(Prefix.REXXB);
2260 } else { 2260 } else {
2282 } 2282 }
2283 } 2283 }
2284 } 2284 }
2285 } 2285 }
2286 2286
2287 private void prefixq(CiAddress adr, CiRegister src) { 2287 private void prefixq(Address adr, Register src) {
2288 if (src.encoding < 8) { 2288 if (src.encoding < 8) {
2289 if (needsRex(adr.base)) { 2289 if (needsRex(adr.base)) {
2290 if (needsRex(adr.index)) { 2290 if (needsRex(adr.index)) {
2291 emitByte(Prefix.REXWXB); 2291 emitByte(Prefix.REXWXB);
2292 } else { 2292 } else {
2314 } 2314 }
2315 } 2315 }
2316 } 2316 }
2317 } 2317 }
2318 2318
2319 public final void addq(CiAddress dst, int imm32) { 2319 public final void addq(Address dst, int imm32) {
2320 prefixq(dst); 2320 prefixq(dst);
2321 emitArithOperand(0x81, rax, dst, imm32); 2321 emitArithOperand(0x81, rax, dst, imm32);
2322 } 2322 }
2323 2323
2324 public final void addq(CiAddress dst, CiRegister src) { 2324 public final void addq(Address dst, Register src) {
2325 prefixq(dst, src); 2325 prefixq(dst, src);
2326 emitByte(0x01); 2326 emitByte(0x01);
2327 emitOperandHelper(src, dst); 2327 emitOperandHelper(src, dst);
2328 } 2328 }
2329 2329
2330 public final void addq(CiRegister dst, int imm32) { 2330 public final void addq(Register dst, int imm32) {
2331 prefixqAndEncode(dst.encoding); 2331 prefixqAndEncode(dst.encoding);
2332 emitArith(0x81, 0xC0, dst, imm32); 2332 emitArith(0x81, 0xC0, dst, imm32);
2333 } 2333 }
2334 2334
2335 public final void addq(CiRegister dst, CiAddress src) { 2335 public final void addq(Register dst, Address src) {
2336 prefixq(src, dst); 2336 prefixq(src, dst);
2337 emitByte(0x03); 2337 emitByte(0x03);
2338 emitOperandHelper(dst, src); 2338 emitOperandHelper(dst, src);
2339 } 2339 }
2340 2340
2341 public final void addq(CiRegister dst, CiRegister src) { 2341 public final void addq(Register dst, Register src) {
2342 prefixqAndEncode(dst.encoding, src.encoding); 2342 prefixqAndEncode(dst.encoding, src.encoding);
2343 emitArith(0x03, 0xC0, dst, src); 2343 emitArith(0x03, 0xC0, dst, src);
2344 } 2344 }
2345 2345
2346 public final void andq(CiRegister dst, int imm32) { 2346 public final void andq(Register dst, int imm32) {
2347 prefixqAndEncode(dst.encoding); 2347 prefixqAndEncode(dst.encoding);
2348 emitArith(0x81, 0xE0, dst, imm32); 2348 emitArith(0x81, 0xE0, dst, imm32);
2349 } 2349 }
2350 2350
2351 public final void andq(CiRegister dst, CiAddress src) { 2351 public final void andq(Register dst, Address src) {
2352 prefixq(src, dst); 2352 prefixq(src, dst);
2353 emitByte(0x23); 2353 emitByte(0x23);
2354 emitOperandHelper(dst, src); 2354 emitOperandHelper(dst, src);
2355 } 2355 }
2356 2356
2357 public final void andq(CiRegister dst, CiRegister src) { 2357 public final void andq(Register dst, Register src) {
2358 prefixqAndEncode(dst.encoding, src.encoding); 2358 prefixqAndEncode(dst.encoding, src.encoding);
2359 emitArith(0x23, 0xC0, dst, src); 2359 emitArith(0x23, 0xC0, dst, src);
2360 } 2360 }
2361 2361
2362 public final void bswapq(CiRegister reg) { 2362 public final void bswapq(Register reg) {
2363 int encode = prefixqAndEncode(reg.encoding); 2363 int encode = prefixqAndEncode(reg.encoding);
2364 emitByte(0x0F); 2364 emitByte(0x0F);
2365 emitByte(0xC8 | encode); 2365 emitByte(0xC8 | encode);
2366 } 2366 }
2367 2367
2368 public final void cdqq() { 2368 public final void cdqq() {
2369 emitByte(Prefix.REXW); 2369 emitByte(Prefix.REXW);
2370 emitByte(0x99); 2370 emitByte(0x99);
2371 } 2371 }
2372 2372
2373 public final void cmovq(ConditionFlag cc, CiRegister dst, CiRegister src) { 2373 public final void cmovq(ConditionFlag cc, Register dst, Register src) {
2374 int encode = prefixqAndEncode(dst.encoding, src.encoding); 2374 int encode = prefixqAndEncode(dst.encoding, src.encoding);
2375 emitByte(0x0F); 2375 emitByte(0x0F);
2376 emitByte(0x40 | cc.value); 2376 emitByte(0x40 | cc.value);
2377 emitByte(0xC0 | encode); 2377 emitByte(0xC0 | encode);
2378 } 2378 }
2379 2379
2380 public final void cmovq(ConditionFlag cc, CiRegister dst, CiAddress src) { 2380 public final void cmovq(ConditionFlag cc, Register dst, Address src) {
2381 prefixq(src, dst); 2381 prefixq(src, dst);
2382 emitByte(0x0F); 2382 emitByte(0x0F);
2383 emitByte(0x40 | cc.value); 2383 emitByte(0x40 | cc.value);
2384 emitOperandHelper(dst, src); 2384 emitOperandHelper(dst, src);
2385 } 2385 }
2386 2386
2387 public final void cmpq(CiAddress dst, int imm32) { 2387 public final void cmpq(Address dst, int imm32) {
2388 prefixq(dst); 2388 prefixq(dst);
2389 emitByte(0x81); 2389 emitByte(0x81);
2390 emitOperandHelper(rdi, dst); 2390 emitOperandHelper(rdi, dst);
2391 emitInt(imm32); 2391 emitInt(imm32);
2392 } 2392 }
2393 2393
2394 public final void cmpq(CiRegister dst, int imm32) { 2394 public final void cmpq(Register dst, int imm32) {
2395 prefixqAndEncode(dst.encoding); 2395 prefixqAndEncode(dst.encoding);
2396 emitArith(0x81, 0xF8, dst, imm32); 2396 emitArith(0x81, 0xF8, dst, imm32);
2397 } 2397 }
2398 2398
2399 public final void cmpq(CiAddress dst, CiRegister src) { 2399 public final void cmpq(Address dst, Register src) {
2400 prefixq(dst, src); 2400 prefixq(dst, src);
2401 emitByte(0x3B); 2401 emitByte(0x3B);
2402 emitOperandHelper(src, dst); 2402 emitOperandHelper(src, dst);
2403 } 2403 }
2404 2404
2405 public final void cmpq(CiRegister dst, CiRegister src) { 2405 public final void cmpq(Register dst, Register src) {
2406 prefixqAndEncode(dst.encoding, src.encoding); 2406 prefixqAndEncode(dst.encoding, src.encoding);
2407 emitArith(0x3B, 0xC0, dst, src); 2407 emitArith(0x3B, 0xC0, dst, src);
2408 } 2408 }
2409 2409
2410 public final void cmpq(CiRegister dst, CiAddress src) { 2410 public final void cmpq(Register dst, Address src) {
2411 prefixq(src, dst); 2411 prefixq(src, dst);
2412 emitByte(0x3B); 2412 emitByte(0x3B);
2413 emitOperandHelper(dst, src); 2413 emitOperandHelper(dst, src);
2414 } 2414 }
2415 2415
2416 public final void cmpxchgq(CiRegister reg, CiAddress adr) { 2416 public final void cmpxchgq(Register reg, Address adr) {
2417 prefixq(adr, reg); 2417 prefixq(adr, reg);
2418 emitByte(0x0F); 2418 emitByte(0x0F);
2419 emitByte(0xB1); 2419 emitByte(0xB1);
2420 emitOperandHelper(reg, adr); 2420 emitOperandHelper(reg, adr);
2421 } 2421 }
2422 2422
2423 public final void cvtsi2sdq(CiRegister dst, CiRegister src) { 2423 public final void cvtsi2sdq(Register dst, Register src) {
2424 assert dst.isFpu(); 2424 assert dst.isFpu();
2425 emitByte(0xF2); 2425 emitByte(0xF2);
2426 int encode = prefixqAndEncode(dst.encoding, src.encoding); 2426 int encode = prefixqAndEncode(dst.encoding, src.encoding);
2427 emitByte(0x0F); 2427 emitByte(0x0F);
2428 emitByte(0x2A); 2428 emitByte(0x2A);
2429 emitByte(0xC0 | encode); 2429 emitByte(0xC0 | encode);
2430 } 2430 }
2431 2431
2432 public final void cvtsi2ssq(CiRegister dst, CiRegister src) { 2432 public final void cvtsi2ssq(Register dst, Register src) {
2433 assert dst.isFpu(); 2433 assert dst.isFpu();
2434 emitByte(0xF3); 2434 emitByte(0xF3);
2435 int encode = prefixqAndEncode(dst.encoding, src.encoding); 2435 int encode = prefixqAndEncode(dst.encoding, src.encoding);
2436 emitByte(0x0F); 2436 emitByte(0x0F);
2437 emitByte(0x2A); 2437 emitByte(0x2A);
2438 emitByte(0xC0 | encode); 2438 emitByte(0xC0 | encode);
2439 } 2439 }
2440 2440
2441 public final void cvttsd2siq(CiRegister dst, CiRegister src) { 2441 public final void cvttsd2siq(Register dst, Register src) {
2442 assert src.isFpu(); 2442 assert src.isFpu();
2443 emitByte(0xF2); 2443 emitByte(0xF2);
2444 int encode = prefixqAndEncode(dst.encoding, src.encoding); 2444 int encode = prefixqAndEncode(dst.encoding, src.encoding);
2445 emitByte(0x0F); 2445 emitByte(0x0F);
2446 emitByte(0x2C); 2446 emitByte(0x2C);
2447 emitByte(0xC0 | encode); 2447 emitByte(0xC0 | encode);
2448 } 2448 }
2449 2449
2450 public final void cvttss2siq(CiRegister dst, CiRegister src) { 2450 public final void cvttss2siq(Register dst, Register src) {
2451 assert src.isFpu(); 2451 assert src.isFpu();
2452 emitByte(0xF3); 2452 emitByte(0xF3);
2453 int encode = prefixqAndEncode(dst.encoding, src.encoding); 2453 int encode = prefixqAndEncode(dst.encoding, src.encoding);
2454 emitByte(0x0F); 2454 emitByte(0x0F);
2455 emitByte(0x2C); 2455 emitByte(0x2C);
2456 emitByte(0xC0 | encode); 2456 emitByte(0xC0 | encode);
2457 } 2457 }
2458 2458
2459 public final void decq(CiRegister dst) { 2459 public final void decq(Register dst) {
2460 // Don't use it directly. Use Macrodecrementq() instead. 2460 // Don't use it directly. Use Macrodecrementq() instead.
2461 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 2461 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
2462 int encode = prefixqAndEncode(dst.encoding); 2462 int encode = prefixqAndEncode(dst.encoding);
2463 emitByte(0xFF); 2463 emitByte(0xFF);
2464 emitByte(0xC8 | encode); 2464 emitByte(0xC8 | encode);
2465 } 2465 }
2466 2466
2467 public final void decq(CiAddress dst) { 2467 public final void decq(Address dst) {
2468 // Don't use it directly. Use Macrodecrementq() instead. 2468 // Don't use it directly. Use Macrodecrementq() instead.
2469 prefixq(dst); 2469 prefixq(dst);
2470 emitByte(0xFF); 2470 emitByte(0xFF);
2471 emitOperandHelper(rcx, dst); 2471 emitOperandHelper(rcx, dst);
2472 } 2472 }
2473 2473
2474 public final void divq(CiRegister src) { 2474 public final void divq(Register src) {
2475 int encode = prefixqAndEncode(src.encoding); 2475 int encode = prefixqAndEncode(src.encoding);
2476 emitByte(0xF7); 2476 emitByte(0xF7);
2477 emitByte(0xF0 | encode); 2477 emitByte(0xF0 | encode);
2478 } 2478 }
2479 2479
2480 public final void idivq(CiRegister src) { 2480 public final void idivq(Register src) {
2481 int encode = prefixqAndEncode(src.encoding); 2481 int encode = prefixqAndEncode(src.encoding);
2482 emitByte(0xF7); 2482 emitByte(0xF7);
2483 emitByte(0xF8 | encode); 2483 emitByte(0xF8 | encode);
2484 } 2484 }
2485 2485
2486 public final void imulq(CiRegister dst, CiRegister src) { 2486 public final void imulq(Register dst, Register src) {
2487 int encode = prefixqAndEncode(dst.encoding, src.encoding); 2487 int encode = prefixqAndEncode(dst.encoding, src.encoding);
2488 emitByte(0x0F); 2488 emitByte(0x0F);
2489 emitByte(0xAF); 2489 emitByte(0xAF);
2490 emitByte(0xC0 | encode); 2490 emitByte(0xC0 | encode);
2491 } 2491 }
2492 2492
2493 public final void imulq(CiRegister dst, CiRegister src, int value) { 2493 public final void imulq(Register dst, Register src, int value) {
2494 int encode = prefixqAndEncode(dst.encoding, src.encoding); 2494 int encode = prefixqAndEncode(dst.encoding, src.encoding);
2495 if (isByte(value)) { 2495 if (isByte(value)) {
2496 emitByte(0x6B); 2496 emitByte(0x6B);
2497 emitByte(0xC0 | encode); 2497 emitByte(0xC0 | encode);
2498 emitByte(value); 2498 emitByte(value);
2501 emitByte(0xC0 | encode); 2501 emitByte(0xC0 | encode);
2502 emitInt(value); 2502 emitInt(value);
2503 } 2503 }
2504 } 2504 }
2505 2505
2506 public final void incq(CiRegister dst) { 2506 public final void incq(Register dst) {
2507 // Don't use it directly. Use Macroincrementq() instead. 2507 // Don't use it directly. Use Macroincrementq() instead.
2508 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 2508 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
2509 int encode = prefixqAndEncode(dst.encoding); 2509 int encode = prefixqAndEncode(dst.encoding);
2510 emitByte(0xFF); 2510 emitByte(0xFF);
2511 emitByte(0xC0 | encode); 2511 emitByte(0xC0 | encode);
2512 } 2512 }
2513 2513
2514 public final void incq(CiAddress dst) { 2514 public final void incq(Address dst) {
2515 // Don't use it directly. Use Macroincrementq() instead. 2515 // Don't use it directly. Use Macroincrementq() instead.
2516 prefixq(dst); 2516 prefixq(dst);
2517 emitByte(0xFF); 2517 emitByte(0xFF);
2518 emitOperandHelper(rax, dst); 2518 emitOperandHelper(rax, dst);
2519 } 2519 }
2520 2520
2521 public final void movq(CiRegister dst, long imm64) { 2521 public final void movq(Register dst, long imm64) {
2522 int encode = prefixqAndEncode(dst.encoding); 2522 int encode = prefixqAndEncode(dst.encoding);
2523 emitByte(0xB8 | encode); 2523 emitByte(0xB8 | encode);
2524 emitLong(imm64); 2524 emitLong(imm64);
2525 } 2525 }
2526 2526
2527 public final void movdq(CiRegister dst, CiRegister src) { 2527 public final void movdq(Register dst, Register src) {
2528 2528
2529 // table D-1 says MMX/SSE2 2529 // table D-1 says MMX/SSE2
2530 emitByte(0x66); 2530 emitByte(0x66);
2531 2531
2532 if (dst.isFpu()) { 2532 if (dst.isFpu()) {
2545 } else { 2545 } else {
2546 throw new InternalError("should not reach here"); 2546 throw new InternalError("should not reach here");
2547 } 2547 }
2548 } 2548 }
2549 2549
2550 public final void movsbq(CiRegister dst, CiAddress src) { 2550 public final void movsbq(Register dst, Address src) {
2551 prefixq(src, dst); 2551 prefixq(src, dst);
2552 emitByte(0x0F); 2552 emitByte(0x0F);
2553 emitByte(0xBE); 2553 emitByte(0xBE);
2554 emitOperandHelper(dst, src); 2554 emitOperandHelper(dst, src);
2555 } 2555 }
2556 2556
2557 public final void movsbq(CiRegister dst, CiRegister src) { 2557 public final void movsbq(Register dst, Register src) {
2558 int encode = prefixqAndEncode(dst.encoding, src.encoding); 2558 int encode = prefixqAndEncode(dst.encoding, src.encoding);
2559 emitByte(0x0F); 2559 emitByte(0x0F);
2560 emitByte(0xBE); 2560 emitByte(0xBE);
2561 emitByte(0xC0 | encode); 2561 emitByte(0xC0 | encode);
2562 } 2562 }
2563 2563
2564 public final void movslq(CiRegister dst, int imm32) { 2564 public final void movslq(Register dst, int imm32) {
2565 int encode = prefixqAndEncode(dst.encoding); 2565 int encode = prefixqAndEncode(dst.encoding);
2566 emitByte(0xC7 | encode); 2566 emitByte(0xC7 | encode);
2567 emitInt(imm32); 2567 emitInt(imm32);
2568 // dbx shows movslq(X86.rcx, 3) as movq $0x0000000049000000,(%X86.rbx) 2568 // dbx shows movslq(X86.rcx, 3) as movq $0x0000000049000000,(%X86.rbx)
2569 // and movslq(X86.r8, 3); as movl $0x0000000048000000,(%X86.rbx) 2569 // and movslq(X86.r8, 3); as movl $0x0000000048000000,(%X86.rbx)
2570 // as a result we shouldn't use until tested at runtime... 2570 // as a result we shouldn't use until tested at runtime...
2571 throw new InternalError("untested"); 2571 throw new InternalError("untested");
2572 } 2572 }
2573 2573
2574 public final void movslq(CiAddress dst, int imm32) { 2574 public final void movslq(Address dst, int imm32) {
2575 prefixq(dst); 2575 prefixq(dst);
2576 emitByte(0xC7); 2576 emitByte(0xC7);
2577 emitOperandHelper(rax, dst); 2577 emitOperandHelper(rax, dst);
2578 emitInt(imm32); 2578 emitInt(imm32);
2579 } 2579 }
2580 2580
2581 public final void movslq(CiRegister dst, CiAddress src) { 2581 public final void movslq(Register dst, Address src) {
2582 prefixq(src, dst); 2582 prefixq(src, dst);
2583 emitByte(0x63); 2583 emitByte(0x63);
2584 emitOperandHelper(dst, src); 2584 emitOperandHelper(dst, src);
2585 } 2585 }
2586 2586
2587 public final void movslq(CiRegister dst, CiRegister src) { 2587 public final void movslq(Register dst, Register src) {
2588 int encode = prefixqAndEncode(dst.encoding, src.encoding); 2588 int encode = prefixqAndEncode(dst.encoding, src.encoding);
2589 emitByte(0x63); 2589 emitByte(0x63);
2590 emitByte(0xC0 | encode); 2590 emitByte(0xC0 | encode);
2591 } 2591 }
2592 2592
2593 public final void movswq(CiRegister dst, CiAddress src) { 2593 public final void movswq(Register dst, Address src) {
2594 prefixq(src, dst); 2594 prefixq(src, dst);
2595 emitByte(0x0F); 2595 emitByte(0x0F);
2596 emitByte(0xBF); 2596 emitByte(0xBF);
2597 emitOperandHelper(dst, src); 2597 emitOperandHelper(dst, src);
2598 } 2598 }
2599 2599
2600 public final void movswq(CiRegister dst, CiRegister src) { 2600 public final void movswq(Register dst, Register src) {
2601 int encode = prefixqAndEncode(dst.encoding, src.encoding); 2601 int encode = prefixqAndEncode(dst.encoding, src.encoding);
2602 emitByte(0x0F); 2602 emitByte(0x0F);
2603 emitByte(0xBF); 2603 emitByte(0xBF);
2604 emitByte(0xC0 | encode); 2604 emitByte(0xC0 | encode);
2605 } 2605 }
2606 2606
2607 public final void movzbq(CiRegister dst, CiAddress src) { 2607 public final void movzbq(Register dst, Address src) {
2608 prefixq(src, dst); 2608 prefixq(src, dst);
2609 emitByte(0x0F); 2609 emitByte(0x0F);
2610 emitByte(0xB6); 2610 emitByte(0xB6);
2611 emitOperandHelper(dst, src); 2611 emitOperandHelper(dst, src);
2612 } 2612 }
2613 2613
2614 public final void movzbq(CiRegister dst, CiRegister src) { 2614 public final void movzbq(Register dst, Register src) {
2615 int encode = prefixqAndEncode(dst.encoding, src.encoding); 2615 int encode = prefixqAndEncode(dst.encoding, src.encoding);
2616 emitByte(0x0F); 2616 emitByte(0x0F);
2617 emitByte(0xB6); 2617 emitByte(0xB6);
2618 emitByte(0xC0 | encode); 2618 emitByte(0xC0 | encode);
2619 } 2619 }
2620 2620
2621 public final void movzwq(CiRegister dst, CiAddress src) { 2621 public final void movzwq(Register dst, Address src) {
2622 prefixq(src, dst); 2622 prefixq(src, dst);
2623 emitByte(0x0F); 2623 emitByte(0x0F);
2624 emitByte(0xB7); 2624 emitByte(0xB7);
2625 emitOperandHelper(dst, src); 2625 emitOperandHelper(dst, src);
2626 } 2626 }
2627 2627
2628 public final void movzwq(CiRegister dst, CiRegister src) { 2628 public final void movzwq(Register dst, Register src) {
2629 int encode = prefixqAndEncode(dst.encoding, src.encoding); 2629 int encode = prefixqAndEncode(dst.encoding, src.encoding);
2630 emitByte(0x0F); 2630 emitByte(0x0F);
2631 emitByte(0xB7); 2631 emitByte(0xB7);
2632 emitByte(0xC0 | encode); 2632 emitByte(0xC0 | encode);
2633 } 2633 }
2634 2634
2635 public final void negq(CiRegister dst) { 2635 public final void negq(Register dst) {
2636 int encode = prefixqAndEncode(dst.encoding); 2636 int encode = prefixqAndEncode(dst.encoding);
2637 emitByte(0xF7); 2637 emitByte(0xF7);
2638 emitByte(0xD8 | encode); 2638 emitByte(0xD8 | encode);
2639 } 2639 }
2640 2640
2641 public final void notq(CiRegister dst) { 2641 public final void notq(Register dst) {
2642 int encode = prefixqAndEncode(dst.encoding); 2642 int encode = prefixqAndEncode(dst.encoding);
2643 emitByte(0xF7); 2643 emitByte(0xF7);
2644 emitByte(0xD0 | encode); 2644 emitByte(0xD0 | encode);
2645 } 2645 }
2646 2646
2647 public final void orq(CiAddress dst, int imm32) { 2647 public final void orq(Address dst, int imm32) {
2648 prefixq(dst); 2648 prefixq(dst);
2649 emitByte(0x81); 2649 emitByte(0x81);
2650 emitOperandHelper(rcx, dst); 2650 emitOperandHelper(rcx, dst);
2651 emitInt(imm32); 2651 emitInt(imm32);
2652 } 2652 }
2653 2653
2654 public final void orq(CiRegister dst, int imm32) { 2654 public final void orq(Register dst, int imm32) {
2655 prefixqAndEncode(dst.encoding); 2655 prefixqAndEncode(dst.encoding);
2656 emitArith(0x81, 0xC8, dst, imm32); 2656 emitArith(0x81, 0xC8, dst, imm32);
2657 } 2657 }
2658 2658
2659 public final void orq(CiRegister dst, CiAddress src) { 2659 public final void orq(Register dst, Address src) {
2660 prefixq(src, dst); 2660 prefixq(src, dst);
2661 emitByte(0x0B); 2661 emitByte(0x0B);
2662 emitOperandHelper(dst, src); 2662 emitOperandHelper(dst, src);
2663 } 2663 }
2664 2664
2665 public final void orq(CiRegister dst, CiRegister src) { 2665 public final void orq(Register dst, Register src) {
2666 prefixqAndEncode(dst.encoding, src.encoding); 2666 prefixqAndEncode(dst.encoding, src.encoding);
2667 emitArith(0x0B, 0xC0, dst, src); 2667 emitArith(0x0B, 0xC0, dst, src);
2668 } 2668 }
2669 2669
2670 public final void popq(CiAddress dst) { 2670 public final void popq(Address dst) {
2671 prefixq(dst); 2671 prefixq(dst);
2672 emitByte(0x8F); 2672 emitByte(0x8F);
2673 emitOperandHelper(rax, dst); 2673 emitOperandHelper(rax, dst);
2674 } 2674 }
2675 2675
2676 public final void pushq(CiAddress src) { 2676 public final void pushq(Address src) {
2677 prefixq(src); 2677 prefixq(src);
2678 emitByte(0xFF); 2678 emitByte(0xFF);
2679 emitOperandHelper(rsi, src); 2679 emitOperandHelper(rsi, src);
2680 } 2680 }
2681 2681
2682 public final void rclq(CiRegister dst, int imm8) { 2682 public final void rclq(Register dst, int imm8) {
2683 assert isShiftCount(imm8 >> 1) : "illegal shift count"; 2683 assert isShiftCount(imm8 >> 1) : "illegal shift count";
2684 int encode = prefixqAndEncode(dst.encoding); 2684 int encode = prefixqAndEncode(dst.encoding);
2685 if (imm8 == 1) { 2685 if (imm8 == 1) {
2686 emitByte(0xD1); 2686 emitByte(0xD1);
2687 emitByte(0xD0 | encode); 2687 emitByte(0xD0 | encode);
2690 emitByte(0xD0 | encode); 2690 emitByte(0xD0 | encode);
2691 emitByte(imm8); 2691 emitByte(imm8);
2692 } 2692 }
2693 } 2693 }
2694 2694
2695 public final void sarq(CiRegister dst, int imm8) { 2695 public final void sarq(Register dst, int imm8) {
2696 assert isShiftCount(imm8 >> 1) : "illegal shift count"; 2696 assert isShiftCount(imm8 >> 1) : "illegal shift count";
2697 int encode = prefixqAndEncode(dst.encoding); 2697 int encode = prefixqAndEncode(dst.encoding);
2698 if (imm8 == 1) { 2698 if (imm8 == 1) {
2699 emitByte(0xD1); 2699 emitByte(0xD1);
2700 emitByte(0xF8 | encode); 2700 emitByte(0xF8 | encode);
2703 emitByte(0xF8 | encode); 2703 emitByte(0xF8 | encode);
2704 emitByte(imm8); 2704 emitByte(imm8);
2705 } 2705 }
2706 } 2706 }
2707 2707
2708 public final void sarq(CiRegister dst) { 2708 public final void sarq(Register dst) {
2709 int encode = prefixqAndEncode(dst.encoding); 2709 int encode = prefixqAndEncode(dst.encoding);
2710 emitByte(0xD3); 2710 emitByte(0xD3);
2711 emitByte(0xF8 | encode); 2711 emitByte(0xF8 | encode);
2712 } 2712 }
2713 2713
2714 public final void shlq(CiRegister dst, int imm8) { 2714 public final void shlq(Register dst, int imm8) {
2715 assert isShiftCount(imm8 >> 1) : "illegal shift count"; 2715 assert isShiftCount(imm8 >> 1) : "illegal shift count";
2716 int encode = prefixqAndEncode(dst.encoding); 2716 int encode = prefixqAndEncode(dst.encoding);
2717 if (imm8 == 1) { 2717 if (imm8 == 1) {
2718 emitByte(0xD1); 2718 emitByte(0xD1);
2719 emitByte(0xE0 | encode); 2719 emitByte(0xE0 | encode);
2722 emitByte(0xE0 | encode); 2722 emitByte(0xE0 | encode);
2723 emitByte(imm8); 2723 emitByte(imm8);
2724 } 2724 }
2725 } 2725 }
2726 2726
2727 public final void shlq(CiRegister dst) { 2727 public final void shlq(Register dst) {
2728 int encode = prefixqAndEncode(dst.encoding); 2728 int encode = prefixqAndEncode(dst.encoding);
2729 emitByte(0xD3); 2729 emitByte(0xD3);
2730 emitByte(0xE0 | encode); 2730 emitByte(0xE0 | encode);
2731 } 2731 }
2732 2732
2733 public final void shrq(CiRegister dst, int imm8) { 2733 public final void shrq(Register dst, int imm8) {
2734 assert isShiftCount(imm8 >> 1) : "illegal shift count"; 2734 assert isShiftCount(imm8 >> 1) : "illegal shift count";
2735 int encode = prefixqAndEncode(dst.encoding); 2735 int encode = prefixqAndEncode(dst.encoding);
2736 emitByte(0xC1); 2736 emitByte(0xC1);
2737 emitByte(0xE8 | encode); 2737 emitByte(0xE8 | encode);
2738 emitByte(imm8); 2738 emitByte(imm8);
2739 } 2739 }
2740 2740
2741 public final void shrq(CiRegister dst) { 2741 public final void shrq(Register dst) {
2742 int encode = prefixqAndEncode(dst.encoding); 2742 int encode = prefixqAndEncode(dst.encoding);
2743 emitByte(0xD3); 2743 emitByte(0xD3);
2744 emitByte(0xE8 | encode); 2744 emitByte(0xE8 | encode);
2745 } 2745 }
2746 2746
2747 public final void sqrtsd(CiRegister dst, CiAddress src) { 2747 public final void sqrtsd(Register dst, Address src) {
2748 assert dst.isFpu(); 2748 assert dst.isFpu();
2749 2749
2750 emitByte(0xF2); 2750 emitByte(0xF2);
2751 prefix(src, dst); 2751 prefix(src, dst);
2752 emitByte(0x0F); 2752 emitByte(0x0F);
2753 emitByte(0x51); 2753 emitByte(0x51);
2754 emitOperandHelper(dst, src); 2754 emitOperandHelper(dst, src);
2755 } 2755 }
2756 2756
2757 public final void subq(CiAddress dst, int imm32) { 2757 public final void subq(Address dst, int imm32) {
2758 prefixq(dst); 2758 prefixq(dst);
2759 if (isByte(imm32)) { 2759 if (isByte(imm32)) {
2760 emitByte(0x83); 2760 emitByte(0x83);
2761 emitOperandHelper(rbp, dst); 2761 emitOperandHelper(rbp, dst);
2762 emitByte(imm32 & 0xFF); 2762 emitByte(imm32 & 0xFF);
2765 emitOperandHelper(rbp, dst); 2765 emitOperandHelper(rbp, dst);
2766 emitInt(imm32); 2766 emitInt(imm32);
2767 } 2767 }
2768 } 2768 }
2769 2769
2770 public final void subq(CiRegister dst, int imm32) { 2770 public final void subq(Register dst, int imm32) {
2771 prefixqAndEncode(dst.encoding); 2771 prefixqAndEncode(dst.encoding);
2772 emitArith(0x81, 0xE8, dst, imm32); 2772 emitArith(0x81, 0xE8, dst, imm32);
2773 } 2773 }
2774 2774
2775 public final void subq(CiAddress dst, CiRegister src) { 2775 public final void subq(Address dst, Register src) {
2776 prefixq(dst, src); 2776 prefixq(dst, src);
2777 emitByte(0x29); 2777 emitByte(0x29);
2778 emitOperandHelper(src, dst); 2778 emitOperandHelper(src, dst);
2779 } 2779 }
2780 2780
2781 public final void subq(CiRegister dst, CiAddress src) { 2781 public final void subq(Register dst, Address src) {
2782 prefixq(src, dst); 2782 prefixq(src, dst);
2783 emitByte(0x2B); 2783 emitByte(0x2B);
2784 emitOperandHelper(dst, src); 2784 emitOperandHelper(dst, src);
2785 } 2785 }
2786 2786
2787 public final void subq(CiRegister dst, CiRegister src) { 2787 public final void subq(Register dst, Register src) {
2788 prefixqAndEncode(dst.encoding, src.encoding); 2788 prefixqAndEncode(dst.encoding, src.encoding);
2789 emitArith(0x2B, 0xC0, dst, src); 2789 emitArith(0x2B, 0xC0, dst, src);
2790 } 2790 }
2791 2791
2792 public final void testq(CiRegister dst, int imm32) { 2792 public final void testq(Register dst, int imm32) {
2793 // not using emitArith because test 2793 // not using emitArith because test
2794 // doesn't support sign-extension of 2794 // doesn't support sign-extension of
2795 // 8bit operands 2795 // 8bit operands
2796 int encode = dst.encoding; 2796 int encode = dst.encoding;
2797 if (encode == 0) { 2797 if (encode == 0) {
2803 emitByte(0xC0 | encode); 2803 emitByte(0xC0 | encode);
2804 } 2804 }
2805 emitInt(imm32); 2805 emitInt(imm32);
2806 } 2806 }
2807 2807
2808 public final void testq(CiRegister dst, CiRegister src) { 2808 public final void testq(Register dst, Register src) {
2809 prefixqAndEncode(dst.encoding, src.encoding); 2809 prefixqAndEncode(dst.encoding, src.encoding);
2810 emitArith(0x85, 0xC0, dst, src); 2810 emitArith(0x85, 0xC0, dst, src);
2811 } 2811 }
2812 2812
2813 public final void xaddq(CiAddress dst, CiRegister src) { 2813 public final void xaddq(Address dst, Register src) {
2814 prefixq(dst, src); 2814 prefixq(dst, src);
2815 emitByte(0x0F); 2815 emitByte(0x0F);
2816 emitByte(0xC1); 2816 emitByte(0xC1);
2817 emitOperandHelper(src, dst); 2817 emitOperandHelper(src, dst);
2818 } 2818 }
2819 2819
2820 public final void xchgq(CiRegister dst, CiAddress src) { 2820 public final void xchgq(Register dst, Address src) {
2821 prefixq(src, dst); 2821 prefixq(src, dst);
2822 emitByte(0x87); 2822 emitByte(0x87);
2823 emitOperandHelper(dst, src); 2823 emitOperandHelper(dst, src);
2824 } 2824 }
2825 2825
2826 public final void xchgq(CiRegister dst, CiRegister src) { 2826 public final void xchgq(Register dst, Register src) {
2827 int encode = prefixqAndEncode(dst.encoding, src.encoding); 2827 int encode = prefixqAndEncode(dst.encoding, src.encoding);
2828 emitByte(0x87); 2828 emitByte(0x87);
2829 emitByte(0xc0 | encode); 2829 emitByte(0xc0 | encode);
2830 } 2830 }
2831 2831
2832 public final void xorq(CiRegister dst, int imm32) { 2832 public final void xorq(Register dst, int imm32) {
2833 prefixqAndEncode(dst.encoding); 2833 prefixqAndEncode(dst.encoding);
2834 emitArith(0x81, 0xF0, dst, imm32); 2834 emitArith(0x81, 0xF0, dst, imm32);
2835 } 2835 }
2836 2836
2837 public final void xorq(CiRegister dst, CiRegister src) { 2837 public final void xorq(Register dst, Register src) {
2838 prefixqAndEncode(dst.encoding, src.encoding); 2838 prefixqAndEncode(dst.encoding, src.encoding);
2839 emitArith(0x33, 0xC0, dst, src); 2839 emitArith(0x33, 0xC0, dst, src);
2840 } 2840 }
2841 2841
2842 public final void xorq(CiRegister dst, CiAddress src) { 2842 public final void xorq(Register dst, Address src) {
2843 2843
2844 prefixq(src, dst); 2844 prefixq(src, dst);
2845 emitByte(0x33); 2845 emitByte(0x33);
2846 emitOperandHelper(dst, src); 2846 emitOperandHelper(dst, src);
2847 2847
2858 // flags. 2858 // flags.
2859 // Any change to this code may need to revisit other places in 2859 // Any change to this code may need to revisit other places in
2860 // the code where this idiom is used, in particular the 2860 // the code where this idiom is used, in particular the
2861 // orderAccess code. 2861 // orderAccess code.
2862 lock(); 2862 lock();
2863 addl(new CiAddress(Word, RSP, 0), 0); // Assert the lock# signal here 2863 addl(new Address(Word, RSP, 0), 0); // Assert the lock# signal here
2864 } 2864 }
2865 } 2865 }
2866 } 2866 }
2867 2867
2868 @Override 2868 @Override
2897 int imm32 = branchTarget - (branch + 4 + off); 2897 int imm32 = branchTarget - (branch + 4 + off);
2898 codeBuffer.emitInt(imm32, branch + off); 2898 codeBuffer.emitInt(imm32, branch + off);
2899 } 2899 }
2900 } 2900 }
2901 2901
2902 public void nullCheck(CiRegister r) { 2902 public void nullCheck(Register r) {
2903 testl(AMD64.rax, new CiAddress(Word, r.asValue(Word), 0)); 2903 testl(AMD64.rax, new Address(Word, r.asValue(Word), 0));
2904 } 2904 }
2905 2905
2906 @Override 2906 @Override
2907 public void align(int modulus) { 2907 public void align(int modulus) {
2908 if (codeBuffer.position() % modulus != 0) { 2908 if (codeBuffer.position() % modulus != 0) {
2938 public final void call() { 2938 public final void call() {
2939 emitByte(0xE8); 2939 emitByte(0xE8);
2940 emitInt(0); 2940 emitInt(0);
2941 } 2941 }
2942 2942
2943 public final void call(CiRegister src) { 2943 public final void call(Register src) {
2944 int encode = prefixAndEncode(src.encoding); 2944 int encode = prefixAndEncode(src.encoding);
2945 emitByte(0xFF); 2945 emitByte(0xFF);
2946 emitByte(0xD0 | encode); 2946 emitByte(0xD0 | encode);
2947 } 2947 }
2948 2948
2962 assert 0 <= i && i < 8 : "illegal stack offset"; 2962 assert 0 <= i && i < 8 : "illegal stack offset";
2963 emitByte(b1); 2963 emitByte(b1);
2964 emitByte(b2 + i); 2964 emitByte(b2 + i);
2965 } 2965 }
2966 2966
2967 public void fld(CiAddress src) { 2967 public void fld(Address src) {
2968 emitByte(0xDD); 2968 emitByte(0xDD);
2969 emitOperandHelper(rax, src); 2969 emitOperandHelper(rax, src);
2970 } 2970 }
2971 2971
2972 public void fld(int i) { 2972 public void fld(int i) {
2986 public void fyl2x() { 2986 public void fyl2x() {
2987 emitByte(0xD9); 2987 emitByte(0xD9);
2988 emitByte(0xF1); 2988 emitByte(0xF1);
2989 } 2989 }
2990 2990
2991 public void fstp(CiAddress src) { 2991 public void fstp(Address src) {
2992 emitByte(0xDD); 2992 emitByte(0xDD);
2993 emitOperandHelper(rbx, src); 2993 emitOperandHelper(rbx, src);
2994 } 2994 }
2995 2995
2996 public void fsin() { 2996 public void fsin() {
3012 emitx87(0xDD, 0xD8, i); 3012 emitx87(0xDD, 0xD8, i);
3013 } 3013 }
3014 3014
3015 @Override 3015 @Override
3016 public void bangStack(int disp) { 3016 public void bangStack(int disp) {
3017 movq(new CiAddress(target.wordKind, AMD64.RSP, -disp), AMD64.rax); 3017 movq(new Address(target.wordKind, AMD64.RSP, -disp), AMD64.rax);
3018 } 3018 }
3019 } 3019 }