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comparison src/cpu/x86/vm/x86_64.ad @ 3738:c7c81f18c834

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7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly Summary: Use ins_encode %{ %} form to encode cadd_cmpLTMask() instruction and remove unused code. Reviewed-by: never
author kvn
date Wed, 25 May 2011 21:17:07 -0700
parents b40d4fa697bf
children a3081a3a2b54
comparison
equal deleted inserted replaced
3403:7db2b9499c36 3738:c7c81f18c834
3177 emit_opcode(cbuf, 0x0F); 3177 emit_opcode(cbuf, 0x0F);
3178 emit_opcode(cbuf, 0x95); 3178 emit_opcode(cbuf, 0x95);
3179 emit_rm(cbuf, 0x3, 0x0, dstenc); 3179 emit_rm(cbuf, 0x3, 0x0, dstenc);
3180 %} 3180 %}
3181 3181
3182 enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y,
3183 rcx_RegI tmp)
3184 %{
3185 // cadd_cmpLT
3186
3187 int tmpReg = $tmp$$reg;
3188
3189 int penc = $p$$reg;
3190 int qenc = $q$$reg;
3191 int yenc = $y$$reg;
3192
3193 // subl $p,$q
3194 if (penc < 8) {
3195 if (qenc >= 8) {
3196 emit_opcode(cbuf, Assembler::REX_B);
3197 }
3198 } else {
3199 if (qenc < 8) {
3200 emit_opcode(cbuf, Assembler::REX_R);
3201 } else {
3202 emit_opcode(cbuf, Assembler::REX_RB);
3203 }
3204 }
3205 emit_opcode(cbuf, 0x2B);
3206 emit_rm(cbuf, 0x3, penc & 7, qenc & 7);
3207
3208 // sbbl $tmp, $tmp
3209 emit_opcode(cbuf, 0x1B);
3210 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
3211
3212 // andl $tmp, $y
3213 if (yenc >= 8) {
3214 emit_opcode(cbuf, Assembler::REX_B);
3215 }
3216 emit_opcode(cbuf, 0x23);
3217 emit_rm(cbuf, 0x3, tmpReg, yenc & 7);
3218
3219 // addl $p,$tmp
3220 if (penc >= 8) {
3221 emit_opcode(cbuf, Assembler::REX_R);
3222 }
3223 emit_opcode(cbuf, 0x03);
3224 emit_rm(cbuf, 0x3, penc & 7, tmpReg);
3225 %}
3226 3182
3227 // Compare the lonogs and set -1, 0, or 1 into dst 3183 // Compare the lonogs and set -1, 0, or 1 into dst
3228 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) 3184 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
3229 %{ 3185 %{
3230 int src1enc = $src1$$reg; 3186 int src1enc = $src1$$reg;
10204 ins_encode(reg_opc_imm(dst, 0x1F)); 10160 ins_encode(reg_opc_imm(dst, 0x1F));
10205 ins_pipe(ialu_reg); 10161 ins_pipe(ialu_reg);
10206 %} 10162 %}
10207 10163
10208 10164
10209 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, 10165 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rRegI tmp, rFlagsReg cr)
10210 rRegI tmp,
10211 rFlagsReg cr)
10212 %{ 10166 %{
10213 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 10167 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10214 effect(TEMP tmp, KILL cr); 10168 effect(TEMP tmp, KILL cr);
10215 10169
10216 ins_cost(400); // XXX 10170 ins_cost(400); // XXX
10217 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t" 10171 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t"
10218 "sbbl $tmp, $tmp\n\t" 10172 "sbbl $tmp, $tmp\n\t"
10219 "andl $tmp, $y\n\t" 10173 "andl $tmp, $y\n\t"
10220 "addl $p, $tmp" %} 10174 "addl $p, $tmp" %}
10221 ins_encode(enc_cmpLTP(p, q, y, tmp)); 10175 ins_encode %{
10176 Register Rp = $p$$Register;
10177 Register Rq = $q$$Register;
10178 Register Ry = $y$$Register;
10179 Register Rt = $tmp$$Register;
10180 __ subl(Rp, Rq);
10181 __ sbbl(Rt, Rt);
10182 __ andl(Rt, Ry);
10183 __ addl(Rp, Rt);
10184 %}
10222 ins_pipe(pipe_cmplt); 10185 ins_pipe(pipe_cmplt);
10223 %} 10186 %}
10224
10225 /* If I enable this, I encourage spilling in the inner loop of compress.
10226 instruct cadd_cmpLTMask_mem( rRegI p, rRegI q, memory y, rRegI tmp, rFlagsReg cr )
10227 %{
10228 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
10229 effect( TEMP tmp, KILL cr );
10230 ins_cost(400);
10231
10232 format %{ "SUB $p,$q\n\t"
10233 "SBB RCX,RCX\n\t"
10234 "AND RCX,$y\n\t"
10235 "ADD $p,RCX" %}
10236 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
10237 %}
10238 */
10239 10187
10240 //---------- FP Instructions------------------------------------------------ 10188 //---------- FP Instructions------------------------------------------------
10241 10189
10242 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) 10190 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10243 %{ 10191 %{