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comparison src/share/vm/opto/loopnode.cpp @ 4779:c8d8e124380c

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7064302: JDK7 build 147 crashed after testing my java 6-compiled web app Summary: Don't split CMove node if it's control edge is different from split region. Reviewed-by: never
author kvn
date Thu, 12 Jan 2012 12:28:59 -0800
parents 1bd45abaa507
children f457154eee8b
comparison
equal deleted inserted replaced
4778:35acf8f0a2e4 4779:c8d8e124380c
3276 Node *least = legal; // Best legal position so far 3276 Node *least = legal; // Best legal position so far
3277 while( early != legal ) { // While not at earliest legal 3277 while( early != legal ) { // While not at earliest legal
3278 #ifdef ASSERT 3278 #ifdef ASSERT
3279 if (legal->is_Start() && !early->is_Root()) { 3279 if (legal->is_Start() && !early->is_Root()) {
3280 // Bad graph. Print idom path and fail. 3280 // Bad graph. Print idom path and fail.
3281 tty->print_cr( "Bad graph detected in build_loop_late"); 3281 dump_bad_graph(n, early, LCA);
3282 tty->print("n: ");n->dump(); tty->cr();
3283 tty->print("early: ");early->dump(); tty->cr();
3284 int ct = 0;
3285 Node *dbg_legal = LCA;
3286 while(!dbg_legal->is_Start() && ct < 100) {
3287 tty->print("idom[%d] ",ct); dbg_legal->dump(); tty->cr();
3288 ct++;
3289 dbg_legal = idom(dbg_legal);
3290 }
3291 assert(false, "Bad graph detected in build_loop_late"); 3282 assert(false, "Bad graph detected in build_loop_late");
3292 } 3283 }
3293 #endif 3284 #endif
3294 // Find least loop nesting depth 3285 // Find least loop nesting depth
3295 legal = idom(legal); // Bump up the IDOM tree 3286 legal = idom(legal); // Bump up the IDOM tree
3334 // Collect inner loop bodies 3325 // Collect inner loop bodies
3335 IdealLoopTree *chosen_loop = get_loop(least); 3326 IdealLoopTree *chosen_loop = get_loop(least);
3336 if( !chosen_loop->_child ) // Inner loop? 3327 if( !chosen_loop->_child ) // Inner loop?
3337 chosen_loop->_body.push(n);// Collect inner loops 3328 chosen_loop->_body.push(n);// Collect inner loops
3338 } 3329 }
3330
3331 #ifdef ASSERT
3332 void PhaseIdealLoop::dump_bad_graph(Node* n, Node* early, Node* LCA) {
3333 tty->print_cr( "Bad graph detected in build_loop_late");
3334 tty->print("n: "); n->dump();
3335 tty->print("early(n): "); early->dump();
3336 if (n->in(0) != NULL && !n->in(0)->is_top() &&
3337 n->in(0) != early && !n->in(0)->is_Root()) {
3338 tty->print("n->in(0): "); n->in(0)->dump();
3339 }
3340 for (uint i = 1; i < n->req(); i++) {
3341 Node* in1 = n->in(i);
3342 if (in1 != NULL && in1 != n && !in1->is_top()) {
3343 tty->print("n->in(%d): ", i); in1->dump();
3344 Node* in1_early = get_ctrl(in1);
3345 tty->print("early(n->in(%d)): ", i); in1_early->dump();
3346 if (in1->in(0) != NULL && !in1->in(0)->is_top() &&
3347 in1->in(0) != in1_early && !in1->in(0)->is_Root()) {
3348 tty->print("n->in(%d)->in(0): ", i); in1->in(0)->dump();
3349 }
3350 for (uint j = 1; j < in1->req(); j++) {
3351 Node* in2 = in1->in(j);
3352 if (in2 != NULL && in2 != n && in2 != in1 && !in2->is_top()) {
3353 tty->print("n->in(%d)->in(%d): ", i, j); in2->dump();
3354 Node* in2_early = get_ctrl(in2);
3355 tty->print("early(n->in(%d)->in(%d)): ", i, j); in2_early->dump();
3356 if (in2->in(0) != NULL && !in2->in(0)->is_top() &&
3357 in2->in(0) != in2_early && !in2->in(0)->is_Root()) {
3358 tty->print("n->in(%d)->in(%d)->in(0): ", i, j); in2->in(0)->dump();
3359 }
3360 }
3361 }
3362 }
3363 }
3364 tty->cr();
3365 tty->print("LCA(n): "); LCA->dump();
3366 for (uint i = 0; i < n->outcnt(); i++) {
3367 Node* u1 = n->raw_out(i);
3368 if (u1 == n)
3369 continue;
3370 tty->print("n->out(%d): ", i); u1->dump();
3371 if (u1->is_CFG()) {
3372 for (uint j = 0; j < u1->outcnt(); j++) {
3373 Node* u2 = u1->raw_out(j);
3374 if (u2 != u1 && u2 != n && u2->is_CFG()) {
3375 tty->print("n->out(%d)->out(%d): ", i, j); u2->dump();
3376 }
3377 }
3378 } else {
3379 Node* u1_later = get_ctrl(u1);
3380 tty->print("later(n->out(%d)): ", i); u1_later->dump();
3381 if (u1->in(0) != NULL && !u1->in(0)->is_top() &&
3382 u1->in(0) != u1_later && !u1->in(0)->is_Root()) {
3383 tty->print("n->out(%d)->in(0): ", i); u1->in(0)->dump();
3384 }
3385 for (uint j = 0; j < u1->outcnt(); j++) {
3386 Node* u2 = u1->raw_out(j);
3387 if (u2 == n || u2 == u1)
3388 continue;
3389 tty->print("n->out(%d)->out(%d): ", i, j); u2->dump();
3390 if (!u2->is_CFG()) {
3391 Node* u2_later = get_ctrl(u2);
3392 tty->print("later(n->out(%d)->out(%d)): ", i, j); u2_later->dump();
3393 if (u2->in(0) != NULL && !u2->in(0)->is_top() &&
3394 u2->in(0) != u2_later && !u2->in(0)->is_Root()) {
3395 tty->print("n->out(%d)->in(0): ", i); u2->in(0)->dump();
3396 }
3397 }
3398 }
3399 }
3400 }
3401 tty->cr();
3402 int ct = 0;
3403 Node *dbg_legal = LCA;
3404 while(!dbg_legal->is_Start() && ct < 100) {
3405 tty->print("idom[%d] ",ct); dbg_legal->dump();
3406 ct++;
3407 dbg_legal = idom(dbg_legal);
3408 }
3409 tty->cr();
3410 }
3411 #endif
3339 3412
3340 #ifndef PRODUCT 3413 #ifndef PRODUCT
3341 //------------------------------dump------------------------------------------- 3414 //------------------------------dump-------------------------------------------
3342 void PhaseIdealLoop::dump( ) const { 3415 void PhaseIdealLoop::dump( ) const {
3343 ResourceMark rm; 3416 ResourceMark rm;