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8027754: Enable loop optimizations for loops with MathExact inside Reviewed-by: kvn, iveresov
author rbackman
date Thu, 23 Jan 2014 12:08:28 +0100
parents 5292439ef895
children 9e9af3aa4278 4ca6dc0799b6
comparison
equal deleted inserted replaced
14494:5292439ef895 14495:cd5d10655495
1655 1655
1656 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1656 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1657 return PTR_RBP_REG_mask(); 1657 return PTR_RBP_REG_mask();
1658 } 1658 }
1659 1659
1660 const RegMask Matcher::mathExactI_result_proj_mask() {
1661 return INT_RAX_REG_mask();
1662 }
1663
1664 const RegMask Matcher::mathExactL_result_proj_mask() {
1665 return LONG_RAX_REG_mask();
1666 }
1667
1668 const RegMask Matcher::mathExactI_flags_proj_mask() {
1669 return INT_FLAGS_mask();
1670 }
1671
1672 %} 1660 %}
1673 1661
1674 //----------ENCODING BLOCK----------------------------------------------------- 1662 //----------ENCODING BLOCK-----------------------------------------------------
1675 // This block specifies the encoding classes used by the compiler to 1663 // This block specifies the encoding classes used by the compiler to
1676 // output byte streams. Encoding classes are parameterized macros 1664 // output byte streams. Encoding classes are parameterized macros
6736 %} 6724 %}
6737 6725
6738 //----------Arithmetic Instructions-------------------------------------------- 6726 //----------Arithmetic Instructions--------------------------------------------
6739 //----------Addition Instructions---------------------------------------------- 6727 //----------Addition Instructions----------------------------------------------
6740 6728
6741 instruct addExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
6742 %{
6743 match(AddExactI dst src);
6744 effect(DEF cr);
6745
6746 format %{ "addl $dst, $src\t# addExact int" %}
6747 ins_encode %{
6748 __ addl($dst$$Register, $src$$Register);
6749 %}
6750 ins_pipe(ialu_reg_reg);
6751 %}
6752
6753 instruct addExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
6754 %{
6755 match(AddExactI dst src);
6756 effect(DEF cr);
6757
6758 format %{ "addl $dst, $src\t# addExact int" %}
6759 ins_encode %{
6760 __ addl($dst$$Register, $src$$constant);
6761 %}
6762 ins_pipe(ialu_reg_reg);
6763 %}
6764
6765 instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
6766 %{
6767 match(AddExactI dst (LoadI src));
6768 effect(DEF cr);
6769
6770 ins_cost(125); // XXX
6771 format %{ "addl $dst, $src\t# addExact int" %}
6772 ins_encode %{
6773 __ addl($dst$$Register, $src$$Address);
6774 %}
6775
6776 ins_pipe(ialu_reg_mem);
6777 %}
6778
6779 instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
6780 %{
6781 match(AddExactL dst src);
6782 effect(DEF cr);
6783
6784 format %{ "addq $dst, $src\t# addExact long" %}
6785 ins_encode %{
6786 __ addq($dst$$Register, $src$$Register);
6787 %}
6788 ins_pipe(ialu_reg_reg);
6789 %}
6790
6791 instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
6792 %{
6793 match(AddExactL dst src);
6794 effect(DEF cr);
6795
6796 format %{ "addq $dst, $src\t# addExact long" %}
6797 ins_encode %{
6798 __ addq($dst$$Register, $src$$constant);
6799 %}
6800 ins_pipe(ialu_reg_reg);
6801 %}
6802
6803 instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
6804 %{
6805 match(AddExactL dst (LoadL src));
6806 effect(DEF cr);
6807
6808 ins_cost(125); // XXX
6809 format %{ "addq $dst, $src\t# addExact long" %}
6810 ins_encode %{
6811 __ addq($dst$$Register, $src$$Address);
6812 %}
6813
6814 ins_pipe(ialu_reg_mem);
6815 %}
6816
6817 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) 6729 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6818 %{ 6730 %{
6819 match(Set dst (AddI dst src)); 6731 match(Set dst (AddI dst src));
6820 effect(KILL cr); 6732 effect(KILL cr);
6821 6733
7424 opcode(0x81); /* Opcode 81 /5 id */ 7336 opcode(0x81); /* Opcode 81 /5 id */
7425 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); 7337 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7426 ins_pipe(ialu_mem_imm); 7338 ins_pipe(ialu_mem_imm);
7427 %} 7339 %}
7428 7340
7429 instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
7430 %{
7431 match(SubExactI dst src);
7432 effect(DEF cr);
7433
7434 format %{ "subl $dst, $src\t# subExact int" %}
7435 ins_encode %{
7436 __ subl($dst$$Register, $src$$Register);
7437 %}
7438 ins_pipe(ialu_reg_reg);
7439 %}
7440
7441 instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
7442 %{
7443 match(SubExactI dst src);
7444 effect(DEF cr);
7445
7446 format %{ "subl $dst, $src\t# subExact int" %}
7447 ins_encode %{
7448 __ subl($dst$$Register, $src$$constant);
7449 %}
7450 ins_pipe(ialu_reg_reg);
7451 %}
7452
7453 instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7454 %{
7455 match(SubExactI dst (LoadI src));
7456 effect(DEF cr);
7457
7458 ins_cost(125);
7459 format %{ "subl $dst, $src\t# subExact int" %}
7460 ins_encode %{
7461 __ subl($dst$$Register, $src$$Address);
7462 %}
7463 ins_pipe(ialu_reg_mem);
7464 %}
7465
7466 instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
7467 %{
7468 match(SubExactL dst src);
7469 effect(DEF cr);
7470
7471 format %{ "subq $dst, $src\t# subExact long" %}
7472 ins_encode %{
7473 __ subq($dst$$Register, $src$$Register);
7474 %}
7475 ins_pipe(ialu_reg_reg);
7476 %}
7477
7478 instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
7479 %{
7480 match(SubExactL dst (LoadL src));
7481 effect(DEF cr);
7482
7483 format %{ "subq $dst, $src\t# subExact long" %}
7484 ins_encode %{
7485 __ subq($dst$$Register, $src$$constant);
7486 %}
7487 ins_pipe(ialu_reg_reg);
7488 %}
7489
7490 instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7491 %{
7492 match(SubExactI dst src);
7493 effect(DEF cr);
7494
7495 ins_cost(125);
7496 format %{ "subq $dst, $src\t# subExact long" %}
7497 ins_encode %{
7498 __ subq($dst$$Register, $src$$Address);
7499 %}
7500 ins_pipe(ialu_reg_mem);
7501 %}
7502
7503 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) 7341 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7504 %{ 7342 %{
7505 match(Set dst (SubL dst src)); 7343 match(Set dst (SubL dst src));
7506 effect(KILL cr); 7344 effect(KILL cr);
7507 7345
7614 opcode(0xF7, 0x03); // Opcode F7 /3 7452 opcode(0xF7, 0x03); // Opcode F7 /3
7615 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); 7453 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7616 ins_pipe(ialu_reg); 7454 ins_pipe(ialu_reg);
7617 %} 7455 %}
7618 7456
7619 instruct negExactI_rReg(rax_RegI dst, rFlagsReg cr)
7620 %{
7621 match(NegExactI dst);
7622 effect(KILL cr);
7623
7624 format %{ "negl $dst\t# negExact int" %}
7625 ins_encode %{
7626 __ negl($dst$$Register);
7627 %}
7628 ins_pipe(ialu_reg);
7629 %}
7630
7631 instruct negExactL_rReg(rax_RegL dst, rFlagsReg cr)
7632 %{
7633 match(NegExactL dst);
7634 effect(KILL cr);
7635
7636 format %{ "negq $dst\t# negExact long" %}
7637 ins_encode %{
7638 __ negq($dst$$Register);
7639 %}
7640 ins_pipe(ialu_reg);
7641 %}
7642
7643
7644 //----------Multiplication/Division Instructions------------------------------- 7457 //----------Multiplication/Division Instructions-------------------------------
7645 // Integer Multiplication Instructions 7458 // Integer Multiplication Instructions
7646 // Multiply Register 7459 // Multiply Register
7647 7460
7648 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) 7461 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7753 ins_cost(300); 7566 ins_cost(300);
7754 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} 7567 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7755 opcode(0xF7, 0x5); /* Opcode F7 /5 */ 7568 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7756 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); 7569 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7757 ins_pipe(ialu_reg_reg_alu0); 7570 ins_pipe(ialu_reg_reg_alu0);
7758 %}
7759
7760
7761 instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
7762 %{
7763 match(MulExactI dst src);
7764 effect(DEF cr);
7765
7766 ins_cost(300);
7767 format %{ "imull $dst, $src\t# mulExact int" %}
7768 ins_encode %{
7769 __ imull($dst$$Register, $src$$Register);
7770 %}
7771 ins_pipe(ialu_reg_reg_alu0);
7772 %}
7773
7774
7775 instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr)
7776 %{
7777 match(MulExactI src imm);
7778 effect(DEF cr);
7779
7780 ins_cost(300);
7781 format %{ "imull $dst, $src, $imm\t# mulExact int" %}
7782 ins_encode %{
7783 __ imull($dst$$Register, $src$$Register, $imm$$constant);
7784 %}
7785 ins_pipe(ialu_reg_reg_alu0);
7786 %}
7787
7788 instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7789 %{
7790 match(MulExactI dst (LoadI src));
7791 effect(DEF cr);
7792
7793 ins_cost(350);
7794 format %{ "imull $dst, $src\t# mulExact int" %}
7795 ins_encode %{
7796 __ imull($dst$$Register, $src$$Address);
7797 %}
7798 ins_pipe(ialu_reg_mem_alu0);
7799 %}
7800
7801 instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
7802 %{
7803 match(MulExactL dst src);
7804 effect(DEF cr);
7805
7806 ins_cost(300);
7807 format %{ "imulq $dst, $src\t# mulExact long" %}
7808 ins_encode %{
7809 __ imulq($dst$$Register, $src$$Register);
7810 %}
7811 ins_pipe(ialu_reg_reg_alu0);
7812 %}
7813
7814 instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7815 %{
7816 match(MulExactL src imm);
7817 effect(DEF cr);
7818
7819 ins_cost(300);
7820 format %{ "imulq $dst, $src, $imm\t# mulExact long" %}
7821 ins_encode %{
7822 __ imulq($dst$$Register, $src$$Register, $imm$$constant);
7823 %}
7824 ins_pipe(ialu_reg_reg_alu0);
7825 %}
7826
7827 instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
7828 %{
7829 match(MulExactL dst (LoadL src));
7830 effect(DEF cr);
7831
7832 ins_cost(350);
7833 format %{ "imulq $dst, $src\t# mulExact long" %}
7834 ins_encode %{
7835 __ imulq($dst$$Register, $src$$Address);
7836 %}
7837 ins_pipe(ialu_reg_mem_alu0);
7838 %} 7571 %}
7839 7572
7840 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, 7573 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7841 rFlagsReg cr) 7574 rFlagsReg cr)
7842 %{ 7575 %{
10441 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, 10174 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10442 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, 10175 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10443 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); 10176 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10444 %} 10177 %}
10445 ins_pipe( pipe_slow ); 10178 ins_pipe( pipe_slow );
10179 %}
10180
10181 //----------Overflow Math Instructions-----------------------------------------
10182
10183 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10184 %{
10185 match(Set cr (OverflowAddI op1 op2));
10186 effect(DEF cr, USE_KILL op1, USE op2);
10187
10188 format %{ "addl $op1, $op2\t# overflow check int" %}
10189
10190 ins_encode %{
10191 __ addl($op1$$Register, $op2$$Register);
10192 %}
10193 ins_pipe(ialu_reg_reg);
10194 %}
10195
10196 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10197 %{
10198 match(Set cr (OverflowAddI op1 op2));
10199 effect(DEF cr, USE_KILL op1, USE op2);
10200
10201 format %{ "addl $op1, $op2\t# overflow check int" %}
10202
10203 ins_encode %{
10204 __ addl($op1$$Register, $op2$$constant);
10205 %}
10206 ins_pipe(ialu_reg_reg);
10207 %}
10208
10209 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10210 %{
10211 match(Set cr (OverflowAddL op1 op2));
10212 effect(DEF cr, USE_KILL op1, USE op2);
10213
10214 format %{ "addq $op1, $op2\t# overflow check long" %}
10215 ins_encode %{
10216 __ addq($op1$$Register, $op2$$Register);
10217 %}
10218 ins_pipe(ialu_reg_reg);
10219 %}
10220
10221 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
10222 %{
10223 match(Set cr (OverflowAddL op1 op2));
10224 effect(DEF cr, USE_KILL op1, USE op2);
10225
10226 format %{ "addq $op1, $op2\t# overflow check long" %}
10227 ins_encode %{
10228 __ addq($op1$$Register, $op2$$constant);
10229 %}
10230 ins_pipe(ialu_reg_reg);
10231 %}
10232
10233 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10234 %{
10235 match(Set cr (OverflowSubI op1 op2));
10236
10237 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10238 ins_encode %{
10239 __ cmpl($op1$$Register, $op2$$Register);
10240 %}
10241 ins_pipe(ialu_reg_reg);
10242 %}
10243
10244 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10245 %{
10246 match(Set cr (OverflowSubI op1 op2));
10247
10248 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10249 ins_encode %{
10250 __ cmpl($op1$$Register, $op2$$constant);
10251 %}
10252 ins_pipe(ialu_reg_reg);
10253 %}
10254
10255 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10256 %{
10257 match(Set cr (OverflowSubL op1 op2));
10258
10259 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10260 ins_encode %{
10261 __ cmpq($op1$$Register, $op2$$Register);
10262 %}
10263 ins_pipe(ialu_reg_reg);
10264 %}
10265
10266 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10267 %{
10268 match(Set cr (OverflowSubL op1 op2));
10269
10270 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10271 ins_encode %{
10272 __ cmpq($op1$$Register, $op2$$constant);
10273 %}
10274 ins_pipe(ialu_reg_reg);
10275 %}
10276
10277 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
10278 %{
10279 match(Set cr (OverflowSubI zero op2));
10280 effect(DEF cr, USE_KILL op2);
10281
10282 format %{ "negl $op2\t# overflow check int" %}
10283 ins_encode %{
10284 __ negl($op2$$Register);
10285 %}
10286 ins_pipe(ialu_reg_reg);
10287 %}
10288
10289 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
10290 %{
10291 match(Set cr (OverflowSubL zero op2));
10292 effect(DEF cr, USE_KILL op2);
10293
10294 format %{ "negq $op2\t# overflow check long" %}
10295 ins_encode %{
10296 __ negq($op2$$Register);
10297 %}
10298 ins_pipe(ialu_reg_reg);
10299 %}
10300
10301 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10302 %{
10303 match(Set cr (OverflowMulI op1 op2));
10304 effect(DEF cr, USE_KILL op1, USE op2);
10305
10306 format %{ "imull $op1, $op2\t# overflow check int" %}
10307 ins_encode %{
10308 __ imull($op1$$Register, $op2$$Register);
10309 %}
10310 ins_pipe(ialu_reg_reg_alu0);
10311 %}
10312
10313 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
10314 %{
10315 match(Set cr (OverflowMulI op1 op2));
10316 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10317
10318 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
10319 ins_encode %{
10320 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
10321 %}
10322 ins_pipe(ialu_reg_reg_alu0);
10323 %}
10324
10325 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10326 %{
10327 match(Set cr (OverflowMulL op1 op2));
10328 effect(DEF cr, USE_KILL op1, USE op2);
10329
10330 format %{ "imulq $op1, $op2\t# overflow check long" %}
10331 ins_encode %{
10332 __ imulq($op1$$Register, $op2$$Register);
10333 %}
10334 ins_pipe(ialu_reg_reg_alu0);
10335 %}
10336
10337 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
10338 %{
10339 match(Set cr (OverflowMulL op1 op2));
10340 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10341
10342 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
10343 ins_encode %{
10344 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
10345 %}
10346 ins_pipe(ialu_reg_reg_alu0);
10446 %} 10347 %}
10447 10348
10448 10349
10449 //----------Control Flow Instructions------------------------------------------ 10350 //----------Control Flow Instructions------------------------------------------
10450 // Signed compare Instructions 10351 // Signed compare Instructions