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comparison src/cpu/x86/vm/assembler_x86.cpp @ 671:d0994e5bebce

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6822204: volatile fences should prefer lock:addl to actual mfence instructions Reviewed-by: kvn, phh
author never
date Thu, 26 Mar 2009 14:31:45 -0700
parents c89f86385056
children fbde8ec322d0
comparison
equal deleted inserted replaced
668:90a66aa50514 671:d0994e5bebce
1436 } else { 1436 } else {
1437 emit_byte(0xF0); 1437 emit_byte(0xF0);
1438 } 1438 }
1439 } 1439 }
1440 1440
1441 // Serializes memory. 1441 // Emit mfence instruction
1442 void Assembler::mfence() { 1442 void Assembler::mfence() {
1443 // Memory barriers are only needed on multiprocessors 1443 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1444 if (os::is_MP()) { 1444 emit_byte( 0x0F );
1445 if( LP64_ONLY(true ||) VM_Version::supports_sse2() ) { 1445 emit_byte( 0xAE );
1446 emit_byte( 0x0F ); // MFENCE; faster blows no regs 1446 emit_byte( 0xF0 );
1447 emit_byte( 0xAE );
1448 emit_byte( 0xF0 );
1449 } else {
1450 // All usable chips support "locked" instructions which suffice
1451 // as barriers, and are much faster than the alternative of
1452 // using cpuid instruction. We use here a locked add [esp],0.
1453 // This is conveniently otherwise a no-op except for blowing
1454 // flags (which we save and restore.)
1455 pushf(); // Save eflags register
1456 lock();
1457 addl(Address(rsp, 0), 0);// Assert the lock# signal here
1458 popf(); // Restore eflags register
1459 }
1460 }
1461 } 1447 }
1462 1448
1463 void Assembler::mov(Register dst, Register src) { 1449 void Assembler::mov(Register dst, Register src) {
1464 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 1450 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1465 } 1451 }