truffle: src/cpu/x86/vm/assembler

6822204: volatile fences should prefer lock:addl to actual mfence instructions Reviewed-by: kvn, phh

comparison

equal deleted inserted replaced

-:90a66aa50514
+:d0994e5bebce
 LoadStore  = 1 << 2,
 StoreLoad  = 1 << 1,
 LoadLoad   = 1 << 0
 };
-// Serializes memory.
+// Serializes memory and blows flags
 void membar(Membar_mask_bits order_constraint) {
-// We only have to handle StoreLoad and LoadLoad
+if (os::is_MP()) {
-if (order_constraint & StoreLoad) {
+// We only have to handle StoreLoad
-// MFENCE subsumes LFENCE
+if (order_constraint & StoreLoad) {
-mfence();
+// All usable chips support "locked" instructions which suffice
-} /* [jk] not needed currently: else if (order_constraint & LoadLoad) {
+// as barriers, and are much faster than the alternative of
-lfence();
+// using cpuid instruction. We use here a locked add [esp],0.
-} */
+// This is conveniently otherwise a no-op except for blowing
+// flags.
+// Any change to this code may need to revisit other places in
+// the code where this idiom is used, in particular the
+// orderAccess code.
+lock();
+addl(Address(rsp, 0), 0);// Assert the lock# signal here
+}
+}
 }
 void mfence();
 // Moves

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