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comparison src/cpu/sparc/vm/c1_LIRGenerator_sparc.cpp @ 1783:d5d065957597

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6953144: Tiered compilation Summary: Infrastructure for tiered compilation support (interpreter + c1 + c2) for 32 and 64 bit. Simple tiered policy implementation. Reviewed-by: kvn, never, phh, twisti
author iveresov
date Fri, 03 Sep 2010 17:51:07 -0700
parents 126ea7725993
children 3a294e483abc
comparison
equal deleted inserted replaced
1782:f353275af40e 1783:d5d065957597
1 /* 1 /*
2 * Copyright (c) 2005, 2009, Oracle and/or its affiliates. All rights reserved. 2 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 * 4 *
5 * This code is free software; you can redistribute it and/or modify it 5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as 6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
225 } else { 225 } else {
226 return new LIR_Address(base_opr, offset, type); 226 return new LIR_Address(base_opr, offset, type);
227 } 227 }
228 } 228 }
229 229
230 230 LIR_Opr LIRGenerator::load_immediate(int x, BasicType type) {
231 void LIRGenerator::increment_counter(address counter, int step) { 231 LIR_Opr r;
232 if (type == T_LONG) {
233 r = LIR_OprFact::longConst(x);
234 } else if (type == T_INT) {
235 r = LIR_OprFact::intConst(x);
236 } else {
237 ShouldNotReachHere();
238 }
239 if (!Assembler::is_simm13(x)) {
240 LIR_Opr tmp = new_register(type);
241 __ move(r, tmp);
242 return tmp;
243 }
244 return r;
245 }
246
247 void LIRGenerator::increment_counter(address counter, BasicType type, int step) {
232 LIR_Opr pointer = new_pointer_register(); 248 LIR_Opr pointer = new_pointer_register();
233 __ move(LIR_OprFact::intptrConst(counter), pointer); 249 __ move(LIR_OprFact::intptrConst(counter), pointer);
234 LIR_Address* addr = new LIR_Address(pointer, T_INT); 250 LIR_Address* addr = new LIR_Address(pointer, type);
235 increment_counter(addr, step); 251 increment_counter(addr, step);
236 } 252 }
237 253
238 void LIRGenerator::increment_counter(LIR_Address* addr, int step) { 254 void LIRGenerator::increment_counter(LIR_Address* addr, int step) {
239 LIR_Opr temp = new_register(T_INT); 255 LIR_Opr temp = new_register(addr->type());
240 __ move(addr, temp); 256 __ move(addr, temp);
241 LIR_Opr c = LIR_OprFact::intConst(step); 257 __ add(temp, load_immediate(step, addr->type()), temp);
242 if (Assembler::is_simm13(step)) {
243 __ add(temp, c, temp);
244 } else {
245 LIR_Opr temp2 = new_register(T_INT);
246 __ move(c, temp2);
247 __ add(temp, temp2, temp);
248 }
249 __ move(temp, addr); 258 __ move(temp, addr);
250 } 259 }
251
252 260
253 void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { 261 void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
254 LIR_Opr o7opr = FrameMap::O7_opr; 262 LIR_Opr o7opr = FrameMap::O7_opr;
255 __ load(new LIR_Address(base, disp, T_INT), o7opr, info); 263 __ load(new LIR_Address(base, disp, T_INT), o7opr, info);
256 __ cmp(condition, o7opr, c); 264 __ cmp(condition, o7opr, c);
609 LIRItem left(x->x(), this); 617 LIRItem left(x->x(), this);
610 LIRItem right(x->y(), this); 618 LIRItem right(x->y(), this);
611 left.load_item(); 619 left.load_item();
612 right.load_item(); 620 right.load_item();
613 LIR_Opr reg = rlock_result(x); 621 LIR_Opr reg = rlock_result(x);
614
615 if (x->x()->type()->is_float_kind()) { 622 if (x->x()->type()->is_float_kind()) {
616 Bytecodes::Code code = x->op(); 623 Bytecodes::Code code = x->op();
617 __ fcmp2int(left.result(), right.result(), reg, (code == Bytecodes::_fcmpl || code == Bytecodes::_dcmpl)); 624 __ fcmp2int(left.result(), right.result(), reg, (code == Bytecodes::_fcmpl || code == Bytecodes::_dcmpl));
618 } else if (x->x()->type()->tag() == longTag) { 625 } else if (x->x()->type()->tag() == longTag) {
619 __ lcmp2int(left.result(), right.result(), reg); 626 __ lcmp2int(left.result(), right.result(), reg);
1087 set_no_result(x); 1094 set_no_result(x);
1088 1095
1089 // add safepoint before generating condition code so it can be recomputed 1096 // add safepoint before generating condition code so it can be recomputed
1090 if (x->is_safepoint()) { 1097 if (x->is_safepoint()) {
1091 // increment backedge counter if needed 1098 // increment backedge counter if needed
1092 increment_backedge_counter(state_for(x, x->state_before())); 1099 increment_backedge_counter(state_for(x, x->state_before()), x->profiled_bci());
1093
1094 __ safepoint(new_register(T_INT), state_for(x, x->state_before())); 1100 __ safepoint(new_register(T_INT), state_for(x, x->state_before()));
1095 } 1101 }
1096 1102
1097 __ cmp(lir_cond(cond), left, right); 1103 __ cmp(lir_cond(cond), left, right);
1104 // Generate branch profiling. Profiling code doesn't kill flags.
1098 profile_branch(x, cond); 1105 profile_branch(x, cond);
1099 move_to_phi(x->state()); 1106 move_to_phi(x->state());
1100 if (x->x()->type()->is_float_kind()) { 1107 if (x->x()->type()->is_float_kind()) {
1101 __ branch(lir_cond(cond), right->type(), x->tsux(), x->usux()); 1108 __ branch(lir_cond(cond), right->type(), x->tsux(), x->usux());
1102 } else { 1109 } else {