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comparison src/cpu/x86/vm/assembler_x86.hpp @ 304:dc7f315e41f7

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5108146: Merge i486 and amd64 cpu directories 6459804: Want client (c1) compiler for x86_64 (amd64) for faster start-up Reviewed-by: kvn
author never
date Wed, 27 Aug 2008 00:21:55 -0700
parents src/cpu/x86/vm/assembler_x86_32.hpp@d1605aabd0a1
children f8199438385b
comparison
equal deleted inserted replaced
303:fa4d1d240383 304:dc7f315e41f7
1 /*
2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 class BiasedLockingCounters;
26
27 // Contains all the definitions needed for x86 assembly code generation.
28
29 // Calling convention
30 class Argument VALUE_OBJ_CLASS_SPEC {
31 public:
32 enum {
33 #ifdef _LP64
34 #ifdef _WIN64
35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
37 #else
38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
40 #endif // _WIN64
41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
43 #else
44 n_register_parameters = 0 // 0 registers used to pass arguments
45 #endif // _LP64
46 };
47 };
48
49
50 #ifdef _LP64
51 // Symbolically name the register arguments used by the c calling convention.
52 // Windows is different from linux/solaris. So much for standards...
53
54 #ifdef _WIN64
55
56 REGISTER_DECLARATION(Register, c_rarg0, rcx);
57 REGISTER_DECLARATION(Register, c_rarg1, rdx);
58 REGISTER_DECLARATION(Register, c_rarg2, r8);
59 REGISTER_DECLARATION(Register, c_rarg3, r9);
60
61 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
62 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
63 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
64 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
65
66 #else
67
68 REGISTER_DECLARATION(Register, c_rarg0, rdi);
69 REGISTER_DECLARATION(Register, c_rarg1, rsi);
70 REGISTER_DECLARATION(Register, c_rarg2, rdx);
71 REGISTER_DECLARATION(Register, c_rarg3, rcx);
72 REGISTER_DECLARATION(Register, c_rarg4, r8);
73 REGISTER_DECLARATION(Register, c_rarg5, r9);
74
75 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
76 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
77 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
78 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
79 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
80 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
81 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
82 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
83
84 #endif // _WIN64
85
86 // Symbolically name the register arguments used by the Java calling convention.
87 // We have control over the convention for java so we can do what we please.
88 // What pleases us is to offset the java calling convention so that when
89 // we call a suitable jni method the arguments are lined up and we don't
90 // have to do little shuffling. A suitable jni method is non-static and a
91 // small number of arguments (two fewer args on windows)
92 //
93 // |-------------------------------------------------------|
94 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
95 // |-------------------------------------------------------|
96 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
97 // | rdi rsi rdx rcx r8 r9 | solaris/linux
98 // |-------------------------------------------------------|
99 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
100 // |-------------------------------------------------------|
101
102 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
103 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
104 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
105 // Windows runs out of register args here
106 #ifdef _WIN64
107 REGISTER_DECLARATION(Register, j_rarg3, rdi);
108 REGISTER_DECLARATION(Register, j_rarg4, rsi);
109 #else
110 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
111 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
112 #endif /* _WIN64 */
113 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
114
115 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
116 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
117 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
118 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
119 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
120 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
121 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
122 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
123
124 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
125 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
126
127 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
128 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
129
130 #else
131 // rscratch1 will apear in 32bit code that is dead but of course must compile
132 // Using noreg ensures if the dead code is incorrectly live and executed it
133 // will cause an assertion failure
134 #define rscratch1 noreg
135
136 #endif // _LP64
137
138 // Address is an abstraction used to represent a memory location
139 // using any of the amd64 addressing modes with one object.
140 //
141 // Note: A register location is represented via a Register, not
142 // via an address for efficiency & simplicity reasons.
143
144 class ArrayAddress;
145
146 class Address VALUE_OBJ_CLASS_SPEC {
147 public:
148 enum ScaleFactor {
149 no_scale = -1,
150 times_1 = 0,
151 times_2 = 1,
152 times_4 = 2,
153 times_8 = 3,
154 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
155 };
156
157 private:
158 Register _base;
159 Register _index;
160 ScaleFactor _scale;
161 int _disp;
162 RelocationHolder _rspec;
163
164 // Easily misused constructors make them private
165 // %%% can we make these go away?
166 NOT_LP64(Address(address loc, RelocationHolder spec);)
167 Address(int disp, address loc, relocInfo::relocType rtype);
168 Address(int disp, address loc, RelocationHolder spec);
169
170 public:
171
172 int disp() { return _disp; }
173 // creation
174 Address()
175 : _base(noreg),
176 _index(noreg),
177 _scale(no_scale),
178 _disp(0) {
179 }
180
181 // No default displacement otherwise Register can be implicitly
182 // converted to 0(Register) which is quite a different animal.
183
184 Address(Register base, int disp)
185 : _base(base),
186 _index(noreg),
187 _scale(no_scale),
188 _disp(disp) {
189 }
190
191 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
192 : _base (base),
193 _index(index),
194 _scale(scale),
195 _disp (disp) {
196 assert(!index->is_valid() == (scale == Address::no_scale),
197 "inconsistent address");
198 }
199
200 // The following two overloads are used in connection with the
201 // ByteSize type (see sizes.hpp). They simplify the use of
202 // ByteSize'd arguments in assembly code. Note that their equivalent
203 // for the optimized build are the member functions with int disp
204 // argument since ByteSize is mapped to an int type in that case.
205 //
206 // Note: DO NOT introduce similar overloaded functions for WordSize
207 // arguments as in the optimized mode, both ByteSize and WordSize
208 // are mapped to the same type and thus the compiler cannot make a
209 // distinction anymore (=> compiler errors).
210
211 #ifdef ASSERT
212 Address(Register base, ByteSize disp)
213 : _base(base),
214 _index(noreg),
215 _scale(no_scale),
216 _disp(in_bytes(disp)) {
217 }
218
219 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
220 : _base(base),
221 _index(index),
222 _scale(scale),
223 _disp(in_bytes(disp)) {
224 assert(!index->is_valid() == (scale == Address::no_scale),
225 "inconsistent address");
226 }
227 #endif // ASSERT
228
229 // accessors
230 bool uses(Register reg) const {
231 return _base == reg || _index == reg;
232 }
233
234 // Convert the raw encoding form into the form expected by the constructor for
235 // Address. An index of 4 (rsp) corresponds to having no index, so convert
236 // that to noreg for the Address constructor.
237 static Address make_raw(int base, int index, int scale, int disp);
238
239 static Address make_array(ArrayAddress);
240
241
242 private:
243 bool base_needs_rex() const {
244 return _base != noreg && _base->encoding() >= 8;
245 }
246
247 bool index_needs_rex() const {
248 return _index != noreg &&_index->encoding() >= 8;
249 }
250
251 relocInfo::relocType reloc() const { return _rspec.type(); }
252
253 friend class Assembler;
254 friend class MacroAssembler;
255 friend class LIR_Assembler; // base/index/scale/disp
256 };
257
258 //
259 // AddressLiteral has been split out from Address because operands of this type
260 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
261 // the few instructions that need to deal with address literals are unique and the
262 // MacroAssembler does not have to implement every instruction in the Assembler
263 // in order to search for address literals that may need special handling depending
264 // on the instruction and the platform. As small step on the way to merging i486/amd64
265 // directories.
266 //
267 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
268 friend class ArrayAddress;
269 RelocationHolder _rspec;
270 // Typically we use AddressLiterals we want to use their rval
271 // However in some situations we want the lval (effect address) of the item.
272 // We provide a special factory for making those lvals.
273 bool _is_lval;
274
275 // If the target is far we'll need to load the ea of this to
276 // a register to reach it. Otherwise if near we can do rip
277 // relative addressing.
278
279 address _target;
280
281 protected:
282 // creation
283 AddressLiteral()
284 : _is_lval(false),
285 _target(NULL)
286 {}
287
288 public:
289
290
291 AddressLiteral(address target, relocInfo::relocType rtype);
292
293 AddressLiteral(address target, RelocationHolder const& rspec)
294 : _rspec(rspec),
295 _is_lval(false),
296 _target(target)
297 {}
298
299 AddressLiteral addr() {
300 AddressLiteral ret = *this;
301 ret._is_lval = true;
302 return ret;
303 }
304
305
306 private:
307
308 address target() { return _target; }
309 bool is_lval() { return _is_lval; }
310
311 relocInfo::relocType reloc() const { return _rspec.type(); }
312 const RelocationHolder& rspec() const { return _rspec; }
313
314 friend class Assembler;
315 friend class MacroAssembler;
316 friend class Address;
317 friend class LIR_Assembler;
318 };
319
320 // Convience classes
321 class RuntimeAddress: public AddressLiteral {
322
323 public:
324
325 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
326
327 };
328
329 class OopAddress: public AddressLiteral {
330
331 public:
332
333 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
334
335 };
336
337 class ExternalAddress: public AddressLiteral {
338
339 public:
340
341 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
342
343 };
344
345 class InternalAddress: public AddressLiteral {
346
347 public:
348
349 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
350
351 };
352
353 // x86 can do array addressing as a single operation since disp can be an absolute
354 // address amd64 can't. We create a class that expresses the concept but does extra
355 // magic on amd64 to get the final result
356
357 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
358 private:
359
360 AddressLiteral _base;
361 Address _index;
362
363 public:
364
365 ArrayAddress() {};
366 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
367 AddressLiteral base() { return _base; }
368 Address index() { return _index; }
369
370 };
371
372 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
373
374 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
375 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
376 // is what you get. The Assembler is generating code into a CodeBuffer.
377
378 class Assembler : public AbstractAssembler {
379 friend class AbstractAssembler; // for the non-virtual hack
380 friend class LIR_Assembler; // as_Address()
381 friend class StubGenerator;
382
383 public:
384 enum Condition { // The x86 condition codes used for conditional jumps/moves.
385 zero = 0x4,
386 notZero = 0x5,
387 equal = 0x4,
388 notEqual = 0x5,
389 less = 0xc,
390 lessEqual = 0xe,
391 greater = 0xf,
392 greaterEqual = 0xd,
393 below = 0x2,
394 belowEqual = 0x6,
395 above = 0x7,
396 aboveEqual = 0x3,
397 overflow = 0x0,
398 noOverflow = 0x1,
399 carrySet = 0x2,
400 carryClear = 0x3,
401 negative = 0x8,
402 positive = 0x9,
403 parity = 0xa,
404 noParity = 0xb
405 };
406
407 enum Prefix {
408 // segment overrides
409 CS_segment = 0x2e,
410 SS_segment = 0x36,
411 DS_segment = 0x3e,
412 ES_segment = 0x26,
413 FS_segment = 0x64,
414 GS_segment = 0x65,
415
416 REX = 0x40,
417
418 REX_B = 0x41,
419 REX_X = 0x42,
420 REX_XB = 0x43,
421 REX_R = 0x44,
422 REX_RB = 0x45,
423 REX_RX = 0x46,
424 REX_RXB = 0x47,
425
426 REX_W = 0x48,
427
428 REX_WB = 0x49,
429 REX_WX = 0x4A,
430 REX_WXB = 0x4B,
431 REX_WR = 0x4C,
432 REX_WRB = 0x4D,
433 REX_WRX = 0x4E,
434 REX_WRXB = 0x4F
435 };
436
437 enum WhichOperand {
438 // input to locate_operand, and format code for relocations
439 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
440 disp32_operand = 1, // embedded 32-bit displacement or address
441 call32_operand = 2, // embedded 32-bit self-relative displacement
442 #ifndef _LP64
443 _WhichOperand_limit = 3
444 #else
445 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
446 _WhichOperand_limit = 4
447 #endif
448 };
449
450
451
452 // NOTE: The general philopsophy of the declarations here is that 64bit versions
453 // of instructions are freely declared without the need for wrapping them an ifdef.
454 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
455 // In the .cpp file the implementations are wrapped so that they are dropped out
456 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
457 // to the size it was prior to merging up the 32bit and 64bit assemblers.
458 //
459 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
460 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
461
462 private:
463
464
465 // 64bit prefixes
466 int prefix_and_encode(int reg_enc, bool byteinst = false);
467 int prefixq_and_encode(int reg_enc);
468
469 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
470 int prefixq_and_encode(int dst_enc, int src_enc);
471
472 void prefix(Register reg);
473 void prefix(Address adr);
474 void prefixq(Address adr);
475
476 void prefix(Address adr, Register reg, bool byteinst = false);
477 void prefixq(Address adr, Register reg);
478
479 void prefix(Address adr, XMMRegister reg);
480
481 void prefetch_prefix(Address src);
482
483 // Helper functions for groups of instructions
484 void emit_arith_b(int op1, int op2, Register dst, int imm8);
485
486 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
487 // only 32bit??
488 void emit_arith(int op1, int op2, Register dst, jobject obj);
489 void emit_arith(int op1, int op2, Register dst, Register src);
490
491 void emit_operand(Register reg,
492 Register base, Register index, Address::ScaleFactor scale,
493 int disp,
494 RelocationHolder const& rspec,
495 int rip_relative_correction = 0);
496
497 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
498
499 // operands that only take the original 32bit registers
500 void emit_operand32(Register reg, Address adr);
501
502 void emit_operand(XMMRegister reg,
503 Register base, Register index, Address::ScaleFactor scale,
504 int disp,
505 RelocationHolder const& rspec);
506
507 void emit_operand(XMMRegister reg, Address adr);
508
509 void emit_operand(MMXRegister reg, Address adr);
510
511 // workaround gcc (3.2.1-7) bug
512 void emit_operand(Address adr, MMXRegister reg);
513
514
515 // Immediate-to-memory forms
516 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
517
518 void emit_farith(int b1, int b2, int i);
519
520
521 protected:
522 #ifdef ASSERT
523 void check_relocation(RelocationHolder const& rspec, int format);
524 #endif
525
526 inline void emit_long64(jlong x);
527
528 void emit_data(jint data, relocInfo::relocType rtype, int format);
529 void emit_data(jint data, RelocationHolder const& rspec, int format);
530 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
531 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
532
533
534 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
535
536 // These are all easily abused and hence protected
537
538 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec, int format = 0);
539
540 // 32BIT ONLY SECTION
541 #ifndef _LP64
542 // Make these disappear in 64bit mode since they would never be correct
543 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
544 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
545
546 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
547
548 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
549 #else
550 // 64BIT ONLY SECTION
551 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
552 #endif // _LP64
553
554 // These are unique in that we are ensured by the caller that the 32bit
555 // relative in these instructions will always be able to reach the potentially
556 // 64bit address described by entry. Since they can take a 64bit address they
557 // don't have the 32 suffix like the other instructions in this class.
558
559 void call_literal(address entry, RelocationHolder const& rspec);
560 void jmp_literal(address entry, RelocationHolder const& rspec);
561
562 // Avoid using directly section
563 // Instructions in this section are actually usable by anyone without danger
564 // of failure but have performance issues that are addressed my enhanced
565 // instructions which will do the proper thing base on the particular cpu.
566 // We protect them because we don't trust you...
567
568 // Don't use next inc() and dec() methods directly. INC & DEC instructions
569 // could cause a partial flag stall since they don't set CF flag.
570 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
571 // which call inc() & dec() or add() & sub() in accordance with
572 // the product flag UseIncDec value.
573
574 void decl(Register dst);
575 void decl(Address dst);
576 void decq(Register dst);
577 void decq(Address dst);
578
579 void incl(Register dst);
580 void incl(Address dst);
581 void incq(Register dst);
582 void incq(Address dst);
583
584 // New cpus require use of movsd and movss to avoid partial register stall
585 // when loading from memory. But for old Opteron use movlpd instead of movsd.
586 // The selection is done in MacroAssembler::movdbl() and movflt().
587
588 // Move Scalar Single-Precision Floating-Point Values
589 void movss(XMMRegister dst, Address src);
590 void movss(XMMRegister dst, XMMRegister src);
591 void movss(Address dst, XMMRegister src);
592
593 // Move Scalar Double-Precision Floating-Point Values
594 void movsd(XMMRegister dst, Address src);
595 void movsd(XMMRegister dst, XMMRegister src);
596 void movsd(Address dst, XMMRegister src);
597 void movlpd(XMMRegister dst, Address src);
598
599 // New cpus require use of movaps and movapd to avoid partial register stall
600 // when moving between registers.
601 void movaps(XMMRegister dst, XMMRegister src);
602 void movapd(XMMRegister dst, XMMRegister src);
603
604 // End avoid using directly
605
606
607 // Instruction prefixes
608 void prefix(Prefix p);
609
610 public:
611
612 // Creation
613 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
614
615 // Decoding
616 static address locate_operand(address inst, WhichOperand which);
617 static address locate_next_instruction(address inst);
618
619 // Utilities
620
621 #ifdef _LP64
622 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); }
623 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; }
624 #else
625 static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) ) <= x && x < ( 1 << (nbits-1) ); }
626 static bool is_simm32(int32_t x) { return true; }
627 #endif // LP64
628
629 // Generic instructions
630 // Does 32bit or 64bit as needed for the platform. In some sense these
631 // belong in macro assembler but there is no need for both varieties to exist
632
633 void lea(Register dst, Address src);
634
635 void mov(Register dst, Register src);
636
637 void pusha();
638 void popa();
639
640 void pushf();
641 void popf();
642
643 void push(int32_t imm32);
644
645 void push(Register src);
646
647 void pop(Register dst);
648
649 // These are dummies to prevent surprise implicit conversions to Register
650 void push(void* v);
651 void pop(void* v);
652
653
654 // These do register sized moves/scans
655 void rep_mov();
656 void rep_set();
657 void repne_scan();
658 #ifdef _LP64
659 void repne_scanl();
660 #endif
661
662 // Vanilla instructions in lexical order
663
664 void adcl(Register dst, int32_t imm32);
665 void adcl(Register dst, Address src);
666 void adcl(Register dst, Register src);
667
668 void adcq(Register dst, int32_t imm32);
669 void adcq(Register dst, Address src);
670 void adcq(Register dst, Register src);
671
672
673 void addl(Address dst, int32_t imm32);
674 void addl(Address dst, Register src);
675 void addl(Register dst, int32_t imm32);
676 void addl(Register dst, Address src);
677 void addl(Register dst, Register src);
678
679 void addq(Address dst, int32_t imm32);
680 void addq(Address dst, Register src);
681 void addq(Register dst, int32_t imm32);
682 void addq(Register dst, Address src);
683 void addq(Register dst, Register src);
684
685
686 void addr_nop_4();
687 void addr_nop_5();
688 void addr_nop_7();
689 void addr_nop_8();
690
691 // Add Scalar Double-Precision Floating-Point Values
692 void addsd(XMMRegister dst, Address src);
693 void addsd(XMMRegister dst, XMMRegister src);
694
695 // Add Scalar Single-Precision Floating-Point Values
696 void addss(XMMRegister dst, Address src);
697 void addss(XMMRegister dst, XMMRegister src);
698
699 void andl(Register dst, int32_t imm32);
700 void andl(Register dst, Address src);
701 void andl(Register dst, Register src);
702
703 void andq(Register dst, int32_t imm32);
704 void andq(Register dst, Address src);
705 void andq(Register dst, Register src);
706
707
708 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
709 void andpd(XMMRegister dst, Address src);
710 void andpd(XMMRegister dst, XMMRegister src);
711
712 void bswapl(Register reg);
713
714 void bswapq(Register reg);
715
716 void call(Label& L, relocInfo::relocType rtype);
717 void call(Register reg); // push pc; pc <- reg
718 void call(Address adr); // push pc; pc <- adr
719
720 void cdql();
721
722 void cdqq();
723
724 void cld() { emit_byte(0xfc); }
725
726 void clflush(Address adr);
727
728 void cmovl(Condition cc, Register dst, Register src);
729 void cmovl(Condition cc, Register dst, Address src);
730
731 void cmovq(Condition cc, Register dst, Register src);
732 void cmovq(Condition cc, Register dst, Address src);
733
734
735 void cmpb(Address dst, int imm8);
736
737 void cmpl(Address dst, int32_t imm32);
738
739 void cmpl(Register dst, int32_t imm32);
740 void cmpl(Register dst, Register src);
741 void cmpl(Register dst, Address src);
742
743 void cmpq(Address dst, int32_t imm32);
744 void cmpq(Address dst, Register src);
745
746 void cmpq(Register dst, int32_t imm32);
747 void cmpq(Register dst, Register src);
748 void cmpq(Register dst, Address src);
749
750 // these are dummies used to catch attempting to convert NULL to Register
751 void cmpl(Register dst, void* junk); // dummy
752 void cmpq(Register dst, void* junk); // dummy
753
754 void cmpw(Address dst, int imm16);
755
756 void cmpxchg8 (Address adr);
757
758 void cmpxchgl(Register reg, Address adr);
759
760 void cmpxchgq(Register reg, Address adr);
761
762 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
763 void comisd(XMMRegister dst, Address src);
764
765 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
766 void comiss(XMMRegister dst, Address src);
767
768 // Identify processor type and features
769 void cpuid() {
770 emit_byte(0x0F);
771 emit_byte(0xA2);
772 }
773
774 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
775 void cvtsd2ss(XMMRegister dst, XMMRegister src);
776
777 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
778 void cvtsi2sdl(XMMRegister dst, Register src);
779 void cvtsi2sdq(XMMRegister dst, Register src);
780
781 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
782 void cvtsi2ssl(XMMRegister dst, Register src);
783 void cvtsi2ssq(XMMRegister dst, Register src);
784
785 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
786 void cvtdq2pd(XMMRegister dst, XMMRegister src);
787
788 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
789 void cvtdq2ps(XMMRegister dst, XMMRegister src);
790
791 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
792 void cvtss2sd(XMMRegister dst, XMMRegister src);
793
794 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
795 void cvttsd2sil(Register dst, Address src);
796 void cvttsd2sil(Register dst, XMMRegister src);
797 void cvttsd2siq(Register dst, XMMRegister src);
798
799 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
800 void cvttss2sil(Register dst, XMMRegister src);
801 void cvttss2siq(Register dst, XMMRegister src);
802
803 // Divide Scalar Double-Precision Floating-Point Values
804 void divsd(XMMRegister dst, Address src);
805 void divsd(XMMRegister dst, XMMRegister src);
806
807 // Divide Scalar Single-Precision Floating-Point Values
808 void divss(XMMRegister dst, Address src);
809 void divss(XMMRegister dst, XMMRegister src);
810
811 void emms();
812
813 void fabs();
814
815 void fadd(int i);
816
817 void fadd_d(Address src);
818 void fadd_s(Address src);
819
820 // "Alternate" versions of x87 instructions place result down in FPU
821 // stack instead of on TOS
822
823 void fadda(int i); // "alternate" fadd
824 void faddp(int i = 1);
825
826 void fchs();
827
828 void fcom(int i);
829
830 void fcomp(int i = 1);
831 void fcomp_d(Address src);
832 void fcomp_s(Address src);
833
834 void fcompp();
835
836 void fcos();
837
838 void fdecstp();
839
840 void fdiv(int i);
841 void fdiv_d(Address src);
842 void fdivr_s(Address src);
843 void fdiva(int i); // "alternate" fdiv
844 void fdivp(int i = 1);
845
846 void fdivr(int i);
847 void fdivr_d(Address src);
848 void fdiv_s(Address src);
849
850 void fdivra(int i); // "alternate" reversed fdiv
851
852 void fdivrp(int i = 1);
853
854 void ffree(int i = 0);
855
856 void fild_d(Address adr);
857 void fild_s(Address adr);
858
859 void fincstp();
860
861 void finit();
862
863 void fist_s (Address adr);
864 void fistp_d(Address adr);
865 void fistp_s(Address adr);
866
867 void fld1();
868
869 void fld_d(Address adr);
870 void fld_s(Address adr);
871 void fld_s(int index);
872 void fld_x(Address adr); // extended-precision (80-bit) format
873
874 void fldcw(Address src);
875
876 void fldenv(Address src);
877
878 void fldlg2();
879
880 void fldln2();
881
882 void fldz();
883
884 void flog();
885 void flog10();
886
887 void fmul(int i);
888
889 void fmul_d(Address src);
890 void fmul_s(Address src);
891
892 void fmula(int i); // "alternate" fmul
893
894 void fmulp(int i = 1);
895
896 void fnsave(Address dst);
897
898 void fnstcw(Address src);
899
900 void fnstsw_ax();
901
902 void fprem();
903 void fprem1();
904
905 void frstor(Address src);
906
907 void fsin();
908
909 void fsqrt();
910
911 void fst_d(Address adr);
912 void fst_s(Address adr);
913
914 void fstp_d(Address adr);
915 void fstp_d(int index);
916 void fstp_s(Address adr);
917 void fstp_x(Address adr); // extended-precision (80-bit) format
918
919 void fsub(int i);
920 void fsub_d(Address src);
921 void fsub_s(Address src);
922
923 void fsuba(int i); // "alternate" fsub
924
925 void fsubp(int i = 1);
926
927 void fsubr(int i);
928 void fsubr_d(Address src);
929 void fsubr_s(Address src);
930
931 void fsubra(int i); // "alternate" reversed fsub
932
933 void fsubrp(int i = 1);
934
935 void ftan();
936
937 void ftst();
938
939 void fucomi(int i = 1);
940 void fucomip(int i = 1);
941
942 void fwait();
943
944 void fxch(int i = 1);
945
946 void fxrstor(Address src);
947
948 void fxsave(Address dst);
949
950 void fyl2x();
951
952 void hlt();
953
954 void idivl(Register src);
955
956 void idivq(Register src);
957
958 void imull(Register dst, Register src);
959 void imull(Register dst, Register src, int value);
960
961 void imulq(Register dst, Register src);
962 void imulq(Register dst, Register src, int value);
963
964
965 // jcc is the generic conditional branch generator to run-
966 // time routines, jcc is used for branches to labels. jcc
967 // takes a branch opcode (cc) and a label (L) and generates
968 // either a backward branch or a forward branch and links it
969 // to the label fixup chain. Usage:
970 //
971 // Label L; // unbound label
972 // jcc(cc, L); // forward branch to unbound label
973 // bind(L); // bind label to the current pc
974 // jcc(cc, L); // backward branch to bound label
975 // bind(L); // illegal: a label may be bound only once
976 //
977 // Note: The same Label can be used for forward and backward branches
978 // but it may be bound only once.
979
980 void jcc(Condition cc, Label& L,
981 relocInfo::relocType rtype = relocInfo::none);
982
983 // Conditional jump to a 8-bit offset to L.
984 // WARNING: be very careful using this for forward jumps. If the label is
985 // not bound within an 8-bit offset of this instruction, a run-time error
986 // will occur.
987 void jccb(Condition cc, Label& L);
988
989 void jmp(Address entry); // pc <- entry
990
991 // Label operations & relative jumps (PPUM Appendix D)
992 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L
993
994 void jmp(Register entry); // pc <- entry
995
996 // Unconditional 8-bit offset jump to L.
997 // WARNING: be very careful using this for forward jumps. If the label is
998 // not bound within an 8-bit offset of this instruction, a run-time error
999 // will occur.
1000 void jmpb(Label& L);
1001
1002 void ldmxcsr( Address src );
1003
1004 void leal(Register dst, Address src);
1005
1006 void leaq(Register dst, Address src);
1007
1008 void lfence() {
1009 emit_byte(0x0F);
1010 emit_byte(0xAE);
1011 emit_byte(0xE8);
1012 }
1013
1014 void lock();
1015
1016 enum Membar_mask_bits {
1017 StoreStore = 1 << 3,
1018 LoadStore = 1 << 2,
1019 StoreLoad = 1 << 1,
1020 LoadLoad = 1 << 0
1021 };
1022
1023 // Serializes memory.
1024 void membar(Membar_mask_bits order_constraint) {
1025 // We only have to handle StoreLoad and LoadLoad
1026 if (order_constraint & StoreLoad) {
1027 // MFENCE subsumes LFENCE
1028 mfence();
1029 } /* [jk] not needed currently: else if (order_constraint & LoadLoad) {
1030 lfence();
1031 } */
1032 }
1033
1034 void mfence();
1035
1036 // Moves
1037
1038 void mov64(Register dst, int64_t imm64);
1039
1040 void movb(Address dst, Register src);
1041 void movb(Address dst, int imm8);
1042 void movb(Register dst, Address src);
1043
1044 void movdl(XMMRegister dst, Register src);
1045 void movdl(Register dst, XMMRegister src);
1046
1047 // Move Double Quadword
1048 void movdq(XMMRegister dst, Register src);
1049 void movdq(Register dst, XMMRegister src);
1050
1051 // Move Aligned Double Quadword
1052 void movdqa(Address dst, XMMRegister src);
1053 void movdqa(XMMRegister dst, Address src);
1054 void movdqa(XMMRegister dst, XMMRegister src);
1055
1056 void movl(Register dst, int32_t imm32);
1057 void movl(Address dst, int32_t imm32);
1058 void movl(Register dst, Register src);
1059 void movl(Register dst, Address src);
1060 void movl(Address dst, Register src);
1061
1062 // These dummies prevent using movl from converting a zero (like NULL) into Register
1063 // by giving the compiler two choices it can't resolve
1064
1065 void movl(Address dst, void* junk);
1066 void movl(Register dst, void* junk);
1067
1068 #ifdef _LP64
1069 void movq(Register dst, Register src);
1070 void movq(Register dst, Address src);
1071 void movq(Address dst, Register src);
1072 #endif
1073
1074 void movq(Address dst, MMXRegister src );
1075 void movq(MMXRegister dst, Address src );
1076
1077 #ifdef _LP64
1078 // These dummies prevent using movq from converting a zero (like NULL) into Register
1079 // by giving the compiler two choices it can't resolve
1080
1081 void movq(Address dst, void* dummy);
1082 void movq(Register dst, void* dummy);
1083 #endif
1084
1085 // Move Quadword
1086 void movq(Address dst, XMMRegister src);
1087 void movq(XMMRegister dst, Address src);
1088
1089 void movsbl(Register dst, Address src);
1090 void movsbl(Register dst, Register src);
1091
1092 #ifdef _LP64
1093 // Move signed 32bit immediate to 64bit extending sign
1094 void movslq(Address dst, int32_t imm64);
1095 void movslq(Register dst, int32_t imm64);
1096
1097 void movslq(Register dst, Address src);
1098 void movslq(Register dst, Register src);
1099 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1100 #endif
1101
1102 void movswl(Register dst, Address src);
1103 void movswl(Register dst, Register src);
1104
1105 void movw(Address dst, int imm16);
1106 void movw(Register dst, Address src);
1107 void movw(Address dst, Register src);
1108
1109 void movzbl(Register dst, Address src);
1110 void movzbl(Register dst, Register src);
1111
1112 void movzwl(Register dst, Address src);
1113 void movzwl(Register dst, Register src);
1114
1115 void mull(Address src);
1116 void mull(Register src);
1117
1118 // Multiply Scalar Double-Precision Floating-Point Values
1119 void mulsd(XMMRegister dst, Address src);
1120 void mulsd(XMMRegister dst, XMMRegister src);
1121
1122 // Multiply Scalar Single-Precision Floating-Point Values
1123 void mulss(XMMRegister dst, Address src);
1124 void mulss(XMMRegister dst, XMMRegister src);
1125
1126 void negl(Register dst);
1127
1128 #ifdef _LP64
1129 void negq(Register dst);
1130 #endif
1131
1132 void nop(int i = 1);
1133
1134 void notl(Register dst);
1135
1136 #ifdef _LP64
1137 void notq(Register dst);
1138 #endif
1139
1140 void orl(Address dst, int32_t imm32);
1141 void orl(Register dst, int32_t imm32);
1142 void orl(Register dst, Address src);
1143 void orl(Register dst, Register src);
1144
1145 void orq(Address dst, int32_t imm32);
1146 void orq(Register dst, int32_t imm32);
1147 void orq(Register dst, Address src);
1148 void orq(Register dst, Register src);
1149
1150 void popl(Address dst);
1151
1152 #ifdef _LP64
1153 void popq(Address dst);
1154 #endif
1155
1156 // Prefetches (SSE, SSE2, 3DNOW only)
1157
1158 void prefetchnta(Address src);
1159 void prefetchr(Address src);
1160 void prefetcht0(Address src);
1161 void prefetcht1(Address src);
1162 void prefetcht2(Address src);
1163 void prefetchw(Address src);
1164
1165 // Shuffle Packed Doublewords
1166 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1167 void pshufd(XMMRegister dst, Address src, int mode);
1168
1169 // Shuffle Packed Low Words
1170 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1171 void pshuflw(XMMRegister dst, Address src, int mode);
1172
1173 // Shift Right Logical Quadword Immediate
1174 void psrlq(XMMRegister dst, int shift);
1175
1176 // Interleave Low Bytes
1177 void punpcklbw(XMMRegister dst, XMMRegister src);
1178
1179 void pushl(Address src);
1180
1181 void pushq(Address src);
1182
1183 // Xor Packed Byte Integer Values
1184 void pxor(XMMRegister dst, Address src);
1185 void pxor(XMMRegister dst, XMMRegister src);
1186
1187 void rcll(Register dst, int imm8);
1188
1189 void rclq(Register dst, int imm8);
1190
1191 void ret(int imm16);
1192
1193 void sahf();
1194
1195 void sarl(Register dst, int imm8);
1196 void sarl(Register dst);
1197
1198 void sarq(Register dst, int imm8);
1199 void sarq(Register dst);
1200
1201 void sbbl(Address dst, int32_t imm32);
1202 void sbbl(Register dst, int32_t imm32);
1203 void sbbl(Register dst, Address src);
1204 void sbbl(Register dst, Register src);
1205
1206 void sbbq(Address dst, int32_t imm32);
1207 void sbbq(Register dst, int32_t imm32);
1208 void sbbq(Register dst, Address src);
1209 void sbbq(Register dst, Register src);
1210
1211 void setb(Condition cc, Register dst);
1212
1213 void shldl(Register dst, Register src);
1214
1215 void shll(Register dst, int imm8);
1216 void shll(Register dst);
1217
1218 void shlq(Register dst, int imm8);
1219 void shlq(Register dst);
1220
1221 void shrdl(Register dst, Register src);
1222
1223 void shrl(Register dst, int imm8);
1224 void shrl(Register dst);
1225
1226 void shrq(Register dst, int imm8);
1227 void shrq(Register dst);
1228
1229 void smovl(); // QQQ generic?
1230
1231 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1232 void sqrtsd(XMMRegister dst, Address src);
1233 void sqrtsd(XMMRegister dst, XMMRegister src);
1234
1235 void std() { emit_byte(0xfd); }
1236
1237 void stmxcsr( Address dst );
1238
1239 void subl(Address dst, int32_t imm32);
1240 void subl(Address dst, Register src);
1241 void subl(Register dst, int32_t imm32);
1242 void subl(Register dst, Address src);
1243 void subl(Register dst, Register src);
1244
1245 void subq(Address dst, int32_t imm32);
1246 void subq(Address dst, Register src);
1247 void subq(Register dst, int32_t imm32);
1248 void subq(Register dst, Address src);
1249 void subq(Register dst, Register src);
1250
1251
1252 // Subtract Scalar Double-Precision Floating-Point Values
1253 void subsd(XMMRegister dst, Address src);
1254 void subsd(XMMRegister dst, XMMRegister src);
1255
1256 // Subtract Scalar Single-Precision Floating-Point Values
1257 void subss(XMMRegister dst, Address src);
1258 void subss(XMMRegister dst, XMMRegister src);
1259
1260 void testb(Register dst, int imm8);
1261
1262 void testl(Register dst, int32_t imm32);
1263 void testl(Register dst, Register src);
1264 void testl(Register dst, Address src);
1265
1266 void testq(Register dst, int32_t imm32);
1267 void testq(Register dst, Register src);
1268
1269
1270 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1271 void ucomisd(XMMRegister dst, Address src);
1272 void ucomisd(XMMRegister dst, XMMRegister src);
1273
1274 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1275 void ucomiss(XMMRegister dst, Address src);
1276 void ucomiss(XMMRegister dst, XMMRegister src);
1277
1278 void xaddl(Address dst, Register src);
1279
1280 void xaddq(Address dst, Register src);
1281
1282 void xchgl(Register reg, Address adr);
1283 void xchgl(Register dst, Register src);
1284
1285 void xchgq(Register reg, Address adr);
1286 void xchgq(Register dst, Register src);
1287
1288 void xorl(Register dst, int32_t imm32);
1289 void xorl(Register dst, Address src);
1290 void xorl(Register dst, Register src);
1291
1292 void xorq(Register dst, Address src);
1293 void xorq(Register dst, Register src);
1294
1295 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1296 void xorpd(XMMRegister dst, Address src);
1297 void xorpd(XMMRegister dst, XMMRegister src);
1298
1299 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1300 void xorps(XMMRegister dst, Address src);
1301 void xorps(XMMRegister dst, XMMRegister src);
1302
1303 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1304 };
1305
1306
1307 // MacroAssembler extends Assembler by frequently used macros.
1308 //
1309 // Instructions for which a 'better' code sequence exists depending
1310 // on arguments should also go in here.
1311
1312 class MacroAssembler: public Assembler {
1313 friend class LIR_Assembler;
1314 protected:
1315
1316 Address as_Address(AddressLiteral adr);
1317 Address as_Address(ArrayAddress adr);
1318
1319 // Support for VM calls
1320 //
1321 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1322 // may customize this version by overriding it for its purposes (e.g., to save/restore
1323 // additional registers when doing a VM call).
1324 #ifdef CC_INTERP
1325 // c++ interpreter never wants to use interp_masm version of call_VM
1326 #define VIRTUAL
1327 #else
1328 #define VIRTUAL virtual
1329 #endif
1330
1331 VIRTUAL void call_VM_leaf_base(
1332 address entry_point, // the entry point
1333 int number_of_arguments // the number of arguments to pop after the call
1334 );
1335
1336 // This is the base routine called by the different versions of call_VM. The interpreter
1337 // may customize this version by overriding it for its purposes (e.g., to save/restore
1338 // additional registers when doing a VM call).
1339 //
1340 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1341 // returns the register which contains the thread upon return. If a thread register has been
1342 // specified, the return value will correspond to that register. If no last_java_sp is specified
1343 // (noreg) than rsp will be used instead.
1344 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1345 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1346 Register java_thread, // the thread if computed before ; use noreg otherwise
1347 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1348 address entry_point, // the entry point
1349 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1350 bool check_exceptions // whether to check for pending exceptions after return
1351 );
1352
1353 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1354 // The implementation is only non-empty for the InterpreterMacroAssembler,
1355 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1356 virtual void check_and_handle_popframe(Register java_thread);
1357 virtual void check_and_handle_earlyret(Register java_thread);
1358
1359 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1360
1361 // helpers for FPU flag access
1362 // tmp is a temporary register, if none is available use noreg
1363 void save_rax (Register tmp);
1364 void restore_rax(Register tmp);
1365
1366 public:
1367 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1368
1369 // Support for NULL-checks
1370 //
1371 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1372 // If the accessed location is M[reg + offset] and the offset is known, provide the
1373 // offset. No explicit code generation is needed if the offset is within a certain
1374 // range (0 <= offset <= page_size).
1375
1376 void null_check(Register reg, int offset = -1);
1377 static bool needs_explicit_null_check(intptr_t offset);
1378
1379 // Required platform-specific helpers for Label::patch_instructions.
1380 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1381 void pd_patch_instruction(address branch, address target);
1382 #ifndef PRODUCT
1383 static void pd_print_patched_instruction(address branch);
1384 #endif
1385
1386 // The following 4 methods return the offset of the appropriate move instruction
1387
1388 // Support for fast byte/word loading with zero extension (depending on particular CPU)
1389 int load_unsigned_byte(Register dst, Address src);
1390 int load_unsigned_word(Register dst, Address src);
1391
1392 // Support for fast byte/word loading with sign extension (depending on particular CPU)
1393 int load_signed_byte(Register dst, Address src);
1394 int load_signed_word(Register dst, Address src);
1395
1396 // Support for sign-extension (hi:lo = extend_sign(lo))
1397 void extend_sign(Register hi, Register lo);
1398
1399 // Support for inc/dec with optimal instruction selection depending on value
1400
1401 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1402 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1403
1404 void decrementl(Address dst, int value = 1);
1405 void decrementl(Register reg, int value = 1);
1406
1407 void decrementq(Register reg, int value = 1);
1408 void decrementq(Address dst, int value = 1);
1409
1410 void incrementl(Address dst, int value = 1);
1411 void incrementl(Register reg, int value = 1);
1412
1413 void incrementq(Register reg, int value = 1);
1414 void incrementq(Address dst, int value = 1);
1415
1416
1417 // Support optimal SSE move instructions.
1418 void movflt(XMMRegister dst, XMMRegister src) {
1419 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1420 else { movss (dst, src); return; }
1421 }
1422 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1423 void movflt(XMMRegister dst, AddressLiteral src);
1424 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1425
1426 void movdbl(XMMRegister dst, XMMRegister src) {
1427 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1428 else { movsd (dst, src); return; }
1429 }
1430
1431 void movdbl(XMMRegister dst, AddressLiteral src);
1432
1433 void movdbl(XMMRegister dst, Address src) {
1434 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1435 else { movlpd(dst, src); return; }
1436 }
1437 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1438
1439 void incrementl(AddressLiteral dst);
1440 void incrementl(ArrayAddress dst);
1441
1442 // Alignment
1443 void align(int modulus);
1444
1445 // Misc
1446 void fat_nop(); // 5 byte nop
1447
1448 // Stack frame creation/removal
1449 void enter();
1450 void leave();
1451
1452 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1453 // The pointer will be loaded into the thread register.
1454 void get_thread(Register thread);
1455
1456 // Support for VM calls
1457 //
1458 // It is imperative that all calls into the VM are handled via the call_VM macros.
1459 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1460 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1461
1462
1463 void call_VM(Register oop_result,
1464 address entry_point,
1465 bool check_exceptions = true);
1466 void call_VM(Register oop_result,
1467 address entry_point,
1468 Register arg_1,
1469 bool check_exceptions = true);
1470 void call_VM(Register oop_result,
1471 address entry_point,
1472 Register arg_1, Register arg_2,
1473 bool check_exceptions = true);
1474 void call_VM(Register oop_result,
1475 address entry_point,
1476 Register arg_1, Register arg_2, Register arg_3,
1477 bool check_exceptions = true);
1478
1479 // Overloadings with last_Java_sp
1480 void call_VM(Register oop_result,
1481 Register last_java_sp,
1482 address entry_point,
1483 int number_of_arguments = 0,
1484 bool check_exceptions = true);
1485 void call_VM(Register oop_result,
1486 Register last_java_sp,
1487 address entry_point,
1488 Register arg_1, bool
1489 check_exceptions = true);
1490 void call_VM(Register oop_result,
1491 Register last_java_sp,
1492 address entry_point,
1493 Register arg_1, Register arg_2,
1494 bool check_exceptions = true);
1495 void call_VM(Register oop_result,
1496 Register last_java_sp,
1497 address entry_point,
1498 Register arg_1, Register arg_2, Register arg_3,
1499 bool check_exceptions = true);
1500
1501 void call_VM_leaf(address entry_point,
1502 int number_of_arguments = 0);
1503 void call_VM_leaf(address entry_point,
1504 Register arg_1);
1505 void call_VM_leaf(address entry_point,
1506 Register arg_1, Register arg_2);
1507 void call_VM_leaf(address entry_point,
1508 Register arg_1, Register arg_2, Register arg_3);
1509
1510 // last Java Frame (fills frame anchor)
1511 void set_last_Java_frame(Register thread,
1512 Register last_java_sp,
1513 Register last_java_fp,
1514 address last_java_pc);
1515
1516 // thread in the default location (r15_thread on 64bit)
1517 void set_last_Java_frame(Register last_java_sp,
1518 Register last_java_fp,
1519 address last_java_pc);
1520
1521 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1522
1523 // thread in the default location (r15_thread on 64bit)
1524 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1525
1526 // Stores
1527 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1528 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1529
1530 // split store_check(Register obj) to enhance instruction interleaving
1531 void store_check_part_1(Register obj);
1532 void store_check_part_2(Register obj);
1533
1534 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1535 void c2bool(Register x);
1536
1537 // C++ bool manipulation
1538
1539 void movbool(Register dst, Address src);
1540 void movbool(Address dst, bool boolconst);
1541 void movbool(Address dst, Register src);
1542 void testbool(Register dst);
1543
1544 // oop manipulations
1545 void load_klass(Register dst, Register src);
1546 void store_klass(Register dst, Register src);
1547
1548 void load_prototype_header(Register dst, Register src);
1549
1550 #ifdef _LP64
1551 void store_klass_gap(Register dst, Register src);
1552
1553 void load_heap_oop(Register dst, Address src);
1554 void store_heap_oop(Address dst, Register src);
1555 void encode_heap_oop(Register r);
1556 void decode_heap_oop(Register r);
1557 void encode_heap_oop_not_null(Register r);
1558 void decode_heap_oop_not_null(Register r);
1559 void encode_heap_oop_not_null(Register dst, Register src);
1560 void decode_heap_oop_not_null(Register dst, Register src);
1561
1562 void set_narrow_oop(Register dst, jobject obj);
1563
1564 // if heap base register is used - reinit it with the correct value
1565 void reinit_heapbase();
1566 #endif // _LP64
1567
1568 // Int division/remainder for Java
1569 // (as idivl, but checks for special case as described in JVM spec.)
1570 // returns idivl instruction offset for implicit exception handling
1571 int corrected_idivl(Register reg);
1572
1573 // Long division/remainder for Java
1574 // (as idivq, but checks for special case as described in JVM spec.)
1575 // returns idivq instruction offset for implicit exception handling
1576 int corrected_idivq(Register reg);
1577
1578 void int3();
1579
1580 // Long operation macros for a 32bit cpu
1581 // Long negation for Java
1582 void lneg(Register hi, Register lo);
1583
1584 // Long multiplication for Java
1585 // (destroys contents of eax, ebx, ecx and edx)
1586 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1587
1588 // Long shifts for Java
1589 // (semantics as described in JVM spec.)
1590 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
1591 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
1592
1593 // Long compare for Java
1594 // (semantics as described in JVM spec.)
1595 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1596
1597
1598 // misc
1599
1600 // Sign extension
1601 void sign_extend_short(Register reg);
1602 void sign_extend_byte(Register reg);
1603
1604 // Division by power of 2, rounding towards 0
1605 void division_with_shift(Register reg, int shift_value);
1606
1607 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1608 //
1609 // CF (corresponds to C0) if x < y
1610 // PF (corresponds to C2) if unordered
1611 // ZF (corresponds to C3) if x = y
1612 //
1613 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1614 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1615 void fcmp(Register tmp);
1616 // Variant of the above which allows y to be further down the stack
1617 // and which only pops x and y if specified. If pop_right is
1618 // specified then pop_left must also be specified.
1619 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
1620
1621 // Floating-point comparison for Java
1622 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
1623 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1624 // (semantics as described in JVM spec.)
1625 void fcmp2int(Register dst, bool unordered_is_less);
1626 // Variant of the above which allows y to be further down the stack
1627 // and which only pops x and y if specified. If pop_right is
1628 // specified then pop_left must also be specified.
1629 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
1630
1631 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
1632 // tmp is a temporary register, if none is available use noreg
1633 void fremr(Register tmp);
1634
1635
1636 // same as fcmp2int, but using SSE2
1637 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1638 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1639
1640 // Inlined sin/cos generator for Java; must not use CPU instruction
1641 // directly on Intel as it does not have high enough precision
1642 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
1643 // number of FPU stack slots in use; all but the topmost will
1644 // require saving if a slow case is necessary. Assumes argument is
1645 // on FP TOS; result is on FP TOS. No cpu registers are changed by
1646 // this code.
1647 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
1648
1649 // branch to L if FPU flag C2 is set/not set
1650 // tmp is a temporary register, if none is available use noreg
1651 void jC2 (Register tmp, Label& L);
1652 void jnC2(Register tmp, Label& L);
1653
1654 // Pop ST (ffree & fincstp combined)
1655 void fpop();
1656
1657 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1658 void push_fTOS();
1659
1660 // pops double TOS element from CPU stack and pushes on FPU stack
1661 void pop_fTOS();
1662
1663 void empty_FPU_stack();
1664
1665 void push_IU_state();
1666 void pop_IU_state();
1667
1668 void push_FPU_state();
1669 void pop_FPU_state();
1670
1671 void push_CPU_state();
1672 void pop_CPU_state();
1673
1674 // Round up to a power of two
1675 void round_to(Register reg, int modulus);
1676
1677 // Callee saved registers handling
1678 void push_callee_saved_registers();
1679 void pop_callee_saved_registers();
1680
1681 // allocation
1682 void eden_allocate(
1683 Register obj, // result: pointer to object after successful allocation
1684 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1685 int con_size_in_bytes, // object size in bytes if known at compile time
1686 Register t1, // temp register
1687 Label& slow_case // continuation point if fast allocation fails
1688 );
1689 void tlab_allocate(
1690 Register obj, // result: pointer to object after successful allocation
1691 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1692 int con_size_in_bytes, // object size in bytes if known at compile time
1693 Register t1, // temp register
1694 Register t2, // temp register
1695 Label& slow_case // continuation point if fast allocation fails
1696 );
1697 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
1698
1699 //----
1700 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
1701
1702 // Debugging
1703
1704 // only if +VerifyOops
1705 void verify_oop(Register reg, const char* s = "broken oop");
1706 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1707
1708 // only if +VerifyFPU
1709 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1710
1711 // prints msg, dumps registers and stops execution
1712 void stop(const char* msg);
1713
1714 // prints msg and continues
1715 void warn(const char* msg);
1716
1717 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
1718 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1719
1720 void os_breakpoint();
1721
1722 void untested() { stop("untested"); }
1723
1724 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); }
1725
1726 void should_not_reach_here() { stop("should not reach here"); }
1727
1728 void print_CPU_state();
1729
1730 // Stack overflow checking
1731 void bang_stack_with_offset(int offset) {
1732 // stack grows down, caller passes positive offset
1733 assert(offset > 0, "must bang with negative offset");
1734 movl(Address(rsp, (-offset)), rax);
1735 }
1736
1737 // Writes to stack successive pages until offset reached to check for
1738 // stack overflow + shadow pages. Also, clobbers tmp
1739 void bang_stack_size(Register size, Register tmp);
1740
1741 // Support for serializing memory accesses between threads
1742 void serialize_memory(Register thread, Register tmp);
1743
1744 void verify_tlab();
1745
1746 // Biased locking support
1747 // lock_reg and obj_reg must be loaded up with the appropriate values.
1748 // swap_reg must be rax, and is killed.
1749 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
1750 // be killed; if not supplied, push/pop will be used internally to
1751 // allocate a temporary (inefficient, avoid if possible).
1752 // Optional slow case is for implementations (interpreter and C1) which branch to
1753 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
1754 // Returns offset of first potentially-faulting instruction for null
1755 // check info (currently consumed only by C1). If
1756 // swap_reg_contains_mark is true then returns -1 as it is assumed
1757 // the calling code has already passed any potential faults.
1758 int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
1759 bool swap_reg_contains_mark,
1760 Label& done, Label* slow_case = NULL,
1761 BiasedLockingCounters* counters = NULL);
1762 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
1763
1764
1765 Condition negate_condition(Condition cond);
1766
1767 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
1768 // operands. In general the names are modified to avoid hiding the instruction in Assembler
1769 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
1770 // here in MacroAssembler. The major exception to this rule is call
1771
1772 // Arithmetics
1773
1774
1775 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
1776 void addptr(Address dst, Register src);
1777
1778 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
1779 void addptr(Register dst, int32_t src);
1780 void addptr(Register dst, Register src);
1781
1782 void andptr(Register dst, int32_t src);
1783 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
1784
1785 void cmp8(AddressLiteral src1, int imm);
1786
1787 // renamed to drag out the casting of address to int32_t/intptr_t
1788 void cmp32(Register src1, int32_t imm);
1789
1790 void cmp32(AddressLiteral src1, int32_t imm);
1791 // compare reg - mem, or reg - &mem
1792 void cmp32(Register src1, AddressLiteral src2);
1793
1794 void cmp32(Register src1, Address src2);
1795
1796 #ifndef _LP64
1797 void cmpoop(Address dst, jobject obj);
1798 void cmpoop(Register dst, jobject obj);
1799 #endif // _LP64
1800
1801 // NOTE src2 must be the lval. This is NOT an mem-mem compare
1802 void cmpptr(Address src1, AddressLiteral src2);
1803
1804 void cmpptr(Register src1, AddressLiteral src2);
1805
1806 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1807 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1808 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1809
1810 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1811 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1812
1813 // cmp64 to avoild hiding cmpq
1814 void cmp64(Register src1, AddressLiteral src);
1815
1816 void cmpxchgptr(Register reg, Address adr);
1817
1818 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
1819
1820
1821 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
1822
1823
1824 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
1825
1826 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
1827
1828 void shlptr(Register dst, int32_t shift);
1829 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
1830
1831 void shrptr(Register dst, int32_t shift);
1832 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
1833
1834 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
1835 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
1836
1837 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
1838
1839 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
1840 void subptr(Register dst, int32_t src);
1841 void subptr(Register dst, Register src);
1842
1843
1844 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
1845 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
1846
1847 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
1848 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
1849
1850 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
1851
1852
1853
1854 // Helper functions for statistics gathering.
1855 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
1856 void cond_inc32(Condition cond, AddressLiteral counter_addr);
1857 // Unconditional atomic increment.
1858 void atomic_incl(AddressLiteral counter_addr);
1859
1860 void lea(Register dst, AddressLiteral adr);
1861 void lea(Address dst, AddressLiteral adr);
1862 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
1863
1864 void leal32(Register dst, Address src) { leal(dst, src); }
1865
1866 void test32(Register src1, AddressLiteral src2);
1867
1868 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
1869 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
1870 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
1871
1872 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
1873 void testptr(Register src1, Register src2);
1874
1875 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
1876 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
1877
1878 // Calls
1879
1880 void call(Label& L, relocInfo::relocType rtype);
1881 void call(Register entry);
1882
1883 // NOTE: this call tranfers to the effective address of entry NOT
1884 // the address contained by entry. This is because this is more natural
1885 // for jumps/calls.
1886 void call(AddressLiteral entry);
1887
1888 // Jumps
1889
1890 // NOTE: these jumps tranfer to the effective address of dst NOT
1891 // the address contained by dst. This is because this is more natural
1892 // for jumps/calls.
1893 void jump(AddressLiteral dst);
1894 void jump_cc(Condition cc, AddressLiteral dst);
1895
1896 // 32bit can do a case table jump in one instruction but we no longer allow the base
1897 // to be installed in the Address class. This jump will tranfers to the address
1898 // contained in the location described by entry (not the address of entry)
1899 void jump(ArrayAddress entry);
1900
1901 // Floating
1902
1903 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
1904 void andpd(XMMRegister dst, AddressLiteral src);
1905
1906 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
1907 void comiss(XMMRegister dst, AddressLiteral src);
1908
1909 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
1910 void comisd(XMMRegister dst, AddressLiteral src);
1911
1912 void fldcw(Address src) { Assembler::fldcw(src); }
1913 void fldcw(AddressLiteral src);
1914
1915 void fld_s(int index) { Assembler::fld_s(index); }
1916 void fld_s(Address src) { Assembler::fld_s(src); }
1917 void fld_s(AddressLiteral src);
1918
1919 void fld_d(Address src) { Assembler::fld_d(src); }
1920 void fld_d(AddressLiteral src);
1921
1922 void fld_x(Address src) { Assembler::fld_x(src); }
1923 void fld_x(AddressLiteral src);
1924
1925 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
1926 void ldmxcsr(AddressLiteral src);
1927
1928 private:
1929 // these are private because users should be doing movflt/movdbl
1930
1931 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1932 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1933 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1934 void movss(XMMRegister dst, AddressLiteral src);
1935
1936 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1937 void movlpd(XMMRegister dst, AddressLiteral src);
1938
1939 public:
1940
1941 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1942 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1943 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1944 void movsd(XMMRegister dst, AddressLiteral src);
1945
1946 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1947 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1948 void ucomiss(XMMRegister dst, AddressLiteral src);
1949
1950 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1951 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1952 void ucomisd(XMMRegister dst, AddressLiteral src);
1953
1954 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1955 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
1956 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1957 void xorpd(XMMRegister dst, AddressLiteral src);
1958
1959 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1960 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
1961 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1962 void xorps(XMMRegister dst, AddressLiteral src);
1963
1964 // Data
1965
1966 void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
1967
1968 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
1969 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
1970
1971 void movoop(Register dst, jobject obj);
1972 void movoop(Address dst, jobject obj);
1973
1974 void movptr(ArrayAddress dst, Register src);
1975 // can this do an lea?
1976 void movptr(Register dst, ArrayAddress src);
1977
1978 void movptr(Register dst, Address src);
1979
1980 void movptr(Register dst, AddressLiteral src);
1981
1982 void movptr(Register dst, intptr_t src);
1983 void movptr(Register dst, Register src);
1984 void movptr(Address dst, intptr_t src);
1985
1986 void movptr(Address dst, Register src);
1987
1988 #ifdef _LP64
1989 // Generally the next two are only used for moving NULL
1990 // Although there are situations in initializing the mark word where
1991 // they could be used. They are dangerous.
1992
1993 // They only exist on LP64 so that int32_t and intptr_t are not the same
1994 // and we have ambiguous declarations.
1995
1996 void movptr(Address dst, int32_t imm32);
1997 void movptr(Register dst, int32_t imm32);
1998 #endif // _LP64
1999
2000 // to avoid hiding movl
2001 void mov32(AddressLiteral dst, Register src);
2002 void mov32(Register dst, AddressLiteral src);
2003
2004 // to avoid hiding movb
2005 void movbyte(ArrayAddress dst, int src);
2006
2007 // Can push value or effective address
2008 void pushptr(AddressLiteral src);
2009
2010 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2011 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2012
2013 void pushoop(jobject obj);
2014
2015 // sign extend as need a l to ptr sized element
2016 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2017 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2018
2019
2020 #undef VIRTUAL
2021
2022 };
2023
2024 /**
2025 * class SkipIfEqual:
2026 *
2027 * Instantiating this class will result in assembly code being output that will
2028 * jump around any code emitted between the creation of the instance and it's
2029 * automatic destruction at the end of a scope block, depending on the value of
2030 * the flag passed to the constructor, which will be checked at run-time.
2031 */
2032 class SkipIfEqual {
2033 private:
2034 MacroAssembler* _masm;
2035 Label _label;
2036
2037 public:
2038 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2039 ~SkipIfEqual();
2040 };
2041
2042 #ifdef ASSERT
2043 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2044 #endif