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comparison src/cpu/x86/vm/c1_Defs_x86.hpp @ 304:dc7f315e41f7

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5108146: Merge i486 and amd64 cpu directories 6459804: Want client (c1) compiler for x86_64 (amd64) for faster start-up Reviewed-by: kvn
author never
date Wed, 27 Aug 2008 00:21:55 -0700
parents a61af66fc99e
children 9ee9cf798b59
comparison
equal deleted inserted replaced
303:fa4d1d240383 304:dc7f315e41f7
34 }; 34 };
35 35
36 36
37 // registers 37 // registers
38 enum { 38 enum {
39 pd_nof_cpu_regs_frame_map = 8, // number of registers used during code emission 39 pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers, // number of registers used during code emission
40 pd_nof_fpu_regs_frame_map = 8, // number of registers used during code emission 40 pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers, // number of registers used during code emission
41 pd_nof_xmm_regs_frame_map = 8, // number of registers used during code emission 41 pd_nof_xmm_regs_frame_map = XMMRegisterImpl::number_of_registers, // number of registers used during code emission
42 pd_nof_caller_save_cpu_regs_frame_map = 6, // number of registers killed by calls
43 pd_nof_caller_save_fpu_regs_frame_map = 8, // number of registers killed by calls
44 pd_nof_caller_save_xmm_regs_frame_map = 8, // number of registers killed by calls
45 42
46 pd_nof_cpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator 43 #ifdef _LP64
44 #define UNALLOCATED 4 // rsp, rbp, r15, r10
45 #else
46 #define UNALLOCATED 2 // rsp, rbp
47 #endif // LP64
48
49 pd_nof_caller_save_cpu_regs_frame_map = pd_nof_cpu_regs_frame_map - UNALLOCATED, // number of registers killed by calls
50 pd_nof_caller_save_fpu_regs_frame_map = pd_nof_fpu_regs_frame_map, // number of registers killed by calls
51 pd_nof_caller_save_xmm_regs_frame_map = pd_nof_xmm_regs_frame_map, // number of registers killed by calls
52
53 pd_nof_cpu_regs_reg_alloc = pd_nof_caller_save_cpu_regs_frame_map, // number of registers that are visible to register allocator
47 pd_nof_fpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator 54 pd_nof_fpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator
48 55
49 pd_nof_cpu_regs_linearscan = 8, // number of registers visible to linear scan 56 pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan
50 pd_nof_fpu_regs_linearscan = 8, // number of registers visible to linear scan 57 pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan
51 pd_nof_xmm_regs_linearscan = 8, // number of registers visible to linear scan 58 pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan
52 pd_first_cpu_reg = 0, 59 pd_first_cpu_reg = 0,
53 pd_last_cpu_reg = 5, 60 pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11),
54 pd_first_byte_reg = 2, 61 pd_first_byte_reg = 2,
55 pd_last_byte_reg = 5, 62 pd_last_byte_reg = 5,
56 pd_first_fpu_reg = pd_nof_cpu_regs_frame_map, 63 pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
57 pd_last_fpu_reg = pd_first_fpu_reg + 7, 64 pd_last_fpu_reg = pd_first_fpu_reg + 7,
58 pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map, 65 pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map,
59 pd_last_xmm_reg = pd_first_xmm_reg + 7 66 pd_last_xmm_reg = pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 1
60 }; 67 };
61 68
62 69
63 // encoding of float value in debug info: 70 // encoding of float value in debug info:
64 enum { 71 enum {