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comparison src/cpu/x86/vm/c1_FrameMap_x86.cpp @ 304:dc7f315e41f7

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5108146: Merge i486 and amd64 cpu directories 6459804: Want client (c1) compiler for x86_64 (amd64) for faster start-up Reviewed-by: kvn
author never
date Wed, 27 Aug 2008 00:21:55 -0700
parents a61af66fc99e
children 9ee9cf798b59
comparison
equal deleted inserted replaced
303:fa4d1d240383 304:dc7f315e41f7
37 // so we must add it in here. 37 // so we must add it in here.
38 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; 38 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
39 opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type)); 39 opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type));
40 } else if (r_1->is_Register()) { 40 } else if (r_1->is_Register()) {
41 Register reg = r_1->as_Register(); 41 Register reg = r_1->as_Register();
42 if (r_2->is_Register()) { 42 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
43 Register reg2 = r_2->as_Register(); 43 Register reg2 = r_2->as_Register();
44 #ifdef _LP64
45 assert(reg2 == reg, "must be same register");
46 opr = as_long_opr(reg);
47 #else
44 opr = as_long_opr(reg2, reg); 48 opr = as_long_opr(reg2, reg);
45 } else if (type == T_OBJECT) { 49 #endif // _LP64
50 } else if (type == T_OBJECT || type == T_ARRAY) {
46 opr = as_oop_opr(reg); 51 opr = as_oop_opr(reg);
47 } else { 52 } else {
48 opr = as_opr(reg); 53 opr = as_opr(reg);
49 } 54 }
50 } else if (r_1->is_FloatRegister()) { 55 } else if (r_1->is_FloatRegister()) {
86 LIR_Opr FrameMap::rbx_oop_opr; 91 LIR_Opr FrameMap::rbx_oop_opr;
87 LIR_Opr FrameMap::rax_oop_opr; 92 LIR_Opr FrameMap::rax_oop_opr;
88 LIR_Opr FrameMap::rdx_oop_opr; 93 LIR_Opr FrameMap::rdx_oop_opr;
89 LIR_Opr FrameMap::rcx_oop_opr; 94 LIR_Opr FrameMap::rcx_oop_opr;
90 95
91 LIR_Opr FrameMap::rax_rdx_long_opr; 96 LIR_Opr FrameMap::long0_opr;
92 LIR_Opr FrameMap::rbx_rcx_long_opr; 97 LIR_Opr FrameMap::long1_opr;
93 LIR_Opr FrameMap::fpu0_float_opr; 98 LIR_Opr FrameMap::fpu0_float_opr;
94 LIR_Opr FrameMap::fpu0_double_opr; 99 LIR_Opr FrameMap::fpu0_double_opr;
95 LIR_Opr FrameMap::xmm0_float_opr; 100 LIR_Opr FrameMap::xmm0_float_opr;
96 LIR_Opr FrameMap::xmm0_double_opr; 101 LIR_Opr FrameMap::xmm0_double_opr;
97 102
103 #ifdef _LP64
104
105 LIR_Opr FrameMap::r8_opr;
106 LIR_Opr FrameMap::r9_opr;
107 LIR_Opr FrameMap::r10_opr;
108 LIR_Opr FrameMap::r11_opr;
109 LIR_Opr FrameMap::r12_opr;
110 LIR_Opr FrameMap::r13_opr;
111 LIR_Opr FrameMap::r14_opr;
112 LIR_Opr FrameMap::r15_opr;
113
114 // r10 and r15 can never contain oops since they aren't available to
115 // the allocator
116 LIR_Opr FrameMap::r8_oop_opr;
117 LIR_Opr FrameMap::r9_oop_opr;
118 LIR_Opr FrameMap::r11_oop_opr;
119 LIR_Opr FrameMap::r12_oop_opr;
120 LIR_Opr FrameMap::r13_oop_opr;
121 LIR_Opr FrameMap::r14_oop_opr;
122 #endif // _LP64
123
98 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, }; 124 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
99 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, }; 125 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
100 LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, }; 126 LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, };
101 127
102 XMMRegister FrameMap::_xmm_regs [8] = { 0, }; 128 XMMRegister FrameMap::_xmm_regs [] = { 0, };
103 129
104 XMMRegister FrameMap::nr2xmmreg(int rnr) { 130 XMMRegister FrameMap::nr2xmmreg(int rnr) {
105 assert(_init_done, "tables not initialized"); 131 assert(_init_done, "tables not initialized");
106 return _xmm_regs[rnr]; 132 return _xmm_regs[rnr];
107 } 133 }
111 //-------------------------------------------------------- 137 //--------------------------------------------------------
112 138
113 void FrameMap::init() { 139 void FrameMap::init() {
114 if (_init_done) return; 140 if (_init_done) return;
115 141
116 assert(nof_cpu_regs == 8, "wrong number of CPU registers"); 142 assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
117 map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0); rsi_oop_opr = LIR_OprFact::single_cpu_oop(0); 143 map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0);
118 map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1); rdi_oop_opr = LIR_OprFact::single_cpu_oop(1); 144 map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1);
119 map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2); rbx_oop_opr = LIR_OprFact::single_cpu_oop(2); 145 map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2);
120 map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3); rax_oop_opr = LIR_OprFact::single_cpu_oop(3); 146 map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3);
121 map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4); rdx_oop_opr = LIR_OprFact::single_cpu_oop(4); 147 map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4);
122 map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5); rcx_oop_opr = LIR_OprFact::single_cpu_oop(5); 148 map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5);
123 map_register(6, rsp); rsp_opr = LIR_OprFact::single_cpu(6); 149
124 map_register(7, rbp); rbp_opr = LIR_OprFact::single_cpu(7); 150 #ifndef _LP64
125 151 // The unallocatable registers are at the end
126 rax_rdx_long_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/); 152 map_register(6, rsp);
127 rbx_rcx_long_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/); 153 map_register(7, rbp);
154 #else
155 map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6);
156 map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7);
157 map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8);
158 map_register( 9, r12); r12_opr = LIR_OprFact::single_cpu(9);
159 map_register(10, r13); r13_opr = LIR_OprFact::single_cpu(10);
160 map_register(11, r14); r14_opr = LIR_OprFact::single_cpu(11);
161 // The unallocatable registers are at the end
162 map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12);
163 map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13);
164 map_register(14, rsp);
165 map_register(15, rbp);
166 #endif // _LP64
167
168 #ifdef _LP64
169 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/);
170 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/);
171 #else
172 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
173 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
174 #endif // _LP64
128 fpu0_float_opr = LIR_OprFact::single_fpu(0); 175 fpu0_float_opr = LIR_OprFact::single_fpu(0);
129 fpu0_double_opr = LIR_OprFact::double_fpu(0); 176 fpu0_double_opr = LIR_OprFact::double_fpu(0);
130 xmm0_float_opr = LIR_OprFact::single_xmm(0); 177 xmm0_float_opr = LIR_OprFact::single_xmm(0);
131 xmm0_double_opr = LIR_OprFact::double_xmm(0); 178 xmm0_double_opr = LIR_OprFact::double_xmm(0);
132 179
134 _caller_save_cpu_regs[1] = rdi_opr; 181 _caller_save_cpu_regs[1] = rdi_opr;
135 _caller_save_cpu_regs[2] = rbx_opr; 182 _caller_save_cpu_regs[2] = rbx_opr;
136 _caller_save_cpu_regs[3] = rax_opr; 183 _caller_save_cpu_regs[3] = rax_opr;
137 _caller_save_cpu_regs[4] = rdx_opr; 184 _caller_save_cpu_regs[4] = rdx_opr;
138 _caller_save_cpu_regs[5] = rcx_opr; 185 _caller_save_cpu_regs[5] = rcx_opr;
186
187 #ifdef _LP64
188 _caller_save_cpu_regs[6] = r8_opr;
189 _caller_save_cpu_regs[7] = r9_opr;
190 _caller_save_cpu_regs[8] = r11_opr;
191 _caller_save_cpu_regs[9] = r12_opr;
192 _caller_save_cpu_regs[10] = r13_opr;
193 _caller_save_cpu_regs[11] = r14_opr;
194 #endif // _LP64
139 195
140 196
141 _xmm_regs[0] = xmm0; 197 _xmm_regs[0] = xmm0;
142 _xmm_regs[1] = xmm1; 198 _xmm_regs[1] = xmm1;
143 _xmm_regs[2] = xmm2; 199 _xmm_regs[2] = xmm2;
145 _xmm_regs[4] = xmm4; 201 _xmm_regs[4] = xmm4;
146 _xmm_regs[5] = xmm5; 202 _xmm_regs[5] = xmm5;
147 _xmm_regs[6] = xmm6; 203 _xmm_regs[6] = xmm6;
148 _xmm_regs[7] = xmm7; 204 _xmm_regs[7] = xmm7;
149 205
206 #ifdef _LP64
207 _xmm_regs[8] = xmm8;
208 _xmm_regs[9] = xmm9;
209 _xmm_regs[10] = xmm10;
210 _xmm_regs[11] = xmm11;
211 _xmm_regs[12] = xmm12;
212 _xmm_regs[13] = xmm13;
213 _xmm_regs[14] = xmm14;
214 _xmm_regs[15] = xmm15;
215 #endif // _LP64
216
150 for (int i = 0; i < 8; i++) { 217 for (int i = 0; i < 8; i++) {
151 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i); 218 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
219 }
220
221 for (int i = 0; i < nof_caller_save_xmm_regs ; i++) {
152 _caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i); 222 _caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i);
153 } 223 }
154 224
155 _init_done = true; 225 _init_done = true;
226
227 rsi_oop_opr = as_oop_opr(rsi);
228 rdi_oop_opr = as_oop_opr(rdi);
229 rbx_oop_opr = as_oop_opr(rbx);
230 rax_oop_opr = as_oop_opr(rax);
231 rdx_oop_opr = as_oop_opr(rdx);
232 rcx_oop_opr = as_oop_opr(rcx);
233
234 rsp_opr = as_pointer_opr(rsp);
235 rbp_opr = as_pointer_opr(rbp);
236
237 #ifdef _LP64
238 r8_oop_opr = as_oop_opr(r8);
239 r9_oop_opr = as_oop_opr(r9);
240 r11_oop_opr = as_oop_opr(r11);
241 r12_oop_opr = as_oop_opr(r12);
242 r13_oop_opr = as_oop_opr(r13);
243 r14_oop_opr = as_oop_opr(r14);
244 #endif // _LP64
156 245
157 VMRegPair regs; 246 VMRegPair regs;
158 BasicType sig_bt = T_OBJECT; 247 BasicType sig_bt = T_OBJECT;
159 SharedRuntime::java_calling_convention(&sig_bt, &regs, 1, true); 248 SharedRuntime::java_calling_convention(&sig_bt, &regs, 1, true);
160 receiver_opr = as_oop_opr(regs.first()->as_Register()); 249 receiver_opr = as_oop_opr(regs.first()->as_Register());
161 assert(receiver_opr == rcx_oop_opr, "rcvr ought to be rcx"); 250
162 } 251 }
163 252
164 253
165 Address FrameMap::make_new_address(ByteSize sp_offset) const { 254 Address FrameMap::make_new_address(ByteSize sp_offset) const {
166 // for rbp, based address use this: 255 // for rbp, based address use this: