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comparison src/share/vm/opto/mulnode.cpp @ 570:dca06e7f503d

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Merge
author kvn
date Tue, 17 Feb 2009 14:30:24 -0800
parents 7628781568e1
children 337400e7a5dd
comparison
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549:fe3d7c11b4b7 570:dca06e7f503d
1 /* 1 /*
2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved. 2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 * 4 *
5 * This code is free software; you can redistribute it and/or modify it 5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as 6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
440 jint t1_support = ((jint)1 << (1 + log2_intptr(t1->_hi))) - 1; 440 jint t1_support = ((jint)1 << (1 + log2_intptr(t1->_hi))) - 1;
441 if ((t1_support & con) == t1_support) 441 if ((t1_support & con) == t1_support)
442 return load; 442 return load;
443 } 443 }
444 uint lop = load->Opcode(); 444 uint lop = load->Opcode();
445 if( lop == Op_LoadC && 445 if( lop == Op_LoadUS &&
446 con == 0x0000FFFF ) // Already zero-extended 446 con == 0x0000FFFF ) // Already zero-extended
447 return load; 447 return load;
448 // Masking off the high bits of a unsigned-shift-right is not 448 // Masking off the high bits of a unsigned-shift-right is not
449 // needed either. 449 // needed either.
450 if( lop == Op_URShiftI ) { 450 if( lop == Op_URShiftI ) {
451 const TypeInt *t12 = phase->type( load->in(2) )->isa_int(); 451 const TypeInt *t12 = phase->type( load->in(2) )->isa_int();
452 if( t12 && t12->is_con() ) { 452 if( t12 && t12->is_con() ) { // Shift is by a constant
453 int shift_con = t12->get_con(); 453 int shift = t12->get_con();
454 int mask = max_juint >> shift_con; 454 shift &= BitsPerJavaInteger - 1; // semantics of Java shifts
455 int mask = max_juint >> shift;
455 if( (mask&con) == mask ) // If AND is useless, skip it 456 if( (mask&con) == mask ) // If AND is useless, skip it
456 return load; 457 return load;
457 } 458 }
458 } 459 }
459 } 460 }
468 const int mask = t2->get_con(); 469 const int mask = t2->get_con();
469 Node *load = in(1); 470 Node *load = in(1);
470 uint lop = load->Opcode(); 471 uint lop = load->Opcode();
471 472
472 // Masking bits off of a Character? Hi bits are already zero. 473 // Masking bits off of a Character? Hi bits are already zero.
473 if( lop == Op_LoadC && 474 if( lop == Op_LoadUS &&
474 (mask & 0xFFFF0000) ) // Can we make a smaller mask? 475 (mask & 0xFFFF0000) ) // Can we make a smaller mask?
475 return new (phase->C, 3) AndINode(load,phase->intcon(mask&0xFFFF)); 476 return new (phase->C, 3) AndINode(load,phase->intcon(mask&0xFFFF));
476 477
477 // Masking bits off of a Short? Loading a Character does some masking 478 // Masking bits off of a Short? Loading a Character does some masking
478 if( lop == Op_LoadS && 479 if( lop == Op_LoadS &&
479 (mask & 0xFFFF0000) == 0 ) { 480 (mask & 0xFFFF0000) == 0 ) {
480 Node *ldc = new (phase->C, 3) LoadCNode(load->in(MemNode::Control), 481 Node *ldus = new (phase->C, 3) LoadUSNode(load->in(MemNode::Control),
481 load->in(MemNode::Memory), 482 load->in(MemNode::Memory),
482 load->in(MemNode::Address), 483 load->in(MemNode::Address),
483 load->adr_type()); 484 load->adr_type());
484 ldc = phase->transform(ldc); 485 ldus = phase->transform(ldus);
485 return new (phase->C, 3) AndINode(ldc,phase->intcon(mask&0xFFFF)); 486 return new (phase->C, 3) AndINode(ldus, phase->intcon(mask&0xFFFF));
486 } 487 }
487 488
488 // Masking sign bits off of a Byte? Let the matcher use an unsigned load 489 // Masking sign bits off of a Byte? Let the matcher use an unsigned load
489 if( lop == Op_LoadB && 490 if( lop == Op_LoadB &&
490 (!in(0) && load->in(0)) && 491 (!in(0) && load->in(0)) &&
577 uint lop = usr->Opcode(); 578 uint lop = usr->Opcode();
578 // Masking off the high bits of a unsigned-shift-right is not 579 // Masking off the high bits of a unsigned-shift-right is not
579 // needed either. 580 // needed either.
580 if( lop == Op_URShiftL ) { 581 if( lop == Op_URShiftL ) {
581 const TypeInt *t12 = phase->type( usr->in(2) )->isa_int(); 582 const TypeInt *t12 = phase->type( usr->in(2) )->isa_int();
582 if( t12 && t12->is_con() ) { 583 if( t12 && t12->is_con() ) { // Shift is by a constant
583 int shift_con = t12->get_con(); 584 int shift = t12->get_con();
584 jlong mask = max_julong >> shift_con; 585 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
586 jlong mask = max_julong >> shift;
585 if( (mask&con) == mask ) // If AND is useless, skip it 587 if( (mask&con) == mask ) // If AND is useless, skip it
586 return usr; 588 return usr;
587 } 589 }
588 } 590 }
589 } 591 }
603 // Masking off sign bits? Dont make them! 605 // Masking off sign bits? Dont make them!
604 if( rop == Op_RShiftL ) { 606 if( rop == Op_RShiftL ) {
605 const TypeInt *t12 = phase->type(rsh->in(2))->isa_int(); 607 const TypeInt *t12 = phase->type(rsh->in(2))->isa_int();
606 if( t12 && t12->is_con() ) { // Shift is by a constant 608 if( t12 && t12->is_con() ) { // Shift is by a constant
607 int shift = t12->get_con(); 609 int shift = t12->get_con();
608 shift &= (BitsPerJavaInteger*2)-1; // semantics of Java shifts 610 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
609 const jlong sign_bits_mask = ~(((jlong)CONST64(1) << (jlong)(BitsPerJavaInteger*2 - shift)) -1); 611 const jlong sign_bits_mask = ~(((jlong)CONST64(1) << (jlong)(BitsPerJavaLong - shift)) -1);
610 // If the AND'ing of the 2 masks has no bits, then only original shifted 612 // If the AND'ing of the 2 masks has no bits, then only original shifted
611 // bits survive. NO sign-extension bits survive the maskings. 613 // bits survive. NO sign-extension bits survive the maskings.
612 if( (sign_bits_mask & mask) == 0 ) { 614 if( (sign_bits_mask & mask) == 0 ) {
613 // Use zero-fill shift instead 615 // Use zero-fill shift instead
614 Node *zshift = phase->transform(new (phase->C, 3) URShiftLNode(rsh->in(1),rsh->in(2))); 616 Node *zshift = phase->transform(new (phase->C, 3) URShiftLNode(rsh->in(1),rsh->in(2)));
784 } 786 }
785 } 787 }
786 788
787 // Check for ((x & ((CONST64(1)<<(64-c0))-1)) << c0) which ANDs off high bits 789 // Check for ((x & ((CONST64(1)<<(64-c0))-1)) << c0) which ANDs off high bits
788 // before shifting them away. 790 // before shifting them away.
789 const jlong bits_mask = ((jlong)CONST64(1) << (jlong)(BitsPerJavaInteger*2 - con)) - CONST64(1); 791 const jlong bits_mask = ((jlong)CONST64(1) << (jlong)(BitsPerJavaLong - con)) - CONST64(1);
790 if( add1_op == Op_AndL && 792 if( add1_op == Op_AndL &&
791 phase->type(add1->in(2)) == TypeLong::make( bits_mask ) ) 793 phase->type(add1->in(2)) == TypeLong::make( bits_mask ) )
792 return new (phase->C, 3) LShiftLNode( add1->in(1), in(2) ); 794 return new (phase->C, 3) LShiftLNode( add1->in(1), in(2) );
793 795
794 return NULL; 796 return NULL;
818 820
819 if (!r2->is_con()) 821 if (!r2->is_con())
820 return TypeLong::LONG; 822 return TypeLong::LONG;
821 823
822 uint shift = r2->get_con(); 824 uint shift = r2->get_con();
823 shift &= (BitsPerJavaInteger*2)-1; // semantics of Java shifts 825 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
824 // Shift by a multiple of 64 does nothing: 826 // Shift by a multiple of 64 does nothing:
825 if (shift == 0) return t1; 827 if (shift == 0) return t1;
826 828
827 // If the shift is a constant, shift the bounds of the type, 829 // If the shift is a constant, shift the bounds of the type,
828 // unless this could lead to an overflow. 830 // unless this could lead to an overflow.
911 // combined optimization requires Identity only return direct inputs. 913 // combined optimization requires Identity only return direct inputs.
912 set_req(1, ld); 914 set_req(1, ld);
913 set_req(2, phase->intcon(0)); 915 set_req(2, phase->intcon(0));
914 return this; 916 return this;
915 } 917 }
916 else if( ld->Opcode() == Op_LoadC ) 918 else if( ld->Opcode() == Op_LoadUS )
917 // Replace zero-extension-load with sign-extension-load 919 // Replace zero-extension-load with sign-extension-load
918 return new (phase->C, 3) LoadSNode( ld->in(MemNode::Control), 920 return new (phase->C, 3) LoadSNode( ld->in(MemNode::Control),
919 ld->in(MemNode::Memory), 921 ld->in(MemNode::Memory),
920 ld->in(MemNode::Address), 922 ld->in(MemNode::Address),
921 ld->adr_type()); 923 ld->adr_type());
1233 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant 1235 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
1234 const int con = t2->get_con() & ( BitsPerLong - 1 ); // Shift count is always masked 1236 const int con = t2->get_con() & ( BitsPerLong - 1 ); // Shift count is always masked
1235 if ( con == 0 ) return NULL; // let Identity() handle a 0 shift count 1237 if ( con == 0 ) return NULL; // let Identity() handle a 0 shift count
1236 // note: mask computation below does not work for 0 shift count 1238 // note: mask computation below does not work for 0 shift count
1237 // We'll be wanting the right-shift amount as a mask of that many bits 1239 // We'll be wanting the right-shift amount as a mask of that many bits
1238 const jlong mask = (((jlong)CONST64(1) << (jlong)(BitsPerJavaInteger*2 - con)) -1); 1240 const jlong mask = (((jlong)CONST64(1) << (jlong)(BitsPerJavaLong - con)) -1);
1239 1241
1240 // Check for ((x << z) + Y) >>> z. Replace with x + con>>>z 1242 // Check for ((x << z) + Y) >>> z. Replace with x + con>>>z
1241 // The idiom for rounding to a power of 2 is "(Q+(2^z-1)) >>> z". 1243 // The idiom for rounding to a power of 2 is "(Q+(2^z-1)) >>> z".
1242 // If Q is "X << z" the rounding is useless. Look for patterns like 1244 // If Q is "X << z" the rounding is useless. Look for patterns like
1243 // ((X<<Z) + Y) >>> Z and replace with (X + Y>>>Z) & Z-mask. 1245 // ((X<<Z) + Y) >>> Z and replace with (X + Y>>>Z) & Z-mask.
1300 const TypeLong *r1 = t1->is_long(); // Handy access 1302 const TypeLong *r1 = t1->is_long(); // Handy access
1301 const TypeInt *r2 = t2->is_int (); // Handy access 1303 const TypeInt *r2 = t2->is_int (); // Handy access
1302 1304
1303 if (r2->is_con()) { 1305 if (r2->is_con()) {
1304 uint shift = r2->get_con(); 1306 uint shift = r2->get_con();
1305 shift &= (2*BitsPerJavaInteger)-1; // semantics of Java shifts 1307 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
1306 // Shift by a multiple of 64 does nothing: 1308 // Shift by a multiple of 64 does nothing:
1307 if (shift == 0) return t1; 1309 if (shift == 0) return t1;
1308 // Calculate reasonably aggressive bounds for the result. 1310 // Calculate reasonably aggressive bounds for the result.
1309 jlong lo = (julong)r1->_lo >> (juint)shift; 1311 jlong lo = (julong)r1->_lo >> (juint)shift;
1310 jlong hi = (julong)r1->_hi >> (juint)shift; 1312 jlong hi = (julong)r1->_hi >> (juint)shift;
1323 } 1325 }
1324 assert(lo <= hi, "must have valid bounds"); 1326 assert(lo <= hi, "must have valid bounds");
1325 const TypeLong* tl = TypeLong::make(lo, hi, MAX2(r1->_widen,r2->_widen)); 1327 const TypeLong* tl = TypeLong::make(lo, hi, MAX2(r1->_widen,r2->_widen));
1326 #ifdef ASSERT 1328 #ifdef ASSERT
1327 // Make sure we get the sign-capture idiom correct. 1329 // Make sure we get the sign-capture idiom correct.
1328 if (shift == (2*BitsPerJavaInteger)-1) { 1330 if (shift == BitsPerJavaLong - 1) {
1329 if (r1->_lo >= 0) assert(tl == TypeLong::ZERO, ">>>63 of + is 0"); 1331 if (r1->_lo >= 0) assert(tl == TypeLong::ZERO, ">>>63 of + is 0");
1330 if (r1->_hi < 0) assert(tl == TypeLong::ONE, ">>>63 of - is +1"); 1332 if (r1->_hi < 0) assert(tl == TypeLong::ONE, ">>>63 of - is +1");
1331 } 1333 }
1332 #endif 1334 #endif
1333 return tl; 1335 return tl;