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comparison graal/com.oracle.max.asmdis/src/com/sun/max/asm/arm/complete/ARMRawAssembler.java @ 3733:e233f5660da4

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Added Java files from Maxine project.
author Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
date Sat, 17 Dec 2011 19:59:18 +0100
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3732:3e2e8b8abdaf 3733:e233f5660da4
1 /*
2 * Copyright (c) 2007, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 */
23
24 package com.sun.max.asm.arm.complete;
25
26 import com.sun.max.asm.arm.*;
27
28 public abstract class ARMRawAssembler extends AbstractARMAssembler {
29
30 protected ARMRawAssembler(int startAddress) {
31 super(startAddress);
32 }
33
34 protected ARMRawAssembler() {
35 super();
36 }
37
38 // START GENERATED RAW ASSEMBLER METHODS
39 /**
40 * Pseudo-external assembler syntax: {@code adc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immediate</i>
41 * Example disassembly syntax: {@code adceq r0, r0, #0x0}
42 * <p>
43 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
44 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
45 *
46 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
47 *
48 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.2"
49 */
50 // Template#: 1, Serial#: 1
51 public void adc(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immediate) {
52 int instruction = 0x02A00000;
53 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
54 instruction |= ((cond.value() & 0xf) << 28);
55 instruction |= ((s.value() & 0x1) << 20);
56 instruction |= ((Rd.value() & 0xf) << 12);
57 instruction |= ((Rn.value() & 0xf) << 16);
58 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
59 emitInt(instruction);
60 }
61
62 /**
63 * Pseudo-external assembler syntax: {@code adc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immed_8</i>, <i>rotate_amount</i>
64 * Example disassembly syntax: {@code adceq r0, r0, #0x0, 0x0}
65 * <p>
66 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
67 * Constraint: {@code (rotate_amount % 2) == 0}<br />
68 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
69 *
70 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.2"
71 */
72 // Template#: 2, Serial#: 2
73 public void adc(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immed_8, final int rotate_amount) {
74 int instruction = 0x02A00000;
75 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
76 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
77 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
78 instruction |= ((cond.value() & 0xf) << 28);
79 instruction |= ((s.value() & 0x1) << 20);
80 instruction |= ((Rd.value() & 0xf) << 12);
81 instruction |= ((Rn.value() & 0xf) << 16);
82 instruction |= (immed_8 & 0xff);
83 instruction |= ((rotate_amount / 2 & 0xf) << 8);
84 emitInt(instruction);
85 }
86
87 /**
88 * Pseudo-external assembler syntax: {@code adc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
89 * Example disassembly syntax: {@code adceq r0, r0, r0}
90 *
91 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.2"
92 */
93 // Template#: 3, Serial#: 3
94 public void adc(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
95 int instruction = 0x00A00000;
96 instruction |= ((cond.value() & 0xf) << 28);
97 instruction |= ((s.value() & 0x1) << 20);
98 instruction |= ((Rd.value() & 0xf) << 12);
99 instruction |= ((Rn.value() & 0xf) << 16);
100 instruction |= (Rm.value() & 0xf);
101 emitInt(instruction);
102 }
103
104 /**
105 * Pseudo-external assembler syntax: {@code adc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
106 * Example disassembly syntax: {@code adceq r0, r0, r0, lsl #0x0}
107 * <p>
108 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
109 *
110 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.2"
111 */
112 // Template#: 4, Serial#: 4
113 public void adclsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
114 int instruction = 0x00A00000;
115 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
116 instruction |= ((cond.value() & 0xf) << 28);
117 instruction |= ((s.value() & 0x1) << 20);
118 instruction |= ((Rd.value() & 0xf) << 12);
119 instruction |= ((Rn.value() & 0xf) << 16);
120 instruction |= (Rm.value() & 0xf);
121 instruction |= ((shift_imm & 0x1f) << 7);
122 emitInt(instruction);
123 }
124
125 /**
126 * Pseudo-external assembler syntax: {@code adc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
127 * Example disassembly syntax: {@code adceq r0, r0, r0, lsr #0x0}
128 * <p>
129 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
130 *
131 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.2"
132 */
133 // Template#: 5, Serial#: 5
134 public void adclsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
135 int instruction = 0x00A00020;
136 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
137 instruction |= ((cond.value() & 0xf) << 28);
138 instruction |= ((s.value() & 0x1) << 20);
139 instruction |= ((Rd.value() & 0xf) << 12);
140 instruction |= ((Rn.value() & 0xf) << 16);
141 instruction |= (Rm.value() & 0xf);
142 instruction |= ((shift_imm % 32 & 0x1f) << 7);
143 emitInt(instruction);
144 }
145
146 /**
147 * Pseudo-external assembler syntax: {@code adc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
148 * Example disassembly syntax: {@code adceq r0, r0, r0, asr #0x0}
149 * <p>
150 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
151 *
152 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.2"
153 */
154 // Template#: 6, Serial#: 6
155 public void adcasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
156 int instruction = 0x00A00040;
157 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
158 instruction |= ((cond.value() & 0xf) << 28);
159 instruction |= ((s.value() & 0x1) << 20);
160 instruction |= ((Rd.value() & 0xf) << 12);
161 instruction |= ((Rn.value() & 0xf) << 16);
162 instruction |= (Rm.value() & 0xf);
163 instruction |= ((shift_imm % 32 & 0x1f) << 7);
164 emitInt(instruction);
165 }
166
167 /**
168 * Pseudo-external assembler syntax: {@code adc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
169 * Example disassembly syntax: {@code adceq r0, r0, r0, ror #0x0}
170 * <p>
171 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
172 *
173 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.2"
174 */
175 // Template#: 7, Serial#: 7
176 public void adcror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
177 int instruction = 0x00A00060;
178 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
179 instruction |= ((cond.value() & 0xf) << 28);
180 instruction |= ((s.value() & 0x1) << 20);
181 instruction |= ((Rd.value() & 0xf) << 12);
182 instruction |= ((Rn.value() & 0xf) << 16);
183 instruction |= (Rm.value() & 0xf);
184 instruction |= ((shift_imm & 0x1f) << 7);
185 emitInt(instruction);
186 }
187
188 /**
189 * Pseudo-external assembler syntax: {@code adc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
190 * Example disassembly syntax: {@code adceq r0, r0, r0, lsl r0}
191 *
192 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.2"
193 */
194 // Template#: 8, Serial#: 8
195 public void adclsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
196 int instruction = 0x00A00010;
197 instruction |= ((cond.value() & 0xf) << 28);
198 instruction |= ((s.value() & 0x1) << 20);
199 instruction |= ((Rd.value() & 0xf) << 12);
200 instruction |= ((Rn.value() & 0xf) << 16);
201 instruction |= (Rm.value() & 0xf);
202 instruction |= ((Rs.value() & 0xf) << 8);
203 emitInt(instruction);
204 }
205
206 /**
207 * Pseudo-external assembler syntax: {@code adc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
208 * Example disassembly syntax: {@code adceq r0, r0, r0, lsr r0}
209 *
210 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.2"
211 */
212 // Template#: 9, Serial#: 9
213 public void adclsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
214 int instruction = 0x00A00030;
215 instruction |= ((cond.value() & 0xf) << 28);
216 instruction |= ((s.value() & 0x1) << 20);
217 instruction |= ((Rd.value() & 0xf) << 12);
218 instruction |= ((Rn.value() & 0xf) << 16);
219 instruction |= (Rm.value() & 0xf);
220 instruction |= ((Rs.value() & 0xf) << 8);
221 emitInt(instruction);
222 }
223
224 /**
225 * Pseudo-external assembler syntax: {@code adc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
226 * Example disassembly syntax: {@code adceq r0, r0, r0, asr r0}
227 *
228 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.2"
229 */
230 // Template#: 10, Serial#: 10
231 public void adcasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
232 int instruction = 0x00A00050;
233 instruction |= ((cond.value() & 0xf) << 28);
234 instruction |= ((s.value() & 0x1) << 20);
235 instruction |= ((Rd.value() & 0xf) << 12);
236 instruction |= ((Rn.value() & 0xf) << 16);
237 instruction |= (Rm.value() & 0xf);
238 instruction |= ((Rs.value() & 0xf) << 8);
239 emitInt(instruction);
240 }
241
242 /**
243 * Pseudo-external assembler syntax: {@code adc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
244 * Example disassembly syntax: {@code adceq r0, r0, r0, ror r0}
245 *
246 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.2"
247 */
248 // Template#: 11, Serial#: 11
249 public void adcror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
250 int instruction = 0x00A00070;
251 instruction |= ((cond.value() & 0xf) << 28);
252 instruction |= ((s.value() & 0x1) << 20);
253 instruction |= ((Rd.value() & 0xf) << 12);
254 instruction |= ((Rn.value() & 0xf) << 16);
255 instruction |= (Rm.value() & 0xf);
256 instruction |= ((Rs.value() & 0xf) << 8);
257 emitInt(instruction);
258 }
259
260 /**
261 * Pseudo-external assembler syntax: {@code adc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
262 * Example disassembly syntax: {@code adceq r0, r0, r0, rrx }
263 *
264 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.2"
265 */
266 // Template#: 12, Serial#: 12
267 public void adcrrx(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
268 int instruction = 0x00A00060;
269 instruction |= ((cond.value() & 0xf) << 28);
270 instruction |= ((s.value() & 0x1) << 20);
271 instruction |= ((Rd.value() & 0xf) << 12);
272 instruction |= ((Rn.value() & 0xf) << 16);
273 instruction |= (Rm.value() & 0xf);
274 emitInt(instruction);
275 }
276
277 /**
278 * Pseudo-external assembler syntax: {@code add{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immediate</i>
279 * Example disassembly syntax: {@code addeq r0, r0, #0x0}
280 * <p>
281 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
282 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
283 *
284 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
285 *
286 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.3"
287 */
288 // Template#: 13, Serial#: 13
289 public void add(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immediate) {
290 int instruction = 0x02800000;
291 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
292 instruction |= ((cond.value() & 0xf) << 28);
293 instruction |= ((s.value() & 0x1) << 20);
294 instruction |= ((Rd.value() & 0xf) << 12);
295 instruction |= ((Rn.value() & 0xf) << 16);
296 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
297 emitInt(instruction);
298 }
299
300 /**
301 * Pseudo-external assembler syntax: {@code add{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immed_8</i>, <i>rotate_amount</i>
302 * Example disassembly syntax: {@code addeq r0, r0, #0x0, 0x0}
303 * <p>
304 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
305 * Constraint: {@code (rotate_amount % 2) == 0}<br />
306 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
307 *
308 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.3"
309 */
310 // Template#: 14, Serial#: 14
311 public void add(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immed_8, final int rotate_amount) {
312 int instruction = 0x02800000;
313 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
314 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
315 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
316 instruction |= ((cond.value() & 0xf) << 28);
317 instruction |= ((s.value() & 0x1) << 20);
318 instruction |= ((Rd.value() & 0xf) << 12);
319 instruction |= ((Rn.value() & 0xf) << 16);
320 instruction |= (immed_8 & 0xff);
321 instruction |= ((rotate_amount / 2 & 0xf) << 8);
322 emitInt(instruction);
323 }
324
325 /**
326 * Pseudo-external assembler syntax: {@code add{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
327 * Example disassembly syntax: {@code addeq r0, r0, r0}
328 *
329 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.3"
330 */
331 // Template#: 15, Serial#: 15
332 public void add(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
333 int instruction = 0x00800000;
334 instruction |= ((cond.value() & 0xf) << 28);
335 instruction |= ((s.value() & 0x1) << 20);
336 instruction |= ((Rd.value() & 0xf) << 12);
337 instruction |= ((Rn.value() & 0xf) << 16);
338 instruction |= (Rm.value() & 0xf);
339 emitInt(instruction);
340 }
341
342 /**
343 * Pseudo-external assembler syntax: {@code add{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
344 * Example disassembly syntax: {@code addeq r0, r0, r0, lsl #0x0}
345 * <p>
346 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
347 *
348 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.3"
349 */
350 // Template#: 16, Serial#: 16
351 public void addlsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
352 int instruction = 0x00800000;
353 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
354 instruction |= ((cond.value() & 0xf) << 28);
355 instruction |= ((s.value() & 0x1) << 20);
356 instruction |= ((Rd.value() & 0xf) << 12);
357 instruction |= ((Rn.value() & 0xf) << 16);
358 instruction |= (Rm.value() & 0xf);
359 instruction |= ((shift_imm & 0x1f) << 7);
360 emitInt(instruction);
361 }
362
363 /**
364 * Pseudo-external assembler syntax: {@code add{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
365 * Example disassembly syntax: {@code addeq r0, r0, r0, lsr #0x0}
366 * <p>
367 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
368 *
369 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.3"
370 */
371 // Template#: 17, Serial#: 17
372 public void addlsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
373 int instruction = 0x00800020;
374 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
375 instruction |= ((cond.value() & 0xf) << 28);
376 instruction |= ((s.value() & 0x1) << 20);
377 instruction |= ((Rd.value() & 0xf) << 12);
378 instruction |= ((Rn.value() & 0xf) << 16);
379 instruction |= (Rm.value() & 0xf);
380 instruction |= ((shift_imm % 32 & 0x1f) << 7);
381 emitInt(instruction);
382 }
383
384 /**
385 * Pseudo-external assembler syntax: {@code add{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
386 * Example disassembly syntax: {@code addeq r0, r0, r0, asr #0x0}
387 * <p>
388 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
389 *
390 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.3"
391 */
392 // Template#: 18, Serial#: 18
393 public void addasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
394 int instruction = 0x00800040;
395 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
396 instruction |= ((cond.value() & 0xf) << 28);
397 instruction |= ((s.value() & 0x1) << 20);
398 instruction |= ((Rd.value() & 0xf) << 12);
399 instruction |= ((Rn.value() & 0xf) << 16);
400 instruction |= (Rm.value() & 0xf);
401 instruction |= ((shift_imm % 32 & 0x1f) << 7);
402 emitInt(instruction);
403 }
404
405 /**
406 * Pseudo-external assembler syntax: {@code add{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
407 * Example disassembly syntax: {@code addeq r0, r0, r0, ror #0x0}
408 * <p>
409 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
410 *
411 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.3"
412 */
413 // Template#: 19, Serial#: 19
414 public void addror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
415 int instruction = 0x00800060;
416 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
417 instruction |= ((cond.value() & 0xf) << 28);
418 instruction |= ((s.value() & 0x1) << 20);
419 instruction |= ((Rd.value() & 0xf) << 12);
420 instruction |= ((Rn.value() & 0xf) << 16);
421 instruction |= (Rm.value() & 0xf);
422 instruction |= ((shift_imm & 0x1f) << 7);
423 emitInt(instruction);
424 }
425
426 /**
427 * Pseudo-external assembler syntax: {@code add{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
428 * Example disassembly syntax: {@code addeq r0, r0, r0, lsl r0}
429 *
430 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.3"
431 */
432 // Template#: 20, Serial#: 20
433 public void addlsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
434 int instruction = 0x00800010;
435 instruction |= ((cond.value() & 0xf) << 28);
436 instruction |= ((s.value() & 0x1) << 20);
437 instruction |= ((Rd.value() & 0xf) << 12);
438 instruction |= ((Rn.value() & 0xf) << 16);
439 instruction |= (Rm.value() & 0xf);
440 instruction |= ((Rs.value() & 0xf) << 8);
441 emitInt(instruction);
442 }
443
444 /**
445 * Pseudo-external assembler syntax: {@code add{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
446 * Example disassembly syntax: {@code addeq r0, r0, r0, lsr r0}
447 *
448 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.3"
449 */
450 // Template#: 21, Serial#: 21
451 public void addlsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
452 int instruction = 0x00800030;
453 instruction |= ((cond.value() & 0xf) << 28);
454 instruction |= ((s.value() & 0x1) << 20);
455 instruction |= ((Rd.value() & 0xf) << 12);
456 instruction |= ((Rn.value() & 0xf) << 16);
457 instruction |= (Rm.value() & 0xf);
458 instruction |= ((Rs.value() & 0xf) << 8);
459 emitInt(instruction);
460 }
461
462 /**
463 * Pseudo-external assembler syntax: {@code add{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
464 * Example disassembly syntax: {@code addeq r0, r0, r0, asr r0}
465 *
466 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.3"
467 */
468 // Template#: 22, Serial#: 22
469 public void addasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
470 int instruction = 0x00800050;
471 instruction |= ((cond.value() & 0xf) << 28);
472 instruction |= ((s.value() & 0x1) << 20);
473 instruction |= ((Rd.value() & 0xf) << 12);
474 instruction |= ((Rn.value() & 0xf) << 16);
475 instruction |= (Rm.value() & 0xf);
476 instruction |= ((Rs.value() & 0xf) << 8);
477 emitInt(instruction);
478 }
479
480 /**
481 * Pseudo-external assembler syntax: {@code add{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
482 * Example disassembly syntax: {@code addeq r0, r0, r0, ror r0}
483 *
484 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.3"
485 */
486 // Template#: 23, Serial#: 23
487 public void addror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
488 int instruction = 0x00800070;
489 instruction |= ((cond.value() & 0xf) << 28);
490 instruction |= ((s.value() & 0x1) << 20);
491 instruction |= ((Rd.value() & 0xf) << 12);
492 instruction |= ((Rn.value() & 0xf) << 16);
493 instruction |= (Rm.value() & 0xf);
494 instruction |= ((Rs.value() & 0xf) << 8);
495 emitInt(instruction);
496 }
497
498 /**
499 * Pseudo-external assembler syntax: {@code add{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
500 * Example disassembly syntax: {@code addeq r0, r0, r0, rrx }
501 *
502 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.3"
503 */
504 // Template#: 24, Serial#: 24
505 public void addrrx(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
506 int instruction = 0x00800060;
507 instruction |= ((cond.value() & 0xf) << 28);
508 instruction |= ((s.value() & 0x1) << 20);
509 instruction |= ((Rd.value() & 0xf) << 12);
510 instruction |= ((Rn.value() & 0xf) << 16);
511 instruction |= (Rm.value() & 0xf);
512 emitInt(instruction);
513 }
514
515 /**
516 * Pseudo-external assembler syntax: {@code and{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immediate</i>
517 * Example disassembly syntax: {@code andeq r0, r0, #0x0}
518 * <p>
519 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
520 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
521 *
522 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
523 *
524 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.4"
525 */
526 // Template#: 25, Serial#: 25
527 public void and(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immediate) {
528 int instruction = 0x02000000;
529 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
530 instruction |= ((cond.value() & 0xf) << 28);
531 instruction |= ((s.value() & 0x1) << 20);
532 instruction |= ((Rd.value() & 0xf) << 12);
533 instruction |= ((Rn.value() & 0xf) << 16);
534 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
535 emitInt(instruction);
536 }
537
538 /**
539 * Pseudo-external assembler syntax: {@code and{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immed_8</i>, <i>rotate_amount</i>
540 * Example disassembly syntax: {@code andeq r0, r0, #0x0, 0x0}
541 * <p>
542 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
543 * Constraint: {@code (rotate_amount % 2) == 0}<br />
544 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
545 *
546 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.4"
547 */
548 // Template#: 26, Serial#: 26
549 public void and(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immed_8, final int rotate_amount) {
550 int instruction = 0x02000000;
551 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
552 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
553 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
554 instruction |= ((cond.value() & 0xf) << 28);
555 instruction |= ((s.value() & 0x1) << 20);
556 instruction |= ((Rd.value() & 0xf) << 12);
557 instruction |= ((Rn.value() & 0xf) << 16);
558 instruction |= (immed_8 & 0xff);
559 instruction |= ((rotate_amount / 2 & 0xf) << 8);
560 emitInt(instruction);
561 }
562
563 /**
564 * Pseudo-external assembler syntax: {@code and{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
565 * Example disassembly syntax: {@code andeq r0, r0, r0}
566 *
567 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.4"
568 */
569 // Template#: 27, Serial#: 27
570 public void and(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
571 int instruction = 0x00000000;
572 instruction |= ((cond.value() & 0xf) << 28);
573 instruction |= ((s.value() & 0x1) << 20);
574 instruction |= ((Rd.value() & 0xf) << 12);
575 instruction |= ((Rn.value() & 0xf) << 16);
576 instruction |= (Rm.value() & 0xf);
577 emitInt(instruction);
578 }
579
580 /**
581 * Pseudo-external assembler syntax: {@code and{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
582 * Example disassembly syntax: {@code andeq r0, r0, r0, lsl #0x0}
583 * <p>
584 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
585 *
586 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.4"
587 */
588 // Template#: 28, Serial#: 28
589 public void andlsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
590 int instruction = 0x00000000;
591 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
592 instruction |= ((cond.value() & 0xf) << 28);
593 instruction |= ((s.value() & 0x1) << 20);
594 instruction |= ((Rd.value() & 0xf) << 12);
595 instruction |= ((Rn.value() & 0xf) << 16);
596 instruction |= (Rm.value() & 0xf);
597 instruction |= ((shift_imm & 0x1f) << 7);
598 emitInt(instruction);
599 }
600
601 /**
602 * Pseudo-external assembler syntax: {@code and{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
603 * Example disassembly syntax: {@code andeq r0, r0, r0, lsr #0x0}
604 * <p>
605 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
606 *
607 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.4"
608 */
609 // Template#: 29, Serial#: 29
610 public void andlsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
611 int instruction = 0x00000020;
612 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
613 instruction |= ((cond.value() & 0xf) << 28);
614 instruction |= ((s.value() & 0x1) << 20);
615 instruction |= ((Rd.value() & 0xf) << 12);
616 instruction |= ((Rn.value() & 0xf) << 16);
617 instruction |= (Rm.value() & 0xf);
618 instruction |= ((shift_imm % 32 & 0x1f) << 7);
619 emitInt(instruction);
620 }
621
622 /**
623 * Pseudo-external assembler syntax: {@code and{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
624 * Example disassembly syntax: {@code andeq r0, r0, r0, asr #0x0}
625 * <p>
626 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
627 *
628 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.4"
629 */
630 // Template#: 30, Serial#: 30
631 public void andasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
632 int instruction = 0x00000040;
633 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
634 instruction |= ((cond.value() & 0xf) << 28);
635 instruction |= ((s.value() & 0x1) << 20);
636 instruction |= ((Rd.value() & 0xf) << 12);
637 instruction |= ((Rn.value() & 0xf) << 16);
638 instruction |= (Rm.value() & 0xf);
639 instruction |= ((shift_imm % 32 & 0x1f) << 7);
640 emitInt(instruction);
641 }
642
643 /**
644 * Pseudo-external assembler syntax: {@code and{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
645 * Example disassembly syntax: {@code andeq r0, r0, r0, ror #0x0}
646 * <p>
647 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
648 *
649 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.4"
650 */
651 // Template#: 31, Serial#: 31
652 public void andror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
653 int instruction = 0x00000060;
654 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
655 instruction |= ((cond.value() & 0xf) << 28);
656 instruction |= ((s.value() & 0x1) << 20);
657 instruction |= ((Rd.value() & 0xf) << 12);
658 instruction |= ((Rn.value() & 0xf) << 16);
659 instruction |= (Rm.value() & 0xf);
660 instruction |= ((shift_imm & 0x1f) << 7);
661 emitInt(instruction);
662 }
663
664 /**
665 * Pseudo-external assembler syntax: {@code and{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
666 * Example disassembly syntax: {@code andeq r0, r0, r0, lsl r0}
667 *
668 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.4"
669 */
670 // Template#: 32, Serial#: 32
671 public void andlsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
672 int instruction = 0x00000010;
673 instruction |= ((cond.value() & 0xf) << 28);
674 instruction |= ((s.value() & 0x1) << 20);
675 instruction |= ((Rd.value() & 0xf) << 12);
676 instruction |= ((Rn.value() & 0xf) << 16);
677 instruction |= (Rm.value() & 0xf);
678 instruction |= ((Rs.value() & 0xf) << 8);
679 emitInt(instruction);
680 }
681
682 /**
683 * Pseudo-external assembler syntax: {@code and{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
684 * Example disassembly syntax: {@code andeq r0, r0, r0, lsr r0}
685 *
686 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.4"
687 */
688 // Template#: 33, Serial#: 33
689 public void andlsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
690 int instruction = 0x00000030;
691 instruction |= ((cond.value() & 0xf) << 28);
692 instruction |= ((s.value() & 0x1) << 20);
693 instruction |= ((Rd.value() & 0xf) << 12);
694 instruction |= ((Rn.value() & 0xf) << 16);
695 instruction |= (Rm.value() & 0xf);
696 instruction |= ((Rs.value() & 0xf) << 8);
697 emitInt(instruction);
698 }
699
700 /**
701 * Pseudo-external assembler syntax: {@code and{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
702 * Example disassembly syntax: {@code andeq r0, r0, r0, asr r0}
703 *
704 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.4"
705 */
706 // Template#: 34, Serial#: 34
707 public void andasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
708 int instruction = 0x00000050;
709 instruction |= ((cond.value() & 0xf) << 28);
710 instruction |= ((s.value() & 0x1) << 20);
711 instruction |= ((Rd.value() & 0xf) << 12);
712 instruction |= ((Rn.value() & 0xf) << 16);
713 instruction |= (Rm.value() & 0xf);
714 instruction |= ((Rs.value() & 0xf) << 8);
715 emitInt(instruction);
716 }
717
718 /**
719 * Pseudo-external assembler syntax: {@code and{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
720 * Example disassembly syntax: {@code andeq r0, r0, r0, ror r0}
721 *
722 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.4"
723 */
724 // Template#: 35, Serial#: 35
725 public void andror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
726 int instruction = 0x00000070;
727 instruction |= ((cond.value() & 0xf) << 28);
728 instruction |= ((s.value() & 0x1) << 20);
729 instruction |= ((Rd.value() & 0xf) << 12);
730 instruction |= ((Rn.value() & 0xf) << 16);
731 instruction |= (Rm.value() & 0xf);
732 instruction |= ((Rs.value() & 0xf) << 8);
733 emitInt(instruction);
734 }
735
736 /**
737 * Pseudo-external assembler syntax: {@code and{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
738 * Example disassembly syntax: {@code andeq r0, r0, r0, rrx }
739 *
740 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.4"
741 */
742 // Template#: 36, Serial#: 36
743 public void andrrx(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
744 int instruction = 0x00000060;
745 instruction |= ((cond.value() & 0xf) << 28);
746 instruction |= ((s.value() & 0x1) << 20);
747 instruction |= ((Rd.value() & 0xf) << 12);
748 instruction |= ((Rn.value() & 0xf) << 16);
749 instruction |= (Rm.value() & 0xf);
750 emitInt(instruction);
751 }
752
753 /**
754 * Pseudo-external assembler syntax: {@code bic{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immediate</i>
755 * Example disassembly syntax: {@code biceq r0, r0, #0x0}
756 * <p>
757 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
758 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
759 *
760 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
761 *
762 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.6"
763 */
764 // Template#: 37, Serial#: 37
765 public void bic(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immediate) {
766 int instruction = 0x03C00000;
767 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
768 instruction |= ((cond.value() & 0xf) << 28);
769 instruction |= ((s.value() & 0x1) << 20);
770 instruction |= ((Rd.value() & 0xf) << 12);
771 instruction |= ((Rn.value() & 0xf) << 16);
772 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
773 emitInt(instruction);
774 }
775
776 /**
777 * Pseudo-external assembler syntax: {@code bic{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immed_8</i>, <i>rotate_amount</i>
778 * Example disassembly syntax: {@code biceq r0, r0, #0x0, 0x0}
779 * <p>
780 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
781 * Constraint: {@code (rotate_amount % 2) == 0}<br />
782 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
783 *
784 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.6"
785 */
786 // Template#: 38, Serial#: 38
787 public void bic(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immed_8, final int rotate_amount) {
788 int instruction = 0x03C00000;
789 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
790 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
791 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
792 instruction |= ((cond.value() & 0xf) << 28);
793 instruction |= ((s.value() & 0x1) << 20);
794 instruction |= ((Rd.value() & 0xf) << 12);
795 instruction |= ((Rn.value() & 0xf) << 16);
796 instruction |= (immed_8 & 0xff);
797 instruction |= ((rotate_amount / 2 & 0xf) << 8);
798 emitInt(instruction);
799 }
800
801 /**
802 * Pseudo-external assembler syntax: {@code bic{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
803 * Example disassembly syntax: {@code biceq r0, r0, r0}
804 *
805 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.6"
806 */
807 // Template#: 39, Serial#: 39
808 public void bic(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
809 int instruction = 0x01C00000;
810 instruction |= ((cond.value() & 0xf) << 28);
811 instruction |= ((s.value() & 0x1) << 20);
812 instruction |= ((Rd.value() & 0xf) << 12);
813 instruction |= ((Rn.value() & 0xf) << 16);
814 instruction |= (Rm.value() & 0xf);
815 emitInt(instruction);
816 }
817
818 /**
819 * Pseudo-external assembler syntax: {@code bic{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
820 * Example disassembly syntax: {@code biceq r0, r0, r0, lsl #0x0}
821 * <p>
822 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
823 *
824 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.6"
825 */
826 // Template#: 40, Serial#: 40
827 public void biclsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
828 int instruction = 0x01C00000;
829 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
830 instruction |= ((cond.value() & 0xf) << 28);
831 instruction |= ((s.value() & 0x1) << 20);
832 instruction |= ((Rd.value() & 0xf) << 12);
833 instruction |= ((Rn.value() & 0xf) << 16);
834 instruction |= (Rm.value() & 0xf);
835 instruction |= ((shift_imm & 0x1f) << 7);
836 emitInt(instruction);
837 }
838
839 /**
840 * Pseudo-external assembler syntax: {@code bic{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
841 * Example disassembly syntax: {@code biceq r0, r0, r0, lsr #0x0}
842 * <p>
843 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
844 *
845 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.6"
846 */
847 // Template#: 41, Serial#: 41
848 public void biclsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
849 int instruction = 0x01C00020;
850 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
851 instruction |= ((cond.value() & 0xf) << 28);
852 instruction |= ((s.value() & 0x1) << 20);
853 instruction |= ((Rd.value() & 0xf) << 12);
854 instruction |= ((Rn.value() & 0xf) << 16);
855 instruction |= (Rm.value() & 0xf);
856 instruction |= ((shift_imm % 32 & 0x1f) << 7);
857 emitInt(instruction);
858 }
859
860 /**
861 * Pseudo-external assembler syntax: {@code bic{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
862 * Example disassembly syntax: {@code biceq r0, r0, r0, asr #0x0}
863 * <p>
864 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
865 *
866 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.6"
867 */
868 // Template#: 42, Serial#: 42
869 public void bicasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
870 int instruction = 0x01C00040;
871 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
872 instruction |= ((cond.value() & 0xf) << 28);
873 instruction |= ((s.value() & 0x1) << 20);
874 instruction |= ((Rd.value() & 0xf) << 12);
875 instruction |= ((Rn.value() & 0xf) << 16);
876 instruction |= (Rm.value() & 0xf);
877 instruction |= ((shift_imm % 32 & 0x1f) << 7);
878 emitInt(instruction);
879 }
880
881 /**
882 * Pseudo-external assembler syntax: {@code bic{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
883 * Example disassembly syntax: {@code biceq r0, r0, r0, ror #0x0}
884 * <p>
885 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
886 *
887 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.6"
888 */
889 // Template#: 43, Serial#: 43
890 public void bicror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
891 int instruction = 0x01C00060;
892 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
893 instruction |= ((cond.value() & 0xf) << 28);
894 instruction |= ((s.value() & 0x1) << 20);
895 instruction |= ((Rd.value() & 0xf) << 12);
896 instruction |= ((Rn.value() & 0xf) << 16);
897 instruction |= (Rm.value() & 0xf);
898 instruction |= ((shift_imm & 0x1f) << 7);
899 emitInt(instruction);
900 }
901
902 /**
903 * Pseudo-external assembler syntax: {@code bic{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
904 * Example disassembly syntax: {@code biceq r0, r0, r0, lsl r0}
905 *
906 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.6"
907 */
908 // Template#: 44, Serial#: 44
909 public void biclsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
910 int instruction = 0x01C00010;
911 instruction |= ((cond.value() & 0xf) << 28);
912 instruction |= ((s.value() & 0x1) << 20);
913 instruction |= ((Rd.value() & 0xf) << 12);
914 instruction |= ((Rn.value() & 0xf) << 16);
915 instruction |= (Rm.value() & 0xf);
916 instruction |= ((Rs.value() & 0xf) << 8);
917 emitInt(instruction);
918 }
919
920 /**
921 * Pseudo-external assembler syntax: {@code bic{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
922 * Example disassembly syntax: {@code biceq r0, r0, r0, lsr r0}
923 *
924 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.6"
925 */
926 // Template#: 45, Serial#: 45
927 public void biclsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
928 int instruction = 0x01C00030;
929 instruction |= ((cond.value() & 0xf) << 28);
930 instruction |= ((s.value() & 0x1) << 20);
931 instruction |= ((Rd.value() & 0xf) << 12);
932 instruction |= ((Rn.value() & 0xf) << 16);
933 instruction |= (Rm.value() & 0xf);
934 instruction |= ((Rs.value() & 0xf) << 8);
935 emitInt(instruction);
936 }
937
938 /**
939 * Pseudo-external assembler syntax: {@code bic{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
940 * Example disassembly syntax: {@code biceq r0, r0, r0, asr r0}
941 *
942 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.6"
943 */
944 // Template#: 46, Serial#: 46
945 public void bicasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
946 int instruction = 0x01C00050;
947 instruction |= ((cond.value() & 0xf) << 28);
948 instruction |= ((s.value() & 0x1) << 20);
949 instruction |= ((Rd.value() & 0xf) << 12);
950 instruction |= ((Rn.value() & 0xf) << 16);
951 instruction |= (Rm.value() & 0xf);
952 instruction |= ((Rs.value() & 0xf) << 8);
953 emitInt(instruction);
954 }
955
956 /**
957 * Pseudo-external assembler syntax: {@code bic{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
958 * Example disassembly syntax: {@code biceq r0, r0, r0, ror r0}
959 *
960 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.6"
961 */
962 // Template#: 47, Serial#: 47
963 public void bicror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
964 int instruction = 0x01C00070;
965 instruction |= ((cond.value() & 0xf) << 28);
966 instruction |= ((s.value() & 0x1) << 20);
967 instruction |= ((Rd.value() & 0xf) << 12);
968 instruction |= ((Rn.value() & 0xf) << 16);
969 instruction |= (Rm.value() & 0xf);
970 instruction |= ((Rs.value() & 0xf) << 8);
971 emitInt(instruction);
972 }
973
974 /**
975 * Pseudo-external assembler syntax: {@code bic{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
976 * Example disassembly syntax: {@code biceq r0, r0, r0, rrx }
977 *
978 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.6"
979 */
980 // Template#: 48, Serial#: 48
981 public void bicrrx(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
982 int instruction = 0x01C00060;
983 instruction |= ((cond.value() & 0xf) << 28);
984 instruction |= ((s.value() & 0x1) << 20);
985 instruction |= ((Rd.value() & 0xf) << 12);
986 instruction |= ((Rn.value() & 0xf) << 16);
987 instruction |= (Rm.value() & 0xf);
988 emitInt(instruction);
989 }
990
991 /**
992 * Pseudo-external assembler syntax: {@code cmn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>immediate</i>
993 * Example disassembly syntax: {@code cmneq r0, #0x0}
994 * <p>
995 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
996 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
997 *
998 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
999 *
1000 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.13"
1001 */
1002 // Template#: 49, Serial#: 49
1003 public void cmn(final ConditionCode cond, final GPR Rn, final int immediate) {
1004 int instruction = 0x03700000;
1005 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
1006 instruction |= ((cond.value() & 0xf) << 28);
1007 instruction |= ((Rn.value() & 0xf) << 16);
1008 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
1009 emitInt(instruction);
1010 }
1011
1012 /**
1013 * Pseudo-external assembler syntax: {@code cmn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>immed_8</i>, <i>rotate_amount</i>
1014 * Example disassembly syntax: {@code cmneq r0, #0x0, 0x0}
1015 * <p>
1016 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
1017 * Constraint: {@code (rotate_amount % 2) == 0}<br />
1018 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
1019 *
1020 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.13"
1021 */
1022 // Template#: 50, Serial#: 50
1023 public void cmn(final ConditionCode cond, final GPR Rn, final int immed_8, final int rotate_amount) {
1024 int instruction = 0x03700000;
1025 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
1026 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
1027 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
1028 instruction |= ((cond.value() & 0xf) << 28);
1029 instruction |= ((Rn.value() & 0xf) << 16);
1030 instruction |= (immed_8 & 0xff);
1031 instruction |= ((rotate_amount / 2 & 0xf) << 8);
1032 emitInt(instruction);
1033 }
1034
1035 /**
1036 * Pseudo-external assembler syntax: {@code cmn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>
1037 * Example disassembly syntax: {@code cmneq r0, r0}
1038 *
1039 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.13"
1040 */
1041 // Template#: 51, Serial#: 51
1042 public void cmn(final ConditionCode cond, final GPR Rn, final GPR Rm) {
1043 int instruction = 0x01700000;
1044 instruction |= ((cond.value() & 0xf) << 28);
1045 instruction |= ((Rn.value() & 0xf) << 16);
1046 instruction |= (Rm.value() & 0xf);
1047 emitInt(instruction);
1048 }
1049
1050 /**
1051 * Pseudo-external assembler syntax: {@code cmn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
1052 * Example disassembly syntax: {@code cmneq r0, r0, lsl #0x0}
1053 * <p>
1054 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
1055 *
1056 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.13"
1057 */
1058 // Template#: 52, Serial#: 52
1059 public void cmnlsl(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
1060 int instruction = 0x01700000;
1061 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
1062 instruction |= ((cond.value() & 0xf) << 28);
1063 instruction |= ((Rn.value() & 0xf) << 16);
1064 instruction |= (Rm.value() & 0xf);
1065 instruction |= ((shift_imm & 0x1f) << 7);
1066 emitInt(instruction);
1067 }
1068
1069 /**
1070 * Pseudo-external assembler syntax: {@code cmn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
1071 * Example disassembly syntax: {@code cmneq r0, r0, lsr #0x0}
1072 * <p>
1073 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
1074 *
1075 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.13"
1076 */
1077 // Template#: 53, Serial#: 53
1078 public void cmnlsr(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
1079 int instruction = 0x01700020;
1080 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
1081 instruction |= ((cond.value() & 0xf) << 28);
1082 instruction |= ((Rn.value() & 0xf) << 16);
1083 instruction |= (Rm.value() & 0xf);
1084 instruction |= ((shift_imm % 32 & 0x1f) << 7);
1085 emitInt(instruction);
1086 }
1087
1088 /**
1089 * Pseudo-external assembler syntax: {@code cmn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
1090 * Example disassembly syntax: {@code cmneq r0, r0, asr #0x0}
1091 * <p>
1092 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
1093 *
1094 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.13"
1095 */
1096 // Template#: 54, Serial#: 54
1097 public void cmnasr(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
1098 int instruction = 0x01700040;
1099 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
1100 instruction |= ((cond.value() & 0xf) << 28);
1101 instruction |= ((Rn.value() & 0xf) << 16);
1102 instruction |= (Rm.value() & 0xf);
1103 instruction |= ((shift_imm % 32 & 0x1f) << 7);
1104 emitInt(instruction);
1105 }
1106
1107 /**
1108 * Pseudo-external assembler syntax: {@code cmn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
1109 * Example disassembly syntax: {@code cmneq r0, r0, ror #0x0}
1110 * <p>
1111 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
1112 *
1113 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.13"
1114 */
1115 // Template#: 55, Serial#: 55
1116 public void cmnror(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
1117 int instruction = 0x01700060;
1118 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
1119 instruction |= ((cond.value() & 0xf) << 28);
1120 instruction |= ((Rn.value() & 0xf) << 16);
1121 instruction |= (Rm.value() & 0xf);
1122 instruction |= ((shift_imm & 0x1f) << 7);
1123 emitInt(instruction);
1124 }
1125
1126 /**
1127 * Pseudo-external assembler syntax: {@code cmn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
1128 * Example disassembly syntax: {@code cmneq r0, r0, lsl r0}
1129 *
1130 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.13"
1131 */
1132 // Template#: 56, Serial#: 56
1133 public void cmnlsl(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
1134 int instruction = 0x01700010;
1135 instruction |= ((cond.value() & 0xf) << 28);
1136 instruction |= ((Rn.value() & 0xf) << 16);
1137 instruction |= (Rm.value() & 0xf);
1138 instruction |= ((Rs.value() & 0xf) << 8);
1139 emitInt(instruction);
1140 }
1141
1142 /**
1143 * Pseudo-external assembler syntax: {@code cmn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
1144 * Example disassembly syntax: {@code cmneq r0, r0, lsr r0}
1145 *
1146 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.13"
1147 */
1148 // Template#: 57, Serial#: 57
1149 public void cmnlsr(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
1150 int instruction = 0x01700030;
1151 instruction |= ((cond.value() & 0xf) << 28);
1152 instruction |= ((Rn.value() & 0xf) << 16);
1153 instruction |= (Rm.value() & 0xf);
1154 instruction |= ((Rs.value() & 0xf) << 8);
1155 emitInt(instruction);
1156 }
1157
1158 /**
1159 * Pseudo-external assembler syntax: {@code cmn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
1160 * Example disassembly syntax: {@code cmneq r0, r0, asr r0}
1161 *
1162 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.13"
1163 */
1164 // Template#: 58, Serial#: 58
1165 public void cmnasr(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
1166 int instruction = 0x01700050;
1167 instruction |= ((cond.value() & 0xf) << 28);
1168 instruction |= ((Rn.value() & 0xf) << 16);
1169 instruction |= (Rm.value() & 0xf);
1170 instruction |= ((Rs.value() & 0xf) << 8);
1171 emitInt(instruction);
1172 }
1173
1174 /**
1175 * Pseudo-external assembler syntax: {@code cmn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
1176 * Example disassembly syntax: {@code cmneq r0, r0, ror r0}
1177 *
1178 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.13"
1179 */
1180 // Template#: 59, Serial#: 59
1181 public void cmnror(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
1182 int instruction = 0x01700070;
1183 instruction |= ((cond.value() & 0xf) << 28);
1184 instruction |= ((Rn.value() & 0xf) << 16);
1185 instruction |= (Rm.value() & 0xf);
1186 instruction |= ((Rs.value() & 0xf) << 8);
1187 emitInt(instruction);
1188 }
1189
1190 /**
1191 * Pseudo-external assembler syntax: {@code cmn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>
1192 * Example disassembly syntax: {@code cmneq r0, r0, rrx }
1193 *
1194 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.13"
1195 */
1196 // Template#: 60, Serial#: 60
1197 public void cmnrrx(final ConditionCode cond, final GPR Rn, final GPR Rm) {
1198 int instruction = 0x01700060;
1199 instruction |= ((cond.value() & 0xf) << 28);
1200 instruction |= ((Rn.value() & 0xf) << 16);
1201 instruction |= (Rm.value() & 0xf);
1202 emitInt(instruction);
1203 }
1204
1205 /**
1206 * Pseudo-external assembler syntax: {@code cmp{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>immediate</i>
1207 * Example disassembly syntax: {@code cmpeq r0, #0x0}
1208 * <p>
1209 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
1210 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
1211 *
1212 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
1213 *
1214 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.14"
1215 */
1216 // Template#: 61, Serial#: 61
1217 public void cmp(final ConditionCode cond, final GPR Rn, final int immediate) {
1218 int instruction = 0x03500000;
1219 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
1220 instruction |= ((cond.value() & 0xf) << 28);
1221 instruction |= ((Rn.value() & 0xf) << 16);
1222 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
1223 emitInt(instruction);
1224 }
1225
1226 /**
1227 * Pseudo-external assembler syntax: {@code cmp{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>immed_8</i>, <i>rotate_amount</i>
1228 * Example disassembly syntax: {@code cmpeq r0, #0x0, 0x0}
1229 * <p>
1230 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
1231 * Constraint: {@code (rotate_amount % 2) == 0}<br />
1232 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
1233 *
1234 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.14"
1235 */
1236 // Template#: 62, Serial#: 62
1237 public void cmp(final ConditionCode cond, final GPR Rn, final int immed_8, final int rotate_amount) {
1238 int instruction = 0x03500000;
1239 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
1240 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
1241 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
1242 instruction |= ((cond.value() & 0xf) << 28);
1243 instruction |= ((Rn.value() & 0xf) << 16);
1244 instruction |= (immed_8 & 0xff);
1245 instruction |= ((rotate_amount / 2 & 0xf) << 8);
1246 emitInt(instruction);
1247 }
1248
1249 /**
1250 * Pseudo-external assembler syntax: {@code cmp{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>
1251 * Example disassembly syntax: {@code cmpeq r0, r0}
1252 *
1253 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.14"
1254 */
1255 // Template#: 63, Serial#: 63
1256 public void cmp(final ConditionCode cond, final GPR Rn, final GPR Rm) {
1257 int instruction = 0x01500000;
1258 instruction |= ((cond.value() & 0xf) << 28);
1259 instruction |= ((Rn.value() & 0xf) << 16);
1260 instruction |= (Rm.value() & 0xf);
1261 emitInt(instruction);
1262 }
1263
1264 /**
1265 * Pseudo-external assembler syntax: {@code cmp{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
1266 * Example disassembly syntax: {@code cmpeq r0, r0, lsl #0x0}
1267 * <p>
1268 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
1269 *
1270 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.14"
1271 */
1272 // Template#: 64, Serial#: 64
1273 public void cmplsl(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
1274 int instruction = 0x01500000;
1275 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
1276 instruction |= ((cond.value() & 0xf) << 28);
1277 instruction |= ((Rn.value() & 0xf) << 16);
1278 instruction |= (Rm.value() & 0xf);
1279 instruction |= ((shift_imm & 0x1f) << 7);
1280 emitInt(instruction);
1281 }
1282
1283 /**
1284 * Pseudo-external assembler syntax: {@code cmp{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
1285 * Example disassembly syntax: {@code cmpeq r0, r0, lsr #0x0}
1286 * <p>
1287 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
1288 *
1289 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.14"
1290 */
1291 // Template#: 65, Serial#: 65
1292 public void cmplsr(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
1293 int instruction = 0x01500020;
1294 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
1295 instruction |= ((cond.value() & 0xf) << 28);
1296 instruction |= ((Rn.value() & 0xf) << 16);
1297 instruction |= (Rm.value() & 0xf);
1298 instruction |= ((shift_imm % 32 & 0x1f) << 7);
1299 emitInt(instruction);
1300 }
1301
1302 /**
1303 * Pseudo-external assembler syntax: {@code cmp{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
1304 * Example disassembly syntax: {@code cmpeq r0, r0, asr #0x0}
1305 * <p>
1306 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
1307 *
1308 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.14"
1309 */
1310 // Template#: 66, Serial#: 66
1311 public void cmpasr(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
1312 int instruction = 0x01500040;
1313 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
1314 instruction |= ((cond.value() & 0xf) << 28);
1315 instruction |= ((Rn.value() & 0xf) << 16);
1316 instruction |= (Rm.value() & 0xf);
1317 instruction |= ((shift_imm % 32 & 0x1f) << 7);
1318 emitInt(instruction);
1319 }
1320
1321 /**
1322 * Pseudo-external assembler syntax: {@code cmp{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
1323 * Example disassembly syntax: {@code cmpeq r0, r0, ror #0x0}
1324 * <p>
1325 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
1326 *
1327 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.14"
1328 */
1329 // Template#: 67, Serial#: 67
1330 public void cmpror(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
1331 int instruction = 0x01500060;
1332 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
1333 instruction |= ((cond.value() & 0xf) << 28);
1334 instruction |= ((Rn.value() & 0xf) << 16);
1335 instruction |= (Rm.value() & 0xf);
1336 instruction |= ((shift_imm & 0x1f) << 7);
1337 emitInt(instruction);
1338 }
1339
1340 /**
1341 * Pseudo-external assembler syntax: {@code cmp{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
1342 * Example disassembly syntax: {@code cmpeq r0, r0, lsl r0}
1343 *
1344 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.14"
1345 */
1346 // Template#: 68, Serial#: 68
1347 public void cmplsl(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
1348 int instruction = 0x01500010;
1349 instruction |= ((cond.value() & 0xf) << 28);
1350 instruction |= ((Rn.value() & 0xf) << 16);
1351 instruction |= (Rm.value() & 0xf);
1352 instruction |= ((Rs.value() & 0xf) << 8);
1353 emitInt(instruction);
1354 }
1355
1356 /**
1357 * Pseudo-external assembler syntax: {@code cmp{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
1358 * Example disassembly syntax: {@code cmpeq r0, r0, lsr r0}
1359 *
1360 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.14"
1361 */
1362 // Template#: 69, Serial#: 69
1363 public void cmplsr(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
1364 int instruction = 0x01500030;
1365 instruction |= ((cond.value() & 0xf) << 28);
1366 instruction |= ((Rn.value() & 0xf) << 16);
1367 instruction |= (Rm.value() & 0xf);
1368 instruction |= ((Rs.value() & 0xf) << 8);
1369 emitInt(instruction);
1370 }
1371
1372 /**
1373 * Pseudo-external assembler syntax: {@code cmp{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
1374 * Example disassembly syntax: {@code cmpeq r0, r0, asr r0}
1375 *
1376 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.14"
1377 */
1378 // Template#: 70, Serial#: 70
1379 public void cmpasr(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
1380 int instruction = 0x01500050;
1381 instruction |= ((cond.value() & 0xf) << 28);
1382 instruction |= ((Rn.value() & 0xf) << 16);
1383 instruction |= (Rm.value() & 0xf);
1384 instruction |= ((Rs.value() & 0xf) << 8);
1385 emitInt(instruction);
1386 }
1387
1388 /**
1389 * Pseudo-external assembler syntax: {@code cmp{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
1390 * Example disassembly syntax: {@code cmpeq r0, r0, ror r0}
1391 *
1392 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.14"
1393 */
1394 // Template#: 71, Serial#: 71
1395 public void cmpror(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
1396 int instruction = 0x01500070;
1397 instruction |= ((cond.value() & 0xf) << 28);
1398 instruction |= ((Rn.value() & 0xf) << 16);
1399 instruction |= (Rm.value() & 0xf);
1400 instruction |= ((Rs.value() & 0xf) << 8);
1401 emitInt(instruction);
1402 }
1403
1404 /**
1405 * Pseudo-external assembler syntax: {@code cmp{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>
1406 * Example disassembly syntax: {@code cmpeq r0, r0, rrx }
1407 *
1408 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.14"
1409 */
1410 // Template#: 72, Serial#: 72
1411 public void cmprrx(final ConditionCode cond, final GPR Rn, final GPR Rm) {
1412 int instruction = 0x01500060;
1413 instruction |= ((cond.value() & 0xf) << 28);
1414 instruction |= ((Rn.value() & 0xf) << 16);
1415 instruction |= (Rm.value() & 0xf);
1416 emitInt(instruction);
1417 }
1418
1419 /**
1420 * Pseudo-external assembler syntax: {@code eor{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immediate</i>
1421 * Example disassembly syntax: {@code eoreq r0, r0, #0x0}
1422 * <p>
1423 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
1424 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
1425 *
1426 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
1427 *
1428 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.15"
1429 */
1430 // Template#: 73, Serial#: 73
1431 public void eor(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immediate) {
1432 int instruction = 0x02200000;
1433 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
1434 instruction |= ((cond.value() & 0xf) << 28);
1435 instruction |= ((s.value() & 0x1) << 20);
1436 instruction |= ((Rd.value() & 0xf) << 12);
1437 instruction |= ((Rn.value() & 0xf) << 16);
1438 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
1439 emitInt(instruction);
1440 }
1441
1442 /**
1443 * Pseudo-external assembler syntax: {@code eor{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immed_8</i>, <i>rotate_amount</i>
1444 * Example disassembly syntax: {@code eoreq r0, r0, #0x0, 0x0}
1445 * <p>
1446 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
1447 * Constraint: {@code (rotate_amount % 2) == 0}<br />
1448 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
1449 *
1450 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.15"
1451 */
1452 // Template#: 74, Serial#: 74
1453 public void eor(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immed_8, final int rotate_amount) {
1454 int instruction = 0x02200000;
1455 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
1456 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
1457 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
1458 instruction |= ((cond.value() & 0xf) << 28);
1459 instruction |= ((s.value() & 0x1) << 20);
1460 instruction |= ((Rd.value() & 0xf) << 12);
1461 instruction |= ((Rn.value() & 0xf) << 16);
1462 instruction |= (immed_8 & 0xff);
1463 instruction |= ((rotate_amount / 2 & 0xf) << 8);
1464 emitInt(instruction);
1465 }
1466
1467 /**
1468 * Pseudo-external assembler syntax: {@code eor{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
1469 * Example disassembly syntax: {@code eoreq r0, r0, r0}
1470 *
1471 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.15"
1472 */
1473 // Template#: 75, Serial#: 75
1474 public void eor(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
1475 int instruction = 0x00200000;
1476 instruction |= ((cond.value() & 0xf) << 28);
1477 instruction |= ((s.value() & 0x1) << 20);
1478 instruction |= ((Rd.value() & 0xf) << 12);
1479 instruction |= ((Rn.value() & 0xf) << 16);
1480 instruction |= (Rm.value() & 0xf);
1481 emitInt(instruction);
1482 }
1483
1484 /**
1485 * Pseudo-external assembler syntax: {@code eor{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
1486 * Example disassembly syntax: {@code eoreq r0, r0, r0, lsl #0x0}
1487 * <p>
1488 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
1489 *
1490 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.15"
1491 */
1492 // Template#: 76, Serial#: 76
1493 public void eorlsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
1494 int instruction = 0x00200000;
1495 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
1496 instruction |= ((cond.value() & 0xf) << 28);
1497 instruction |= ((s.value() & 0x1) << 20);
1498 instruction |= ((Rd.value() & 0xf) << 12);
1499 instruction |= ((Rn.value() & 0xf) << 16);
1500 instruction |= (Rm.value() & 0xf);
1501 instruction |= ((shift_imm & 0x1f) << 7);
1502 emitInt(instruction);
1503 }
1504
1505 /**
1506 * Pseudo-external assembler syntax: {@code eor{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
1507 * Example disassembly syntax: {@code eoreq r0, r0, r0, lsr #0x0}
1508 * <p>
1509 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
1510 *
1511 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.15"
1512 */
1513 // Template#: 77, Serial#: 77
1514 public void eorlsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
1515 int instruction = 0x00200020;
1516 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
1517 instruction |= ((cond.value() & 0xf) << 28);
1518 instruction |= ((s.value() & 0x1) << 20);
1519 instruction |= ((Rd.value() & 0xf) << 12);
1520 instruction |= ((Rn.value() & 0xf) << 16);
1521 instruction |= (Rm.value() & 0xf);
1522 instruction |= ((shift_imm % 32 & 0x1f) << 7);
1523 emitInt(instruction);
1524 }
1525
1526 /**
1527 * Pseudo-external assembler syntax: {@code eor{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
1528 * Example disassembly syntax: {@code eoreq r0, r0, r0, asr #0x0}
1529 * <p>
1530 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
1531 *
1532 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.15"
1533 */
1534 // Template#: 78, Serial#: 78
1535 public void eorasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
1536 int instruction = 0x00200040;
1537 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
1538 instruction |= ((cond.value() & 0xf) << 28);
1539 instruction |= ((s.value() & 0x1) << 20);
1540 instruction |= ((Rd.value() & 0xf) << 12);
1541 instruction |= ((Rn.value() & 0xf) << 16);
1542 instruction |= (Rm.value() & 0xf);
1543 instruction |= ((shift_imm % 32 & 0x1f) << 7);
1544 emitInt(instruction);
1545 }
1546
1547 /**
1548 * Pseudo-external assembler syntax: {@code eor{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
1549 * Example disassembly syntax: {@code eoreq r0, r0, r0, ror #0x0}
1550 * <p>
1551 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
1552 *
1553 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.15"
1554 */
1555 // Template#: 79, Serial#: 79
1556 public void eorror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
1557 int instruction = 0x00200060;
1558 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
1559 instruction |= ((cond.value() & 0xf) << 28);
1560 instruction |= ((s.value() & 0x1) << 20);
1561 instruction |= ((Rd.value() & 0xf) << 12);
1562 instruction |= ((Rn.value() & 0xf) << 16);
1563 instruction |= (Rm.value() & 0xf);
1564 instruction |= ((shift_imm & 0x1f) << 7);
1565 emitInt(instruction);
1566 }
1567
1568 /**
1569 * Pseudo-external assembler syntax: {@code eor{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
1570 * Example disassembly syntax: {@code eoreq r0, r0, r0, lsl r0}
1571 *
1572 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.15"
1573 */
1574 // Template#: 80, Serial#: 80
1575 public void eorlsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
1576 int instruction = 0x00200010;
1577 instruction |= ((cond.value() & 0xf) << 28);
1578 instruction |= ((s.value() & 0x1) << 20);
1579 instruction |= ((Rd.value() & 0xf) << 12);
1580 instruction |= ((Rn.value() & 0xf) << 16);
1581 instruction |= (Rm.value() & 0xf);
1582 instruction |= ((Rs.value() & 0xf) << 8);
1583 emitInt(instruction);
1584 }
1585
1586 /**
1587 * Pseudo-external assembler syntax: {@code eor{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
1588 * Example disassembly syntax: {@code eoreq r0, r0, r0, lsr r0}
1589 *
1590 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.15"
1591 */
1592 // Template#: 81, Serial#: 81
1593 public void eorlsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
1594 int instruction = 0x00200030;
1595 instruction |= ((cond.value() & 0xf) << 28);
1596 instruction |= ((s.value() & 0x1) << 20);
1597 instruction |= ((Rd.value() & 0xf) << 12);
1598 instruction |= ((Rn.value() & 0xf) << 16);
1599 instruction |= (Rm.value() & 0xf);
1600 instruction |= ((Rs.value() & 0xf) << 8);
1601 emitInt(instruction);
1602 }
1603
1604 /**
1605 * Pseudo-external assembler syntax: {@code eor{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
1606 * Example disassembly syntax: {@code eoreq r0, r0, r0, asr r0}
1607 *
1608 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.15"
1609 */
1610 // Template#: 82, Serial#: 82
1611 public void eorasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
1612 int instruction = 0x00200050;
1613 instruction |= ((cond.value() & 0xf) << 28);
1614 instruction |= ((s.value() & 0x1) << 20);
1615 instruction |= ((Rd.value() & 0xf) << 12);
1616 instruction |= ((Rn.value() & 0xf) << 16);
1617 instruction |= (Rm.value() & 0xf);
1618 instruction |= ((Rs.value() & 0xf) << 8);
1619 emitInt(instruction);
1620 }
1621
1622 /**
1623 * Pseudo-external assembler syntax: {@code eor{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
1624 * Example disassembly syntax: {@code eoreq r0, r0, r0, ror r0}
1625 *
1626 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.15"
1627 */
1628 // Template#: 83, Serial#: 83
1629 public void eorror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
1630 int instruction = 0x00200070;
1631 instruction |= ((cond.value() & 0xf) << 28);
1632 instruction |= ((s.value() & 0x1) << 20);
1633 instruction |= ((Rd.value() & 0xf) << 12);
1634 instruction |= ((Rn.value() & 0xf) << 16);
1635 instruction |= (Rm.value() & 0xf);
1636 instruction |= ((Rs.value() & 0xf) << 8);
1637 emitInt(instruction);
1638 }
1639
1640 /**
1641 * Pseudo-external assembler syntax: {@code eor{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
1642 * Example disassembly syntax: {@code eoreq r0, r0, r0, rrx }
1643 *
1644 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.15"
1645 */
1646 // Template#: 84, Serial#: 84
1647 public void eorrrx(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
1648 int instruction = 0x00200060;
1649 instruction |= ((cond.value() & 0xf) << 28);
1650 instruction |= ((s.value() & 0x1) << 20);
1651 instruction |= ((Rd.value() & 0xf) << 12);
1652 instruction |= ((Rn.value() & 0xf) << 16);
1653 instruction |= (Rm.value() & 0xf);
1654 emitInt(instruction);
1655 }
1656
1657 /**
1658 * Pseudo-external assembler syntax: {@code mov{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>immediate</i>
1659 * Example disassembly syntax: {@code moveq r0, #0x0}
1660 * <p>
1661 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
1662 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
1663 *
1664 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
1665 *
1666 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.29"
1667 */
1668 // Template#: 85, Serial#: 85
1669 public void mov(final ConditionCode cond, final SBit s, final GPR Rd, final int immediate) {
1670 int instruction = 0x03A00000;
1671 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
1672 instruction |= ((cond.value() & 0xf) << 28);
1673 instruction |= ((s.value() & 0x1) << 20);
1674 instruction |= ((Rd.value() & 0xf) << 12);
1675 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
1676 emitInt(instruction);
1677 }
1678
1679 /**
1680 * Pseudo-external assembler syntax: {@code mov{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>immed_8</i>, <i>rotate_amount</i>
1681 * Example disassembly syntax: {@code moveq r0, #0x0, 0x0}
1682 * <p>
1683 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
1684 * Constraint: {@code (rotate_amount % 2) == 0}<br />
1685 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
1686 *
1687 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.29"
1688 */
1689 // Template#: 86, Serial#: 86
1690 public void mov(final ConditionCode cond, final SBit s, final GPR Rd, final int immed_8, final int rotate_amount) {
1691 int instruction = 0x03A00000;
1692 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
1693 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
1694 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
1695 instruction |= ((cond.value() & 0xf) << 28);
1696 instruction |= ((s.value() & 0x1) << 20);
1697 instruction |= ((Rd.value() & 0xf) << 12);
1698 instruction |= (immed_8 & 0xff);
1699 instruction |= ((rotate_amount / 2 & 0xf) << 8);
1700 emitInt(instruction);
1701 }
1702
1703 /**
1704 * Pseudo-external assembler syntax: {@code mov{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>
1705 * Example disassembly syntax: {@code moveq r0, r0}
1706 *
1707 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.29"
1708 */
1709 // Template#: 87, Serial#: 87
1710 public void mov(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm) {
1711 int instruction = 0x01A00000;
1712 instruction |= ((cond.value() & 0xf) << 28);
1713 instruction |= ((s.value() & 0x1) << 20);
1714 instruction |= ((Rd.value() & 0xf) << 12);
1715 instruction |= (Rm.value() & 0xf);
1716 emitInt(instruction);
1717 }
1718
1719 /**
1720 * Pseudo-external assembler syntax: {@code mov{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>shift_imm</i>
1721 * Example disassembly syntax: {@code moveq r0, r0, lsl #0x0}
1722 * <p>
1723 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
1724 *
1725 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.29"
1726 */
1727 // Template#: 88, Serial#: 88
1728 public void movlsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final int shift_imm) {
1729 int instruction = 0x01A00000;
1730 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
1731 instruction |= ((cond.value() & 0xf) << 28);
1732 instruction |= ((s.value() & 0x1) << 20);
1733 instruction |= ((Rd.value() & 0xf) << 12);
1734 instruction |= (Rm.value() & 0xf);
1735 instruction |= ((shift_imm & 0x1f) << 7);
1736 emitInt(instruction);
1737 }
1738
1739 /**
1740 * Pseudo-external assembler syntax: {@code mov{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>shift_imm</i>
1741 * Example disassembly syntax: {@code moveq r0, r0, lsr #0x0}
1742 * <p>
1743 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
1744 *
1745 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.29"
1746 */
1747 // Template#: 89, Serial#: 89
1748 public void movlsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final int shift_imm) {
1749 int instruction = 0x01A00020;
1750 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
1751 instruction |= ((cond.value() & 0xf) << 28);
1752 instruction |= ((s.value() & 0x1) << 20);
1753 instruction |= ((Rd.value() & 0xf) << 12);
1754 instruction |= (Rm.value() & 0xf);
1755 instruction |= ((shift_imm % 32 & 0x1f) << 7);
1756 emitInt(instruction);
1757 }
1758
1759 /**
1760 * Pseudo-external assembler syntax: {@code mov{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>shift_imm</i>
1761 * Example disassembly syntax: {@code moveq r0, r0, asr #0x0}
1762 * <p>
1763 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
1764 *
1765 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.29"
1766 */
1767 // Template#: 90, Serial#: 90
1768 public void movasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final int shift_imm) {
1769 int instruction = 0x01A00040;
1770 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
1771 instruction |= ((cond.value() & 0xf) << 28);
1772 instruction |= ((s.value() & 0x1) << 20);
1773 instruction |= ((Rd.value() & 0xf) << 12);
1774 instruction |= (Rm.value() & 0xf);
1775 instruction |= ((shift_imm % 32 & 0x1f) << 7);
1776 emitInt(instruction);
1777 }
1778
1779 /**
1780 * Pseudo-external assembler syntax: {@code mov{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>shift_imm</i>
1781 * Example disassembly syntax: {@code moveq r0, r0, ror #0x0}
1782 * <p>
1783 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
1784 *
1785 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.29"
1786 */
1787 // Template#: 91, Serial#: 91
1788 public void movror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final int shift_imm) {
1789 int instruction = 0x01A00060;
1790 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
1791 instruction |= ((cond.value() & 0xf) << 28);
1792 instruction |= ((s.value() & 0x1) << 20);
1793 instruction |= ((Rd.value() & 0xf) << 12);
1794 instruction |= (Rm.value() & 0xf);
1795 instruction |= ((shift_imm & 0x1f) << 7);
1796 emitInt(instruction);
1797 }
1798
1799 /**
1800 * Pseudo-external assembler syntax: {@code mov{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>Rs</i>
1801 * Example disassembly syntax: {@code moveq r0, r0, lsl r0}
1802 *
1803 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.29"
1804 */
1805 // Template#: 92, Serial#: 92
1806 public void movlsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final GPR Rs) {
1807 int instruction = 0x01A00010;
1808 instruction |= ((cond.value() & 0xf) << 28);
1809 instruction |= ((s.value() & 0x1) << 20);
1810 instruction |= ((Rd.value() & 0xf) << 12);
1811 instruction |= (Rm.value() & 0xf);
1812 instruction |= ((Rs.value() & 0xf) << 8);
1813 emitInt(instruction);
1814 }
1815
1816 /**
1817 * Pseudo-external assembler syntax: {@code mov{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>Rs</i>
1818 * Example disassembly syntax: {@code moveq r0, r0, lsr r0}
1819 *
1820 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.29"
1821 */
1822 // Template#: 93, Serial#: 93
1823 public void movlsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final GPR Rs) {
1824 int instruction = 0x01A00030;
1825 instruction |= ((cond.value() & 0xf) << 28);
1826 instruction |= ((s.value() & 0x1) << 20);
1827 instruction |= ((Rd.value() & 0xf) << 12);
1828 instruction |= (Rm.value() & 0xf);
1829 instruction |= ((Rs.value() & 0xf) << 8);
1830 emitInt(instruction);
1831 }
1832
1833 /**
1834 * Pseudo-external assembler syntax: {@code mov{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>Rs</i>
1835 * Example disassembly syntax: {@code moveq r0, r0, asr r0}
1836 *
1837 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.29"
1838 */
1839 // Template#: 94, Serial#: 94
1840 public void movasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final GPR Rs) {
1841 int instruction = 0x01A00050;
1842 instruction |= ((cond.value() & 0xf) << 28);
1843 instruction |= ((s.value() & 0x1) << 20);
1844 instruction |= ((Rd.value() & 0xf) << 12);
1845 instruction |= (Rm.value() & 0xf);
1846 instruction |= ((Rs.value() & 0xf) << 8);
1847 emitInt(instruction);
1848 }
1849
1850 /**
1851 * Pseudo-external assembler syntax: {@code mov{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>Rs</i>
1852 * Example disassembly syntax: {@code moveq r0, r0, ror r0}
1853 *
1854 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.29"
1855 */
1856 // Template#: 95, Serial#: 95
1857 public void movror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final GPR Rs) {
1858 int instruction = 0x01A00070;
1859 instruction |= ((cond.value() & 0xf) << 28);
1860 instruction |= ((s.value() & 0x1) << 20);
1861 instruction |= ((Rd.value() & 0xf) << 12);
1862 instruction |= (Rm.value() & 0xf);
1863 instruction |= ((Rs.value() & 0xf) << 8);
1864 emitInt(instruction);
1865 }
1866
1867 /**
1868 * Pseudo-external assembler syntax: {@code mov{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>
1869 * Example disassembly syntax: {@code moveq r0, r0, rrx }
1870 *
1871 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.29"
1872 */
1873 // Template#: 96, Serial#: 96
1874 public void movrrx(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm) {
1875 int instruction = 0x01A00060;
1876 instruction |= ((cond.value() & 0xf) << 28);
1877 instruction |= ((s.value() & 0x1) << 20);
1878 instruction |= ((Rd.value() & 0xf) << 12);
1879 instruction |= (Rm.value() & 0xf);
1880 emitInt(instruction);
1881 }
1882
1883 /**
1884 * Pseudo-external assembler syntax: {@code mvn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>immediate</i>
1885 * Example disassembly syntax: {@code mvneq r0, #0x0}
1886 * <p>
1887 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
1888 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
1889 *
1890 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
1891 *
1892 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.34"
1893 */
1894 // Template#: 97, Serial#: 97
1895 public void mvn(final ConditionCode cond, final SBit s, final GPR Rd, final int immediate) {
1896 int instruction = 0x03E00000;
1897 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
1898 instruction |= ((cond.value() & 0xf) << 28);
1899 instruction |= ((s.value() & 0x1) << 20);
1900 instruction |= ((Rd.value() & 0xf) << 12);
1901 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
1902 emitInt(instruction);
1903 }
1904
1905 /**
1906 * Pseudo-external assembler syntax: {@code mvn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>immed_8</i>, <i>rotate_amount</i>
1907 * Example disassembly syntax: {@code mvneq r0, #0x0, 0x0}
1908 * <p>
1909 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
1910 * Constraint: {@code (rotate_amount % 2) == 0}<br />
1911 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
1912 *
1913 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.34"
1914 */
1915 // Template#: 98, Serial#: 98
1916 public void mvn(final ConditionCode cond, final SBit s, final GPR Rd, final int immed_8, final int rotate_amount) {
1917 int instruction = 0x03E00000;
1918 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
1919 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
1920 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
1921 instruction |= ((cond.value() & 0xf) << 28);
1922 instruction |= ((s.value() & 0x1) << 20);
1923 instruction |= ((Rd.value() & 0xf) << 12);
1924 instruction |= (immed_8 & 0xff);
1925 instruction |= ((rotate_amount / 2 & 0xf) << 8);
1926 emitInt(instruction);
1927 }
1928
1929 /**
1930 * Pseudo-external assembler syntax: {@code mvn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>
1931 * Example disassembly syntax: {@code mvneq r0, r0}
1932 *
1933 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.34"
1934 */
1935 // Template#: 99, Serial#: 99
1936 public void mvn(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm) {
1937 int instruction = 0x01E00000;
1938 instruction |= ((cond.value() & 0xf) << 28);
1939 instruction |= ((s.value() & 0x1) << 20);
1940 instruction |= ((Rd.value() & 0xf) << 12);
1941 instruction |= (Rm.value() & 0xf);
1942 emitInt(instruction);
1943 }
1944
1945 /**
1946 * Pseudo-external assembler syntax: {@code mvn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>shift_imm</i>
1947 * Example disassembly syntax: {@code mvneq r0, r0, lsl #0x0}
1948 * <p>
1949 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
1950 *
1951 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.34"
1952 */
1953 // Template#: 100, Serial#: 100
1954 public void mvnlsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final int shift_imm) {
1955 int instruction = 0x01E00000;
1956 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
1957 instruction |= ((cond.value() & 0xf) << 28);
1958 instruction |= ((s.value() & 0x1) << 20);
1959 instruction |= ((Rd.value() & 0xf) << 12);
1960 instruction |= (Rm.value() & 0xf);
1961 instruction |= ((shift_imm & 0x1f) << 7);
1962 emitInt(instruction);
1963 }
1964
1965 /**
1966 * Pseudo-external assembler syntax: {@code mvn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>shift_imm</i>
1967 * Example disassembly syntax: {@code mvneq r0, r0, lsr #0x0}
1968 * <p>
1969 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
1970 *
1971 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.34"
1972 */
1973 // Template#: 101, Serial#: 101
1974 public void mvnlsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final int shift_imm) {
1975 int instruction = 0x01E00020;
1976 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
1977 instruction |= ((cond.value() & 0xf) << 28);
1978 instruction |= ((s.value() & 0x1) << 20);
1979 instruction |= ((Rd.value() & 0xf) << 12);
1980 instruction |= (Rm.value() & 0xf);
1981 instruction |= ((shift_imm % 32 & 0x1f) << 7);
1982 emitInt(instruction);
1983 }
1984
1985 /**
1986 * Pseudo-external assembler syntax: {@code mvn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>shift_imm</i>
1987 * Example disassembly syntax: {@code mvneq r0, r0, asr #0x0}
1988 * <p>
1989 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
1990 *
1991 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.34"
1992 */
1993 // Template#: 102, Serial#: 102
1994 public void mvnasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final int shift_imm) {
1995 int instruction = 0x01E00040;
1996 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
1997 instruction |= ((cond.value() & 0xf) << 28);
1998 instruction |= ((s.value() & 0x1) << 20);
1999 instruction |= ((Rd.value() & 0xf) << 12);
2000 instruction |= (Rm.value() & 0xf);
2001 instruction |= ((shift_imm % 32 & 0x1f) << 7);
2002 emitInt(instruction);
2003 }
2004
2005 /**
2006 * Pseudo-external assembler syntax: {@code mvn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>shift_imm</i>
2007 * Example disassembly syntax: {@code mvneq r0, r0, ror #0x0}
2008 * <p>
2009 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
2010 *
2011 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.34"
2012 */
2013 // Template#: 103, Serial#: 103
2014 public void mvnror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final int shift_imm) {
2015 int instruction = 0x01E00060;
2016 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
2017 instruction |= ((cond.value() & 0xf) << 28);
2018 instruction |= ((s.value() & 0x1) << 20);
2019 instruction |= ((Rd.value() & 0xf) << 12);
2020 instruction |= (Rm.value() & 0xf);
2021 instruction |= ((shift_imm & 0x1f) << 7);
2022 emitInt(instruction);
2023 }
2024
2025 /**
2026 * Pseudo-external assembler syntax: {@code mvn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>Rs</i>
2027 * Example disassembly syntax: {@code mvneq r0, r0, lsl r0}
2028 *
2029 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.34"
2030 */
2031 // Template#: 104, Serial#: 104
2032 public void mvnlsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final GPR Rs) {
2033 int instruction = 0x01E00010;
2034 instruction |= ((cond.value() & 0xf) << 28);
2035 instruction |= ((s.value() & 0x1) << 20);
2036 instruction |= ((Rd.value() & 0xf) << 12);
2037 instruction |= (Rm.value() & 0xf);
2038 instruction |= ((Rs.value() & 0xf) << 8);
2039 emitInt(instruction);
2040 }
2041
2042 /**
2043 * Pseudo-external assembler syntax: {@code mvn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>Rs</i>
2044 * Example disassembly syntax: {@code mvneq r0, r0, lsr r0}
2045 *
2046 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.34"
2047 */
2048 // Template#: 105, Serial#: 105
2049 public void mvnlsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final GPR Rs) {
2050 int instruction = 0x01E00030;
2051 instruction |= ((cond.value() & 0xf) << 28);
2052 instruction |= ((s.value() & 0x1) << 20);
2053 instruction |= ((Rd.value() & 0xf) << 12);
2054 instruction |= (Rm.value() & 0xf);
2055 instruction |= ((Rs.value() & 0xf) << 8);
2056 emitInt(instruction);
2057 }
2058
2059 /**
2060 * Pseudo-external assembler syntax: {@code mvn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>Rs</i>
2061 * Example disassembly syntax: {@code mvneq r0, r0, asr r0}
2062 *
2063 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.34"
2064 */
2065 // Template#: 106, Serial#: 106
2066 public void mvnasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final GPR Rs) {
2067 int instruction = 0x01E00050;
2068 instruction |= ((cond.value() & 0xf) << 28);
2069 instruction |= ((s.value() & 0x1) << 20);
2070 instruction |= ((Rd.value() & 0xf) << 12);
2071 instruction |= (Rm.value() & 0xf);
2072 instruction |= ((Rs.value() & 0xf) << 8);
2073 emitInt(instruction);
2074 }
2075
2076 /**
2077 * Pseudo-external assembler syntax: {@code mvn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>Rs</i>
2078 * Example disassembly syntax: {@code mvneq r0, r0, ror r0}
2079 *
2080 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.34"
2081 */
2082 // Template#: 107, Serial#: 107
2083 public void mvnror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final GPR Rs) {
2084 int instruction = 0x01E00070;
2085 instruction |= ((cond.value() & 0xf) << 28);
2086 instruction |= ((s.value() & 0x1) << 20);
2087 instruction |= ((Rd.value() & 0xf) << 12);
2088 instruction |= (Rm.value() & 0xf);
2089 instruction |= ((Rs.value() & 0xf) << 8);
2090 emitInt(instruction);
2091 }
2092
2093 /**
2094 * Pseudo-external assembler syntax: {@code mvn{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>
2095 * Example disassembly syntax: {@code mvneq r0, r0, rrx }
2096 *
2097 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.34"
2098 */
2099 // Template#: 108, Serial#: 108
2100 public void mvnrrx(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm) {
2101 int instruction = 0x01E00060;
2102 instruction |= ((cond.value() & 0xf) << 28);
2103 instruction |= ((s.value() & 0x1) << 20);
2104 instruction |= ((Rd.value() & 0xf) << 12);
2105 instruction |= (Rm.value() & 0xf);
2106 emitInt(instruction);
2107 }
2108
2109 /**
2110 * Pseudo-external assembler syntax: {@code orr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immediate</i>
2111 * Example disassembly syntax: {@code orreq r0, r0, #0x0}
2112 * <p>
2113 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
2114 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
2115 *
2116 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
2117 *
2118 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.35"
2119 */
2120 // Template#: 109, Serial#: 109
2121 public void orr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immediate) {
2122 int instruction = 0x03800000;
2123 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
2124 instruction |= ((cond.value() & 0xf) << 28);
2125 instruction |= ((s.value() & 0x1) << 20);
2126 instruction |= ((Rd.value() & 0xf) << 12);
2127 instruction |= ((Rn.value() & 0xf) << 16);
2128 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
2129 emitInt(instruction);
2130 }
2131
2132 /**
2133 * Pseudo-external assembler syntax: {@code orr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immed_8</i>, <i>rotate_amount</i>
2134 * Example disassembly syntax: {@code orreq r0, r0, #0x0, 0x0}
2135 * <p>
2136 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
2137 * Constraint: {@code (rotate_amount % 2) == 0}<br />
2138 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
2139 *
2140 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.35"
2141 */
2142 // Template#: 110, Serial#: 110
2143 public void orr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immed_8, final int rotate_amount) {
2144 int instruction = 0x03800000;
2145 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
2146 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
2147 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
2148 instruction |= ((cond.value() & 0xf) << 28);
2149 instruction |= ((s.value() & 0x1) << 20);
2150 instruction |= ((Rd.value() & 0xf) << 12);
2151 instruction |= ((Rn.value() & 0xf) << 16);
2152 instruction |= (immed_8 & 0xff);
2153 instruction |= ((rotate_amount / 2 & 0xf) << 8);
2154 emitInt(instruction);
2155 }
2156
2157 /**
2158 * Pseudo-external assembler syntax: {@code orr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
2159 * Example disassembly syntax: {@code orreq r0, r0, r0}
2160 *
2161 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.35"
2162 */
2163 // Template#: 111, Serial#: 111
2164 public void orr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
2165 int instruction = 0x01800000;
2166 instruction |= ((cond.value() & 0xf) << 28);
2167 instruction |= ((s.value() & 0x1) << 20);
2168 instruction |= ((Rd.value() & 0xf) << 12);
2169 instruction |= ((Rn.value() & 0xf) << 16);
2170 instruction |= (Rm.value() & 0xf);
2171 emitInt(instruction);
2172 }
2173
2174 /**
2175 * Pseudo-external assembler syntax: {@code orr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2176 * Example disassembly syntax: {@code orreq r0, r0, r0, lsl #0x0}
2177 * <p>
2178 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
2179 *
2180 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.35"
2181 */
2182 // Template#: 112, Serial#: 112
2183 public void orrlsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2184 int instruction = 0x01800000;
2185 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
2186 instruction |= ((cond.value() & 0xf) << 28);
2187 instruction |= ((s.value() & 0x1) << 20);
2188 instruction |= ((Rd.value() & 0xf) << 12);
2189 instruction |= ((Rn.value() & 0xf) << 16);
2190 instruction |= (Rm.value() & 0xf);
2191 instruction |= ((shift_imm & 0x1f) << 7);
2192 emitInt(instruction);
2193 }
2194
2195 /**
2196 * Pseudo-external assembler syntax: {@code orr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2197 * Example disassembly syntax: {@code orreq r0, r0, r0, lsr #0x0}
2198 * <p>
2199 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
2200 *
2201 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.35"
2202 */
2203 // Template#: 113, Serial#: 113
2204 public void orrlsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2205 int instruction = 0x01800020;
2206 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
2207 instruction |= ((cond.value() & 0xf) << 28);
2208 instruction |= ((s.value() & 0x1) << 20);
2209 instruction |= ((Rd.value() & 0xf) << 12);
2210 instruction |= ((Rn.value() & 0xf) << 16);
2211 instruction |= (Rm.value() & 0xf);
2212 instruction |= ((shift_imm % 32 & 0x1f) << 7);
2213 emitInt(instruction);
2214 }
2215
2216 /**
2217 * Pseudo-external assembler syntax: {@code orr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2218 * Example disassembly syntax: {@code orreq r0, r0, r0, asr #0x0}
2219 * <p>
2220 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
2221 *
2222 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.35"
2223 */
2224 // Template#: 114, Serial#: 114
2225 public void orrasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2226 int instruction = 0x01800040;
2227 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
2228 instruction |= ((cond.value() & 0xf) << 28);
2229 instruction |= ((s.value() & 0x1) << 20);
2230 instruction |= ((Rd.value() & 0xf) << 12);
2231 instruction |= ((Rn.value() & 0xf) << 16);
2232 instruction |= (Rm.value() & 0xf);
2233 instruction |= ((shift_imm % 32 & 0x1f) << 7);
2234 emitInt(instruction);
2235 }
2236
2237 /**
2238 * Pseudo-external assembler syntax: {@code orr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2239 * Example disassembly syntax: {@code orreq r0, r0, r0, ror #0x0}
2240 * <p>
2241 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
2242 *
2243 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.35"
2244 */
2245 // Template#: 115, Serial#: 115
2246 public void orrror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2247 int instruction = 0x01800060;
2248 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
2249 instruction |= ((cond.value() & 0xf) << 28);
2250 instruction |= ((s.value() & 0x1) << 20);
2251 instruction |= ((Rd.value() & 0xf) << 12);
2252 instruction |= ((Rn.value() & 0xf) << 16);
2253 instruction |= (Rm.value() & 0xf);
2254 instruction |= ((shift_imm & 0x1f) << 7);
2255 emitInt(instruction);
2256 }
2257
2258 /**
2259 * Pseudo-external assembler syntax: {@code orr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
2260 * Example disassembly syntax: {@code orreq r0, r0, r0, lsl r0}
2261 *
2262 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.35"
2263 */
2264 // Template#: 116, Serial#: 116
2265 public void orrlsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
2266 int instruction = 0x01800010;
2267 instruction |= ((cond.value() & 0xf) << 28);
2268 instruction |= ((s.value() & 0x1) << 20);
2269 instruction |= ((Rd.value() & 0xf) << 12);
2270 instruction |= ((Rn.value() & 0xf) << 16);
2271 instruction |= (Rm.value() & 0xf);
2272 instruction |= ((Rs.value() & 0xf) << 8);
2273 emitInt(instruction);
2274 }
2275
2276 /**
2277 * Pseudo-external assembler syntax: {@code orr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
2278 * Example disassembly syntax: {@code orreq r0, r0, r0, lsr r0}
2279 *
2280 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.35"
2281 */
2282 // Template#: 117, Serial#: 117
2283 public void orrlsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
2284 int instruction = 0x01800030;
2285 instruction |= ((cond.value() & 0xf) << 28);
2286 instruction |= ((s.value() & 0x1) << 20);
2287 instruction |= ((Rd.value() & 0xf) << 12);
2288 instruction |= ((Rn.value() & 0xf) << 16);
2289 instruction |= (Rm.value() & 0xf);
2290 instruction |= ((Rs.value() & 0xf) << 8);
2291 emitInt(instruction);
2292 }
2293
2294 /**
2295 * Pseudo-external assembler syntax: {@code orr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
2296 * Example disassembly syntax: {@code orreq r0, r0, r0, asr r0}
2297 *
2298 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.35"
2299 */
2300 // Template#: 118, Serial#: 118
2301 public void orrasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
2302 int instruction = 0x01800050;
2303 instruction |= ((cond.value() & 0xf) << 28);
2304 instruction |= ((s.value() & 0x1) << 20);
2305 instruction |= ((Rd.value() & 0xf) << 12);
2306 instruction |= ((Rn.value() & 0xf) << 16);
2307 instruction |= (Rm.value() & 0xf);
2308 instruction |= ((Rs.value() & 0xf) << 8);
2309 emitInt(instruction);
2310 }
2311
2312 /**
2313 * Pseudo-external assembler syntax: {@code orr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
2314 * Example disassembly syntax: {@code orreq r0, r0, r0, ror r0}
2315 *
2316 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.35"
2317 */
2318 // Template#: 119, Serial#: 119
2319 public void orrror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
2320 int instruction = 0x01800070;
2321 instruction |= ((cond.value() & 0xf) << 28);
2322 instruction |= ((s.value() & 0x1) << 20);
2323 instruction |= ((Rd.value() & 0xf) << 12);
2324 instruction |= ((Rn.value() & 0xf) << 16);
2325 instruction |= (Rm.value() & 0xf);
2326 instruction |= ((Rs.value() & 0xf) << 8);
2327 emitInt(instruction);
2328 }
2329
2330 /**
2331 * Pseudo-external assembler syntax: {@code orr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
2332 * Example disassembly syntax: {@code orreq r0, r0, r0, rrx }
2333 *
2334 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.35"
2335 */
2336 // Template#: 120, Serial#: 120
2337 public void orrrrx(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
2338 int instruction = 0x01800060;
2339 instruction |= ((cond.value() & 0xf) << 28);
2340 instruction |= ((s.value() & 0x1) << 20);
2341 instruction |= ((Rd.value() & 0xf) << 12);
2342 instruction |= ((Rn.value() & 0xf) << 16);
2343 instruction |= (Rm.value() & 0xf);
2344 emitInt(instruction);
2345 }
2346
2347 /**
2348 * Pseudo-external assembler syntax: {@code rsb{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immediate</i>
2349 * Example disassembly syntax: {@code rsbeq r0, r0, #0x0}
2350 * <p>
2351 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
2352 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
2353 *
2354 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
2355 *
2356 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.36"
2357 */
2358 // Template#: 121, Serial#: 121
2359 public void rsb(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immediate) {
2360 int instruction = 0x02600000;
2361 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
2362 instruction |= ((cond.value() & 0xf) << 28);
2363 instruction |= ((s.value() & 0x1) << 20);
2364 instruction |= ((Rd.value() & 0xf) << 12);
2365 instruction |= ((Rn.value() & 0xf) << 16);
2366 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
2367 emitInt(instruction);
2368 }
2369
2370 /**
2371 * Pseudo-external assembler syntax: {@code rsb{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immed_8</i>, <i>rotate_amount</i>
2372 * Example disassembly syntax: {@code rsbeq r0, r0, #0x0, 0x0}
2373 * <p>
2374 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
2375 * Constraint: {@code (rotate_amount % 2) == 0}<br />
2376 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
2377 *
2378 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.36"
2379 */
2380 // Template#: 122, Serial#: 122
2381 public void rsb(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immed_8, final int rotate_amount) {
2382 int instruction = 0x02600000;
2383 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
2384 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
2385 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
2386 instruction |= ((cond.value() & 0xf) << 28);
2387 instruction |= ((s.value() & 0x1) << 20);
2388 instruction |= ((Rd.value() & 0xf) << 12);
2389 instruction |= ((Rn.value() & 0xf) << 16);
2390 instruction |= (immed_8 & 0xff);
2391 instruction |= ((rotate_amount / 2 & 0xf) << 8);
2392 emitInt(instruction);
2393 }
2394
2395 /**
2396 * Pseudo-external assembler syntax: {@code rsb{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
2397 * Example disassembly syntax: {@code rsbeq r0, r0, r0}
2398 *
2399 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.36"
2400 */
2401 // Template#: 123, Serial#: 123
2402 public void rsb(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
2403 int instruction = 0x00600000;
2404 instruction |= ((cond.value() & 0xf) << 28);
2405 instruction |= ((s.value() & 0x1) << 20);
2406 instruction |= ((Rd.value() & 0xf) << 12);
2407 instruction |= ((Rn.value() & 0xf) << 16);
2408 instruction |= (Rm.value() & 0xf);
2409 emitInt(instruction);
2410 }
2411
2412 /**
2413 * Pseudo-external assembler syntax: {@code rsb{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2414 * Example disassembly syntax: {@code rsbeq r0, r0, r0, lsl #0x0}
2415 * <p>
2416 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
2417 *
2418 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.36"
2419 */
2420 // Template#: 124, Serial#: 124
2421 public void rsblsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2422 int instruction = 0x00600000;
2423 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
2424 instruction |= ((cond.value() & 0xf) << 28);
2425 instruction |= ((s.value() & 0x1) << 20);
2426 instruction |= ((Rd.value() & 0xf) << 12);
2427 instruction |= ((Rn.value() & 0xf) << 16);
2428 instruction |= (Rm.value() & 0xf);
2429 instruction |= ((shift_imm & 0x1f) << 7);
2430 emitInt(instruction);
2431 }
2432
2433 /**
2434 * Pseudo-external assembler syntax: {@code rsb{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2435 * Example disassembly syntax: {@code rsbeq r0, r0, r0, lsr #0x0}
2436 * <p>
2437 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
2438 *
2439 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.36"
2440 */
2441 // Template#: 125, Serial#: 125
2442 public void rsblsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2443 int instruction = 0x00600020;
2444 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
2445 instruction |= ((cond.value() & 0xf) << 28);
2446 instruction |= ((s.value() & 0x1) << 20);
2447 instruction |= ((Rd.value() & 0xf) << 12);
2448 instruction |= ((Rn.value() & 0xf) << 16);
2449 instruction |= (Rm.value() & 0xf);
2450 instruction |= ((shift_imm % 32 & 0x1f) << 7);
2451 emitInt(instruction);
2452 }
2453
2454 /**
2455 * Pseudo-external assembler syntax: {@code rsb{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2456 * Example disassembly syntax: {@code rsbeq r0, r0, r0, asr #0x0}
2457 * <p>
2458 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
2459 *
2460 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.36"
2461 */
2462 // Template#: 126, Serial#: 126
2463 public void rsbasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2464 int instruction = 0x00600040;
2465 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
2466 instruction |= ((cond.value() & 0xf) << 28);
2467 instruction |= ((s.value() & 0x1) << 20);
2468 instruction |= ((Rd.value() & 0xf) << 12);
2469 instruction |= ((Rn.value() & 0xf) << 16);
2470 instruction |= (Rm.value() & 0xf);
2471 instruction |= ((shift_imm % 32 & 0x1f) << 7);
2472 emitInt(instruction);
2473 }
2474
2475 /**
2476 * Pseudo-external assembler syntax: {@code rsb{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2477 * Example disassembly syntax: {@code rsbeq r0, r0, r0, ror #0x0}
2478 * <p>
2479 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
2480 *
2481 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.36"
2482 */
2483 // Template#: 127, Serial#: 127
2484 public void rsbror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2485 int instruction = 0x00600060;
2486 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
2487 instruction |= ((cond.value() & 0xf) << 28);
2488 instruction |= ((s.value() & 0x1) << 20);
2489 instruction |= ((Rd.value() & 0xf) << 12);
2490 instruction |= ((Rn.value() & 0xf) << 16);
2491 instruction |= (Rm.value() & 0xf);
2492 instruction |= ((shift_imm & 0x1f) << 7);
2493 emitInt(instruction);
2494 }
2495
2496 /**
2497 * Pseudo-external assembler syntax: {@code rsb{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
2498 * Example disassembly syntax: {@code rsbeq r0, r0, r0, lsl r0}
2499 *
2500 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.36"
2501 */
2502 // Template#: 128, Serial#: 128
2503 public void rsblsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
2504 int instruction = 0x00600010;
2505 instruction |= ((cond.value() & 0xf) << 28);
2506 instruction |= ((s.value() & 0x1) << 20);
2507 instruction |= ((Rd.value() & 0xf) << 12);
2508 instruction |= ((Rn.value() & 0xf) << 16);
2509 instruction |= (Rm.value() & 0xf);
2510 instruction |= ((Rs.value() & 0xf) << 8);
2511 emitInt(instruction);
2512 }
2513
2514 /**
2515 * Pseudo-external assembler syntax: {@code rsb{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
2516 * Example disassembly syntax: {@code rsbeq r0, r0, r0, lsr r0}
2517 *
2518 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.36"
2519 */
2520 // Template#: 129, Serial#: 129
2521 public void rsblsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
2522 int instruction = 0x00600030;
2523 instruction |= ((cond.value() & 0xf) << 28);
2524 instruction |= ((s.value() & 0x1) << 20);
2525 instruction |= ((Rd.value() & 0xf) << 12);
2526 instruction |= ((Rn.value() & 0xf) << 16);
2527 instruction |= (Rm.value() & 0xf);
2528 instruction |= ((Rs.value() & 0xf) << 8);
2529 emitInt(instruction);
2530 }
2531
2532 /**
2533 * Pseudo-external assembler syntax: {@code rsb{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
2534 * Example disassembly syntax: {@code rsbeq r0, r0, r0, asr r0}
2535 *
2536 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.36"
2537 */
2538 // Template#: 130, Serial#: 130
2539 public void rsbasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
2540 int instruction = 0x00600050;
2541 instruction |= ((cond.value() & 0xf) << 28);
2542 instruction |= ((s.value() & 0x1) << 20);
2543 instruction |= ((Rd.value() & 0xf) << 12);
2544 instruction |= ((Rn.value() & 0xf) << 16);
2545 instruction |= (Rm.value() & 0xf);
2546 instruction |= ((Rs.value() & 0xf) << 8);
2547 emitInt(instruction);
2548 }
2549
2550 /**
2551 * Pseudo-external assembler syntax: {@code rsb{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
2552 * Example disassembly syntax: {@code rsbeq r0, r0, r0, ror r0}
2553 *
2554 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.36"
2555 */
2556 // Template#: 131, Serial#: 131
2557 public void rsbror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
2558 int instruction = 0x00600070;
2559 instruction |= ((cond.value() & 0xf) << 28);
2560 instruction |= ((s.value() & 0x1) << 20);
2561 instruction |= ((Rd.value() & 0xf) << 12);
2562 instruction |= ((Rn.value() & 0xf) << 16);
2563 instruction |= (Rm.value() & 0xf);
2564 instruction |= ((Rs.value() & 0xf) << 8);
2565 emitInt(instruction);
2566 }
2567
2568 /**
2569 * Pseudo-external assembler syntax: {@code rsb{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
2570 * Example disassembly syntax: {@code rsbeq r0, r0, r0, rrx }
2571 *
2572 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.36"
2573 */
2574 // Template#: 132, Serial#: 132
2575 public void rsbrrx(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
2576 int instruction = 0x00600060;
2577 instruction |= ((cond.value() & 0xf) << 28);
2578 instruction |= ((s.value() & 0x1) << 20);
2579 instruction |= ((Rd.value() & 0xf) << 12);
2580 instruction |= ((Rn.value() & 0xf) << 16);
2581 instruction |= (Rm.value() & 0xf);
2582 emitInt(instruction);
2583 }
2584
2585 /**
2586 * Pseudo-external assembler syntax: {@code rsc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immediate</i>
2587 * Example disassembly syntax: {@code rsceq r0, r0, #0x0}
2588 * <p>
2589 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
2590 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
2591 *
2592 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
2593 *
2594 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.37"
2595 */
2596 // Template#: 133, Serial#: 133
2597 public void rsc(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immediate) {
2598 int instruction = 0x02E00000;
2599 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
2600 instruction |= ((cond.value() & 0xf) << 28);
2601 instruction |= ((s.value() & 0x1) << 20);
2602 instruction |= ((Rd.value() & 0xf) << 12);
2603 instruction |= ((Rn.value() & 0xf) << 16);
2604 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
2605 emitInt(instruction);
2606 }
2607
2608 /**
2609 * Pseudo-external assembler syntax: {@code rsc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immed_8</i>, <i>rotate_amount</i>
2610 * Example disassembly syntax: {@code rsceq r0, r0, #0x0, 0x0}
2611 * <p>
2612 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
2613 * Constraint: {@code (rotate_amount % 2) == 0}<br />
2614 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
2615 *
2616 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.37"
2617 */
2618 // Template#: 134, Serial#: 134
2619 public void rsc(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immed_8, final int rotate_amount) {
2620 int instruction = 0x02E00000;
2621 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
2622 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
2623 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
2624 instruction |= ((cond.value() & 0xf) << 28);
2625 instruction |= ((s.value() & 0x1) << 20);
2626 instruction |= ((Rd.value() & 0xf) << 12);
2627 instruction |= ((Rn.value() & 0xf) << 16);
2628 instruction |= (immed_8 & 0xff);
2629 instruction |= ((rotate_amount / 2 & 0xf) << 8);
2630 emitInt(instruction);
2631 }
2632
2633 /**
2634 * Pseudo-external assembler syntax: {@code rsc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
2635 * Example disassembly syntax: {@code rsceq r0, r0, r0}
2636 *
2637 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.37"
2638 */
2639 // Template#: 135, Serial#: 135
2640 public void rsc(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
2641 int instruction = 0x00E00000;
2642 instruction |= ((cond.value() & 0xf) << 28);
2643 instruction |= ((s.value() & 0x1) << 20);
2644 instruction |= ((Rd.value() & 0xf) << 12);
2645 instruction |= ((Rn.value() & 0xf) << 16);
2646 instruction |= (Rm.value() & 0xf);
2647 emitInt(instruction);
2648 }
2649
2650 /**
2651 * Pseudo-external assembler syntax: {@code rsc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2652 * Example disassembly syntax: {@code rsceq r0, r0, r0, lsl #0x0}
2653 * <p>
2654 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
2655 *
2656 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.37"
2657 */
2658 // Template#: 136, Serial#: 136
2659 public void rsclsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2660 int instruction = 0x00E00000;
2661 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
2662 instruction |= ((cond.value() & 0xf) << 28);
2663 instruction |= ((s.value() & 0x1) << 20);
2664 instruction |= ((Rd.value() & 0xf) << 12);
2665 instruction |= ((Rn.value() & 0xf) << 16);
2666 instruction |= (Rm.value() & 0xf);
2667 instruction |= ((shift_imm & 0x1f) << 7);
2668 emitInt(instruction);
2669 }
2670
2671 /**
2672 * Pseudo-external assembler syntax: {@code rsc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2673 * Example disassembly syntax: {@code rsceq r0, r0, r0, lsr #0x0}
2674 * <p>
2675 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
2676 *
2677 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.37"
2678 */
2679 // Template#: 137, Serial#: 137
2680 public void rsclsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2681 int instruction = 0x00E00020;
2682 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
2683 instruction |= ((cond.value() & 0xf) << 28);
2684 instruction |= ((s.value() & 0x1) << 20);
2685 instruction |= ((Rd.value() & 0xf) << 12);
2686 instruction |= ((Rn.value() & 0xf) << 16);
2687 instruction |= (Rm.value() & 0xf);
2688 instruction |= ((shift_imm % 32 & 0x1f) << 7);
2689 emitInt(instruction);
2690 }
2691
2692 /**
2693 * Pseudo-external assembler syntax: {@code rsc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2694 * Example disassembly syntax: {@code rsceq r0, r0, r0, asr #0x0}
2695 * <p>
2696 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
2697 *
2698 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.37"
2699 */
2700 // Template#: 138, Serial#: 138
2701 public void rscasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2702 int instruction = 0x00E00040;
2703 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
2704 instruction |= ((cond.value() & 0xf) << 28);
2705 instruction |= ((s.value() & 0x1) << 20);
2706 instruction |= ((Rd.value() & 0xf) << 12);
2707 instruction |= ((Rn.value() & 0xf) << 16);
2708 instruction |= (Rm.value() & 0xf);
2709 instruction |= ((shift_imm % 32 & 0x1f) << 7);
2710 emitInt(instruction);
2711 }
2712
2713 /**
2714 * Pseudo-external assembler syntax: {@code rsc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2715 * Example disassembly syntax: {@code rsceq r0, r0, r0, ror #0x0}
2716 * <p>
2717 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
2718 *
2719 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.37"
2720 */
2721 // Template#: 139, Serial#: 139
2722 public void rscror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2723 int instruction = 0x00E00060;
2724 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
2725 instruction |= ((cond.value() & 0xf) << 28);
2726 instruction |= ((s.value() & 0x1) << 20);
2727 instruction |= ((Rd.value() & 0xf) << 12);
2728 instruction |= ((Rn.value() & 0xf) << 16);
2729 instruction |= (Rm.value() & 0xf);
2730 instruction |= ((shift_imm & 0x1f) << 7);
2731 emitInt(instruction);
2732 }
2733
2734 /**
2735 * Pseudo-external assembler syntax: {@code rsc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
2736 * Example disassembly syntax: {@code rsceq r0, r0, r0, lsl r0}
2737 *
2738 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.37"
2739 */
2740 // Template#: 140, Serial#: 140
2741 public void rsclsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
2742 int instruction = 0x00E00010;
2743 instruction |= ((cond.value() & 0xf) << 28);
2744 instruction |= ((s.value() & 0x1) << 20);
2745 instruction |= ((Rd.value() & 0xf) << 12);
2746 instruction |= ((Rn.value() & 0xf) << 16);
2747 instruction |= (Rm.value() & 0xf);
2748 instruction |= ((Rs.value() & 0xf) << 8);
2749 emitInt(instruction);
2750 }
2751
2752 /**
2753 * Pseudo-external assembler syntax: {@code rsc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
2754 * Example disassembly syntax: {@code rsceq r0, r0, r0, lsr r0}
2755 *
2756 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.37"
2757 */
2758 // Template#: 141, Serial#: 141
2759 public void rsclsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
2760 int instruction = 0x00E00030;
2761 instruction |= ((cond.value() & 0xf) << 28);
2762 instruction |= ((s.value() & 0x1) << 20);
2763 instruction |= ((Rd.value() & 0xf) << 12);
2764 instruction |= ((Rn.value() & 0xf) << 16);
2765 instruction |= (Rm.value() & 0xf);
2766 instruction |= ((Rs.value() & 0xf) << 8);
2767 emitInt(instruction);
2768 }
2769
2770 /**
2771 * Pseudo-external assembler syntax: {@code rsc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
2772 * Example disassembly syntax: {@code rsceq r0, r0, r0, asr r0}
2773 *
2774 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.37"
2775 */
2776 // Template#: 142, Serial#: 142
2777 public void rscasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
2778 int instruction = 0x00E00050;
2779 instruction |= ((cond.value() & 0xf) << 28);
2780 instruction |= ((s.value() & 0x1) << 20);
2781 instruction |= ((Rd.value() & 0xf) << 12);
2782 instruction |= ((Rn.value() & 0xf) << 16);
2783 instruction |= (Rm.value() & 0xf);
2784 instruction |= ((Rs.value() & 0xf) << 8);
2785 emitInt(instruction);
2786 }
2787
2788 /**
2789 * Pseudo-external assembler syntax: {@code rsc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
2790 * Example disassembly syntax: {@code rsceq r0, r0, r0, ror r0}
2791 *
2792 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.37"
2793 */
2794 // Template#: 143, Serial#: 143
2795 public void rscror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
2796 int instruction = 0x00E00070;
2797 instruction |= ((cond.value() & 0xf) << 28);
2798 instruction |= ((s.value() & 0x1) << 20);
2799 instruction |= ((Rd.value() & 0xf) << 12);
2800 instruction |= ((Rn.value() & 0xf) << 16);
2801 instruction |= (Rm.value() & 0xf);
2802 instruction |= ((Rs.value() & 0xf) << 8);
2803 emitInt(instruction);
2804 }
2805
2806 /**
2807 * Pseudo-external assembler syntax: {@code rsc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
2808 * Example disassembly syntax: {@code rsceq r0, r0, r0, rrx }
2809 *
2810 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.37"
2811 */
2812 // Template#: 144, Serial#: 144
2813 public void rscrrx(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
2814 int instruction = 0x00E00060;
2815 instruction |= ((cond.value() & 0xf) << 28);
2816 instruction |= ((s.value() & 0x1) << 20);
2817 instruction |= ((Rd.value() & 0xf) << 12);
2818 instruction |= ((Rn.value() & 0xf) << 16);
2819 instruction |= (Rm.value() & 0xf);
2820 emitInt(instruction);
2821 }
2822
2823 /**
2824 * Pseudo-external assembler syntax: {@code sbc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immediate</i>
2825 * Example disassembly syntax: {@code sbceq r0, r0, #0x0}
2826 * <p>
2827 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
2828 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
2829 *
2830 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
2831 *
2832 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.38"
2833 */
2834 // Template#: 145, Serial#: 145
2835 public void sbc(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immediate) {
2836 int instruction = 0x02C00000;
2837 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
2838 instruction |= ((cond.value() & 0xf) << 28);
2839 instruction |= ((s.value() & 0x1) << 20);
2840 instruction |= ((Rd.value() & 0xf) << 12);
2841 instruction |= ((Rn.value() & 0xf) << 16);
2842 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
2843 emitInt(instruction);
2844 }
2845
2846 /**
2847 * Pseudo-external assembler syntax: {@code sbc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immed_8</i>, <i>rotate_amount</i>
2848 * Example disassembly syntax: {@code sbceq r0, r0, #0x0, 0x0}
2849 * <p>
2850 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
2851 * Constraint: {@code (rotate_amount % 2) == 0}<br />
2852 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
2853 *
2854 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.38"
2855 */
2856 // Template#: 146, Serial#: 146
2857 public void sbc(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immed_8, final int rotate_amount) {
2858 int instruction = 0x02C00000;
2859 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
2860 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
2861 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
2862 instruction |= ((cond.value() & 0xf) << 28);
2863 instruction |= ((s.value() & 0x1) << 20);
2864 instruction |= ((Rd.value() & 0xf) << 12);
2865 instruction |= ((Rn.value() & 0xf) << 16);
2866 instruction |= (immed_8 & 0xff);
2867 instruction |= ((rotate_amount / 2 & 0xf) << 8);
2868 emitInt(instruction);
2869 }
2870
2871 /**
2872 * Pseudo-external assembler syntax: {@code sbc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
2873 * Example disassembly syntax: {@code sbceq r0, r0, r0}
2874 *
2875 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.38"
2876 */
2877 // Template#: 147, Serial#: 147
2878 public void sbc(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
2879 int instruction = 0x00C00000;
2880 instruction |= ((cond.value() & 0xf) << 28);
2881 instruction |= ((s.value() & 0x1) << 20);
2882 instruction |= ((Rd.value() & 0xf) << 12);
2883 instruction |= ((Rn.value() & 0xf) << 16);
2884 instruction |= (Rm.value() & 0xf);
2885 emitInt(instruction);
2886 }
2887
2888 /**
2889 * Pseudo-external assembler syntax: {@code sbc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2890 * Example disassembly syntax: {@code sbceq r0, r0, r0, lsl #0x0}
2891 * <p>
2892 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
2893 *
2894 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.38"
2895 */
2896 // Template#: 148, Serial#: 148
2897 public void sbclsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2898 int instruction = 0x00C00000;
2899 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
2900 instruction |= ((cond.value() & 0xf) << 28);
2901 instruction |= ((s.value() & 0x1) << 20);
2902 instruction |= ((Rd.value() & 0xf) << 12);
2903 instruction |= ((Rn.value() & 0xf) << 16);
2904 instruction |= (Rm.value() & 0xf);
2905 instruction |= ((shift_imm & 0x1f) << 7);
2906 emitInt(instruction);
2907 }
2908
2909 /**
2910 * Pseudo-external assembler syntax: {@code sbc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2911 * Example disassembly syntax: {@code sbceq r0, r0, r0, lsr #0x0}
2912 * <p>
2913 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
2914 *
2915 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.38"
2916 */
2917 // Template#: 149, Serial#: 149
2918 public void sbclsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2919 int instruction = 0x00C00020;
2920 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
2921 instruction |= ((cond.value() & 0xf) << 28);
2922 instruction |= ((s.value() & 0x1) << 20);
2923 instruction |= ((Rd.value() & 0xf) << 12);
2924 instruction |= ((Rn.value() & 0xf) << 16);
2925 instruction |= (Rm.value() & 0xf);
2926 instruction |= ((shift_imm % 32 & 0x1f) << 7);
2927 emitInt(instruction);
2928 }
2929
2930 /**
2931 * Pseudo-external assembler syntax: {@code sbc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2932 * Example disassembly syntax: {@code sbceq r0, r0, r0, asr #0x0}
2933 * <p>
2934 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
2935 *
2936 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.38"
2937 */
2938 // Template#: 150, Serial#: 150
2939 public void sbcasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2940 int instruction = 0x00C00040;
2941 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
2942 instruction |= ((cond.value() & 0xf) << 28);
2943 instruction |= ((s.value() & 0x1) << 20);
2944 instruction |= ((Rd.value() & 0xf) << 12);
2945 instruction |= ((Rn.value() & 0xf) << 16);
2946 instruction |= (Rm.value() & 0xf);
2947 instruction |= ((shift_imm % 32 & 0x1f) << 7);
2948 emitInt(instruction);
2949 }
2950
2951 /**
2952 * Pseudo-external assembler syntax: {@code sbc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
2953 * Example disassembly syntax: {@code sbceq r0, r0, r0, ror #0x0}
2954 * <p>
2955 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
2956 *
2957 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.38"
2958 */
2959 // Template#: 151, Serial#: 151
2960 public void sbcror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
2961 int instruction = 0x00C00060;
2962 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
2963 instruction |= ((cond.value() & 0xf) << 28);
2964 instruction |= ((s.value() & 0x1) << 20);
2965 instruction |= ((Rd.value() & 0xf) << 12);
2966 instruction |= ((Rn.value() & 0xf) << 16);
2967 instruction |= (Rm.value() & 0xf);
2968 instruction |= ((shift_imm & 0x1f) << 7);
2969 emitInt(instruction);
2970 }
2971
2972 /**
2973 * Pseudo-external assembler syntax: {@code sbc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
2974 * Example disassembly syntax: {@code sbceq r0, r0, r0, lsl r0}
2975 *
2976 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.38"
2977 */
2978 // Template#: 152, Serial#: 152
2979 public void sbclsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
2980 int instruction = 0x00C00010;
2981 instruction |= ((cond.value() & 0xf) << 28);
2982 instruction |= ((s.value() & 0x1) << 20);
2983 instruction |= ((Rd.value() & 0xf) << 12);
2984 instruction |= ((Rn.value() & 0xf) << 16);
2985 instruction |= (Rm.value() & 0xf);
2986 instruction |= ((Rs.value() & 0xf) << 8);
2987 emitInt(instruction);
2988 }
2989
2990 /**
2991 * Pseudo-external assembler syntax: {@code sbc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
2992 * Example disassembly syntax: {@code sbceq r0, r0, r0, lsr r0}
2993 *
2994 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.38"
2995 */
2996 // Template#: 153, Serial#: 153
2997 public void sbclsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
2998 int instruction = 0x00C00030;
2999 instruction |= ((cond.value() & 0xf) << 28);
3000 instruction |= ((s.value() & 0x1) << 20);
3001 instruction |= ((Rd.value() & 0xf) << 12);
3002 instruction |= ((Rn.value() & 0xf) << 16);
3003 instruction |= (Rm.value() & 0xf);
3004 instruction |= ((Rs.value() & 0xf) << 8);
3005 emitInt(instruction);
3006 }
3007
3008 /**
3009 * Pseudo-external assembler syntax: {@code sbc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
3010 * Example disassembly syntax: {@code sbceq r0, r0, r0, asr r0}
3011 *
3012 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.38"
3013 */
3014 // Template#: 154, Serial#: 154
3015 public void sbcasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
3016 int instruction = 0x00C00050;
3017 instruction |= ((cond.value() & 0xf) << 28);
3018 instruction |= ((s.value() & 0x1) << 20);
3019 instruction |= ((Rd.value() & 0xf) << 12);
3020 instruction |= ((Rn.value() & 0xf) << 16);
3021 instruction |= (Rm.value() & 0xf);
3022 instruction |= ((Rs.value() & 0xf) << 8);
3023 emitInt(instruction);
3024 }
3025
3026 /**
3027 * Pseudo-external assembler syntax: {@code sbc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
3028 * Example disassembly syntax: {@code sbceq r0, r0, r0, ror r0}
3029 *
3030 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.38"
3031 */
3032 // Template#: 155, Serial#: 155
3033 public void sbcror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
3034 int instruction = 0x00C00070;
3035 instruction |= ((cond.value() & 0xf) << 28);
3036 instruction |= ((s.value() & 0x1) << 20);
3037 instruction |= ((Rd.value() & 0xf) << 12);
3038 instruction |= ((Rn.value() & 0xf) << 16);
3039 instruction |= (Rm.value() & 0xf);
3040 instruction |= ((Rs.value() & 0xf) << 8);
3041 emitInt(instruction);
3042 }
3043
3044 /**
3045 * Pseudo-external assembler syntax: {@code sbc{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
3046 * Example disassembly syntax: {@code sbceq r0, r0, r0, rrx }
3047 *
3048 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.38"
3049 */
3050 // Template#: 156, Serial#: 156
3051 public void sbcrrx(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
3052 int instruction = 0x00C00060;
3053 instruction |= ((cond.value() & 0xf) << 28);
3054 instruction |= ((s.value() & 0x1) << 20);
3055 instruction |= ((Rd.value() & 0xf) << 12);
3056 instruction |= ((Rn.value() & 0xf) << 16);
3057 instruction |= (Rm.value() & 0xf);
3058 emitInt(instruction);
3059 }
3060
3061 /**
3062 * Pseudo-external assembler syntax: {@code sub{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immediate</i>
3063 * Example disassembly syntax: {@code subeq r0, r0, #0x0}
3064 * <p>
3065 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
3066 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
3067 *
3068 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
3069 *
3070 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.49"
3071 */
3072 // Template#: 157, Serial#: 157
3073 public void sub(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immediate) {
3074 int instruction = 0x02400000;
3075 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
3076 instruction |= ((cond.value() & 0xf) << 28);
3077 instruction |= ((s.value() & 0x1) << 20);
3078 instruction |= ((Rd.value() & 0xf) << 12);
3079 instruction |= ((Rn.value() & 0xf) << 16);
3080 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
3081 emitInt(instruction);
3082 }
3083
3084 /**
3085 * Pseudo-external assembler syntax: {@code sub{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>immed_8</i>, <i>rotate_amount</i>
3086 * Example disassembly syntax: {@code subeq r0, r0, #0x0, 0x0}
3087 * <p>
3088 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
3089 * Constraint: {@code (rotate_amount % 2) == 0}<br />
3090 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
3091 *
3092 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.49"
3093 */
3094 // Template#: 158, Serial#: 158
3095 public void sub(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final int immed_8, final int rotate_amount) {
3096 int instruction = 0x02400000;
3097 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
3098 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
3099 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
3100 instruction |= ((cond.value() & 0xf) << 28);
3101 instruction |= ((s.value() & 0x1) << 20);
3102 instruction |= ((Rd.value() & 0xf) << 12);
3103 instruction |= ((Rn.value() & 0xf) << 16);
3104 instruction |= (immed_8 & 0xff);
3105 instruction |= ((rotate_amount / 2 & 0xf) << 8);
3106 emitInt(instruction);
3107 }
3108
3109 /**
3110 * Pseudo-external assembler syntax: {@code sub{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
3111 * Example disassembly syntax: {@code subeq r0, r0, r0}
3112 *
3113 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.49"
3114 */
3115 // Template#: 159, Serial#: 159
3116 public void sub(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
3117 int instruction = 0x00400000;
3118 instruction |= ((cond.value() & 0xf) << 28);
3119 instruction |= ((s.value() & 0x1) << 20);
3120 instruction |= ((Rd.value() & 0xf) << 12);
3121 instruction |= ((Rn.value() & 0xf) << 16);
3122 instruction |= (Rm.value() & 0xf);
3123 emitInt(instruction);
3124 }
3125
3126 /**
3127 * Pseudo-external assembler syntax: {@code sub{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
3128 * Example disassembly syntax: {@code subeq r0, r0, r0, lsl #0x0}
3129 * <p>
3130 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
3131 *
3132 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.49"
3133 */
3134 // Template#: 160, Serial#: 160
3135 public void sublsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
3136 int instruction = 0x00400000;
3137 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
3138 instruction |= ((cond.value() & 0xf) << 28);
3139 instruction |= ((s.value() & 0x1) << 20);
3140 instruction |= ((Rd.value() & 0xf) << 12);
3141 instruction |= ((Rn.value() & 0xf) << 16);
3142 instruction |= (Rm.value() & 0xf);
3143 instruction |= ((shift_imm & 0x1f) << 7);
3144 emitInt(instruction);
3145 }
3146
3147 /**
3148 * Pseudo-external assembler syntax: {@code sub{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
3149 * Example disassembly syntax: {@code subeq r0, r0, r0, lsr #0x0}
3150 * <p>
3151 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
3152 *
3153 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.49"
3154 */
3155 // Template#: 161, Serial#: 161
3156 public void sublsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
3157 int instruction = 0x00400020;
3158 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
3159 instruction |= ((cond.value() & 0xf) << 28);
3160 instruction |= ((s.value() & 0x1) << 20);
3161 instruction |= ((Rd.value() & 0xf) << 12);
3162 instruction |= ((Rn.value() & 0xf) << 16);
3163 instruction |= (Rm.value() & 0xf);
3164 instruction |= ((shift_imm % 32 & 0x1f) << 7);
3165 emitInt(instruction);
3166 }
3167
3168 /**
3169 * Pseudo-external assembler syntax: {@code sub{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
3170 * Example disassembly syntax: {@code subeq r0, r0, r0, asr #0x0}
3171 * <p>
3172 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
3173 *
3174 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.49"
3175 */
3176 // Template#: 162, Serial#: 162
3177 public void subasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
3178 int instruction = 0x00400040;
3179 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
3180 instruction |= ((cond.value() & 0xf) << 28);
3181 instruction |= ((s.value() & 0x1) << 20);
3182 instruction |= ((Rd.value() & 0xf) << 12);
3183 instruction |= ((Rn.value() & 0xf) << 16);
3184 instruction |= (Rm.value() & 0xf);
3185 instruction |= ((shift_imm % 32 & 0x1f) << 7);
3186 emitInt(instruction);
3187 }
3188
3189 /**
3190 * Pseudo-external assembler syntax: {@code sub{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
3191 * Example disassembly syntax: {@code subeq r0, r0, r0, ror #0x0}
3192 * <p>
3193 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
3194 *
3195 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.49"
3196 */
3197 // Template#: 163, Serial#: 163
3198 public void subror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
3199 int instruction = 0x00400060;
3200 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
3201 instruction |= ((cond.value() & 0xf) << 28);
3202 instruction |= ((s.value() & 0x1) << 20);
3203 instruction |= ((Rd.value() & 0xf) << 12);
3204 instruction |= ((Rn.value() & 0xf) << 16);
3205 instruction |= (Rm.value() & 0xf);
3206 instruction |= ((shift_imm & 0x1f) << 7);
3207 emitInt(instruction);
3208 }
3209
3210 /**
3211 * Pseudo-external assembler syntax: {@code sub{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
3212 * Example disassembly syntax: {@code subeq r0, r0, r0, lsl r0}
3213 *
3214 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.49"
3215 */
3216 // Template#: 164, Serial#: 164
3217 public void sublsl(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
3218 int instruction = 0x00400010;
3219 instruction |= ((cond.value() & 0xf) << 28);
3220 instruction |= ((s.value() & 0x1) << 20);
3221 instruction |= ((Rd.value() & 0xf) << 12);
3222 instruction |= ((Rn.value() & 0xf) << 16);
3223 instruction |= (Rm.value() & 0xf);
3224 instruction |= ((Rs.value() & 0xf) << 8);
3225 emitInt(instruction);
3226 }
3227
3228 /**
3229 * Pseudo-external assembler syntax: {@code sub{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
3230 * Example disassembly syntax: {@code subeq r0, r0, r0, lsr r0}
3231 *
3232 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.49"
3233 */
3234 // Template#: 165, Serial#: 165
3235 public void sublsr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
3236 int instruction = 0x00400030;
3237 instruction |= ((cond.value() & 0xf) << 28);
3238 instruction |= ((s.value() & 0x1) << 20);
3239 instruction |= ((Rd.value() & 0xf) << 12);
3240 instruction |= ((Rn.value() & 0xf) << 16);
3241 instruction |= (Rm.value() & 0xf);
3242 instruction |= ((Rs.value() & 0xf) << 8);
3243 emitInt(instruction);
3244 }
3245
3246 /**
3247 * Pseudo-external assembler syntax: {@code sub{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
3248 * Example disassembly syntax: {@code subeq r0, r0, r0, asr r0}
3249 *
3250 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.49"
3251 */
3252 // Template#: 166, Serial#: 166
3253 public void subasr(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
3254 int instruction = 0x00400050;
3255 instruction |= ((cond.value() & 0xf) << 28);
3256 instruction |= ((s.value() & 0x1) << 20);
3257 instruction |= ((Rd.value() & 0xf) << 12);
3258 instruction |= ((Rn.value() & 0xf) << 16);
3259 instruction |= (Rm.value() & 0xf);
3260 instruction |= ((Rs.value() & 0xf) << 8);
3261 emitInt(instruction);
3262 }
3263
3264 /**
3265 * Pseudo-external assembler syntax: {@code sub{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>Rs</i>
3266 * Example disassembly syntax: {@code subeq r0, r0, r0, ror r0}
3267 *
3268 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.49"
3269 */
3270 // Template#: 167, Serial#: 167
3271 public void subror(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm, final GPR Rs) {
3272 int instruction = 0x00400070;
3273 instruction |= ((cond.value() & 0xf) << 28);
3274 instruction |= ((s.value() & 0x1) << 20);
3275 instruction |= ((Rd.value() & 0xf) << 12);
3276 instruction |= ((Rn.value() & 0xf) << 16);
3277 instruction |= (Rm.value() & 0xf);
3278 instruction |= ((Rs.value() & 0xf) << 8);
3279 emitInt(instruction);
3280 }
3281
3282 /**
3283 * Pseudo-external assembler syntax: {@code sub{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
3284 * Example disassembly syntax: {@code subeq r0, r0, r0, rrx }
3285 *
3286 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.49"
3287 */
3288 // Template#: 168, Serial#: 168
3289 public void subrrx(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rn, final GPR Rm) {
3290 int instruction = 0x00400060;
3291 instruction |= ((cond.value() & 0xf) << 28);
3292 instruction |= ((s.value() & 0x1) << 20);
3293 instruction |= ((Rd.value() & 0xf) << 12);
3294 instruction |= ((Rn.value() & 0xf) << 16);
3295 instruction |= (Rm.value() & 0xf);
3296 emitInt(instruction);
3297 }
3298
3299 /**
3300 * Pseudo-external assembler syntax: {@code teq{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>immediate</i>
3301 * Example disassembly syntax: {@code teqeq r0, #0x0}
3302 * <p>
3303 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
3304 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
3305 *
3306 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
3307 *
3308 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.53"
3309 */
3310 // Template#: 169, Serial#: 169
3311 public void teq(final ConditionCode cond, final GPR Rn, final int immediate) {
3312 int instruction = 0x03300000;
3313 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
3314 instruction |= ((cond.value() & 0xf) << 28);
3315 instruction |= ((Rn.value() & 0xf) << 16);
3316 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
3317 emitInt(instruction);
3318 }
3319
3320 /**
3321 * Pseudo-external assembler syntax: {@code teq{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>immed_8</i>, <i>rotate_amount</i>
3322 * Example disassembly syntax: {@code teqeq r0, #0x0, 0x0}
3323 * <p>
3324 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
3325 * Constraint: {@code (rotate_amount % 2) == 0}<br />
3326 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
3327 *
3328 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.53"
3329 */
3330 // Template#: 170, Serial#: 170
3331 public void teq(final ConditionCode cond, final GPR Rn, final int immed_8, final int rotate_amount) {
3332 int instruction = 0x03300000;
3333 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
3334 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
3335 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
3336 instruction |= ((cond.value() & 0xf) << 28);
3337 instruction |= ((Rn.value() & 0xf) << 16);
3338 instruction |= (immed_8 & 0xff);
3339 instruction |= ((rotate_amount / 2 & 0xf) << 8);
3340 emitInt(instruction);
3341 }
3342
3343 /**
3344 * Pseudo-external assembler syntax: {@code teq{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>
3345 * Example disassembly syntax: {@code teqeq r0, r0}
3346 *
3347 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.53"
3348 */
3349 // Template#: 171, Serial#: 171
3350 public void teq(final ConditionCode cond, final GPR Rn, final GPR Rm) {
3351 int instruction = 0x01300000;
3352 instruction |= ((cond.value() & 0xf) << 28);
3353 instruction |= ((Rn.value() & 0xf) << 16);
3354 instruction |= (Rm.value() & 0xf);
3355 emitInt(instruction);
3356 }
3357
3358 /**
3359 * Pseudo-external assembler syntax: {@code teq{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
3360 * Example disassembly syntax: {@code teqeq r0, r0, lsl #0x0}
3361 * <p>
3362 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
3363 *
3364 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.53"
3365 */
3366 // Template#: 172, Serial#: 172
3367 public void teqlsl(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
3368 int instruction = 0x01300000;
3369 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
3370 instruction |= ((cond.value() & 0xf) << 28);
3371 instruction |= ((Rn.value() & 0xf) << 16);
3372 instruction |= (Rm.value() & 0xf);
3373 instruction |= ((shift_imm & 0x1f) << 7);
3374 emitInt(instruction);
3375 }
3376
3377 /**
3378 * Pseudo-external assembler syntax: {@code teq{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
3379 * Example disassembly syntax: {@code teqeq r0, r0, lsr #0x0}
3380 * <p>
3381 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
3382 *
3383 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.53"
3384 */
3385 // Template#: 173, Serial#: 173
3386 public void teqlsr(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
3387 int instruction = 0x01300020;
3388 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
3389 instruction |= ((cond.value() & 0xf) << 28);
3390 instruction |= ((Rn.value() & 0xf) << 16);
3391 instruction |= (Rm.value() & 0xf);
3392 instruction |= ((shift_imm % 32 & 0x1f) << 7);
3393 emitInt(instruction);
3394 }
3395
3396 /**
3397 * Pseudo-external assembler syntax: {@code teq{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
3398 * Example disassembly syntax: {@code teqeq r0, r0, asr #0x0}
3399 * <p>
3400 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
3401 *
3402 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.53"
3403 */
3404 // Template#: 174, Serial#: 174
3405 public void teqasr(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
3406 int instruction = 0x01300040;
3407 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
3408 instruction |= ((cond.value() & 0xf) << 28);
3409 instruction |= ((Rn.value() & 0xf) << 16);
3410 instruction |= (Rm.value() & 0xf);
3411 instruction |= ((shift_imm % 32 & 0x1f) << 7);
3412 emitInt(instruction);
3413 }
3414
3415 /**
3416 * Pseudo-external assembler syntax: {@code teq{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
3417 * Example disassembly syntax: {@code teqeq r0, r0, ror #0x0}
3418 * <p>
3419 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
3420 *
3421 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.53"
3422 */
3423 // Template#: 175, Serial#: 175
3424 public void teqror(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
3425 int instruction = 0x01300060;
3426 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
3427 instruction |= ((cond.value() & 0xf) << 28);
3428 instruction |= ((Rn.value() & 0xf) << 16);
3429 instruction |= (Rm.value() & 0xf);
3430 instruction |= ((shift_imm & 0x1f) << 7);
3431 emitInt(instruction);
3432 }
3433
3434 /**
3435 * Pseudo-external assembler syntax: {@code teq{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
3436 * Example disassembly syntax: {@code teqeq r0, r0, lsl r0}
3437 *
3438 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.53"
3439 */
3440 // Template#: 176, Serial#: 176
3441 public void teqlsl(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
3442 int instruction = 0x01300010;
3443 instruction |= ((cond.value() & 0xf) << 28);
3444 instruction |= ((Rn.value() & 0xf) << 16);
3445 instruction |= (Rm.value() & 0xf);
3446 instruction |= ((Rs.value() & 0xf) << 8);
3447 emitInt(instruction);
3448 }
3449
3450 /**
3451 * Pseudo-external assembler syntax: {@code teq{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
3452 * Example disassembly syntax: {@code teqeq r0, r0, lsr r0}
3453 *
3454 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.53"
3455 */
3456 // Template#: 177, Serial#: 177
3457 public void teqlsr(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
3458 int instruction = 0x01300030;
3459 instruction |= ((cond.value() & 0xf) << 28);
3460 instruction |= ((Rn.value() & 0xf) << 16);
3461 instruction |= (Rm.value() & 0xf);
3462 instruction |= ((Rs.value() & 0xf) << 8);
3463 emitInt(instruction);
3464 }
3465
3466 /**
3467 * Pseudo-external assembler syntax: {@code teq{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
3468 * Example disassembly syntax: {@code teqeq r0, r0, asr r0}
3469 *
3470 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.53"
3471 */
3472 // Template#: 178, Serial#: 178
3473 public void teqasr(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
3474 int instruction = 0x01300050;
3475 instruction |= ((cond.value() & 0xf) << 28);
3476 instruction |= ((Rn.value() & 0xf) << 16);
3477 instruction |= (Rm.value() & 0xf);
3478 instruction |= ((Rs.value() & 0xf) << 8);
3479 emitInt(instruction);
3480 }
3481
3482 /**
3483 * Pseudo-external assembler syntax: {@code teq{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
3484 * Example disassembly syntax: {@code teqeq r0, r0, ror r0}
3485 *
3486 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.53"
3487 */
3488 // Template#: 179, Serial#: 179
3489 public void teqror(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
3490 int instruction = 0x01300070;
3491 instruction |= ((cond.value() & 0xf) << 28);
3492 instruction |= ((Rn.value() & 0xf) << 16);
3493 instruction |= (Rm.value() & 0xf);
3494 instruction |= ((Rs.value() & 0xf) << 8);
3495 emitInt(instruction);
3496 }
3497
3498 /**
3499 * Pseudo-external assembler syntax: {@code teq{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>
3500 * Example disassembly syntax: {@code teqeq r0, r0, rrx }
3501 *
3502 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.53"
3503 */
3504 // Template#: 180, Serial#: 180
3505 public void teqrrx(final ConditionCode cond, final GPR Rn, final GPR Rm) {
3506 int instruction = 0x01300060;
3507 instruction |= ((cond.value() & 0xf) << 28);
3508 instruction |= ((Rn.value() & 0xf) << 16);
3509 instruction |= (Rm.value() & 0xf);
3510 emitInt(instruction);
3511 }
3512
3513 /**
3514 * Pseudo-external assembler syntax: {@code tst{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>immediate</i>
3515 * Example disassembly syntax: {@code tsteq r0, #0x0}
3516 * <p>
3517 * Constraint: {@code ARMImmediates.isValidImmediate(immediate)}<br />
3518 * Constraint: {@code 0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095}<br />
3519 *
3520 * @see com.sun.max.asm.arm.ARMImmediates#isValidImmediate
3521 *
3522 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.54"
3523 */
3524 // Template#: 181, Serial#: 181
3525 public void tst(final ConditionCode cond, final GPR Rn, final int immediate) {
3526 int instruction = 0x03100000;
3527 checkConstraint(0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095, "0 <= ARMImmediates.calculateShifter(immediate) && ARMImmediates.calculateShifter(immediate) <= 4095");
3528 instruction |= ((cond.value() & 0xf) << 28);
3529 instruction |= ((Rn.value() & 0xf) << 16);
3530 instruction |= (ARMImmediates.calculateShifter(immediate) & 0xfff);
3531 emitInt(instruction);
3532 }
3533
3534 /**
3535 * Pseudo-external assembler syntax: {@code tst{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>immed_8</i>, <i>rotate_amount</i>
3536 * Example disassembly syntax: {@code tsteq r0, #0x0, 0x0}
3537 * <p>
3538 * Constraint: {@code 0 <= immed_8 && immed_8 <= 255}<br />
3539 * Constraint: {@code (rotate_amount % 2) == 0}<br />
3540 * Constraint: {@code 0 <= rotate_amount / 2 && rotate_amount / 2 <= 15}<br />
3541 *
3542 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.54"
3543 */
3544 // Template#: 182, Serial#: 182
3545 public void tst(final ConditionCode cond, final GPR Rn, final int immed_8, final int rotate_amount) {
3546 int instruction = 0x03100000;
3547 checkConstraint(0 <= immed_8 && immed_8 <= 255, "0 <= immed_8 && immed_8 <= 255");
3548 checkConstraint((rotate_amount % 2) == 0, "(rotate_amount % 2) == 0");
3549 checkConstraint(0 <= rotate_amount / 2 && rotate_amount / 2 <= 15, "0 <= rotate_amount / 2 && rotate_amount / 2 <= 15");
3550 instruction |= ((cond.value() & 0xf) << 28);
3551 instruction |= ((Rn.value() & 0xf) << 16);
3552 instruction |= (immed_8 & 0xff);
3553 instruction |= ((rotate_amount / 2 & 0xf) << 8);
3554 emitInt(instruction);
3555 }
3556
3557 /**
3558 * Pseudo-external assembler syntax: {@code tst{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>
3559 * Example disassembly syntax: {@code tsteq r0, r0}
3560 *
3561 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.54"
3562 */
3563 // Template#: 183, Serial#: 183
3564 public void tst(final ConditionCode cond, final GPR Rn, final GPR Rm) {
3565 int instruction = 0x01100000;
3566 instruction |= ((cond.value() & 0xf) << 28);
3567 instruction |= ((Rn.value() & 0xf) << 16);
3568 instruction |= (Rm.value() & 0xf);
3569 emitInt(instruction);
3570 }
3571
3572 /**
3573 * Pseudo-external assembler syntax: {@code tst{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
3574 * Example disassembly syntax: {@code tsteq r0, r0, lsl #0x0}
3575 * <p>
3576 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
3577 *
3578 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.54"
3579 */
3580 // Template#: 184, Serial#: 184
3581 public void tstlsl(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
3582 int instruction = 0x01100000;
3583 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
3584 instruction |= ((cond.value() & 0xf) << 28);
3585 instruction |= ((Rn.value() & 0xf) << 16);
3586 instruction |= (Rm.value() & 0xf);
3587 instruction |= ((shift_imm & 0x1f) << 7);
3588 emitInt(instruction);
3589 }
3590
3591 /**
3592 * Pseudo-external assembler syntax: {@code tst{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
3593 * Example disassembly syntax: {@code tsteq r0, r0, lsr #0x0}
3594 * <p>
3595 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
3596 *
3597 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.54"
3598 */
3599 // Template#: 185, Serial#: 185
3600 public void tstlsr(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
3601 int instruction = 0x01100020;
3602 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
3603 instruction |= ((cond.value() & 0xf) << 28);
3604 instruction |= ((Rn.value() & 0xf) << 16);
3605 instruction |= (Rm.value() & 0xf);
3606 instruction |= ((shift_imm % 32 & 0x1f) << 7);
3607 emitInt(instruction);
3608 }
3609
3610 /**
3611 * Pseudo-external assembler syntax: {@code tst{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
3612 * Example disassembly syntax: {@code tsteq r0, r0, asr #0x0}
3613 * <p>
3614 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
3615 *
3616 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.54"
3617 */
3618 // Template#: 186, Serial#: 186
3619 public void tstasr(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
3620 int instruction = 0x01100040;
3621 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
3622 instruction |= ((cond.value() & 0xf) << 28);
3623 instruction |= ((Rn.value() & 0xf) << 16);
3624 instruction |= (Rm.value() & 0xf);
3625 instruction |= ((shift_imm % 32 & 0x1f) << 7);
3626 emitInt(instruction);
3627 }
3628
3629 /**
3630 * Pseudo-external assembler syntax: {@code tst{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
3631 * Example disassembly syntax: {@code tsteq r0, r0, ror #0x0}
3632 * <p>
3633 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
3634 *
3635 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.54"
3636 */
3637 // Template#: 187, Serial#: 187
3638 public void tstror(final ConditionCode cond, final GPR Rn, final GPR Rm, final int shift_imm) {
3639 int instruction = 0x01100060;
3640 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
3641 instruction |= ((cond.value() & 0xf) << 28);
3642 instruction |= ((Rn.value() & 0xf) << 16);
3643 instruction |= (Rm.value() & 0xf);
3644 instruction |= ((shift_imm & 0x1f) << 7);
3645 emitInt(instruction);
3646 }
3647
3648 /**
3649 * Pseudo-external assembler syntax: {@code tst{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
3650 * Example disassembly syntax: {@code tsteq r0, r0, lsl r0}
3651 *
3652 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.54"
3653 */
3654 // Template#: 188, Serial#: 188
3655 public void tstlsl(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
3656 int instruction = 0x01100010;
3657 instruction |= ((cond.value() & 0xf) << 28);
3658 instruction |= ((Rn.value() & 0xf) << 16);
3659 instruction |= (Rm.value() & 0xf);
3660 instruction |= ((Rs.value() & 0xf) << 8);
3661 emitInt(instruction);
3662 }
3663
3664 /**
3665 * Pseudo-external assembler syntax: {@code tst{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
3666 * Example disassembly syntax: {@code tsteq r0, r0, lsr r0}
3667 *
3668 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.54"
3669 */
3670 // Template#: 189, Serial#: 189
3671 public void tstlsr(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
3672 int instruction = 0x01100030;
3673 instruction |= ((cond.value() & 0xf) << 28);
3674 instruction |= ((Rn.value() & 0xf) << 16);
3675 instruction |= (Rm.value() & 0xf);
3676 instruction |= ((Rs.value() & 0xf) << 8);
3677 emitInt(instruction);
3678 }
3679
3680 /**
3681 * Pseudo-external assembler syntax: {@code tst{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
3682 * Example disassembly syntax: {@code tsteq r0, r0, asr r0}
3683 *
3684 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.54"
3685 */
3686 // Template#: 190, Serial#: 190
3687 public void tstasr(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
3688 int instruction = 0x01100050;
3689 instruction |= ((cond.value() & 0xf) << 28);
3690 instruction |= ((Rn.value() & 0xf) << 16);
3691 instruction |= (Rm.value() & 0xf);
3692 instruction |= ((Rs.value() & 0xf) << 8);
3693 emitInt(instruction);
3694 }
3695
3696 /**
3697 * Pseudo-external assembler syntax: {@code tst{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>, <i>Rs</i>
3698 * Example disassembly syntax: {@code tsteq r0, r0, ror r0}
3699 *
3700 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.54"
3701 */
3702 // Template#: 191, Serial#: 191
3703 public void tstror(final ConditionCode cond, final GPR Rn, final GPR Rm, final GPR Rs) {
3704 int instruction = 0x01100070;
3705 instruction |= ((cond.value() & 0xf) << 28);
3706 instruction |= ((Rn.value() & 0xf) << 16);
3707 instruction |= (Rm.value() & 0xf);
3708 instruction |= ((Rs.value() & 0xf) << 8);
3709 emitInt(instruction);
3710 }
3711
3712 /**
3713 * Pseudo-external assembler syntax: {@code tst{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rn</i>, <i>Rm</i>
3714 * Example disassembly syntax: {@code tsteq r0, r0, rrx }
3715 *
3716 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.54"
3717 */
3718 // Template#: 192, Serial#: 192
3719 public void tstrrx(final ConditionCode cond, final GPR Rn, final GPR Rm) {
3720 int instruction = 0x01100060;
3721 instruction |= ((cond.value() & 0xf) << 28);
3722 instruction |= ((Rn.value() & 0xf) << 16);
3723 instruction |= (Rm.value() & 0xf);
3724 emitInt(instruction);
3725 }
3726
3727 /**
3728 * Pseudo-external assembler syntax: {@code mla{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>Rs</i>, <i>Rn</i>
3729 * Example disassembly syntax: {@code mlaeq r0, r0, r0, r0}
3730 * <p>
3731 * Constraint: {@code Rd.value() != Rm.value()}<br />
3732 * Constraint: {@code Rd.value() != 15}<br />
3733 * Constraint: {@code Rm.value() != 15}<br />
3734 * Constraint: {@code Rs.value() != 15}<br />
3735 * Constraint: {@code Rn.value() != 15}<br />
3736 *
3737 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.28"
3738 */
3739 // Template#: 193, Serial#: 193
3740 public void mla(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final GPR Rs, final GPR Rn) {
3741 int instruction = 0x00200090;
3742 checkConstraint(Rd.value() != Rm.value(), "Rd.value() != Rm.value()");
3743 checkConstraint(Rd.value() != 15, "Rd.value() != 15");
3744 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
3745 checkConstraint(Rs.value() != 15, "Rs.value() != 15");
3746 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
3747 instruction |= ((cond.value() & 0xf) << 28);
3748 instruction |= ((s.value() & 0x1) << 20);
3749 instruction |= ((Rd.value() & 0xf) << 16);
3750 instruction |= (Rm.value() & 0xf);
3751 instruction |= ((Rs.value() & 0xf) << 8);
3752 instruction |= ((Rn.value() & 0xf) << 12);
3753 emitInt(instruction);
3754 }
3755
3756 /**
3757 * Pseudo-external assembler syntax: {@code mul{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>Rd</i>, <i>Rm</i>, <i>Rs</i>
3758 * Example disassembly syntax: {@code muleq r0, r0, r0}
3759 * <p>
3760 * Constraint: {@code Rd.value() != Rm.value()}<br />
3761 * Constraint: {@code Rd.value() != 15}<br />
3762 * Constraint: {@code Rm.value() != 15}<br />
3763 * Constraint: {@code Rs.value() != 15}<br />
3764 *
3765 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.33"
3766 */
3767 // Template#: 194, Serial#: 194
3768 public void mul(final ConditionCode cond, final SBit s, final GPR Rd, final GPR Rm, final GPR Rs) {
3769 int instruction = 0x00000090;
3770 checkConstraint(Rd.value() != Rm.value(), "Rd.value() != Rm.value()");
3771 checkConstraint(Rd.value() != 15, "Rd.value() != 15");
3772 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
3773 checkConstraint(Rs.value() != 15, "Rs.value() != 15");
3774 instruction |= ((cond.value() & 0xf) << 28);
3775 instruction |= ((s.value() & 0x1) << 20);
3776 instruction |= ((Rd.value() & 0xf) << 16);
3777 instruction |= (Rm.value() & 0xf);
3778 instruction |= ((Rs.value() & 0xf) << 8);
3779 emitInt(instruction);
3780 }
3781
3782 /**
3783 * Pseudo-external assembler syntax: {@code smlal{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>RdLo</i>, <i>RdHi</i>, <i>Rm</i>, <i>Rs</i>
3784 * Example disassembly syntax: {@code smlaleq r0, r0, r0, r0}
3785 * <p>
3786 * Constraint: {@code RdLo.value() != RdHi.value()}<br />
3787 * Constraint: {@code RdLo.value() != Rm.value()}<br />
3788 * Constraint: {@code RdHi.value() != Rm.value()}<br />
3789 * Constraint: {@code RdHi.value() != 15}<br />
3790 * Constraint: {@code RdLo.value() != 15}<br />
3791 * Constraint: {@code Rm.value() != 15}<br />
3792 * Constraint: {@code Rs.value() != 15}<br />
3793 *
3794 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.39"
3795 */
3796 // Template#: 195, Serial#: 195
3797 public void smlal(final ConditionCode cond, final SBit s, final GPR RdLo, final GPR RdHi, final GPR Rm, final GPR Rs) {
3798 int instruction = 0x00E00090;
3799 checkConstraint(RdLo.value() != RdHi.value(), "RdLo.value() != RdHi.value()");
3800 checkConstraint(RdLo.value() != Rm.value(), "RdLo.value() != Rm.value()");
3801 checkConstraint(RdHi.value() != Rm.value(), "RdHi.value() != Rm.value()");
3802 checkConstraint(RdHi.value() != 15, "RdHi.value() != 15");
3803 checkConstraint(RdLo.value() != 15, "RdLo.value() != 15");
3804 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
3805 checkConstraint(Rs.value() != 15, "Rs.value() != 15");
3806 instruction |= ((cond.value() & 0xf) << 28);
3807 instruction |= ((s.value() & 0x1) << 20);
3808 instruction |= ((RdLo.value() & 0xf) << 12);
3809 instruction |= ((RdHi.value() & 0xf) << 16);
3810 instruction |= (Rm.value() & 0xf);
3811 instruction |= ((Rs.value() & 0xf) << 8);
3812 emitInt(instruction);
3813 }
3814
3815 /**
3816 * Pseudo-external assembler syntax: {@code smull{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>RdLo</i>, <i>RdHi</i>, <i>Rm</i>, <i>Rs</i>
3817 * Example disassembly syntax: {@code smulleq r0, r0, r0, r0}
3818 * <p>
3819 * Constraint: {@code RdLo.value() != RdHi.value()}<br />
3820 * Constraint: {@code RdLo.value() != Rm.value()}<br />
3821 * Constraint: {@code RdHi.value() != Rm.value()}<br />
3822 * Constraint: {@code RdHi.value() != 15}<br />
3823 * Constraint: {@code RdLo.value() != 15}<br />
3824 * Constraint: {@code Rm.value() != 15}<br />
3825 * Constraint: {@code Rs.value() != 15}<br />
3826 *
3827 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.40"
3828 */
3829 // Template#: 196, Serial#: 196
3830 public void smull(final ConditionCode cond, final SBit s, final GPR RdLo, final GPR RdHi, final GPR Rm, final GPR Rs) {
3831 int instruction = 0x00C00090;
3832 checkConstraint(RdLo.value() != RdHi.value(), "RdLo.value() != RdHi.value()");
3833 checkConstraint(RdLo.value() != Rm.value(), "RdLo.value() != Rm.value()");
3834 checkConstraint(RdHi.value() != Rm.value(), "RdHi.value() != Rm.value()");
3835 checkConstraint(RdHi.value() != 15, "RdHi.value() != 15");
3836 checkConstraint(RdLo.value() != 15, "RdLo.value() != 15");
3837 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
3838 checkConstraint(Rs.value() != 15, "Rs.value() != 15");
3839 instruction |= ((cond.value() & 0xf) << 28);
3840 instruction |= ((s.value() & 0x1) << 20);
3841 instruction |= ((RdLo.value() & 0xf) << 12);
3842 instruction |= ((RdHi.value() & 0xf) << 16);
3843 instruction |= (Rm.value() & 0xf);
3844 instruction |= ((Rs.value() & 0xf) << 8);
3845 emitInt(instruction);
3846 }
3847
3848 /**
3849 * Pseudo-external assembler syntax: {@code umlal{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>RdLo</i>, <i>RdHi</i>, <i>Rm</i>, <i>Rs</i>
3850 * Example disassembly syntax: {@code umlaleq r0, r0, r0, r0}
3851 * <p>
3852 * Constraint: {@code RdLo.value() != RdHi.value()}<br />
3853 * Constraint: {@code RdLo.value() != Rm.value()}<br />
3854 * Constraint: {@code RdHi.value() != Rm.value()}<br />
3855 * Constraint: {@code RdHi.value() != 15}<br />
3856 * Constraint: {@code RdLo.value() != 15}<br />
3857 * Constraint: {@code Rm.value() != 15}<br />
3858 * Constraint: {@code Rs.value() != 15}<br />
3859 *
3860 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.55"
3861 */
3862 // Template#: 197, Serial#: 197
3863 public void umlal(final ConditionCode cond, final SBit s, final GPR RdLo, final GPR RdHi, final GPR Rm, final GPR Rs) {
3864 int instruction = 0x00A00090;
3865 checkConstraint(RdLo.value() != RdHi.value(), "RdLo.value() != RdHi.value()");
3866 checkConstraint(RdLo.value() != Rm.value(), "RdLo.value() != Rm.value()");
3867 checkConstraint(RdHi.value() != Rm.value(), "RdHi.value() != Rm.value()");
3868 checkConstraint(RdHi.value() != 15, "RdHi.value() != 15");
3869 checkConstraint(RdLo.value() != 15, "RdLo.value() != 15");
3870 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
3871 checkConstraint(Rs.value() != 15, "Rs.value() != 15");
3872 instruction |= ((cond.value() & 0xf) << 28);
3873 instruction |= ((s.value() & 0x1) << 20);
3874 instruction |= ((RdLo.value() & 0xf) << 12);
3875 instruction |= ((RdHi.value() & 0xf) << 16);
3876 instruction |= (Rm.value() & 0xf);
3877 instruction |= ((Rs.value() & 0xf) << 8);
3878 emitInt(instruction);
3879 }
3880
3881 /**
3882 * Pseudo-external assembler syntax: {@code umull{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv}{s} }<i>RdLo</i>, <i>RdHi</i>, <i>Rm</i>, <i>Rs</i>
3883 * Example disassembly syntax: {@code umulleq r0, r0, r0, r0}
3884 * <p>
3885 * Constraint: {@code RdLo.value() != RdHi.value()}<br />
3886 * Constraint: {@code RdLo.value() != Rm.value()}<br />
3887 * Constraint: {@code RdHi.value() != Rm.value()}<br />
3888 * Constraint: {@code RdHi.value() != 15}<br />
3889 * Constraint: {@code RdLo.value() != 15}<br />
3890 * Constraint: {@code Rm.value() != 15}<br />
3891 * Constraint: {@code Rs.value() != 15}<br />
3892 *
3893 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.56"
3894 */
3895 // Template#: 198, Serial#: 198
3896 public void umull(final ConditionCode cond, final SBit s, final GPR RdLo, final GPR RdHi, final GPR Rm, final GPR Rs) {
3897 int instruction = 0x00800090;
3898 checkConstraint(RdLo.value() != RdHi.value(), "RdLo.value() != RdHi.value()");
3899 checkConstraint(RdLo.value() != Rm.value(), "RdLo.value() != Rm.value()");
3900 checkConstraint(RdHi.value() != Rm.value(), "RdHi.value() != Rm.value()");
3901 checkConstraint(RdHi.value() != 15, "RdHi.value() != 15");
3902 checkConstraint(RdLo.value() != 15, "RdLo.value() != 15");
3903 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
3904 checkConstraint(Rs.value() != 15, "Rs.value() != 15");
3905 instruction |= ((cond.value() & 0xf) << 28);
3906 instruction |= ((s.value() & 0x1) << 20);
3907 instruction |= ((RdLo.value() & 0xf) << 12);
3908 instruction |= ((RdHi.value() & 0xf) << 16);
3909 instruction |= (Rm.value() & 0xf);
3910 instruction |= ((Rs.value() & 0xf) << 8);
3911 emitInt(instruction);
3912 }
3913
3914 /**
3915 * Pseudo-external assembler syntax: {@code clz{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rm</i>
3916 * Example disassembly syntax: {@code clzeq r0, r0}
3917 * <p>
3918 * Constraint: {@code Rd.value() != 15}<br />
3919 * Constraint: {@code Rm.value() != 15}<br />
3920 *
3921 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.12"
3922 */
3923 // Template#: 199, Serial#: 199
3924 public void clz(final ConditionCode cond, final GPR Rd, final GPR Rm) {
3925 int instruction = 0x016F0F10;
3926 checkConstraint(Rd.value() != 15, "Rd.value() != 15");
3927 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
3928 instruction |= ((cond.value() & 0xf) << 28);
3929 instruction |= ((Rd.value() & 0xf) << 12);
3930 instruction |= (Rm.value() & 0xf);
3931 emitInt(instruction);
3932 }
3933
3934 /**
3935 * Pseudo-external assembler syntax: {@code mrs{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>
3936 * Example disassembly syntax: {@code mrseq r0, cpsr}
3937 *
3938 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.31"
3939 */
3940 // Template#: 200, Serial#: 200
3941 public void mrscpsr(final ConditionCode cond, final GPR Rd) {
3942 int instruction = 0x010F0000;
3943 instruction |= ((cond.value() & 0xf) << 28);
3944 instruction |= ((Rd.value() & 0xf) << 12);
3945 emitInt(instruction);
3946 }
3947
3948 /**
3949 * Pseudo-external assembler syntax: {@code mrs{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>
3950 * Example disassembly syntax: {@code mrseq r0, spsr}
3951 *
3952 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.31"
3953 */
3954 // Template#: 201, Serial#: 201
3955 public void mrsspsr(final ConditionCode cond, final GPR Rd) {
3956 int instruction = 0x014F0000;
3957 instruction |= ((cond.value() & 0xf) << 28);
3958 instruction |= ((Rd.value() & 0xf) << 12);
3959 emitInt(instruction);
3960 }
3961
3962 /**
3963 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>offset_12</i>
3964 * Example disassembly syntax: {@code ldreq r0, [r0, #+0x0]}
3965 * <p>
3966 * Constraint: {@code 0 <= offset_12 && offset_12 <= 4095}<br />
3967 *
3968 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
3969 */
3970 // Template#: 202, Serial#: 202
3971 public void ldradd(final ConditionCode cond, final GPR Rd, final GPR Rn, final int offset_12) {
3972 int instruction = 0x05900000;
3973 checkConstraint(0 <= offset_12 && offset_12 <= 4095, "0 <= offset_12 && offset_12 <= 4095");
3974 instruction |= ((cond.value() & 0xf) << 28);
3975 instruction |= ((Rd.value() & 0xf) << 12);
3976 instruction |= ((Rn.value() & 0xf) << 16);
3977 instruction |= (offset_12 & 0xfff);
3978 emitInt(instruction);
3979 }
3980
3981 /**
3982 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>offset_12</i>
3983 * Example disassembly syntax: {@code ldreq r0, [r0, #-0x0]}
3984 * <p>
3985 * Constraint: {@code 0 <= offset_12 && offset_12 <= 4095}<br />
3986 *
3987 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
3988 */
3989 // Template#: 203, Serial#: 203
3990 public void ldrsub(final ConditionCode cond, final GPR Rd, final GPR Rn, final int offset_12) {
3991 int instruction = 0x05100000;
3992 checkConstraint(0 <= offset_12 && offset_12 <= 4095, "0 <= offset_12 && offset_12 <= 4095");
3993 instruction |= ((cond.value() & 0xf) << 28);
3994 instruction |= ((Rd.value() & 0xf) << 12);
3995 instruction |= ((Rn.value() & 0xf) << 16);
3996 instruction |= (offset_12 & 0xfff);
3997 emitInt(instruction);
3998 }
3999
4000 /**
4001 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
4002 * Example disassembly syntax: {@code ldreq r0, [r0, +r0]}
4003 * <p>
4004 * Constraint: {@code Rm.value() != 15}<br />
4005 *
4006 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4007 */
4008 // Template#: 204, Serial#: 204
4009 public void ldradd(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
4010 int instruction = 0x07900000;
4011 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4012 instruction |= ((cond.value() & 0xf) << 28);
4013 instruction |= ((Rd.value() & 0xf) << 12);
4014 instruction |= ((Rn.value() & 0xf) << 16);
4015 instruction |= (Rm.value() & 0xf);
4016 emitInt(instruction);
4017 }
4018
4019 /**
4020 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
4021 * Example disassembly syntax: {@code ldreq r0, [r0, -r0]}
4022 * <p>
4023 * Constraint: {@code Rm.value() != 15}<br />
4024 *
4025 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4026 */
4027 // Template#: 205, Serial#: 205
4028 public void ldrsub(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
4029 int instruction = 0x07100000;
4030 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4031 instruction |= ((cond.value() & 0xf) << 28);
4032 instruction |= ((Rd.value() & 0xf) << 12);
4033 instruction |= ((Rn.value() & 0xf) << 16);
4034 instruction |= (Rm.value() & 0xf);
4035 emitInt(instruction);
4036 }
4037
4038 /**
4039 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4040 * Example disassembly syntax: {@code ldreq r0, [r0, +r0, lsl #0x0]}
4041 * <p>
4042 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
4043 * Constraint: {@code Rm.value() != 15}<br />
4044 *
4045 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4046 */
4047 // Template#: 206, Serial#: 206
4048 public void ldraddlsl(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4049 int instruction = 0x07900000;
4050 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
4051 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4052 instruction |= ((cond.value() & 0xf) << 28);
4053 instruction |= ((Rd.value() & 0xf) << 12);
4054 instruction |= ((Rn.value() & 0xf) << 16);
4055 instruction |= (Rm.value() & 0xf);
4056 instruction |= ((shift_imm & 0x1f) << 7);
4057 emitInt(instruction);
4058 }
4059
4060 /**
4061 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4062 * Example disassembly syntax: {@code ldreq r0, [r0, -r0, lsl #0x0]}
4063 * <p>
4064 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
4065 * Constraint: {@code Rm.value() != 15}<br />
4066 *
4067 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4068 */
4069 // Template#: 207, Serial#: 207
4070 public void ldrsublsl(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4071 int instruction = 0x07100000;
4072 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
4073 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4074 instruction |= ((cond.value() & 0xf) << 28);
4075 instruction |= ((Rd.value() & 0xf) << 12);
4076 instruction |= ((Rn.value() & 0xf) << 16);
4077 instruction |= (Rm.value() & 0xf);
4078 instruction |= ((shift_imm & 0x1f) << 7);
4079 emitInt(instruction);
4080 }
4081
4082 /**
4083 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4084 * Example disassembly syntax: {@code ldreq r0, [r0, +r0, lsr #0x0]}
4085 * <p>
4086 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
4087 * Constraint: {@code Rm.value() != 15}<br />
4088 *
4089 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4090 */
4091 // Template#: 208, Serial#: 208
4092 public void ldraddlsr(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4093 int instruction = 0x07900020;
4094 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
4095 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4096 instruction |= ((cond.value() & 0xf) << 28);
4097 instruction |= ((Rd.value() & 0xf) << 12);
4098 instruction |= ((Rn.value() & 0xf) << 16);
4099 instruction |= (Rm.value() & 0xf);
4100 instruction |= ((shift_imm % 32 & 0x1f) << 7);
4101 emitInt(instruction);
4102 }
4103
4104 /**
4105 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4106 * Example disassembly syntax: {@code ldreq r0, [r0, -r0, lsr #0x0]}
4107 * <p>
4108 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
4109 * Constraint: {@code Rm.value() != 15}<br />
4110 *
4111 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4112 */
4113 // Template#: 209, Serial#: 209
4114 public void ldrsublsr(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4115 int instruction = 0x07100020;
4116 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
4117 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4118 instruction |= ((cond.value() & 0xf) << 28);
4119 instruction |= ((Rd.value() & 0xf) << 12);
4120 instruction |= ((Rn.value() & 0xf) << 16);
4121 instruction |= (Rm.value() & 0xf);
4122 instruction |= ((shift_imm % 32 & 0x1f) << 7);
4123 emitInt(instruction);
4124 }
4125
4126 /**
4127 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4128 * Example disassembly syntax: {@code ldreq r0, [r0, +r0, asr #0x0]}
4129 * <p>
4130 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
4131 * Constraint: {@code Rm.value() != 15}<br />
4132 *
4133 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4134 */
4135 // Template#: 210, Serial#: 210
4136 public void ldraddasr(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4137 int instruction = 0x07900040;
4138 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
4139 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4140 instruction |= ((cond.value() & 0xf) << 28);
4141 instruction |= ((Rd.value() & 0xf) << 12);
4142 instruction |= ((Rn.value() & 0xf) << 16);
4143 instruction |= (Rm.value() & 0xf);
4144 instruction |= ((shift_imm % 32 & 0x1f) << 7);
4145 emitInt(instruction);
4146 }
4147
4148 /**
4149 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4150 * Example disassembly syntax: {@code ldreq r0, [r0, -r0, asr #0x0]}
4151 * <p>
4152 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
4153 * Constraint: {@code Rm.value() != 15}<br />
4154 *
4155 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4156 */
4157 // Template#: 211, Serial#: 211
4158 public void ldrsubasr(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4159 int instruction = 0x07100040;
4160 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
4161 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4162 instruction |= ((cond.value() & 0xf) << 28);
4163 instruction |= ((Rd.value() & 0xf) << 12);
4164 instruction |= ((Rn.value() & 0xf) << 16);
4165 instruction |= (Rm.value() & 0xf);
4166 instruction |= ((shift_imm % 32 & 0x1f) << 7);
4167 emitInt(instruction);
4168 }
4169
4170 /**
4171 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4172 * Example disassembly syntax: {@code ldreq r0, [r0, +r0, ror #0x0]}
4173 * <p>
4174 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
4175 * Constraint: {@code Rm.value() != 15}<br />
4176 *
4177 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4178 */
4179 // Template#: 212, Serial#: 212
4180 public void ldraddror(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4181 int instruction = 0x07900060;
4182 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
4183 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4184 instruction |= ((cond.value() & 0xf) << 28);
4185 instruction |= ((Rd.value() & 0xf) << 12);
4186 instruction |= ((Rn.value() & 0xf) << 16);
4187 instruction |= (Rm.value() & 0xf);
4188 instruction |= ((shift_imm & 0x1f) << 7);
4189 emitInt(instruction);
4190 }
4191
4192 /**
4193 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4194 * Example disassembly syntax: {@code ldreq r0, [r0, -r0, ror #0x0]}
4195 * <p>
4196 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
4197 * Constraint: {@code Rm.value() != 15}<br />
4198 *
4199 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4200 */
4201 // Template#: 213, Serial#: 213
4202 public void ldrsubror(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4203 int instruction = 0x07100060;
4204 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
4205 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4206 instruction |= ((cond.value() & 0xf) << 28);
4207 instruction |= ((Rd.value() & 0xf) << 12);
4208 instruction |= ((Rn.value() & 0xf) << 16);
4209 instruction |= (Rm.value() & 0xf);
4210 instruction |= ((shift_imm & 0x1f) << 7);
4211 emitInt(instruction);
4212 }
4213
4214 /**
4215 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
4216 * Example disassembly syntax: {@code ldreq r0, [r0, +r0, rrx]}
4217 * <p>
4218 * Constraint: {@code Rm.value() != 15}<br />
4219 *
4220 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4221 */
4222 // Template#: 214, Serial#: 214
4223 public void ldraddrrx(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
4224 int instruction = 0x07900060;
4225 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4226 instruction |= ((cond.value() & 0xf) << 28);
4227 instruction |= ((Rd.value() & 0xf) << 12);
4228 instruction |= ((Rn.value() & 0xf) << 16);
4229 instruction |= (Rm.value() & 0xf);
4230 emitInt(instruction);
4231 }
4232
4233 /**
4234 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
4235 * Example disassembly syntax: {@code ldreq r0, [r0, -r0, rrx]}
4236 * <p>
4237 * Constraint: {@code Rm.value() != 15}<br />
4238 *
4239 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4240 */
4241 // Template#: 215, Serial#: 215
4242 public void ldrsubrrx(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
4243 int instruction = 0x07100060;
4244 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4245 instruction |= ((cond.value() & 0xf) << 28);
4246 instruction |= ((Rd.value() & 0xf) << 12);
4247 instruction |= ((Rn.value() & 0xf) << 16);
4248 instruction |= (Rm.value() & 0xf);
4249 emitInt(instruction);
4250 }
4251
4252 /**
4253 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>offset_12</i>
4254 * Example disassembly syntax: {@code ldreq r0, [r0, #+0x0]!}
4255 * <p>
4256 * Constraint: {@code 0 <= offset_12 && offset_12 <= 4095}<br />
4257 * Constraint: {@code Rd.value() != Rn.value()}<br />
4258 * Constraint: {@code Rn.value() != 15}<br />
4259 *
4260 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4261 */
4262 // Template#: 216, Serial#: 216
4263 public void ldraddw(final ConditionCode cond, final GPR Rd, final GPR Rn, final int offset_12) {
4264 int instruction = 0x05B00000;
4265 checkConstraint(0 <= offset_12 && offset_12 <= 4095, "0 <= offset_12 && offset_12 <= 4095");
4266 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
4267 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4268 instruction |= ((cond.value() & 0xf) << 28);
4269 instruction |= ((Rd.value() & 0xf) << 12);
4270 instruction |= ((Rn.value() & 0xf) << 16);
4271 instruction |= (offset_12 & 0xfff);
4272 emitInt(instruction);
4273 }
4274
4275 /**
4276 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>offset_12</i>
4277 * Example disassembly syntax: {@code ldreq r0, [r0, #-0x0]!}
4278 * <p>
4279 * Constraint: {@code 0 <= offset_12 && offset_12 <= 4095}<br />
4280 * Constraint: {@code Rd.value() != Rn.value()}<br />
4281 * Constraint: {@code Rn.value() != 15}<br />
4282 *
4283 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4284 */
4285 // Template#: 217, Serial#: 217
4286 public void ldrsubw(final ConditionCode cond, final GPR Rd, final GPR Rn, final int offset_12) {
4287 int instruction = 0x05300000;
4288 checkConstraint(0 <= offset_12 && offset_12 <= 4095, "0 <= offset_12 && offset_12 <= 4095");
4289 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
4290 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4291 instruction |= ((cond.value() & 0xf) << 28);
4292 instruction |= ((Rd.value() & 0xf) << 12);
4293 instruction |= ((Rn.value() & 0xf) << 16);
4294 instruction |= (offset_12 & 0xfff);
4295 emitInt(instruction);
4296 }
4297
4298 /**
4299 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
4300 * Example disassembly syntax: {@code ldreq r0, [r0, +r0]!}
4301 * <p>
4302 * Constraint: {@code Rd.value() != Rn.value()}<br />
4303 * Constraint: {@code Rm.value() != Rn.value()}<br />
4304 * Constraint: {@code Rn.value() != 15}<br />
4305 * Constraint: {@code Rm.value() != 15}<br />
4306 *
4307 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4308 */
4309 // Template#: 218, Serial#: 218
4310 public void ldraddw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
4311 int instruction = 0x07B00000;
4312 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
4313 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4314 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4315 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4316 instruction |= ((cond.value() & 0xf) << 28);
4317 instruction |= ((Rd.value() & 0xf) << 12);
4318 instruction |= ((Rn.value() & 0xf) << 16);
4319 instruction |= (Rm.value() & 0xf);
4320 emitInt(instruction);
4321 }
4322
4323 /**
4324 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
4325 * Example disassembly syntax: {@code ldreq r0, [r0, -r0]!}
4326 * <p>
4327 * Constraint: {@code Rd.value() != Rn.value()}<br />
4328 * Constraint: {@code Rm.value() != Rn.value()}<br />
4329 * Constraint: {@code Rn.value() != 15}<br />
4330 * Constraint: {@code Rm.value() != 15}<br />
4331 *
4332 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4333 */
4334 // Template#: 219, Serial#: 219
4335 public void ldrsubw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
4336 int instruction = 0x07300000;
4337 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
4338 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4339 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4340 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4341 instruction |= ((cond.value() & 0xf) << 28);
4342 instruction |= ((Rd.value() & 0xf) << 12);
4343 instruction |= ((Rn.value() & 0xf) << 16);
4344 instruction |= (Rm.value() & 0xf);
4345 emitInt(instruction);
4346 }
4347
4348 /**
4349 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4350 * Example disassembly syntax: {@code ldreq r0, [r0, +r0, lsl #0x0]!}
4351 * <p>
4352 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
4353 * Constraint: {@code Rd.value() != Rn.value()}<br />
4354 * Constraint: {@code Rm.value() != Rn.value()}<br />
4355 * Constraint: {@code Rn.value() != 15}<br />
4356 * Constraint: {@code Rm.value() != 15}<br />
4357 *
4358 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4359 */
4360 // Template#: 220, Serial#: 220
4361 public void ldraddlslw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4362 int instruction = 0x07B00000;
4363 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
4364 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
4365 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4366 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4367 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4368 instruction |= ((cond.value() & 0xf) << 28);
4369 instruction |= ((Rd.value() & 0xf) << 12);
4370 instruction |= ((Rn.value() & 0xf) << 16);
4371 instruction |= (Rm.value() & 0xf);
4372 instruction |= ((shift_imm & 0x1f) << 7);
4373 emitInt(instruction);
4374 }
4375
4376 /**
4377 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4378 * Example disassembly syntax: {@code ldreq r0, [r0, -r0, lsl #0x0]!}
4379 * <p>
4380 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
4381 * Constraint: {@code Rd.value() != Rn.value()}<br />
4382 * Constraint: {@code Rm.value() != Rn.value()}<br />
4383 * Constraint: {@code Rn.value() != 15}<br />
4384 * Constraint: {@code Rm.value() != 15}<br />
4385 *
4386 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4387 */
4388 // Template#: 221, Serial#: 221
4389 public void ldrsublslw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4390 int instruction = 0x07300000;
4391 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
4392 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
4393 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4394 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4395 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4396 instruction |= ((cond.value() & 0xf) << 28);
4397 instruction |= ((Rd.value() & 0xf) << 12);
4398 instruction |= ((Rn.value() & 0xf) << 16);
4399 instruction |= (Rm.value() & 0xf);
4400 instruction |= ((shift_imm & 0x1f) << 7);
4401 emitInt(instruction);
4402 }
4403
4404 /**
4405 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4406 * Example disassembly syntax: {@code ldreq r0, [r0, +r0, lsr #0x0]!}
4407 * <p>
4408 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
4409 * Constraint: {@code Rd.value() != Rn.value()}<br />
4410 * Constraint: {@code Rm.value() != Rn.value()}<br />
4411 * Constraint: {@code Rn.value() != 15}<br />
4412 * Constraint: {@code Rm.value() != 15}<br />
4413 *
4414 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4415 */
4416 // Template#: 222, Serial#: 222
4417 public void ldraddlsrw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4418 int instruction = 0x07B00020;
4419 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
4420 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
4421 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4422 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4423 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4424 instruction |= ((cond.value() & 0xf) << 28);
4425 instruction |= ((Rd.value() & 0xf) << 12);
4426 instruction |= ((Rn.value() & 0xf) << 16);
4427 instruction |= (Rm.value() & 0xf);
4428 instruction |= ((shift_imm % 32 & 0x1f) << 7);
4429 emitInt(instruction);
4430 }
4431
4432 /**
4433 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4434 * Example disassembly syntax: {@code ldreq r0, [r0, -r0, lsr #0x0]!}
4435 * <p>
4436 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
4437 * Constraint: {@code Rd.value() != Rn.value()}<br />
4438 * Constraint: {@code Rm.value() != Rn.value()}<br />
4439 * Constraint: {@code Rn.value() != 15}<br />
4440 * Constraint: {@code Rm.value() != 15}<br />
4441 *
4442 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4443 */
4444 // Template#: 223, Serial#: 223
4445 public void ldrsublsrw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4446 int instruction = 0x07300020;
4447 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
4448 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
4449 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4450 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4451 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4452 instruction |= ((cond.value() & 0xf) << 28);
4453 instruction |= ((Rd.value() & 0xf) << 12);
4454 instruction |= ((Rn.value() & 0xf) << 16);
4455 instruction |= (Rm.value() & 0xf);
4456 instruction |= ((shift_imm % 32 & 0x1f) << 7);
4457 emitInt(instruction);
4458 }
4459
4460 /**
4461 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4462 * Example disassembly syntax: {@code ldreq r0, [r0, +r0, asr #0x0]!}
4463 * <p>
4464 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
4465 * Constraint: {@code Rd.value() != Rn.value()}<br />
4466 * Constraint: {@code Rm.value() != Rn.value()}<br />
4467 * Constraint: {@code Rn.value() != 15}<br />
4468 * Constraint: {@code Rm.value() != 15}<br />
4469 *
4470 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4471 */
4472 // Template#: 224, Serial#: 224
4473 public void ldraddasrw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4474 int instruction = 0x07B00040;
4475 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
4476 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
4477 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4478 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4479 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4480 instruction |= ((cond.value() & 0xf) << 28);
4481 instruction |= ((Rd.value() & 0xf) << 12);
4482 instruction |= ((Rn.value() & 0xf) << 16);
4483 instruction |= (Rm.value() & 0xf);
4484 instruction |= ((shift_imm % 32 & 0x1f) << 7);
4485 emitInt(instruction);
4486 }
4487
4488 /**
4489 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4490 * Example disassembly syntax: {@code ldreq r0, [r0, -r0, asr #0x0]!}
4491 * <p>
4492 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
4493 * Constraint: {@code Rd.value() != Rn.value()}<br />
4494 * Constraint: {@code Rm.value() != Rn.value()}<br />
4495 * Constraint: {@code Rn.value() != 15}<br />
4496 * Constraint: {@code Rm.value() != 15}<br />
4497 *
4498 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4499 */
4500 // Template#: 225, Serial#: 225
4501 public void ldrsubasrw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4502 int instruction = 0x07300040;
4503 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
4504 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
4505 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4506 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4507 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4508 instruction |= ((cond.value() & 0xf) << 28);
4509 instruction |= ((Rd.value() & 0xf) << 12);
4510 instruction |= ((Rn.value() & 0xf) << 16);
4511 instruction |= (Rm.value() & 0xf);
4512 instruction |= ((shift_imm % 32 & 0x1f) << 7);
4513 emitInt(instruction);
4514 }
4515
4516 /**
4517 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4518 * Example disassembly syntax: {@code ldreq r0, [r0, +r0, ror #0x0]!}
4519 * <p>
4520 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
4521 * Constraint: {@code Rd.value() != Rn.value()}<br />
4522 * Constraint: {@code Rm.value() != Rn.value()}<br />
4523 * Constraint: {@code Rn.value() != 15}<br />
4524 * Constraint: {@code Rm.value() != 15}<br />
4525 *
4526 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4527 */
4528 // Template#: 226, Serial#: 226
4529 public void ldraddrorw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4530 int instruction = 0x07B00060;
4531 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
4532 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
4533 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4534 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4535 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4536 instruction |= ((cond.value() & 0xf) << 28);
4537 instruction |= ((Rd.value() & 0xf) << 12);
4538 instruction |= ((Rn.value() & 0xf) << 16);
4539 instruction |= (Rm.value() & 0xf);
4540 instruction |= ((shift_imm & 0x1f) << 7);
4541 emitInt(instruction);
4542 }
4543
4544 /**
4545 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4546 * Example disassembly syntax: {@code ldreq r0, [r0, -r0, ror #0x0]!}
4547 * <p>
4548 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
4549 * Constraint: {@code Rd.value() != Rn.value()}<br />
4550 * Constraint: {@code Rm.value() != Rn.value()}<br />
4551 * Constraint: {@code Rn.value() != 15}<br />
4552 * Constraint: {@code Rm.value() != 15}<br />
4553 *
4554 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4555 */
4556 // Template#: 227, Serial#: 227
4557 public void ldrsubrorw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4558 int instruction = 0x07300060;
4559 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
4560 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
4561 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4562 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4563 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4564 instruction |= ((cond.value() & 0xf) << 28);
4565 instruction |= ((Rd.value() & 0xf) << 12);
4566 instruction |= ((Rn.value() & 0xf) << 16);
4567 instruction |= (Rm.value() & 0xf);
4568 instruction |= ((shift_imm & 0x1f) << 7);
4569 emitInt(instruction);
4570 }
4571
4572 /**
4573 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
4574 * Example disassembly syntax: {@code ldreq r0, [r0, +r0, rrx]!}
4575 * <p>
4576 * Constraint: {@code Rd.value() != Rn.value()}<br />
4577 * Constraint: {@code Rm.value() != Rn.value()}<br />
4578 * Constraint: {@code Rn.value() != 15}<br />
4579 * Constraint: {@code Rm.value() != 15}<br />
4580 *
4581 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4582 */
4583 // Template#: 228, Serial#: 228
4584 public void ldraddrrxw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
4585 int instruction = 0x07B00060;
4586 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
4587 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4588 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4589 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4590 instruction |= ((cond.value() & 0xf) << 28);
4591 instruction |= ((Rd.value() & 0xf) << 12);
4592 instruction |= ((Rn.value() & 0xf) << 16);
4593 instruction |= (Rm.value() & 0xf);
4594 emitInt(instruction);
4595 }
4596
4597 /**
4598 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
4599 * Example disassembly syntax: {@code ldreq r0, [r0, -r0, rrx]!}
4600 * <p>
4601 * Constraint: {@code Rd.value() != Rn.value()}<br />
4602 * Constraint: {@code Rm.value() != Rn.value()}<br />
4603 * Constraint: {@code Rn.value() != 15}<br />
4604 * Constraint: {@code Rm.value() != 15}<br />
4605 *
4606 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4607 */
4608 // Template#: 229, Serial#: 229
4609 public void ldrsubrrxw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
4610 int instruction = 0x07300060;
4611 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
4612 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4613 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4614 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4615 instruction |= ((cond.value() & 0xf) << 28);
4616 instruction |= ((Rd.value() & 0xf) << 12);
4617 instruction |= ((Rn.value() & 0xf) << 16);
4618 instruction |= (Rm.value() & 0xf);
4619 emitInt(instruction);
4620 }
4621
4622 /**
4623 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>offset_12</i>
4624 * Example disassembly syntax: {@code ldreq r0, [r0], #+0x0}
4625 * <p>
4626 * Constraint: {@code 0 <= offset_12 && offset_12 <= 4095}<br />
4627 * Constraint: {@code Rn.value() != 15}<br />
4628 *
4629 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4630 */
4631 // Template#: 230, Serial#: 230
4632 public void ldraddpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final int offset_12) {
4633 int instruction = 0x04900000;
4634 checkConstraint(0 <= offset_12 && offset_12 <= 4095, "0 <= offset_12 && offset_12 <= 4095");
4635 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4636 instruction |= ((cond.value() & 0xf) << 28);
4637 instruction |= ((Rd.value() & 0xf) << 12);
4638 instruction |= ((Rn.value() & 0xf) << 16);
4639 instruction |= (offset_12 & 0xfff);
4640 emitInt(instruction);
4641 }
4642
4643 /**
4644 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>offset_12</i>
4645 * Example disassembly syntax: {@code ldreq r0, [r0], #-0x0}
4646 * <p>
4647 * Constraint: {@code 0 <= offset_12 && offset_12 <= 4095}<br />
4648 * Constraint: {@code Rn.value() != 15}<br />
4649 *
4650 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4651 */
4652 // Template#: 231, Serial#: 231
4653 public void ldrsubpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final int offset_12) {
4654 int instruction = 0x04100000;
4655 checkConstraint(0 <= offset_12 && offset_12 <= 4095, "0 <= offset_12 && offset_12 <= 4095");
4656 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4657 instruction |= ((cond.value() & 0xf) << 28);
4658 instruction |= ((Rd.value() & 0xf) << 12);
4659 instruction |= ((Rn.value() & 0xf) << 16);
4660 instruction |= (offset_12 & 0xfff);
4661 emitInt(instruction);
4662 }
4663
4664 /**
4665 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
4666 * Example disassembly syntax: {@code ldreq r0, [r0], +r0}
4667 * <p>
4668 * Constraint: {@code Rm.value() != Rn.value()}<br />
4669 * Constraint: {@code Rn.value() != 15}<br />
4670 * Constraint: {@code Rm.value() != 15}<br />
4671 *
4672 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4673 */
4674 // Template#: 232, Serial#: 232
4675 public void ldraddpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
4676 int instruction = 0x06900000;
4677 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4678 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4679 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4680 instruction |= ((cond.value() & 0xf) << 28);
4681 instruction |= ((Rd.value() & 0xf) << 12);
4682 instruction |= ((Rn.value() & 0xf) << 16);
4683 instruction |= (Rm.value() & 0xf);
4684 emitInt(instruction);
4685 }
4686
4687 /**
4688 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
4689 * Example disassembly syntax: {@code ldreq r0, [r0], -r0}
4690 * <p>
4691 * Constraint: {@code Rm.value() != Rn.value()}<br />
4692 * Constraint: {@code Rn.value() != 15}<br />
4693 * Constraint: {@code Rm.value() != 15}<br />
4694 *
4695 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4696 */
4697 // Template#: 233, Serial#: 233
4698 public void ldrsubpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
4699 int instruction = 0x06100000;
4700 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4701 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4702 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4703 instruction |= ((cond.value() & 0xf) << 28);
4704 instruction |= ((Rd.value() & 0xf) << 12);
4705 instruction |= ((Rn.value() & 0xf) << 16);
4706 instruction |= (Rm.value() & 0xf);
4707 emitInt(instruction);
4708 }
4709
4710 /**
4711 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4712 * Example disassembly syntax: {@code ldreq r0, [r0], +r0, lsl #0x0}
4713 * <p>
4714 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
4715 * Constraint: {@code Rm.value() != 15}<br />
4716 * Constraint: {@code Rn.value() != 15}<br />
4717 * Constraint: {@code Rm.value() != Rn.value()}<br />
4718 *
4719 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4720 */
4721 // Template#: 234, Serial#: 234
4722 public void ldraddlslpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4723 int instruction = 0x06900000;
4724 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
4725 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4726 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4727 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4728 instruction |= ((cond.value() & 0xf) << 28);
4729 instruction |= ((Rd.value() & 0xf) << 12);
4730 instruction |= ((Rn.value() & 0xf) << 16);
4731 instruction |= (Rm.value() & 0xf);
4732 instruction |= ((shift_imm & 0x1f) << 7);
4733 emitInt(instruction);
4734 }
4735
4736 /**
4737 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4738 * Example disassembly syntax: {@code ldreq r0, [r0], -r0, lsl #0x0}
4739 * <p>
4740 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
4741 * Constraint: {@code Rm.value() != 15}<br />
4742 * Constraint: {@code Rn.value() != 15}<br />
4743 * Constraint: {@code Rm.value() != Rn.value()}<br />
4744 *
4745 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4746 */
4747 // Template#: 235, Serial#: 235
4748 public void ldrsublslpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4749 int instruction = 0x06100000;
4750 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
4751 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4752 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4753 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4754 instruction |= ((cond.value() & 0xf) << 28);
4755 instruction |= ((Rd.value() & 0xf) << 12);
4756 instruction |= ((Rn.value() & 0xf) << 16);
4757 instruction |= (Rm.value() & 0xf);
4758 instruction |= ((shift_imm & 0x1f) << 7);
4759 emitInt(instruction);
4760 }
4761
4762 /**
4763 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4764 * Example disassembly syntax: {@code ldreq r0, [r0], +r0, lsr #0x0}
4765 * <p>
4766 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
4767 * Constraint: {@code Rm.value() != 15}<br />
4768 * Constraint: {@code Rn.value() != 15}<br />
4769 * Constraint: {@code Rm.value() != Rn.value()}<br />
4770 *
4771 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4772 */
4773 // Template#: 236, Serial#: 236
4774 public void ldraddlsrpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4775 int instruction = 0x06900020;
4776 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
4777 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4778 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4779 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4780 instruction |= ((cond.value() & 0xf) << 28);
4781 instruction |= ((Rd.value() & 0xf) << 12);
4782 instruction |= ((Rn.value() & 0xf) << 16);
4783 instruction |= (Rm.value() & 0xf);
4784 instruction |= ((shift_imm % 32 & 0x1f) << 7);
4785 emitInt(instruction);
4786 }
4787
4788 /**
4789 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4790 * Example disassembly syntax: {@code ldreq r0, [r0], -r0, lsr #0x0}
4791 * <p>
4792 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
4793 * Constraint: {@code Rm.value() != 15}<br />
4794 * Constraint: {@code Rn.value() != 15}<br />
4795 * Constraint: {@code Rm.value() != Rn.value()}<br />
4796 *
4797 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4798 */
4799 // Template#: 237, Serial#: 237
4800 public void ldrsublsrpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4801 int instruction = 0x06100020;
4802 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
4803 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4804 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4805 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4806 instruction |= ((cond.value() & 0xf) << 28);
4807 instruction |= ((Rd.value() & 0xf) << 12);
4808 instruction |= ((Rn.value() & 0xf) << 16);
4809 instruction |= (Rm.value() & 0xf);
4810 instruction |= ((shift_imm % 32 & 0x1f) << 7);
4811 emitInt(instruction);
4812 }
4813
4814 /**
4815 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4816 * Example disassembly syntax: {@code ldreq r0, [r0], +r0, asr #0x0}
4817 * <p>
4818 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
4819 * Constraint: {@code Rm.value() != 15}<br />
4820 * Constraint: {@code Rn.value() != 15}<br />
4821 * Constraint: {@code Rm.value() != Rn.value()}<br />
4822 *
4823 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4824 */
4825 // Template#: 238, Serial#: 238
4826 public void ldraddasrpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4827 int instruction = 0x06900040;
4828 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
4829 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4830 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4831 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4832 instruction |= ((cond.value() & 0xf) << 28);
4833 instruction |= ((Rd.value() & 0xf) << 12);
4834 instruction |= ((Rn.value() & 0xf) << 16);
4835 instruction |= (Rm.value() & 0xf);
4836 instruction |= ((shift_imm % 32 & 0x1f) << 7);
4837 emitInt(instruction);
4838 }
4839
4840 /**
4841 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4842 * Example disassembly syntax: {@code ldreq r0, [r0], -r0, asr #0x0}
4843 * <p>
4844 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
4845 * Constraint: {@code Rm.value() != 15}<br />
4846 * Constraint: {@code Rn.value() != 15}<br />
4847 * Constraint: {@code Rm.value() != Rn.value()}<br />
4848 *
4849 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4850 */
4851 // Template#: 239, Serial#: 239
4852 public void ldrsubasrpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4853 int instruction = 0x06100040;
4854 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
4855 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4856 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4857 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4858 instruction |= ((cond.value() & 0xf) << 28);
4859 instruction |= ((Rd.value() & 0xf) << 12);
4860 instruction |= ((Rn.value() & 0xf) << 16);
4861 instruction |= (Rm.value() & 0xf);
4862 instruction |= ((shift_imm % 32 & 0x1f) << 7);
4863 emitInt(instruction);
4864 }
4865
4866 /**
4867 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4868 * Example disassembly syntax: {@code ldreq r0, [r0], +r0, ror #0x0}
4869 * <p>
4870 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
4871 * Constraint: {@code Rm.value() != 15}<br />
4872 * Constraint: {@code Rn.value() != 15}<br />
4873 * Constraint: {@code Rm.value() != Rn.value()}<br />
4874 *
4875 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4876 */
4877 // Template#: 240, Serial#: 240
4878 public void ldraddrorpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4879 int instruction = 0x06900060;
4880 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
4881 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4882 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4883 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4884 instruction |= ((cond.value() & 0xf) << 28);
4885 instruction |= ((Rd.value() & 0xf) << 12);
4886 instruction |= ((Rn.value() & 0xf) << 16);
4887 instruction |= (Rm.value() & 0xf);
4888 instruction |= ((shift_imm & 0x1f) << 7);
4889 emitInt(instruction);
4890 }
4891
4892 /**
4893 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
4894 * Example disassembly syntax: {@code ldreq r0, [r0], -r0, ror #0x0}
4895 * <p>
4896 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
4897 * Constraint: {@code Rm.value() != 15}<br />
4898 * Constraint: {@code Rn.value() != 15}<br />
4899 * Constraint: {@code Rm.value() != Rn.value()}<br />
4900 *
4901 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4902 */
4903 // Template#: 241, Serial#: 241
4904 public void ldrsubrorpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
4905 int instruction = 0x06100060;
4906 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
4907 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4908 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4909 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4910 instruction |= ((cond.value() & 0xf) << 28);
4911 instruction |= ((Rd.value() & 0xf) << 12);
4912 instruction |= ((Rn.value() & 0xf) << 16);
4913 instruction |= (Rm.value() & 0xf);
4914 instruction |= ((shift_imm & 0x1f) << 7);
4915 emitInt(instruction);
4916 }
4917
4918 /**
4919 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
4920 * Example disassembly syntax: {@code ldreq r0, [r0], +r0, rrx}
4921 * <p>
4922 * Constraint: {@code Rm.value() != 15}<br />
4923 * Constraint: {@code Rn.value() != 15}<br />
4924 * Constraint: {@code Rm.value() != Rn.value()}<br />
4925 *
4926 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4927 */
4928 // Template#: 242, Serial#: 242
4929 public void ldraddrrxpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
4930 int instruction = 0x06900060;
4931 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4932 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4933 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4934 instruction |= ((cond.value() & 0xf) << 28);
4935 instruction |= ((Rd.value() & 0xf) << 12);
4936 instruction |= ((Rn.value() & 0xf) << 16);
4937 instruction |= (Rm.value() & 0xf);
4938 emitInt(instruction);
4939 }
4940
4941 /**
4942 * Pseudo-external assembler syntax: {@code ldr{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
4943 * Example disassembly syntax: {@code ldreq r0, [r0], -r0, rrx}
4944 * <p>
4945 * Constraint: {@code Rm.value() != 15}<br />
4946 * Constraint: {@code Rn.value() != 15}<br />
4947 * Constraint: {@code Rm.value() != Rn.value()}<br />
4948 *
4949 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.20"
4950 */
4951 // Template#: 243, Serial#: 243
4952 public void ldrsubrrxpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
4953 int instruction = 0x06100060;
4954 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
4955 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
4956 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
4957 instruction |= ((cond.value() & 0xf) << 28);
4958 instruction |= ((Rd.value() & 0xf) << 12);
4959 instruction |= ((Rn.value() & 0xf) << 16);
4960 instruction |= (Rm.value() & 0xf);
4961 emitInt(instruction);
4962 }
4963
4964 /**
4965 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>offset_12</i>
4966 * Example disassembly syntax: {@code streq r0, [r0, #+0x0]}
4967 * <p>
4968 * Constraint: {@code 0 <= offset_12 && offset_12 <= 4095}<br />
4969 *
4970 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
4971 */
4972 // Template#: 244, Serial#: 244
4973 public void stradd(final ConditionCode cond, final GPR Rd, final GPR Rn, final int offset_12) {
4974 int instruction = 0x05800000;
4975 checkConstraint(0 <= offset_12 && offset_12 <= 4095, "0 <= offset_12 && offset_12 <= 4095");
4976 instruction |= ((cond.value() & 0xf) << 28);
4977 instruction |= ((Rd.value() & 0xf) << 12);
4978 instruction |= ((Rn.value() & 0xf) << 16);
4979 instruction |= (offset_12 & 0xfff);
4980 emitInt(instruction);
4981 }
4982
4983 /**
4984 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>offset_12</i>
4985 * Example disassembly syntax: {@code streq r0, [r0, #-0x0]}
4986 * <p>
4987 * Constraint: {@code 0 <= offset_12 && offset_12 <= 4095}<br />
4988 *
4989 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
4990 */
4991 // Template#: 245, Serial#: 245
4992 public void strsub(final ConditionCode cond, final GPR Rd, final GPR Rn, final int offset_12) {
4993 int instruction = 0x05000000;
4994 checkConstraint(0 <= offset_12 && offset_12 <= 4095, "0 <= offset_12 && offset_12 <= 4095");
4995 instruction |= ((cond.value() & 0xf) << 28);
4996 instruction |= ((Rd.value() & 0xf) << 12);
4997 instruction |= ((Rn.value() & 0xf) << 16);
4998 instruction |= (offset_12 & 0xfff);
4999 emitInt(instruction);
5000 }
5001
5002 /**
5003 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
5004 * Example disassembly syntax: {@code streq r0, [r0, +r0]}
5005 * <p>
5006 * Constraint: {@code Rm.value() != 15}<br />
5007 *
5008 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5009 */
5010 // Template#: 246, Serial#: 246
5011 public void stradd(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
5012 int instruction = 0x07800000;
5013 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5014 instruction |= ((cond.value() & 0xf) << 28);
5015 instruction |= ((Rd.value() & 0xf) << 12);
5016 instruction |= ((Rn.value() & 0xf) << 16);
5017 instruction |= (Rm.value() & 0xf);
5018 emitInt(instruction);
5019 }
5020
5021 /**
5022 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
5023 * Example disassembly syntax: {@code streq r0, [r0, -r0]}
5024 * <p>
5025 * Constraint: {@code Rm.value() != 15}<br />
5026 *
5027 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5028 */
5029 // Template#: 247, Serial#: 247
5030 public void strsub(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
5031 int instruction = 0x07000000;
5032 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5033 instruction |= ((cond.value() & 0xf) << 28);
5034 instruction |= ((Rd.value() & 0xf) << 12);
5035 instruction |= ((Rn.value() & 0xf) << 16);
5036 instruction |= (Rm.value() & 0xf);
5037 emitInt(instruction);
5038 }
5039
5040 /**
5041 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5042 * Example disassembly syntax: {@code streq r0, [r0, +r0, lsl #0x0]}
5043 * <p>
5044 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
5045 * Constraint: {@code Rm.value() != 15}<br />
5046 *
5047 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5048 */
5049 // Template#: 248, Serial#: 248
5050 public void straddlsl(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5051 int instruction = 0x07800000;
5052 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
5053 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5054 instruction |= ((cond.value() & 0xf) << 28);
5055 instruction |= ((Rd.value() & 0xf) << 12);
5056 instruction |= ((Rn.value() & 0xf) << 16);
5057 instruction |= (Rm.value() & 0xf);
5058 instruction |= ((shift_imm & 0x1f) << 7);
5059 emitInt(instruction);
5060 }
5061
5062 /**
5063 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5064 * Example disassembly syntax: {@code streq r0, [r0, -r0, lsl #0x0]}
5065 * <p>
5066 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
5067 * Constraint: {@code Rm.value() != 15}<br />
5068 *
5069 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5070 */
5071 // Template#: 249, Serial#: 249
5072 public void strsublsl(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5073 int instruction = 0x07000000;
5074 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
5075 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5076 instruction |= ((cond.value() & 0xf) << 28);
5077 instruction |= ((Rd.value() & 0xf) << 12);
5078 instruction |= ((Rn.value() & 0xf) << 16);
5079 instruction |= (Rm.value() & 0xf);
5080 instruction |= ((shift_imm & 0x1f) << 7);
5081 emitInt(instruction);
5082 }
5083
5084 /**
5085 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5086 * Example disassembly syntax: {@code streq r0, [r0, +r0, lsr #0x0]}
5087 * <p>
5088 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
5089 * Constraint: {@code Rm.value() != 15}<br />
5090 *
5091 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5092 */
5093 // Template#: 250, Serial#: 250
5094 public void straddlsr(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5095 int instruction = 0x07800020;
5096 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
5097 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5098 instruction |= ((cond.value() & 0xf) << 28);
5099 instruction |= ((Rd.value() & 0xf) << 12);
5100 instruction |= ((Rn.value() & 0xf) << 16);
5101 instruction |= (Rm.value() & 0xf);
5102 instruction |= ((shift_imm % 32 & 0x1f) << 7);
5103 emitInt(instruction);
5104 }
5105
5106 /**
5107 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5108 * Example disassembly syntax: {@code streq r0, [r0, -r0, lsr #0x0]}
5109 * <p>
5110 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
5111 * Constraint: {@code Rm.value() != 15}<br />
5112 *
5113 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5114 */
5115 // Template#: 251, Serial#: 251
5116 public void strsublsr(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5117 int instruction = 0x07000020;
5118 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
5119 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5120 instruction |= ((cond.value() & 0xf) << 28);
5121 instruction |= ((Rd.value() & 0xf) << 12);
5122 instruction |= ((Rn.value() & 0xf) << 16);
5123 instruction |= (Rm.value() & 0xf);
5124 instruction |= ((shift_imm % 32 & 0x1f) << 7);
5125 emitInt(instruction);
5126 }
5127
5128 /**
5129 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5130 * Example disassembly syntax: {@code streq r0, [r0, +r0, asr #0x0]}
5131 * <p>
5132 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
5133 * Constraint: {@code Rm.value() != 15}<br />
5134 *
5135 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5136 */
5137 // Template#: 252, Serial#: 252
5138 public void straddasr(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5139 int instruction = 0x07800040;
5140 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
5141 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5142 instruction |= ((cond.value() & 0xf) << 28);
5143 instruction |= ((Rd.value() & 0xf) << 12);
5144 instruction |= ((Rn.value() & 0xf) << 16);
5145 instruction |= (Rm.value() & 0xf);
5146 instruction |= ((shift_imm % 32 & 0x1f) << 7);
5147 emitInt(instruction);
5148 }
5149
5150 /**
5151 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5152 * Example disassembly syntax: {@code streq r0, [r0, -r0, asr #0x0]}
5153 * <p>
5154 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
5155 * Constraint: {@code Rm.value() != 15}<br />
5156 *
5157 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5158 */
5159 // Template#: 253, Serial#: 253
5160 public void strsubasr(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5161 int instruction = 0x07000040;
5162 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
5163 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5164 instruction |= ((cond.value() & 0xf) << 28);
5165 instruction |= ((Rd.value() & 0xf) << 12);
5166 instruction |= ((Rn.value() & 0xf) << 16);
5167 instruction |= (Rm.value() & 0xf);
5168 instruction |= ((shift_imm % 32 & 0x1f) << 7);
5169 emitInt(instruction);
5170 }
5171
5172 /**
5173 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5174 * Example disassembly syntax: {@code streq r0, [r0, +r0, ror #0x0]}
5175 * <p>
5176 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
5177 * Constraint: {@code Rm.value() != 15}<br />
5178 *
5179 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5180 */
5181 // Template#: 254, Serial#: 254
5182 public void straddror(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5183 int instruction = 0x07800060;
5184 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
5185 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5186 instruction |= ((cond.value() & 0xf) << 28);
5187 instruction |= ((Rd.value() & 0xf) << 12);
5188 instruction |= ((Rn.value() & 0xf) << 16);
5189 instruction |= (Rm.value() & 0xf);
5190 instruction |= ((shift_imm & 0x1f) << 7);
5191 emitInt(instruction);
5192 }
5193
5194 /**
5195 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5196 * Example disassembly syntax: {@code streq r0, [r0, -r0, ror #0x0]}
5197 * <p>
5198 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
5199 * Constraint: {@code Rm.value() != 15}<br />
5200 *
5201 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5202 */
5203 // Template#: 255, Serial#: 255
5204 public void strsubror(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5205 int instruction = 0x07000060;
5206 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
5207 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5208 instruction |= ((cond.value() & 0xf) << 28);
5209 instruction |= ((Rd.value() & 0xf) << 12);
5210 instruction |= ((Rn.value() & 0xf) << 16);
5211 instruction |= (Rm.value() & 0xf);
5212 instruction |= ((shift_imm & 0x1f) << 7);
5213 emitInt(instruction);
5214 }
5215
5216 /**
5217 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
5218 * Example disassembly syntax: {@code streq r0, [r0, +r0, rrx]}
5219 * <p>
5220 * Constraint: {@code Rm.value() != 15}<br />
5221 *
5222 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5223 */
5224 // Template#: 256, Serial#: 256
5225 public void straddrrx(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
5226 int instruction = 0x07800060;
5227 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5228 instruction |= ((cond.value() & 0xf) << 28);
5229 instruction |= ((Rd.value() & 0xf) << 12);
5230 instruction |= ((Rn.value() & 0xf) << 16);
5231 instruction |= (Rm.value() & 0xf);
5232 emitInt(instruction);
5233 }
5234
5235 /**
5236 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
5237 * Example disassembly syntax: {@code streq r0, [r0, -r0, rrx]}
5238 * <p>
5239 * Constraint: {@code Rm.value() != 15}<br />
5240 *
5241 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5242 */
5243 // Template#: 257, Serial#: 257
5244 public void strsubrrx(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
5245 int instruction = 0x07000060;
5246 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5247 instruction |= ((cond.value() & 0xf) << 28);
5248 instruction |= ((Rd.value() & 0xf) << 12);
5249 instruction |= ((Rn.value() & 0xf) << 16);
5250 instruction |= (Rm.value() & 0xf);
5251 emitInt(instruction);
5252 }
5253
5254 /**
5255 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>offset_12</i>
5256 * Example disassembly syntax: {@code streq r0, [r0, #+0x0]!}
5257 * <p>
5258 * Constraint: {@code 0 <= offset_12 && offset_12 <= 4095}<br />
5259 * Constraint: {@code Rd.value() != Rn.value()}<br />
5260 * Constraint: {@code Rn.value() != 15}<br />
5261 *
5262 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5263 */
5264 // Template#: 258, Serial#: 258
5265 public void straddw(final ConditionCode cond, final GPR Rd, final GPR Rn, final int offset_12) {
5266 int instruction = 0x05A00000;
5267 checkConstraint(0 <= offset_12 && offset_12 <= 4095, "0 <= offset_12 && offset_12 <= 4095");
5268 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
5269 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5270 instruction |= ((cond.value() & 0xf) << 28);
5271 instruction |= ((Rd.value() & 0xf) << 12);
5272 instruction |= ((Rn.value() & 0xf) << 16);
5273 instruction |= (offset_12 & 0xfff);
5274 emitInt(instruction);
5275 }
5276
5277 /**
5278 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>offset_12</i>
5279 * Example disassembly syntax: {@code streq r0, [r0, #-0x0]!}
5280 * <p>
5281 * Constraint: {@code 0 <= offset_12 && offset_12 <= 4095}<br />
5282 * Constraint: {@code Rd.value() != Rn.value()}<br />
5283 * Constraint: {@code Rn.value() != 15}<br />
5284 *
5285 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5286 */
5287 // Template#: 259, Serial#: 259
5288 public void strsubw(final ConditionCode cond, final GPR Rd, final GPR Rn, final int offset_12) {
5289 int instruction = 0x05200000;
5290 checkConstraint(0 <= offset_12 && offset_12 <= 4095, "0 <= offset_12 && offset_12 <= 4095");
5291 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
5292 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5293 instruction |= ((cond.value() & 0xf) << 28);
5294 instruction |= ((Rd.value() & 0xf) << 12);
5295 instruction |= ((Rn.value() & 0xf) << 16);
5296 instruction |= (offset_12 & 0xfff);
5297 emitInt(instruction);
5298 }
5299
5300 /**
5301 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
5302 * Example disassembly syntax: {@code streq r0, [r0, +r0]!}
5303 * <p>
5304 * Constraint: {@code Rd.value() != Rn.value()}<br />
5305 * Constraint: {@code Rm.value() != Rn.value()}<br />
5306 * Constraint: {@code Rn.value() != 15}<br />
5307 * Constraint: {@code Rm.value() != 15}<br />
5308 *
5309 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5310 */
5311 // Template#: 260, Serial#: 260
5312 public void straddw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
5313 int instruction = 0x07A00000;
5314 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
5315 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5316 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5317 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5318 instruction |= ((cond.value() & 0xf) << 28);
5319 instruction |= ((Rd.value() & 0xf) << 12);
5320 instruction |= ((Rn.value() & 0xf) << 16);
5321 instruction |= (Rm.value() & 0xf);
5322 emitInt(instruction);
5323 }
5324
5325 /**
5326 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
5327 * Example disassembly syntax: {@code streq r0, [r0, -r0]!}
5328 * <p>
5329 * Constraint: {@code Rd.value() != Rn.value()}<br />
5330 * Constraint: {@code Rm.value() != Rn.value()}<br />
5331 * Constraint: {@code Rn.value() != 15}<br />
5332 * Constraint: {@code Rm.value() != 15}<br />
5333 *
5334 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5335 */
5336 // Template#: 261, Serial#: 261
5337 public void strsubw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
5338 int instruction = 0x07200000;
5339 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
5340 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5341 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5342 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5343 instruction |= ((cond.value() & 0xf) << 28);
5344 instruction |= ((Rd.value() & 0xf) << 12);
5345 instruction |= ((Rn.value() & 0xf) << 16);
5346 instruction |= (Rm.value() & 0xf);
5347 emitInt(instruction);
5348 }
5349
5350 /**
5351 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5352 * Example disassembly syntax: {@code streq r0, [r0, +r0, lsl #0x0]!}
5353 * <p>
5354 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
5355 * Constraint: {@code Rd.value() != Rn.value()}<br />
5356 * Constraint: {@code Rm.value() != Rn.value()}<br />
5357 * Constraint: {@code Rn.value() != 15}<br />
5358 * Constraint: {@code Rm.value() != 15}<br />
5359 *
5360 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5361 */
5362 // Template#: 262, Serial#: 262
5363 public void straddlslw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5364 int instruction = 0x07A00000;
5365 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
5366 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
5367 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5368 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5369 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5370 instruction |= ((cond.value() & 0xf) << 28);
5371 instruction |= ((Rd.value() & 0xf) << 12);
5372 instruction |= ((Rn.value() & 0xf) << 16);
5373 instruction |= (Rm.value() & 0xf);
5374 instruction |= ((shift_imm & 0x1f) << 7);
5375 emitInt(instruction);
5376 }
5377
5378 /**
5379 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5380 * Example disassembly syntax: {@code streq r0, [r0, -r0, lsl #0x0]!}
5381 * <p>
5382 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
5383 * Constraint: {@code Rd.value() != Rn.value()}<br />
5384 * Constraint: {@code Rm.value() != Rn.value()}<br />
5385 * Constraint: {@code Rn.value() != 15}<br />
5386 * Constraint: {@code Rm.value() != 15}<br />
5387 *
5388 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5389 */
5390 // Template#: 263, Serial#: 263
5391 public void strsublslw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5392 int instruction = 0x07200000;
5393 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
5394 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
5395 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5396 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5397 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5398 instruction |= ((cond.value() & 0xf) << 28);
5399 instruction |= ((Rd.value() & 0xf) << 12);
5400 instruction |= ((Rn.value() & 0xf) << 16);
5401 instruction |= (Rm.value() & 0xf);
5402 instruction |= ((shift_imm & 0x1f) << 7);
5403 emitInt(instruction);
5404 }
5405
5406 /**
5407 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5408 * Example disassembly syntax: {@code streq r0, [r0, +r0, lsr #0x0]!}
5409 * <p>
5410 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
5411 * Constraint: {@code Rd.value() != Rn.value()}<br />
5412 * Constraint: {@code Rm.value() != Rn.value()}<br />
5413 * Constraint: {@code Rn.value() != 15}<br />
5414 * Constraint: {@code Rm.value() != 15}<br />
5415 *
5416 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5417 */
5418 // Template#: 264, Serial#: 264
5419 public void straddlsrw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5420 int instruction = 0x07A00020;
5421 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
5422 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
5423 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5424 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5425 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5426 instruction |= ((cond.value() & 0xf) << 28);
5427 instruction |= ((Rd.value() & 0xf) << 12);
5428 instruction |= ((Rn.value() & 0xf) << 16);
5429 instruction |= (Rm.value() & 0xf);
5430 instruction |= ((shift_imm % 32 & 0x1f) << 7);
5431 emitInt(instruction);
5432 }
5433
5434 /**
5435 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5436 * Example disassembly syntax: {@code streq r0, [r0, -r0, lsr #0x0]!}
5437 * <p>
5438 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
5439 * Constraint: {@code Rd.value() != Rn.value()}<br />
5440 * Constraint: {@code Rm.value() != Rn.value()}<br />
5441 * Constraint: {@code Rn.value() != 15}<br />
5442 * Constraint: {@code Rm.value() != 15}<br />
5443 *
5444 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5445 */
5446 // Template#: 265, Serial#: 265
5447 public void strsublsrw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5448 int instruction = 0x07200020;
5449 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
5450 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
5451 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5452 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5453 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5454 instruction |= ((cond.value() & 0xf) << 28);
5455 instruction |= ((Rd.value() & 0xf) << 12);
5456 instruction |= ((Rn.value() & 0xf) << 16);
5457 instruction |= (Rm.value() & 0xf);
5458 instruction |= ((shift_imm % 32 & 0x1f) << 7);
5459 emitInt(instruction);
5460 }
5461
5462 /**
5463 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5464 * Example disassembly syntax: {@code streq r0, [r0, +r0, asr #0x0]!}
5465 * <p>
5466 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
5467 * Constraint: {@code Rd.value() != Rn.value()}<br />
5468 * Constraint: {@code Rm.value() != Rn.value()}<br />
5469 * Constraint: {@code Rn.value() != 15}<br />
5470 * Constraint: {@code Rm.value() != 15}<br />
5471 *
5472 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5473 */
5474 // Template#: 266, Serial#: 266
5475 public void straddasrw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5476 int instruction = 0x07A00040;
5477 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
5478 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
5479 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5480 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5481 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5482 instruction |= ((cond.value() & 0xf) << 28);
5483 instruction |= ((Rd.value() & 0xf) << 12);
5484 instruction |= ((Rn.value() & 0xf) << 16);
5485 instruction |= (Rm.value() & 0xf);
5486 instruction |= ((shift_imm % 32 & 0x1f) << 7);
5487 emitInt(instruction);
5488 }
5489
5490 /**
5491 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5492 * Example disassembly syntax: {@code streq r0, [r0, -r0, asr #0x0]!}
5493 * <p>
5494 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
5495 * Constraint: {@code Rd.value() != Rn.value()}<br />
5496 * Constraint: {@code Rm.value() != Rn.value()}<br />
5497 * Constraint: {@code Rn.value() != 15}<br />
5498 * Constraint: {@code Rm.value() != 15}<br />
5499 *
5500 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5501 */
5502 // Template#: 267, Serial#: 267
5503 public void strsubasrw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5504 int instruction = 0x07200040;
5505 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
5506 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
5507 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5508 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5509 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5510 instruction |= ((cond.value() & 0xf) << 28);
5511 instruction |= ((Rd.value() & 0xf) << 12);
5512 instruction |= ((Rn.value() & 0xf) << 16);
5513 instruction |= (Rm.value() & 0xf);
5514 instruction |= ((shift_imm % 32 & 0x1f) << 7);
5515 emitInt(instruction);
5516 }
5517
5518 /**
5519 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5520 * Example disassembly syntax: {@code streq r0, [r0, +r0, ror #0x0]!}
5521 * <p>
5522 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
5523 * Constraint: {@code Rd.value() != Rn.value()}<br />
5524 * Constraint: {@code Rm.value() != Rn.value()}<br />
5525 * Constraint: {@code Rn.value() != 15}<br />
5526 * Constraint: {@code Rm.value() != 15}<br />
5527 *
5528 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5529 */
5530 // Template#: 268, Serial#: 268
5531 public void straddrorw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5532 int instruction = 0x07A00060;
5533 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
5534 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
5535 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5536 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5537 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5538 instruction |= ((cond.value() & 0xf) << 28);
5539 instruction |= ((Rd.value() & 0xf) << 12);
5540 instruction |= ((Rn.value() & 0xf) << 16);
5541 instruction |= (Rm.value() & 0xf);
5542 instruction |= ((shift_imm & 0x1f) << 7);
5543 emitInt(instruction);
5544 }
5545
5546 /**
5547 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5548 * Example disassembly syntax: {@code streq r0, [r0, -r0, ror #0x0]!}
5549 * <p>
5550 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
5551 * Constraint: {@code Rd.value() != Rn.value()}<br />
5552 * Constraint: {@code Rm.value() != Rn.value()}<br />
5553 * Constraint: {@code Rn.value() != 15}<br />
5554 * Constraint: {@code Rm.value() != 15}<br />
5555 *
5556 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5557 */
5558 // Template#: 269, Serial#: 269
5559 public void strsubrorw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5560 int instruction = 0x07200060;
5561 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
5562 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
5563 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5564 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5565 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5566 instruction |= ((cond.value() & 0xf) << 28);
5567 instruction |= ((Rd.value() & 0xf) << 12);
5568 instruction |= ((Rn.value() & 0xf) << 16);
5569 instruction |= (Rm.value() & 0xf);
5570 instruction |= ((shift_imm & 0x1f) << 7);
5571 emitInt(instruction);
5572 }
5573
5574 /**
5575 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
5576 * Example disassembly syntax: {@code streq r0, [r0, +r0, rrx]!}
5577 * <p>
5578 * Constraint: {@code Rd.value() != Rn.value()}<br />
5579 * Constraint: {@code Rm.value() != Rn.value()}<br />
5580 * Constraint: {@code Rn.value() != 15}<br />
5581 * Constraint: {@code Rm.value() != 15}<br />
5582 *
5583 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5584 */
5585 // Template#: 270, Serial#: 270
5586 public void straddrrxw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
5587 int instruction = 0x07A00060;
5588 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
5589 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5590 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5591 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5592 instruction |= ((cond.value() & 0xf) << 28);
5593 instruction |= ((Rd.value() & 0xf) << 12);
5594 instruction |= ((Rn.value() & 0xf) << 16);
5595 instruction |= (Rm.value() & 0xf);
5596 emitInt(instruction);
5597 }
5598
5599 /**
5600 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
5601 * Example disassembly syntax: {@code streq r0, [r0, -r0, rrx]!}
5602 * <p>
5603 * Constraint: {@code Rd.value() != Rn.value()}<br />
5604 * Constraint: {@code Rm.value() != Rn.value()}<br />
5605 * Constraint: {@code Rn.value() != 15}<br />
5606 * Constraint: {@code Rm.value() != 15}<br />
5607 *
5608 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5609 */
5610 // Template#: 271, Serial#: 271
5611 public void strsubrrxw(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
5612 int instruction = 0x07200060;
5613 checkConstraint(Rd.value() != Rn.value(), "Rd.value() != Rn.value()");
5614 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5615 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5616 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5617 instruction |= ((cond.value() & 0xf) << 28);
5618 instruction |= ((Rd.value() & 0xf) << 12);
5619 instruction |= ((Rn.value() & 0xf) << 16);
5620 instruction |= (Rm.value() & 0xf);
5621 emitInt(instruction);
5622 }
5623
5624 /**
5625 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>offset_12</i>
5626 * Example disassembly syntax: {@code streq r0, [r0], #+0x0}
5627 * <p>
5628 * Constraint: {@code 0 <= offset_12 && offset_12 <= 4095}<br />
5629 * Constraint: {@code Rn.value() != 15}<br />
5630 *
5631 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5632 */
5633 // Template#: 272, Serial#: 272
5634 public void straddpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final int offset_12) {
5635 int instruction = 0x04800000;
5636 checkConstraint(0 <= offset_12 && offset_12 <= 4095, "0 <= offset_12 && offset_12 <= 4095");
5637 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5638 instruction |= ((cond.value() & 0xf) << 28);
5639 instruction |= ((Rd.value() & 0xf) << 12);
5640 instruction |= ((Rn.value() & 0xf) << 16);
5641 instruction |= (offset_12 & 0xfff);
5642 emitInt(instruction);
5643 }
5644
5645 /**
5646 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>offset_12</i>
5647 * Example disassembly syntax: {@code streq r0, [r0], #-0x0}
5648 * <p>
5649 * Constraint: {@code 0 <= offset_12 && offset_12 <= 4095}<br />
5650 * Constraint: {@code Rn.value() != 15}<br />
5651 *
5652 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5653 */
5654 // Template#: 273, Serial#: 273
5655 public void strsubpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final int offset_12) {
5656 int instruction = 0x04000000;
5657 checkConstraint(0 <= offset_12 && offset_12 <= 4095, "0 <= offset_12 && offset_12 <= 4095");
5658 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5659 instruction |= ((cond.value() & 0xf) << 28);
5660 instruction |= ((Rd.value() & 0xf) << 12);
5661 instruction |= ((Rn.value() & 0xf) << 16);
5662 instruction |= (offset_12 & 0xfff);
5663 emitInt(instruction);
5664 }
5665
5666 /**
5667 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
5668 * Example disassembly syntax: {@code streq r0, [r0], +r0}
5669 * <p>
5670 * Constraint: {@code Rm.value() != Rn.value()}<br />
5671 * Constraint: {@code Rn.value() != 15}<br />
5672 * Constraint: {@code Rm.value() != 15}<br />
5673 *
5674 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5675 */
5676 // Template#: 274, Serial#: 274
5677 public void straddpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
5678 int instruction = 0x06800000;
5679 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5680 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5681 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5682 instruction |= ((cond.value() & 0xf) << 28);
5683 instruction |= ((Rd.value() & 0xf) << 12);
5684 instruction |= ((Rn.value() & 0xf) << 16);
5685 instruction |= (Rm.value() & 0xf);
5686 emitInt(instruction);
5687 }
5688
5689 /**
5690 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
5691 * Example disassembly syntax: {@code streq r0, [r0], -r0}
5692 * <p>
5693 * Constraint: {@code Rm.value() != Rn.value()}<br />
5694 * Constraint: {@code Rn.value() != 15}<br />
5695 * Constraint: {@code Rm.value() != 15}<br />
5696 *
5697 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5698 */
5699 // Template#: 275, Serial#: 275
5700 public void strsubpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
5701 int instruction = 0x06000000;
5702 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5703 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5704 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5705 instruction |= ((cond.value() & 0xf) << 28);
5706 instruction |= ((Rd.value() & 0xf) << 12);
5707 instruction |= ((Rn.value() & 0xf) << 16);
5708 instruction |= (Rm.value() & 0xf);
5709 emitInt(instruction);
5710 }
5711
5712 /**
5713 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5714 * Example disassembly syntax: {@code streq r0, [r0], +r0, lsl #0x0}
5715 * <p>
5716 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
5717 * Constraint: {@code Rm.value() != 15}<br />
5718 * Constraint: {@code Rn.value() != 15}<br />
5719 * Constraint: {@code Rm.value() != Rn.value()}<br />
5720 *
5721 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5722 */
5723 // Template#: 276, Serial#: 276
5724 public void straddlslpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5725 int instruction = 0x06800000;
5726 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
5727 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5728 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5729 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5730 instruction |= ((cond.value() & 0xf) << 28);
5731 instruction |= ((Rd.value() & 0xf) << 12);
5732 instruction |= ((Rn.value() & 0xf) << 16);
5733 instruction |= (Rm.value() & 0xf);
5734 instruction |= ((shift_imm & 0x1f) << 7);
5735 emitInt(instruction);
5736 }
5737
5738 /**
5739 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5740 * Example disassembly syntax: {@code streq r0, [r0], -r0, lsl #0x0}
5741 * <p>
5742 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
5743 * Constraint: {@code Rm.value() != 15}<br />
5744 * Constraint: {@code Rn.value() != 15}<br />
5745 * Constraint: {@code Rm.value() != Rn.value()}<br />
5746 *
5747 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5748 */
5749 // Template#: 277, Serial#: 277
5750 public void strsublslpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5751 int instruction = 0x06000000;
5752 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
5753 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5754 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5755 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5756 instruction |= ((cond.value() & 0xf) << 28);
5757 instruction |= ((Rd.value() & 0xf) << 12);
5758 instruction |= ((Rn.value() & 0xf) << 16);
5759 instruction |= (Rm.value() & 0xf);
5760 instruction |= ((shift_imm & 0x1f) << 7);
5761 emitInt(instruction);
5762 }
5763
5764 /**
5765 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5766 * Example disassembly syntax: {@code streq r0, [r0], +r0, lsr #0x0}
5767 * <p>
5768 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
5769 * Constraint: {@code Rm.value() != 15}<br />
5770 * Constraint: {@code Rn.value() != 15}<br />
5771 * Constraint: {@code Rm.value() != Rn.value()}<br />
5772 *
5773 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5774 */
5775 // Template#: 278, Serial#: 278
5776 public void straddlsrpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5777 int instruction = 0x06800020;
5778 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
5779 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5780 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5781 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5782 instruction |= ((cond.value() & 0xf) << 28);
5783 instruction |= ((Rd.value() & 0xf) << 12);
5784 instruction |= ((Rn.value() & 0xf) << 16);
5785 instruction |= (Rm.value() & 0xf);
5786 instruction |= ((shift_imm % 32 & 0x1f) << 7);
5787 emitInt(instruction);
5788 }
5789
5790 /**
5791 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5792 * Example disassembly syntax: {@code streq r0, [r0], -r0, lsr #0x0}
5793 * <p>
5794 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
5795 * Constraint: {@code Rm.value() != 15}<br />
5796 * Constraint: {@code Rn.value() != 15}<br />
5797 * Constraint: {@code Rm.value() != Rn.value()}<br />
5798 *
5799 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5800 */
5801 // Template#: 279, Serial#: 279
5802 public void strsublsrpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5803 int instruction = 0x06000020;
5804 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
5805 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5806 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5807 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5808 instruction |= ((cond.value() & 0xf) << 28);
5809 instruction |= ((Rd.value() & 0xf) << 12);
5810 instruction |= ((Rn.value() & 0xf) << 16);
5811 instruction |= (Rm.value() & 0xf);
5812 instruction |= ((shift_imm % 32 & 0x1f) << 7);
5813 emitInt(instruction);
5814 }
5815
5816 /**
5817 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5818 * Example disassembly syntax: {@code streq r0, [r0], +r0, asr #0x0}
5819 * <p>
5820 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
5821 * Constraint: {@code Rm.value() != 15}<br />
5822 * Constraint: {@code Rn.value() != 15}<br />
5823 * Constraint: {@code Rm.value() != Rn.value()}<br />
5824 *
5825 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5826 */
5827 // Template#: 280, Serial#: 280
5828 public void straddasrpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5829 int instruction = 0x06800040;
5830 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
5831 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5832 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5833 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5834 instruction |= ((cond.value() & 0xf) << 28);
5835 instruction |= ((Rd.value() & 0xf) << 12);
5836 instruction |= ((Rn.value() & 0xf) << 16);
5837 instruction |= (Rm.value() & 0xf);
5838 instruction |= ((shift_imm % 32 & 0x1f) << 7);
5839 emitInt(instruction);
5840 }
5841
5842 /**
5843 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5844 * Example disassembly syntax: {@code streq r0, [r0], -r0, asr #0x0}
5845 * <p>
5846 * Constraint: {@code 0 <= shift_imm % 32 && shift_imm % 32 <= 31}<br />
5847 * Constraint: {@code Rm.value() != 15}<br />
5848 * Constraint: {@code Rn.value() != 15}<br />
5849 * Constraint: {@code Rm.value() != Rn.value()}<br />
5850 *
5851 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5852 */
5853 // Template#: 281, Serial#: 281
5854 public void strsubasrpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5855 int instruction = 0x06000040;
5856 checkConstraint(0 <= shift_imm % 32 && shift_imm % 32 <= 31, "0 <= shift_imm % 32 && shift_imm % 32 <= 31");
5857 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5858 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5859 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5860 instruction |= ((cond.value() & 0xf) << 28);
5861 instruction |= ((Rd.value() & 0xf) << 12);
5862 instruction |= ((Rn.value() & 0xf) << 16);
5863 instruction |= (Rm.value() & 0xf);
5864 instruction |= ((shift_imm % 32 & 0x1f) << 7);
5865 emitInt(instruction);
5866 }
5867
5868 /**
5869 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5870 * Example disassembly syntax: {@code streq r0, [r0], +r0, ror #0x0}
5871 * <p>
5872 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
5873 * Constraint: {@code Rm.value() != 15}<br />
5874 * Constraint: {@code Rn.value() != 15}<br />
5875 * Constraint: {@code Rm.value() != Rn.value()}<br />
5876 *
5877 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5878 */
5879 // Template#: 282, Serial#: 282
5880 public void straddrorpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5881 int instruction = 0x06800060;
5882 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
5883 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5884 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5885 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5886 instruction |= ((cond.value() & 0xf) << 28);
5887 instruction |= ((Rd.value() & 0xf) << 12);
5888 instruction |= ((Rn.value() & 0xf) << 16);
5889 instruction |= (Rm.value() & 0xf);
5890 instruction |= ((shift_imm & 0x1f) << 7);
5891 emitInt(instruction);
5892 }
5893
5894 /**
5895 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>, <i>shift_imm</i>
5896 * Example disassembly syntax: {@code streq r0, [r0], -r0, ror #0x0}
5897 * <p>
5898 * Constraint: {@code 0 <= shift_imm && shift_imm <= 31}<br />
5899 * Constraint: {@code Rm.value() != 15}<br />
5900 * Constraint: {@code Rn.value() != 15}<br />
5901 * Constraint: {@code Rm.value() != Rn.value()}<br />
5902 *
5903 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5904 */
5905 // Template#: 283, Serial#: 283
5906 public void strsubrorpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm, final int shift_imm) {
5907 int instruction = 0x06000060;
5908 checkConstraint(0 <= shift_imm && shift_imm <= 31, "0 <= shift_imm && shift_imm <= 31");
5909 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5910 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5911 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5912 instruction |= ((cond.value() & 0xf) << 28);
5913 instruction |= ((Rd.value() & 0xf) << 12);
5914 instruction |= ((Rn.value() & 0xf) << 16);
5915 instruction |= (Rm.value() & 0xf);
5916 instruction |= ((shift_imm & 0x1f) << 7);
5917 emitInt(instruction);
5918 }
5919
5920 /**
5921 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
5922 * Example disassembly syntax: {@code streq r0, [r0], +r0, rrx}
5923 * <p>
5924 * Constraint: {@code Rm.value() != 15}<br />
5925 * Constraint: {@code Rn.value() != 15}<br />
5926 * Constraint: {@code Rm.value() != Rn.value()}<br />
5927 *
5928 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5929 */
5930 // Template#: 284, Serial#: 284
5931 public void straddrrxpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
5932 int instruction = 0x06800060;
5933 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5934 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5935 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5936 instruction |= ((cond.value() & 0xf) << 28);
5937 instruction |= ((Rd.value() & 0xf) << 12);
5938 instruction |= ((Rn.value() & 0xf) << 16);
5939 instruction |= (Rm.value() & 0xf);
5940 emitInt(instruction);
5941 }
5942
5943 /**
5944 * Pseudo-external assembler syntax: {@code str{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rn</i>, <i>Rm</i>
5945 * Example disassembly syntax: {@code streq r0, [r0], -r0, rrx}
5946 * <p>
5947 * Constraint: {@code Rm.value() != 15}<br />
5948 * Constraint: {@code Rn.value() != 15}<br />
5949 * Constraint: {@code Rm.value() != Rn.value()}<br />
5950 *
5951 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.44"
5952 */
5953 // Template#: 285, Serial#: 285
5954 public void strsubrrxpost(final ConditionCode cond, final GPR Rd, final GPR Rn, final GPR Rm) {
5955 int instruction = 0x06000060;
5956 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5957 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5958 checkConstraint(Rm.value() != Rn.value(), "Rm.value() != Rn.value()");
5959 instruction |= ((cond.value() & 0xf) << 28);
5960 instruction |= ((Rd.value() & 0xf) << 12);
5961 instruction |= ((Rn.value() & 0xf) << 16);
5962 instruction |= (Rm.value() & 0xf);
5963 emitInt(instruction);
5964 }
5965
5966 /**
5967 * Pseudo-external assembler syntax: {@code swp{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rm</i>, <i>Rn</i>
5968 * Example disassembly syntax: {@code swpeq r0, r0, [r0]}
5969 * <p>
5970 * Constraint: {@code Rd.value() != 15}<br />
5971 * Constraint: {@code Rm.value() != 15}<br />
5972 * Constraint: {@code Rn.value() != 15}<br />
5973 * Constraint: {@code Rn.value() != Rd.value()}<br />
5974 * Constraint: {@code Rn.value() != Rm.value()}<br />
5975 *
5976 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.51"
5977 */
5978 // Template#: 286, Serial#: 286
5979 public void swp(final ConditionCode cond, final GPR Rd, final GPR Rm, final GPR Rn) {
5980 int instruction = 0x01000090;
5981 checkConstraint(Rd.value() != 15, "Rd.value() != 15");
5982 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
5983 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
5984 checkConstraint(Rn.value() != Rd.value(), "Rn.value() != Rd.value()");
5985 checkConstraint(Rn.value() != Rm.value(), "Rn.value() != Rm.value()");
5986 instruction |= ((cond.value() & 0xf) << 28);
5987 instruction |= ((Rd.value() & 0xf) << 12);
5988 instruction |= (Rm.value() & 0xf);
5989 instruction |= ((Rn.value() & 0xf) << 16);
5990 emitInt(instruction);
5991 }
5992
5993 /**
5994 * Pseudo-external assembler syntax: {@code swpb{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>Rd</i>, <i>Rm</i>, <i>Rn</i>
5995 * Example disassembly syntax: {@code swpbeq r0, r0, [r0]}
5996 * <p>
5997 * Constraint: {@code Rd.value() != 15}<br />
5998 * Constraint: {@code Rm.value() != 15}<br />
5999 * Constraint: {@code Rn.value() != 15}<br />
6000 * Constraint: {@code Rn.value() != Rd.value()}<br />
6001 * Constraint: {@code Rn.value() != Rm.value()}<br />
6002 *
6003 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.52"
6004 */
6005 // Template#: 287, Serial#: 287
6006 public void swpb(final ConditionCode cond, final GPR Rd, final GPR Rm, final GPR Rn) {
6007 int instruction = 0x01400090;
6008 checkConstraint(Rd.value() != 15, "Rd.value() != 15");
6009 checkConstraint(Rm.value() != 15, "Rm.value() != 15");
6010 checkConstraint(Rn.value() != 15, "Rn.value() != 15");
6011 checkConstraint(Rn.value() != Rd.value(), "Rn.value() != Rd.value()");
6012 checkConstraint(Rn.value() != Rm.value(), "Rn.value() != Rm.value()");
6013 instruction |= ((cond.value() & 0xf) << 28);
6014 instruction |= ((Rd.value() & 0xf) << 12);
6015 instruction |= (Rm.value() & 0xf);
6016 instruction |= ((Rn.value() & 0xf) << 16);
6017 emitInt(instruction);
6018 }
6019
6020 /**
6021 * Pseudo-external assembler syntax: {@code bkpt }<i>immediate</i>
6022 * Example disassembly syntax: {@code bkpt 0x0}
6023 * <p>
6024 * Constraint: {@code 0 <= ((immediate >> 4) & 4095) && ((immediate >> 4) & 4095) <= 4095}<br />
6025 * Constraint: {@code 0 <= (immediate & 15) && (immediate & 15) <= 15}<br />
6026 *
6027 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.7"
6028 */
6029 // Template#: 288, Serial#: 288
6030 public void bkpt(final int immediate) {
6031 int instruction = 0xE1200070;
6032 checkConstraint(0 <= ((immediate >> 4) & 4095) && ((immediate >> 4) & 4095) <= 4095, "0 <= ((immediate >> 4) & 4095) && ((immediate >> 4) & 4095) <= 4095");
6033 checkConstraint(0 <= (immediate & 15) && (immediate & 15) <= 15, "0 <= (immediate & 15) && (immediate & 15) <= 15");
6034 instruction |= ((((immediate >> 4) & 4095) & 0xfff) << 8);
6035 instruction |= ((immediate & 15) & 0xf);
6036 emitInt(instruction);
6037 }
6038
6039 /**
6040 * Pseudo-external assembler syntax: {@code swi{eq|ne|cs|hs|cc|lo|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv} }<i>immed_24</i>
6041 * Example disassembly syntax: {@code swieq 0x0}
6042 * <p>
6043 * Constraint: {@code 0 <= immed_24 && immed_24 <= 16777215}<br />
6044 *
6045 * @see "ARM Architecture Reference Manual, Second Edition - Section 4.1.50"
6046 */
6047 // Template#: 289, Serial#: 289
6048 public void swi(final ConditionCode cond, final int immed_24) {
6049 int instruction = 0x0F000000;
6050 checkConstraint(0 <= immed_24 && immed_24 <= 16777215, "0 <= immed_24 && immed_24 <= 16777215");
6051 instruction |= ((cond.value() & 0xf) << 28);
6052 instruction |= (immed_24 & 0xffffff);
6053 emitInt(instruction);
6054 }
6055
6056 // END GENERATED RAW ASSEMBLER METHODS
6057 }