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comparison graal/com.oracle.max.asmdis/src/com/sun/max/asm/gen/cisc/amd64/AMD64ModRMGroup.java @ 3733:e233f5660da4

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Added Java files from Maxine project.
author Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
date Sat, 17 Dec 2011 19:59:18 +0100
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3732:3e2e8b8abdaf 3733:e233f5660da4
1 /*
2 * Copyright (c) 2007, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 */
23 package com.sun.max.asm.gen.cisc.amd64;
24
25 import static com.sun.max.asm.amd64.AMD64GeneralRegister16.*;
26 import static com.sun.max.asm.amd64.AMD64GeneralRegister32.*;
27 import static com.sun.max.asm.amd64.AMD64GeneralRegister64.*;
28 import static com.sun.max.asm.amd64.AMD64GeneralRegister8.*;
29 import static com.sun.max.asm.gen.cisc.x86.AddressingMethodCode.*;
30 import static com.sun.max.asm.gen.cisc.x86.FloatingPointOperandCode.*;
31 import static com.sun.max.asm.gen.cisc.x86.ModRMGroup.Opcode.*;
32 import static com.sun.max.asm.gen.cisc.x86.OperandCode.*;
33 import static com.sun.max.asm.gen.cisc.x86.OperandTypeCode.*;
34
35 import java.util.*;
36
37 import com.sun.max.asm.amd64.*;
38 import com.sun.max.asm.gen.*;
39 import com.sun.max.asm.gen.cisc.x86.*;
40
41 /**
42 * See A-7 in the book.
43 *
44 * @see com.sun.max.asm.x86
45 */
46 public enum AMD64ModRMGroup implements ModRMGroup {
47
48 GROUP_1(
49 modRM(ModRMGroup.Opcode.OPCODE_0, "ADD"),
50 modRM(OPCODE_1, "OR"),
51 modRM(OPCODE_2, "ADC"),
52 modRM(OPCODE_3, "SBB"),
53 modRM(OPCODE_4, "AND"),
54 modRM(OPCODE_5, "SUB"),
55 modRM(OPCODE_6, "XOR"),
56 modRM(OPCODE_7, "CMP")
57 ),
58 GROUP_2(
59 modRM(OPCODE_0, "ROL"),
60 modRM(OPCODE_1, "ROR"),
61 modRM(OPCODE_2, "RCL"),
62 modRM(OPCODE_3, "RCR"),
63 modRM(OPCODE_4, "SHL"),
64 modRM(OPCODE_5, "SHR"),
65 modRM(OPCODE_6, "SHL"),
66 modRM(OPCODE_7, "SAR")
67 ),
68 GROUP_3b(
69 modRM(OPCODE_0, "TEST", Eb.excludeExternalTestArguments(AL), Ib),
70 modRM(OPCODE_1, "TEST", Eb.excludeExternalTestArguments(AL), Ib),
71 modRM(OPCODE_2, "NOT", Eb),
72 modRM(OPCODE_3, "NEG", Eb),
73 modRM(OPCODE_4, "MUL", Eb, new ExternalOmission(AL)),
74 modRM(OPCODE_5, "IMUL", Eb, new ExternalOmission(AL)),
75 modRM(OPCODE_6, "DIV", Eb, new ExternalOmission(AL)),
76 modRM(OPCODE_7, "IDIV", Eb, new ExternalOmission(AL))
77 ),
78 GROUP_3v(
79 modRM(OPCODE_0, "TEST", Ev.excludeExternalTestArguments(AX, EAX, RAX), Iz.externalRange(0, Integer.MAX_VALUE)),
80 modRM(OPCODE_1, "TEST", Ev.excludeExternalTestArguments(AX, EAX, RAX), Iz.externalRange(0, Integer.MAX_VALUE)),
81 modRM(OPCODE_2, "NOT", Ev),
82 modRM(OPCODE_3, "NEG", Ev),
83 modRM(OPCODE_4, "MUL", Ev),
84 modRM(OPCODE_5, "IMUL", Ev),
85 modRM(OPCODE_6, "DIV", Ev),
86 modRM(OPCODE_7, "IDIV", Ev)
87 ),
88 GROUP_4(
89 modRM(OPCODE_0, "INC"),
90 modRM(OPCODE_1, "DEC")
91 ),
92 GROUP_5a(
93 modRM(OPCODE_0, "INC", v, Ev),
94 modRM(OPCODE_1, "DEC", v, Ev)
95 // modRM(_3, "CALL", Mp), // legacy mode instruction
96 // modRM(_5, "JMP", Mp) // legacy mode instruction
97 ),
98 GROUP_5b(
99 modRM(OPCODE_2, "CALL", Ev),
100 modRM(OPCODE_4, "JMP", Ev),
101 modRM(OPCODE_6, "PUSH", Ev.excludeExternalTestArguments(AMD64GeneralRegister16.ENUMERATOR, AMD64GeneralRegister32.ENUMERATOR, AMD64GeneralRegister64.ENUMERATOR))
102 ),
103 GROUP_6a(
104 modRM(OPCODE_0, "SLDT", Mw),
105 modRM(OPCODE_1, "STR", Mw),
106 modRM(OPCODE_2, "LLDT", Ew),
107 modRM(OPCODE_3, "LTR", Ew),
108 modRM(OPCODE_4, "VERR", Ew),
109 modRM(OPCODE_5, "VERW", Ew)
110 ),
111 GROUP_6b(
112 modRM(OPCODE_0, "SLDT", Rv),
113 modRM(OPCODE_1, "STR", Rv)
114 ),
115 GROUP_7a(
116 modRM(OPCODE_0, "SGDT", Ms),
117 modRM(OPCODE_1, "SIDT", Ms),
118 modRM(OPCODE_2, "LGDT", Ms),
119 modRM(OPCODE_3, "LIDT", Ms),
120 modRM(OPCODE_4, "SMSW", Mw),
121 modRM(OPCODE_6, "LMSW", Ew),
122 modRM(OPCODE_7, "INVLPG", M)
123 ),
124 GROUP_7b(
125 modRM(OPCODE_4, "SMSW", Rv),
126 modRM(OPCODE_7, "SWAPGS", X86TemplateContext.ModCase.MOD_3) // r/m field == 0
127 // modRM(_7, "RDTSCP", X86TemplateContext.ModCase.MOD_3) // r/m field == 1
128 ),
129 GROUP_8(
130 modRM(OPCODE_4, "BT"),
131 modRM(OPCODE_5, "BTS"),
132 modRM(OPCODE_6, "BTR"),
133 modRM(OPCODE_7, "BTC")
134 ),
135 GROUP_9a(
136 modRM(OPCODE_1, "CMPXCHG8B", Mq)
137 ),
138 GROUP_9b(
139 modRM(OPCODE_1, "CMPXCHG16B", Mdq)
140 ),
141 GROUP_10(
142 ),
143 GROUP_11(
144 modRM(OPCODE_0, "MOV", Eb, Ib),
145 modRM(OPCODE_1, "MOV", Ev, Iz)
146 ),
147 GROUP_12a(
148 modRM(OPCODE_2, "PSRLW", PRq, Ib),
149 modRM(OPCODE_4, "PSRAW", PRq, Ib),
150 modRM(OPCODE_6, "PSLLW", PRq, Ib)
151 ),
152 GROUP_12b(
153 modRM(OPCODE_2, "PSRLW", VRdq, Ib),
154 modRM(OPCODE_4, "PSRAW", VRdq, Ib),
155 modRM(OPCODE_6, "PSLLW", VRdq, Ib)
156 ),
157 GROUP_13a(
158 modRM(OPCODE_2, "PSRLD", PRq, Ib),
159 modRM(OPCODE_4, "PSRAD", PRq, Ib),
160 modRM(OPCODE_6, "PSLLD", PRq, Ib)
161 ),
162 GROUP_13b(
163 modRM(OPCODE_2, "PSRLD", VRdq, Ib),
164 modRM(OPCODE_4, "PSRAD", VRdq, Ib),
165 modRM(OPCODE_6, "PSLLD", VRdq, Ib)
166 ),
167 GROUP_14a(
168 modRM(OPCODE_2, "PSRLQ", PRq, Ib),
169 modRM(OPCODE_6, "PSLLQ", PRq, Ib)
170 ),
171 GROUP_14b(
172 modRM(OPCODE_2, "PSRLQ", VRdq, Ib),
173 modRM(OPCODE_3, "PSRLDQ", VRdq, Ib),
174 modRM(OPCODE_6, "PSLLQ", VRdq, Ib),
175 modRM(OPCODE_7, "PSLLDQ", VRdq, Ib)
176 ),
177 GROUP_15a(
178 modRM(OPCODE_0, "FXSAVE", M),
179 modRM(OPCODE_1, "FXRSTOR", M),
180 modRM(OPCODE_2, "LDMXCSR", Md),
181 modRM(OPCODE_3, "STMXCSR", Md),
182 modRM(OPCODE_7, "CLFLUSH", Mb)
183 ),
184 GROUP_15b(
185 modRM(OPCODE_5, "LFENCE"),
186 modRM(OPCODE_6, "MFENCE"),
187 modRM(OPCODE_7, "SFENCE")
188 ),
189 GROUP_16(
190 modRM(OPCODE_0, "PREFETCHNTA"),
191 modRM(OPCODE_1, "PREFETCHT0"),
192 modRM(OPCODE_2, "PREFETCHT1"),
193 modRM(OPCODE_3, "PREFETCHT2")
194 ),
195 GROUP_P(
196 modRM(OPCODE_0, "PREFETCH"),
197 modRM(OPCODE_1, "PREFETCHW"),
198 modRM(OPCODE_3, "PREFETCH")
199 ),
200 FP_D8(
201 modRM(OPCODE_0, "FADD", single_real),
202 modRM(OPCODE_1, "FMUL", single_real),
203 modRM(OPCODE_2, "FCOM", single_real),
204 modRM(OPCODE_3, "FCOMP", single_real),
205 modRM(OPCODE_4, "FSUB", single_real),
206 modRM(OPCODE_5, "FSUBR", single_real),
207 modRM(OPCODE_6, "FDIV", single_real),
208 modRM(OPCODE_7, "FDIVR", single_real)
209 ),
210 FP_D9(
211 modRM(OPCODE_0, "FLD", single_real),
212 modRM(OPCODE_2, "FST", single_real),
213 modRM(OPCODE_3, "FSTP", single_real),
214 modRM(OPCODE_4, "FLDENV", bytes_14_28),
215 modRM(OPCODE_5, "FLDCW", bytes_2),
216 modRM(OPCODE_6, "FSTENV", bytes_14_28),
217 modRM(OPCODE_7, "FSTCW", bytes_2)
218 ),
219 FP_DA(
220 modRM(OPCODE_0, "FIADD", short_integer),
221 modRM(OPCODE_1, "FIMUL", short_integer),
222 modRM(OPCODE_2, "FICOM", short_integer),
223 modRM(OPCODE_3, "FICOMP", short_integer),
224 modRM(OPCODE_4, "FISUB", short_integer),
225 modRM(OPCODE_5, "FISUBR", short_integer),
226 modRM(OPCODE_6, "FIDIV", short_integer),
227 modRM(OPCODE_7, "FIDIVR", short_integer)
228 ),
229 FP_DB(
230 modRM(OPCODE_0, "FILD", short_integer),
231 modRM(OPCODE_2, "FIST", short_integer),
232 modRM(OPCODE_3, "FISTP", short_integer),
233 modRM(OPCODE_5, "FLD", extended_real),
234 modRM(OPCODE_7, "FSTP", extended_real)
235 ),
236 FP_DC(
237 modRM(OPCODE_0, "FADD", double_real),
238 modRM(OPCODE_1, "FMUL", double_real),
239 modRM(OPCODE_2, "FCOM", double_real),
240 modRM(OPCODE_3, "FCOMP", double_real),
241 modRM(OPCODE_4, "FSUB", double_real),
242 modRM(OPCODE_5, "FSUBR", double_real),
243 modRM(OPCODE_6, "FDIV", double_real),
244 modRM(OPCODE_7, "FDIVR", double_real)
245 ),
246 FP_DD(
247 modRM(OPCODE_0, "FLD", double_real),
248 modRM(OPCODE_2, "FST", double_real),
249 modRM(OPCODE_3, "FSTP", double_real),
250 modRM(OPCODE_4, "FRSTOR", bytes_98_108),
251 modRM(OPCODE_6, "FSAVE", bytes_98_108),
252 modRM(OPCODE_7, "FSTSW", bytes_2)
253 ),
254 FP_DE(
255 modRM(OPCODE_0, "FIADD", word_integer),
256 modRM(OPCODE_1, "FIMUL", word_integer),
257 modRM(OPCODE_2, "FICOM", word_integer),
258 modRM(OPCODE_3, "FICOMP", word_integer),
259 modRM(OPCODE_4, "FISUB", word_integer),
260 modRM(OPCODE_5, "FISUBR", word_integer),
261 modRM(OPCODE_6, "FIDIV", word_integer),
262 modRM(OPCODE_7, "FIDIVR", word_integer)
263 ),
264 FP_DF(
265 modRM(OPCODE_0, "FILD", word_integer),
266 modRM(OPCODE_2, "FIST", word_integer),
267 modRM(OPCODE_3, "FISTP", word_integer),
268 modRM(OPCODE_4, "FBLD", packed_bcd),
269 modRM(OPCODE_5, "FILD", long_integer),
270 modRM(OPCODE_6, "FBSTP", packed_bcd),
271 modRM(OPCODE_7, "FISTP", long_integer)
272 );
273
274 private static ModRMDescription modRM(ModRMGroup.Opcode opcode, String name, Object... specifications) {
275 return new ModRMDescription(opcode, name, Arrays.asList(specifications));
276 }
277
278 private final ModRMDescription[] instructionDescriptions;
279
280 private AMD64ModRMGroup(ModRMDescription... instructionDescriptions) {
281 this.instructionDescriptions = instructionDescriptions;
282 }
283
284 public ModRMDescription getInstructionDescription(ModRMGroup.Opcode opcode) {
285 for (ModRMDescription instructionDescription : instructionDescriptions) {
286 if (instructionDescription.opcode() == opcode) {
287 return instructionDescription;
288 }
289 }
290 return null;
291 }
292 }