Mercurial > hg > truffle
comparison graal/com.oracle.max.asmdis/src/com/sun/max/asm/ppc/complete/PPCRawAssembler.java @ 3733:e233f5660da4
Added Java files from Maxine project.
author | Thomas Wuerthinger <thomas.wuerthinger@oracle.com> |
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date | Sat, 17 Dec 2011 19:59:18 +0100 |
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3732:3e2e8b8abdaf | 3733:e233f5660da4 |
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1 /* | |
2 * Copyright (c) 2007, 2011, Oracle and/or its affiliates. All rights reserved. | |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA | |
20 * or visit www.oracle.com if you need additional information or have any | |
21 * questions. | |
22 */ | |
23 | |
24 package com.sun.max.asm.ppc.complete; | |
25 | |
26 import static com.sun.max.asm.ppc.GPR.*; | |
27 | |
28 import com.sun.max.asm.ppc.*; | |
29 | |
30 public abstract class PPCRawAssembler extends AbstractPPCAssembler { | |
31 | |
32 // START GENERATED RAW ASSEMBLER METHODS | |
33 /** | |
34 * Pseudo-external assembler syntax: {@code b }<i>li</i> | |
35 * Example disassembly syntax: {@code b L1: -33554432} | |
36 * <p> | |
37 * Constraint: {@code (-33554432 <= li && li <= 33554428) && ((li % 4) == 0)}<br /> | |
38 * | |
39 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.1 [Book 1]" | |
40 */ | |
41 // Template#: 1, Serial#: 1 | |
42 public void b(final int li) { | |
43 int instruction = 0x48000000; | |
44 checkConstraint((-33554432 <= li && li <= 33554428) && ((li % 4) == 0), "(-33554432 <= li && li <= 33554428) && ((li % 4) == 0)"); | |
45 instruction |= (((li >> 2) & 0xffffff) << 2); | |
46 emitInt(instruction); | |
47 } | |
48 | |
49 /** | |
50 * Pseudo-external assembler syntax: {@code ba }<i>li</i> | |
51 * Example disassembly syntax: {@code ba L1: -33554432} | |
52 * <p> | |
53 * Constraint: {@code (-33554432 <= li && li <= 33554428) && ((li % 4) == 0)}<br /> | |
54 * | |
55 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.1 [Book 1]" | |
56 */ | |
57 // Template#: 2, Serial#: 2 | |
58 public void ba(final int li) { | |
59 int instruction = 0x48000002; | |
60 checkConstraint((-33554432 <= li && li <= 33554428) && ((li % 4) == 0), "(-33554432 <= li && li <= 33554428) && ((li % 4) == 0)"); | |
61 instruction |= (((li >> 2) & 0xffffff) << 2); | |
62 emitInt(instruction); | |
63 } | |
64 | |
65 /** | |
66 * Pseudo-external assembler syntax: {@code bl }<i>li</i> | |
67 * Example disassembly syntax: {@code bl L1: -33554432} | |
68 * <p> | |
69 * Constraint: {@code (-33554432 <= li && li <= 33554428) && ((li % 4) == 0)}<br /> | |
70 * | |
71 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.1 [Book 1]" | |
72 */ | |
73 // Template#: 3, Serial#: 3 | |
74 public void bl(final int li) { | |
75 int instruction = 0x48000001; | |
76 checkConstraint((-33554432 <= li && li <= 33554428) && ((li % 4) == 0), "(-33554432 <= li && li <= 33554428) && ((li % 4) == 0)"); | |
77 instruction |= (((li >> 2) & 0xffffff) << 2); | |
78 emitInt(instruction); | |
79 } | |
80 | |
81 /** | |
82 * Pseudo-external assembler syntax: {@code bla }<i>li</i> | |
83 * Example disassembly syntax: {@code bla L1: -33554432} | |
84 * <p> | |
85 * Constraint: {@code (-33554432 <= li && li <= 33554428) && ((li % 4) == 0)}<br /> | |
86 * | |
87 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.1 [Book 1]" | |
88 */ | |
89 // Template#: 4, Serial#: 4 | |
90 public void bla(final int li) { | |
91 int instruction = 0x48000003; | |
92 checkConstraint((-33554432 <= li && li <= 33554428) && ((li % 4) == 0), "(-33554432 <= li && li <= 33554428) && ((li % 4) == 0)"); | |
93 instruction |= (((li >> 2) & 0xffffff) << 2); | |
94 emitInt(instruction); | |
95 } | |
96 | |
97 /** | |
98 * Pseudo-external assembler syntax: {@code bc }<i>bo</i>, <i>bi</i>, <i>bd</i> | |
99 * Example disassembly syntax: {@code bc 0, 0x0, L1: -32768} | |
100 * <p> | |
101 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
102 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
103 * | |
104 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.1 [Book 1]" | |
105 */ | |
106 // Template#: 5, Serial#: 5 | |
107 public void bc(final BOOperand bo, final int bi, final int bd) { | |
108 int instruction = 0x40000000; | |
109 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
110 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
111 instruction |= ((bo.value() & 0x1f) << 21); | |
112 instruction |= ((bi & 0x1f) << 16); | |
113 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
114 emitInt(instruction); | |
115 } | |
116 | |
117 /** | |
118 * Pseudo-external assembler syntax: {@code bca }<i>bo</i>, <i>bi</i>, <i>bd</i> | |
119 * Example disassembly syntax: {@code bca 0, 0x0, L1: -32768} | |
120 * <p> | |
121 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
122 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
123 * | |
124 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.1 [Book 1]" | |
125 */ | |
126 // Template#: 6, Serial#: 6 | |
127 public void bca(final BOOperand bo, final int bi, final int bd) { | |
128 int instruction = 0x40000002; | |
129 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
130 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
131 instruction |= ((bo.value() & 0x1f) << 21); | |
132 instruction |= ((bi & 0x1f) << 16); | |
133 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
134 emitInt(instruction); | |
135 } | |
136 | |
137 /** | |
138 * Pseudo-external assembler syntax: {@code bcl }<i>bo</i>, <i>bi</i>, <i>bd</i> | |
139 * Example disassembly syntax: {@code bcl 0, 0x0, L1: -32768} | |
140 * <p> | |
141 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
142 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
143 * | |
144 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.1 [Book 1]" | |
145 */ | |
146 // Template#: 7, Serial#: 7 | |
147 public void bcl(final BOOperand bo, final int bi, final int bd) { | |
148 int instruction = 0x40000001; | |
149 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
150 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
151 instruction |= ((bo.value() & 0x1f) << 21); | |
152 instruction |= ((bi & 0x1f) << 16); | |
153 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
154 emitInt(instruction); | |
155 } | |
156 | |
157 /** | |
158 * Pseudo-external assembler syntax: {@code bcla }<i>bo</i>, <i>bi</i>, <i>bd</i> | |
159 * Example disassembly syntax: {@code bcla 0, 0x0, L1: -32768} | |
160 * <p> | |
161 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
162 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
163 * | |
164 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.1 [Book 1]" | |
165 */ | |
166 // Template#: 8, Serial#: 8 | |
167 public void bcla(final BOOperand bo, final int bi, final int bd) { | |
168 int instruction = 0x40000003; | |
169 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
170 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
171 instruction |= ((bo.value() & 0x1f) << 21); | |
172 instruction |= ((bi & 0x1f) << 16); | |
173 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
174 emitInt(instruction); | |
175 } | |
176 | |
177 /** | |
178 * Pseudo-external assembler syntax: {@code bclr }<i>bo</i>, <i>bi</i>, <i>bh</i> | |
179 * Example disassembly syntax: {@code bclr 0, 0x0, 0x0} | |
180 * <p> | |
181 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
182 * Constraint: {@code 0 <= bh && bh <= 3}<br /> | |
183 * Constraint: {@code bh != 2}<br /> | |
184 * | |
185 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.1 [Book 1]" | |
186 */ | |
187 // Template#: 9, Serial#: 9 | |
188 public void bclr(final BOOperand bo, final int bi, final int bh) { | |
189 int instruction = 0x4C000020; | |
190 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
191 checkConstraint(0 <= bh && bh <= 3, "0 <= bh && bh <= 3"); | |
192 checkConstraint(bh != 2, "bh != 2"); | |
193 instruction |= ((bo.value() & 0x1f) << 21); | |
194 instruction |= ((bi & 0x1f) << 16); | |
195 instruction |= ((bh & 0x3) << 11); | |
196 emitInt(instruction); | |
197 } | |
198 | |
199 /** | |
200 * Pseudo-external assembler syntax: {@code bclrl }<i>bo</i>, <i>bi</i>, <i>bh</i> | |
201 * Example disassembly syntax: {@code bclrl 0, 0x0, 0x0} | |
202 * <p> | |
203 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
204 * Constraint: {@code 0 <= bh && bh <= 3}<br /> | |
205 * Constraint: {@code bh != 2}<br /> | |
206 * | |
207 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.1 [Book 1]" | |
208 */ | |
209 // Template#: 10, Serial#: 10 | |
210 public void bclrl(final BOOperand bo, final int bi, final int bh) { | |
211 int instruction = 0x4C000021; | |
212 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
213 checkConstraint(0 <= bh && bh <= 3, "0 <= bh && bh <= 3"); | |
214 checkConstraint(bh != 2, "bh != 2"); | |
215 instruction |= ((bo.value() & 0x1f) << 21); | |
216 instruction |= ((bi & 0x1f) << 16); | |
217 instruction |= ((bh & 0x3) << 11); | |
218 emitInt(instruction); | |
219 } | |
220 | |
221 /** | |
222 * Pseudo-external assembler syntax: {@code bcctr }<i>bo</i>, <i>bi</i>, <i>bh</i> | |
223 * Example disassembly syntax: {@code bcctr 0, 0x0, 0x0} | |
224 * <p> | |
225 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
226 * Constraint: {@code 0 <= bh && bh <= 3}<br /> | |
227 * Constraint: {@code bh != 2}<br /> | |
228 * | |
229 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.1 [Book 1]" | |
230 */ | |
231 // Template#: 11, Serial#: 11 | |
232 public void bcctr(final BOOperand bo, final int bi, final int bh) { | |
233 int instruction = 0x4C000420; | |
234 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
235 checkConstraint(0 <= bh && bh <= 3, "0 <= bh && bh <= 3"); | |
236 checkConstraint(bh != 2, "bh != 2"); | |
237 instruction |= ((bo.value() & 0x1f) << 21); | |
238 instruction |= ((bi & 0x1f) << 16); | |
239 instruction |= ((bh & 0x3) << 11); | |
240 emitInt(instruction); | |
241 } | |
242 | |
243 /** | |
244 * Pseudo-external assembler syntax: {@code bcctrl }<i>bo</i>, <i>bi</i>, <i>bh</i> | |
245 * Example disassembly syntax: {@code bcctrl 0, 0x0, 0x0} | |
246 * <p> | |
247 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
248 * Constraint: {@code 0 <= bh && bh <= 3}<br /> | |
249 * Constraint: {@code bh != 2}<br /> | |
250 * | |
251 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.1 [Book 1]" | |
252 */ | |
253 // Template#: 12, Serial#: 12 | |
254 public void bcctrl(final BOOperand bo, final int bi, final int bh) { | |
255 int instruction = 0x4C000421; | |
256 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
257 checkConstraint(0 <= bh && bh <= 3, "0 <= bh && bh <= 3"); | |
258 checkConstraint(bh != 2, "bh != 2"); | |
259 instruction |= ((bo.value() & 0x1f) << 21); | |
260 instruction |= ((bi & 0x1f) << 16); | |
261 instruction |= ((bh & 0x3) << 11); | |
262 emitInt(instruction); | |
263 } | |
264 | |
265 /** | |
266 * Pseudo-external assembler syntax: {@code crand }<i>bt</i>, <i>ba</i>, <i>bb</i> | |
267 * Example disassembly syntax: {@code crand 0x0, 0x0, 0x0} | |
268 * <p> | |
269 * Constraint: {@code 0 <= bt && bt <= 31}<br /> | |
270 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
271 * Constraint: {@code 0 <= bb && bb <= 31}<br /> | |
272 * | |
273 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.3 [Book 1]" | |
274 */ | |
275 // Template#: 13, Serial#: 13 | |
276 public void crand(final int bt, final int ba, final int bb) { | |
277 int instruction = 0x4C000202; | |
278 checkConstraint(0 <= bt && bt <= 31, "0 <= bt && bt <= 31"); | |
279 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
280 checkConstraint(0 <= bb && bb <= 31, "0 <= bb && bb <= 31"); | |
281 instruction |= ((bt & 0x1f) << 21); | |
282 instruction |= ((ba & 0x1f) << 16); | |
283 instruction |= ((bb & 0x1f) << 11); | |
284 emitInt(instruction); | |
285 } | |
286 | |
287 /** | |
288 * Pseudo-external assembler syntax: {@code crxor }<i>bt</i>, <i>ba</i>, <i>bb</i> | |
289 * Example disassembly syntax: {@code crxor 0x0, 0x0, 0x0} | |
290 * <p> | |
291 * Constraint: {@code 0 <= bt && bt <= 31}<br /> | |
292 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
293 * Constraint: {@code 0 <= bb && bb <= 31}<br /> | |
294 * | |
295 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.3 [Book 1]" | |
296 */ | |
297 // Template#: 14, Serial#: 14 | |
298 public void crxor(final int bt, final int ba, final int bb) { | |
299 int instruction = 0x4C000182; | |
300 checkConstraint(0 <= bt && bt <= 31, "0 <= bt && bt <= 31"); | |
301 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
302 checkConstraint(0 <= bb && bb <= 31, "0 <= bb && bb <= 31"); | |
303 instruction |= ((bt & 0x1f) << 21); | |
304 instruction |= ((ba & 0x1f) << 16); | |
305 instruction |= ((bb & 0x1f) << 11); | |
306 emitInt(instruction); | |
307 } | |
308 | |
309 /** | |
310 * Pseudo-external assembler syntax: {@code cror }<i>bt</i>, <i>ba</i>, <i>bb</i> | |
311 * Example disassembly syntax: {@code cror 0x0, 0x0, 0x0} | |
312 * <p> | |
313 * Constraint: {@code 0 <= bt && bt <= 31}<br /> | |
314 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
315 * Constraint: {@code 0 <= bb && bb <= 31}<br /> | |
316 * | |
317 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.3 [Book 1]" | |
318 */ | |
319 // Template#: 15, Serial#: 15 | |
320 public void cror(final int bt, final int ba, final int bb) { | |
321 int instruction = 0x4C000382; | |
322 checkConstraint(0 <= bt && bt <= 31, "0 <= bt && bt <= 31"); | |
323 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
324 checkConstraint(0 <= bb && bb <= 31, "0 <= bb && bb <= 31"); | |
325 instruction |= ((bt & 0x1f) << 21); | |
326 instruction |= ((ba & 0x1f) << 16); | |
327 instruction |= ((bb & 0x1f) << 11); | |
328 emitInt(instruction); | |
329 } | |
330 | |
331 /** | |
332 * Pseudo-external assembler syntax: {@code crnand }<i>bt</i>, <i>ba</i>, <i>bb</i> | |
333 * Example disassembly syntax: {@code crnand 0x0, 0x0, 0x0} | |
334 * <p> | |
335 * Constraint: {@code 0 <= bt && bt <= 31}<br /> | |
336 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
337 * Constraint: {@code 0 <= bb && bb <= 31}<br /> | |
338 * | |
339 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.3 [Book 1]" | |
340 */ | |
341 // Template#: 16, Serial#: 16 | |
342 public void crnand(final int bt, final int ba, final int bb) { | |
343 int instruction = 0x4C0001C2; | |
344 checkConstraint(0 <= bt && bt <= 31, "0 <= bt && bt <= 31"); | |
345 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
346 checkConstraint(0 <= bb && bb <= 31, "0 <= bb && bb <= 31"); | |
347 instruction |= ((bt & 0x1f) << 21); | |
348 instruction |= ((ba & 0x1f) << 16); | |
349 instruction |= ((bb & 0x1f) << 11); | |
350 emitInt(instruction); | |
351 } | |
352 | |
353 /** | |
354 * Pseudo-external assembler syntax: {@code crnor }<i>bt</i>, <i>ba</i>, <i>bb</i> | |
355 * Example disassembly syntax: {@code crnor 0x0, 0x0, 0x0} | |
356 * <p> | |
357 * Constraint: {@code 0 <= bt && bt <= 31}<br /> | |
358 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
359 * Constraint: {@code 0 <= bb && bb <= 31}<br /> | |
360 * | |
361 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.3 [Book 1]" | |
362 */ | |
363 // Template#: 17, Serial#: 17 | |
364 public void crnor(final int bt, final int ba, final int bb) { | |
365 int instruction = 0x4C000042; | |
366 checkConstraint(0 <= bt && bt <= 31, "0 <= bt && bt <= 31"); | |
367 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
368 checkConstraint(0 <= bb && bb <= 31, "0 <= bb && bb <= 31"); | |
369 instruction |= ((bt & 0x1f) << 21); | |
370 instruction |= ((ba & 0x1f) << 16); | |
371 instruction |= ((bb & 0x1f) << 11); | |
372 emitInt(instruction); | |
373 } | |
374 | |
375 /** | |
376 * Pseudo-external assembler syntax: {@code creqv }<i>bt</i>, <i>ba</i>, <i>bb</i> | |
377 * Example disassembly syntax: {@code creqv 0x0, 0x0, 0x0} | |
378 * <p> | |
379 * Constraint: {@code 0 <= bt && bt <= 31}<br /> | |
380 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
381 * Constraint: {@code 0 <= bb && bb <= 31}<br /> | |
382 * | |
383 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.3 [Book 1]" | |
384 */ | |
385 // Template#: 18, Serial#: 18 | |
386 public void creqv(final int bt, final int ba, final int bb) { | |
387 int instruction = 0x4C000242; | |
388 checkConstraint(0 <= bt && bt <= 31, "0 <= bt && bt <= 31"); | |
389 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
390 checkConstraint(0 <= bb && bb <= 31, "0 <= bb && bb <= 31"); | |
391 instruction |= ((bt & 0x1f) << 21); | |
392 instruction |= ((ba & 0x1f) << 16); | |
393 instruction |= ((bb & 0x1f) << 11); | |
394 emitInt(instruction); | |
395 } | |
396 | |
397 /** | |
398 * Pseudo-external assembler syntax: {@code crandc }<i>bt</i>, <i>ba</i>, <i>bb</i> | |
399 * Example disassembly syntax: {@code crandc 0x0, 0x0, 0x0} | |
400 * <p> | |
401 * Constraint: {@code 0 <= bt && bt <= 31}<br /> | |
402 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
403 * Constraint: {@code 0 <= bb && bb <= 31}<br /> | |
404 * | |
405 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.3 [Book 1]" | |
406 */ | |
407 // Template#: 19, Serial#: 19 | |
408 public void crandc(final int bt, final int ba, final int bb) { | |
409 int instruction = 0x4C000102; | |
410 checkConstraint(0 <= bt && bt <= 31, "0 <= bt && bt <= 31"); | |
411 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
412 checkConstraint(0 <= bb && bb <= 31, "0 <= bb && bb <= 31"); | |
413 instruction |= ((bt & 0x1f) << 21); | |
414 instruction |= ((ba & 0x1f) << 16); | |
415 instruction |= ((bb & 0x1f) << 11); | |
416 emitInt(instruction); | |
417 } | |
418 | |
419 /** | |
420 * Pseudo-external assembler syntax: {@code crorc }<i>bt</i>, <i>ba</i>, <i>bb</i> | |
421 * Example disassembly syntax: {@code crorc 0x0, 0x0, 0x0} | |
422 * <p> | |
423 * Constraint: {@code 0 <= bt && bt <= 31}<br /> | |
424 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
425 * Constraint: {@code 0 <= bb && bb <= 31}<br /> | |
426 * | |
427 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.3 [Book 1]" | |
428 */ | |
429 // Template#: 20, Serial#: 20 | |
430 public void crorc(final int bt, final int ba, final int bb) { | |
431 int instruction = 0x4C000342; | |
432 checkConstraint(0 <= bt && bt <= 31, "0 <= bt && bt <= 31"); | |
433 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
434 checkConstraint(0 <= bb && bb <= 31, "0 <= bb && bb <= 31"); | |
435 instruction |= ((bt & 0x1f) << 21); | |
436 instruction |= ((ba & 0x1f) << 16); | |
437 instruction |= ((bb & 0x1f) << 11); | |
438 emitInt(instruction); | |
439 } | |
440 | |
441 /** | |
442 * Pseudo-external assembler syntax: {@code mcrf }<i>bf</i>, <i>bfa</i> | |
443 * Example disassembly syntax: {@code mcrf 0, 0} | |
444 * | |
445 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 2.4.4 [Book 1]" | |
446 */ | |
447 // Template#: 21, Serial#: 21 | |
448 public void mcrf(final CRF bf, final CRF bfa) { | |
449 int instruction = 0x4C000000; | |
450 instruction |= ((bf.value() & 0x7) << 23); | |
451 instruction |= ((bfa.value() & 0x7) << 18); | |
452 emitInt(instruction); | |
453 } | |
454 | |
455 /** | |
456 * Pseudo-external assembler syntax: {@code lbz }<i>rt</i>, <i>d</i>, <i>ra</i> | |
457 * Example disassembly syntax: {@code lbz r0, -32768(0)} | |
458 * <p> | |
459 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
460 * Constraint: {@code ra != R0}<br /> | |
461 * | |
462 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
463 */ | |
464 // Template#: 22, Serial#: 22 | |
465 public void lbz(final GPR rt, final int d, final ZeroOrRegister ra) { | |
466 int instruction = 0x88000000; | |
467 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
468 checkConstraint(ra != R0, "ra != R0"); | |
469 instruction |= ((rt.value() & 0x1f) << 21); | |
470 instruction |= (d & 0xffff); | |
471 instruction |= ((ra.value() & 0x1f) << 16); | |
472 emitInt(instruction); | |
473 } | |
474 | |
475 /** | |
476 * Pseudo-external assembler syntax: {@code lbzu }<i>rt</i>, <i>d</i>, <i>ra</i> | |
477 * Example disassembly syntax: {@code lbzu r0, -32768(r0)} | |
478 * <p> | |
479 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
480 * Constraint: {@code ra != R0}<br /> | |
481 * Constraint: {@code ra.value() != rt.value()}<br /> | |
482 * | |
483 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
484 */ | |
485 // Template#: 23, Serial#: 23 | |
486 public void lbzu(final GPR rt, final int d, final GPR ra) { | |
487 int instruction = 0x8C000000; | |
488 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
489 checkConstraint(ra != R0, "ra != R0"); | |
490 checkConstraint(ra.value() != rt.value(), "ra.value() != rt.value()"); | |
491 instruction |= ((rt.value() & 0x1f) << 21); | |
492 instruction |= (d & 0xffff); | |
493 instruction |= ((ra.value() & 0x1f) << 16); | |
494 emitInt(instruction); | |
495 } | |
496 | |
497 /** | |
498 * Pseudo-external assembler syntax: {@code lbzx }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
499 * Example disassembly syntax: {@code lbzx r0, 0, r0} | |
500 * <p> | |
501 * Constraint: {@code ra != R0}<br /> | |
502 * | |
503 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
504 */ | |
505 // Template#: 24, Serial#: 24 | |
506 public void lbzx(final GPR rt, final ZeroOrRegister ra, final GPR rb) { | |
507 int instruction = 0x7C0000AE; | |
508 checkConstraint(ra != R0, "ra != R0"); | |
509 instruction |= ((rt.value() & 0x1f) << 21); | |
510 instruction |= ((ra.value() & 0x1f) << 16); | |
511 instruction |= ((rb.value() & 0x1f) << 11); | |
512 emitInt(instruction); | |
513 } | |
514 | |
515 /** | |
516 * Pseudo-external assembler syntax: {@code lbzux }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
517 * Example disassembly syntax: {@code lbzux r0, r0, r0} | |
518 * <p> | |
519 * Constraint: {@code ra != R0}<br /> | |
520 * Constraint: {@code ra.value() != rt.value()}<br /> | |
521 * | |
522 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
523 */ | |
524 // Template#: 25, Serial#: 25 | |
525 public void lbzux(final GPR rt, final GPR ra, final GPR rb) { | |
526 int instruction = 0x7C0000EE; | |
527 checkConstraint(ra != R0, "ra != R0"); | |
528 checkConstraint(ra.value() != rt.value(), "ra.value() != rt.value()"); | |
529 instruction |= ((rt.value() & 0x1f) << 21); | |
530 instruction |= ((ra.value() & 0x1f) << 16); | |
531 instruction |= ((rb.value() & 0x1f) << 11); | |
532 emitInt(instruction); | |
533 } | |
534 | |
535 /** | |
536 * Pseudo-external assembler syntax: {@code lhz }<i>rt</i>, <i>d</i>, <i>ra</i> | |
537 * Example disassembly syntax: {@code lhz r0, -32768(0)} | |
538 * <p> | |
539 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
540 * Constraint: {@code ra != R0}<br /> | |
541 * | |
542 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
543 */ | |
544 // Template#: 26, Serial#: 26 | |
545 public void lhz(final GPR rt, final int d, final ZeroOrRegister ra) { | |
546 int instruction = 0xA0000000; | |
547 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
548 checkConstraint(ra != R0, "ra != R0"); | |
549 instruction |= ((rt.value() & 0x1f) << 21); | |
550 instruction |= (d & 0xffff); | |
551 instruction |= ((ra.value() & 0x1f) << 16); | |
552 emitInt(instruction); | |
553 } | |
554 | |
555 /** | |
556 * Pseudo-external assembler syntax: {@code lhzu }<i>rt</i>, <i>d</i>, <i>ra</i> | |
557 * Example disassembly syntax: {@code lhzu r0, -32768(r0)} | |
558 * <p> | |
559 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
560 * Constraint: {@code ra != R0}<br /> | |
561 * Constraint: {@code ra.value() != rt.value()}<br /> | |
562 * | |
563 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
564 */ | |
565 // Template#: 27, Serial#: 27 | |
566 public void lhzu(final GPR rt, final int d, final GPR ra) { | |
567 int instruction = 0xA4000000; | |
568 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
569 checkConstraint(ra != R0, "ra != R0"); | |
570 checkConstraint(ra.value() != rt.value(), "ra.value() != rt.value()"); | |
571 instruction |= ((rt.value() & 0x1f) << 21); | |
572 instruction |= (d & 0xffff); | |
573 instruction |= ((ra.value() & 0x1f) << 16); | |
574 emitInt(instruction); | |
575 } | |
576 | |
577 /** | |
578 * Pseudo-external assembler syntax: {@code lhzx }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
579 * Example disassembly syntax: {@code lhzx r0, 0, r0} | |
580 * <p> | |
581 * Constraint: {@code ra != R0}<br /> | |
582 * | |
583 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
584 */ | |
585 // Template#: 28, Serial#: 28 | |
586 public void lhzx(final GPR rt, final ZeroOrRegister ra, final GPR rb) { | |
587 int instruction = 0x7C00022E; | |
588 checkConstraint(ra != R0, "ra != R0"); | |
589 instruction |= ((rt.value() & 0x1f) << 21); | |
590 instruction |= ((ra.value() & 0x1f) << 16); | |
591 instruction |= ((rb.value() & 0x1f) << 11); | |
592 emitInt(instruction); | |
593 } | |
594 | |
595 /** | |
596 * Pseudo-external assembler syntax: {@code lhzux }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
597 * Example disassembly syntax: {@code lhzux r0, r0, r0} | |
598 * <p> | |
599 * Constraint: {@code ra != R0}<br /> | |
600 * Constraint: {@code ra.value() != rt.value()}<br /> | |
601 * | |
602 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
603 */ | |
604 // Template#: 29, Serial#: 29 | |
605 public void lhzux(final GPR rt, final GPR ra, final GPR rb) { | |
606 int instruction = 0x7C00026E; | |
607 checkConstraint(ra != R0, "ra != R0"); | |
608 checkConstraint(ra.value() != rt.value(), "ra.value() != rt.value()"); | |
609 instruction |= ((rt.value() & 0x1f) << 21); | |
610 instruction |= ((ra.value() & 0x1f) << 16); | |
611 instruction |= ((rb.value() & 0x1f) << 11); | |
612 emitInt(instruction); | |
613 } | |
614 | |
615 /** | |
616 * Pseudo-external assembler syntax: {@code lha }<i>rt</i>, <i>d</i>, <i>ra</i> | |
617 * Example disassembly syntax: {@code lha r0, -32768(0)} | |
618 * <p> | |
619 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
620 * Constraint: {@code ra != R0}<br /> | |
621 * | |
622 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
623 */ | |
624 // Template#: 30, Serial#: 30 | |
625 public void lha(final GPR rt, final int d, final ZeroOrRegister ra) { | |
626 int instruction = 0xA8000000; | |
627 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
628 checkConstraint(ra != R0, "ra != R0"); | |
629 instruction |= ((rt.value() & 0x1f) << 21); | |
630 instruction |= (d & 0xffff); | |
631 instruction |= ((ra.value() & 0x1f) << 16); | |
632 emitInt(instruction); | |
633 } | |
634 | |
635 /** | |
636 * Pseudo-external assembler syntax: {@code lhau }<i>rt</i>, <i>d</i>, <i>ra</i> | |
637 * Example disassembly syntax: {@code lhau r0, -32768(r0)} | |
638 * <p> | |
639 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
640 * Constraint: {@code ra != R0}<br /> | |
641 * Constraint: {@code ra.value() != rt.value()}<br /> | |
642 * | |
643 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
644 */ | |
645 // Template#: 31, Serial#: 31 | |
646 public void lhau(final GPR rt, final int d, final GPR ra) { | |
647 int instruction = 0xAC000000; | |
648 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
649 checkConstraint(ra != R0, "ra != R0"); | |
650 checkConstraint(ra.value() != rt.value(), "ra.value() != rt.value()"); | |
651 instruction |= ((rt.value() & 0x1f) << 21); | |
652 instruction |= (d & 0xffff); | |
653 instruction |= ((ra.value() & 0x1f) << 16); | |
654 emitInt(instruction); | |
655 } | |
656 | |
657 /** | |
658 * Pseudo-external assembler syntax: {@code lhax }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
659 * Example disassembly syntax: {@code lhax r0, 0, r0} | |
660 * <p> | |
661 * Constraint: {@code ra != R0}<br /> | |
662 * | |
663 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
664 */ | |
665 // Template#: 32, Serial#: 32 | |
666 public void lhax(final GPR rt, final ZeroOrRegister ra, final GPR rb) { | |
667 int instruction = 0x7C0002AE; | |
668 checkConstraint(ra != R0, "ra != R0"); | |
669 instruction |= ((rt.value() & 0x1f) << 21); | |
670 instruction |= ((ra.value() & 0x1f) << 16); | |
671 instruction |= ((rb.value() & 0x1f) << 11); | |
672 emitInt(instruction); | |
673 } | |
674 | |
675 /** | |
676 * Pseudo-external assembler syntax: {@code lhaux }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
677 * Example disassembly syntax: {@code lhaux r0, r0, r0} | |
678 * <p> | |
679 * Constraint: {@code ra != R0}<br /> | |
680 * Constraint: {@code ra.value() != rt.value()}<br /> | |
681 * | |
682 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
683 */ | |
684 // Template#: 33, Serial#: 33 | |
685 public void lhaux(final GPR rt, final GPR ra, final GPR rb) { | |
686 int instruction = 0x7C0002EE; | |
687 checkConstraint(ra != R0, "ra != R0"); | |
688 checkConstraint(ra.value() != rt.value(), "ra.value() != rt.value()"); | |
689 instruction |= ((rt.value() & 0x1f) << 21); | |
690 instruction |= ((ra.value() & 0x1f) << 16); | |
691 instruction |= ((rb.value() & 0x1f) << 11); | |
692 emitInt(instruction); | |
693 } | |
694 | |
695 /** | |
696 * Pseudo-external assembler syntax: {@code lwz }<i>rt</i>, <i>d</i>, <i>ra</i> | |
697 * Example disassembly syntax: {@code lwz r0, -32768(0)} | |
698 * <p> | |
699 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
700 * Constraint: {@code ra != R0}<br /> | |
701 * | |
702 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
703 */ | |
704 // Template#: 34, Serial#: 34 | |
705 public void lwz(final GPR rt, final int d, final ZeroOrRegister ra) { | |
706 int instruction = 0x80000000; | |
707 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
708 checkConstraint(ra != R0, "ra != R0"); | |
709 instruction |= ((rt.value() & 0x1f) << 21); | |
710 instruction |= (d & 0xffff); | |
711 instruction |= ((ra.value() & 0x1f) << 16); | |
712 emitInt(instruction); | |
713 } | |
714 | |
715 /** | |
716 * Pseudo-external assembler syntax: {@code lwzu }<i>rt</i>, <i>d</i>, <i>ra</i> | |
717 * Example disassembly syntax: {@code lwzu r0, -32768(r0)} | |
718 * <p> | |
719 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
720 * Constraint: {@code ra != R0}<br /> | |
721 * Constraint: {@code ra.value() != rt.value()}<br /> | |
722 * | |
723 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
724 */ | |
725 // Template#: 35, Serial#: 35 | |
726 public void lwzu(final GPR rt, final int d, final GPR ra) { | |
727 int instruction = 0x84000000; | |
728 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
729 checkConstraint(ra != R0, "ra != R0"); | |
730 checkConstraint(ra.value() != rt.value(), "ra.value() != rt.value()"); | |
731 instruction |= ((rt.value() & 0x1f) << 21); | |
732 instruction |= (d & 0xffff); | |
733 instruction |= ((ra.value() & 0x1f) << 16); | |
734 emitInt(instruction); | |
735 } | |
736 | |
737 /** | |
738 * Pseudo-external assembler syntax: {@code lwzx }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
739 * Example disassembly syntax: {@code lwzx r0, 0, r0} | |
740 * <p> | |
741 * Constraint: {@code ra != R0}<br /> | |
742 * | |
743 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
744 */ | |
745 // Template#: 36, Serial#: 36 | |
746 public void lwzx(final GPR rt, final ZeroOrRegister ra, final GPR rb) { | |
747 int instruction = 0x7C00002E; | |
748 checkConstraint(ra != R0, "ra != R0"); | |
749 instruction |= ((rt.value() & 0x1f) << 21); | |
750 instruction |= ((ra.value() & 0x1f) << 16); | |
751 instruction |= ((rb.value() & 0x1f) << 11); | |
752 emitInt(instruction); | |
753 } | |
754 | |
755 /** | |
756 * Pseudo-external assembler syntax: {@code lwzux }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
757 * Example disassembly syntax: {@code lwzux r0, r0, r0} | |
758 * <p> | |
759 * Constraint: {@code ra != R0}<br /> | |
760 * Constraint: {@code ra.value() != rt.value()}<br /> | |
761 * | |
762 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
763 */ | |
764 // Template#: 37, Serial#: 37 | |
765 public void lwzux(final GPR rt, final GPR ra, final GPR rb) { | |
766 int instruction = 0x7C00006E; | |
767 checkConstraint(ra != R0, "ra != R0"); | |
768 checkConstraint(ra.value() != rt.value(), "ra.value() != rt.value()"); | |
769 instruction |= ((rt.value() & 0x1f) << 21); | |
770 instruction |= ((ra.value() & 0x1f) << 16); | |
771 instruction |= ((rb.value() & 0x1f) << 11); | |
772 emitInt(instruction); | |
773 } | |
774 | |
775 /** | |
776 * Pseudo-external assembler syntax: {@code lwa }<i>rt</i>, <i>ds</i>, <i>ra</i> | |
777 * Example disassembly syntax: {@code lwa r0, -32768(0)} | |
778 * <p> | |
779 * Constraint: {@code (-32768 <= ds && ds <= 32764) && ((ds % 4) == 0)}<br /> | |
780 * Constraint: {@code ra != R0}<br /> | |
781 * | |
782 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
783 */ | |
784 // Template#: 38, Serial#: 38 | |
785 public void lwa(final GPR rt, final int ds, final ZeroOrRegister ra) { | |
786 int instruction = 0xE8000002; | |
787 checkConstraint((-32768 <= ds && ds <= 32764) && ((ds % 4) == 0), "(-32768 <= ds && ds <= 32764) && ((ds % 4) == 0)"); | |
788 checkConstraint(ra != R0, "ra != R0"); | |
789 instruction |= ((rt.value() & 0x1f) << 21); | |
790 instruction |= (((ds >> 2) & 0x3fff) << 2); | |
791 instruction |= ((ra.value() & 0x1f) << 16); | |
792 emitInt(instruction); | |
793 } | |
794 | |
795 /** | |
796 * Pseudo-external assembler syntax: {@code lwax }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
797 * Example disassembly syntax: {@code lwax r0, 0, r0} | |
798 * <p> | |
799 * Constraint: {@code ra != R0}<br /> | |
800 * | |
801 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
802 */ | |
803 // Template#: 39, Serial#: 39 | |
804 public void lwax(final GPR rt, final ZeroOrRegister ra, final GPR rb) { | |
805 int instruction = 0x7C0002AA; | |
806 checkConstraint(ra != R0, "ra != R0"); | |
807 instruction |= ((rt.value() & 0x1f) << 21); | |
808 instruction |= ((ra.value() & 0x1f) << 16); | |
809 instruction |= ((rb.value() & 0x1f) << 11); | |
810 emitInt(instruction); | |
811 } | |
812 | |
813 /** | |
814 * Pseudo-external assembler syntax: {@code lwaux }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
815 * Example disassembly syntax: {@code lwaux r0, r0, r0} | |
816 * <p> | |
817 * Constraint: {@code ra != R0}<br /> | |
818 * Constraint: {@code ra.value() != rt.value()}<br /> | |
819 * | |
820 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
821 */ | |
822 // Template#: 40, Serial#: 40 | |
823 public void lwaux(final GPR rt, final GPR ra, final GPR rb) { | |
824 int instruction = 0x7C0002EA; | |
825 checkConstraint(ra != R0, "ra != R0"); | |
826 checkConstraint(ra.value() != rt.value(), "ra.value() != rt.value()"); | |
827 instruction |= ((rt.value() & 0x1f) << 21); | |
828 instruction |= ((ra.value() & 0x1f) << 16); | |
829 instruction |= ((rb.value() & 0x1f) << 11); | |
830 emitInt(instruction); | |
831 } | |
832 | |
833 /** | |
834 * Pseudo-external assembler syntax: {@code ld }<i>rt</i>, <i>ds</i>, <i>ra</i> | |
835 * Example disassembly syntax: {@code ld r0, -32768(0)} | |
836 * <p> | |
837 * Constraint: {@code (-32768 <= ds && ds <= 32764) && ((ds % 4) == 0)}<br /> | |
838 * Constraint: {@code ra != R0}<br /> | |
839 * | |
840 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
841 */ | |
842 // Template#: 41, Serial#: 41 | |
843 public void ld(final GPR rt, final int ds, final ZeroOrRegister ra) { | |
844 int instruction = 0xE8000000; | |
845 checkConstraint((-32768 <= ds && ds <= 32764) && ((ds % 4) == 0), "(-32768 <= ds && ds <= 32764) && ((ds % 4) == 0)"); | |
846 checkConstraint(ra != R0, "ra != R0"); | |
847 instruction |= ((rt.value() & 0x1f) << 21); | |
848 instruction |= (((ds >> 2) & 0x3fff) << 2); | |
849 instruction |= ((ra.value() & 0x1f) << 16); | |
850 emitInt(instruction); | |
851 } | |
852 | |
853 /** | |
854 * Pseudo-external assembler syntax: {@code ldu }<i>rt</i>, <i>ds</i>, <i>ra</i> | |
855 * Example disassembly syntax: {@code ldu r0, -32768(r0)} | |
856 * <p> | |
857 * Constraint: {@code (-32768 <= ds && ds <= 32764) && ((ds % 4) == 0)}<br /> | |
858 * Constraint: {@code ra != R0}<br /> | |
859 * Constraint: {@code ra.value() != rt.value()}<br /> | |
860 * | |
861 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
862 */ | |
863 // Template#: 42, Serial#: 42 | |
864 public void ldu(final GPR rt, final int ds, final GPR ra) { | |
865 int instruction = 0xE8000001; | |
866 checkConstraint((-32768 <= ds && ds <= 32764) && ((ds % 4) == 0), "(-32768 <= ds && ds <= 32764) && ((ds % 4) == 0)"); | |
867 checkConstraint(ra != R0, "ra != R0"); | |
868 checkConstraint(ra.value() != rt.value(), "ra.value() != rt.value()"); | |
869 instruction |= ((rt.value() & 0x1f) << 21); | |
870 instruction |= (((ds >> 2) & 0x3fff) << 2); | |
871 instruction |= ((ra.value() & 0x1f) << 16); | |
872 emitInt(instruction); | |
873 } | |
874 | |
875 /** | |
876 * Pseudo-external assembler syntax: {@code ldx }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
877 * Example disassembly syntax: {@code ldx r0, 0, r0} | |
878 * <p> | |
879 * Constraint: {@code ra != R0}<br /> | |
880 * | |
881 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
882 */ | |
883 // Template#: 43, Serial#: 43 | |
884 public void ldx(final GPR rt, final ZeroOrRegister ra, final GPR rb) { | |
885 int instruction = 0x7C00002A; | |
886 checkConstraint(ra != R0, "ra != R0"); | |
887 instruction |= ((rt.value() & 0x1f) << 21); | |
888 instruction |= ((ra.value() & 0x1f) << 16); | |
889 instruction |= ((rb.value() & 0x1f) << 11); | |
890 emitInt(instruction); | |
891 } | |
892 | |
893 /** | |
894 * Pseudo-external assembler syntax: {@code ldux }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
895 * Example disassembly syntax: {@code ldux r0, r0, r0} | |
896 * <p> | |
897 * Constraint: {@code ra != R0}<br /> | |
898 * Constraint: {@code ra.value() != rt.value()}<br /> | |
899 * | |
900 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 1]" | |
901 */ | |
902 // Template#: 44, Serial#: 44 | |
903 public void ldux(final GPR rt, final GPR ra, final GPR rb) { | |
904 int instruction = 0x7C00006A; | |
905 checkConstraint(ra != R0, "ra != R0"); | |
906 checkConstraint(ra.value() != rt.value(), "ra.value() != rt.value()"); | |
907 instruction |= ((rt.value() & 0x1f) << 21); | |
908 instruction |= ((ra.value() & 0x1f) << 16); | |
909 instruction |= ((rb.value() & 0x1f) << 11); | |
910 emitInt(instruction); | |
911 } | |
912 | |
913 /** | |
914 * Pseudo-external assembler syntax: {@code stb }<i>rs</i>, <i>d</i>, <i>ra</i> | |
915 * Example disassembly syntax: {@code stb r0, -32768(0)} | |
916 * <p> | |
917 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
918 * Constraint: {@code ra != R0}<br /> | |
919 * | |
920 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
921 */ | |
922 // Template#: 45, Serial#: 45 | |
923 public void stb(final GPR rs, final int d, final ZeroOrRegister ra) { | |
924 int instruction = 0x98000000; | |
925 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
926 checkConstraint(ra != R0, "ra != R0"); | |
927 instruction |= ((rs.value() & 0x1f) << 21); | |
928 instruction |= (d & 0xffff); | |
929 instruction |= ((ra.value() & 0x1f) << 16); | |
930 emitInt(instruction); | |
931 } | |
932 | |
933 /** | |
934 * Pseudo-external assembler syntax: {@code stbu }<i>rs</i>, <i>d</i>, <i>ra</i> | |
935 * Example disassembly syntax: {@code stbu r0, -32768(r0)} | |
936 * <p> | |
937 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
938 * Constraint: {@code ra != R0}<br /> | |
939 * | |
940 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
941 */ | |
942 // Template#: 46, Serial#: 46 | |
943 public void stbu(final GPR rs, final int d, final GPR ra) { | |
944 int instruction = 0x9C000000; | |
945 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
946 checkConstraint(ra != R0, "ra != R0"); | |
947 instruction |= ((rs.value() & 0x1f) << 21); | |
948 instruction |= (d & 0xffff); | |
949 instruction |= ((ra.value() & 0x1f) << 16); | |
950 emitInt(instruction); | |
951 } | |
952 | |
953 /** | |
954 * Pseudo-external assembler syntax: {@code stbx }<i>rs</i>, <i>ra</i>, <i>rb</i> | |
955 * Example disassembly syntax: {@code stbx r0, 0, r0} | |
956 * <p> | |
957 * Constraint: {@code ra != R0}<br /> | |
958 * | |
959 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
960 */ | |
961 // Template#: 47, Serial#: 47 | |
962 public void stbx(final GPR rs, final ZeroOrRegister ra, final GPR rb) { | |
963 int instruction = 0x7C0001AE; | |
964 checkConstraint(ra != R0, "ra != R0"); | |
965 instruction |= ((rs.value() & 0x1f) << 21); | |
966 instruction |= ((ra.value() & 0x1f) << 16); | |
967 instruction |= ((rb.value() & 0x1f) << 11); | |
968 emitInt(instruction); | |
969 } | |
970 | |
971 /** | |
972 * Pseudo-external assembler syntax: {@code stbux }<i>rs</i>, <i>ra</i>, <i>rb</i> | |
973 * Example disassembly syntax: {@code stbux r0, r0, r0} | |
974 * <p> | |
975 * Constraint: {@code ra != R0}<br /> | |
976 * | |
977 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
978 */ | |
979 // Template#: 48, Serial#: 48 | |
980 public void stbux(final GPR rs, final GPR ra, final GPR rb) { | |
981 int instruction = 0x7C0001EE; | |
982 checkConstraint(ra != R0, "ra != R0"); | |
983 instruction |= ((rs.value() & 0x1f) << 21); | |
984 instruction |= ((ra.value() & 0x1f) << 16); | |
985 instruction |= ((rb.value() & 0x1f) << 11); | |
986 emitInt(instruction); | |
987 } | |
988 | |
989 /** | |
990 * Pseudo-external assembler syntax: {@code sth }<i>rs</i>, <i>d</i>, <i>ra</i> | |
991 * Example disassembly syntax: {@code sth r0, -32768(0)} | |
992 * <p> | |
993 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
994 * Constraint: {@code ra != R0}<br /> | |
995 * | |
996 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
997 */ | |
998 // Template#: 49, Serial#: 49 | |
999 public void sth(final GPR rs, final int d, final ZeroOrRegister ra) { | |
1000 int instruction = 0xB0000000; | |
1001 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
1002 checkConstraint(ra != R0, "ra != R0"); | |
1003 instruction |= ((rs.value() & 0x1f) << 21); | |
1004 instruction |= (d & 0xffff); | |
1005 instruction |= ((ra.value() & 0x1f) << 16); | |
1006 emitInt(instruction); | |
1007 } | |
1008 | |
1009 /** | |
1010 * Pseudo-external assembler syntax: {@code sthu }<i>rs</i>, <i>d</i>, <i>ra</i> | |
1011 * Example disassembly syntax: {@code sthu r0, -32768(r0)} | |
1012 * <p> | |
1013 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
1014 * Constraint: {@code ra != R0}<br /> | |
1015 * | |
1016 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
1017 */ | |
1018 // Template#: 50, Serial#: 50 | |
1019 public void sthu(final GPR rs, final int d, final GPR ra) { | |
1020 int instruction = 0xB4000000; | |
1021 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
1022 checkConstraint(ra != R0, "ra != R0"); | |
1023 instruction |= ((rs.value() & 0x1f) << 21); | |
1024 instruction |= (d & 0xffff); | |
1025 instruction |= ((ra.value() & 0x1f) << 16); | |
1026 emitInt(instruction); | |
1027 } | |
1028 | |
1029 /** | |
1030 * Pseudo-external assembler syntax: {@code sthx }<i>rs</i>, <i>ra</i>, <i>rb</i> | |
1031 * Example disassembly syntax: {@code sthx r0, 0, r0} | |
1032 * <p> | |
1033 * Constraint: {@code ra != R0}<br /> | |
1034 * | |
1035 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
1036 */ | |
1037 // Template#: 51, Serial#: 51 | |
1038 public void sthx(final GPR rs, final ZeroOrRegister ra, final GPR rb) { | |
1039 int instruction = 0x7C00032E; | |
1040 checkConstraint(ra != R0, "ra != R0"); | |
1041 instruction |= ((rs.value() & 0x1f) << 21); | |
1042 instruction |= ((ra.value() & 0x1f) << 16); | |
1043 instruction |= ((rb.value() & 0x1f) << 11); | |
1044 emitInt(instruction); | |
1045 } | |
1046 | |
1047 /** | |
1048 * Pseudo-external assembler syntax: {@code sthux }<i>rs</i>, <i>ra</i>, <i>rb</i> | |
1049 * Example disassembly syntax: {@code sthux r0, r0, r0} | |
1050 * <p> | |
1051 * Constraint: {@code ra != R0}<br /> | |
1052 * | |
1053 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
1054 */ | |
1055 // Template#: 52, Serial#: 52 | |
1056 public void sthux(final GPR rs, final GPR ra, final GPR rb) { | |
1057 int instruction = 0x7C00036E; | |
1058 checkConstraint(ra != R0, "ra != R0"); | |
1059 instruction |= ((rs.value() & 0x1f) << 21); | |
1060 instruction |= ((ra.value() & 0x1f) << 16); | |
1061 instruction |= ((rb.value() & 0x1f) << 11); | |
1062 emitInt(instruction); | |
1063 } | |
1064 | |
1065 /** | |
1066 * Pseudo-external assembler syntax: {@code stw }<i>rs</i>, <i>d</i>, <i>ra</i> | |
1067 * Example disassembly syntax: {@code stw r0, -32768(0)} | |
1068 * <p> | |
1069 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
1070 * Constraint: {@code ra != R0}<br /> | |
1071 * | |
1072 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
1073 */ | |
1074 // Template#: 53, Serial#: 53 | |
1075 public void stw(final GPR rs, final int d, final ZeroOrRegister ra) { | |
1076 int instruction = 0x90000000; | |
1077 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
1078 checkConstraint(ra != R0, "ra != R0"); | |
1079 instruction |= ((rs.value() & 0x1f) << 21); | |
1080 instruction |= (d & 0xffff); | |
1081 instruction |= ((ra.value() & 0x1f) << 16); | |
1082 emitInt(instruction); | |
1083 } | |
1084 | |
1085 /** | |
1086 * Pseudo-external assembler syntax: {@code stwu }<i>rs</i>, <i>d</i>, <i>ra</i> | |
1087 * Example disassembly syntax: {@code stwu r0, -32768(r0)} | |
1088 * <p> | |
1089 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
1090 * Constraint: {@code ra != R0}<br /> | |
1091 * | |
1092 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
1093 */ | |
1094 // Template#: 54, Serial#: 54 | |
1095 public void stwu(final GPR rs, final int d, final GPR ra) { | |
1096 int instruction = 0x94000000; | |
1097 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
1098 checkConstraint(ra != R0, "ra != R0"); | |
1099 instruction |= ((rs.value() & 0x1f) << 21); | |
1100 instruction |= (d & 0xffff); | |
1101 instruction |= ((ra.value() & 0x1f) << 16); | |
1102 emitInt(instruction); | |
1103 } | |
1104 | |
1105 /** | |
1106 * Pseudo-external assembler syntax: {@code stwx }<i>rs</i>, <i>ra</i>, <i>rb</i> | |
1107 * Example disassembly syntax: {@code stwx r0, 0, r0} | |
1108 * <p> | |
1109 * Constraint: {@code ra != R0}<br /> | |
1110 * | |
1111 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
1112 */ | |
1113 // Template#: 55, Serial#: 55 | |
1114 public void stwx(final GPR rs, final ZeroOrRegister ra, final GPR rb) { | |
1115 int instruction = 0x7C00012E; | |
1116 checkConstraint(ra != R0, "ra != R0"); | |
1117 instruction |= ((rs.value() & 0x1f) << 21); | |
1118 instruction |= ((ra.value() & 0x1f) << 16); | |
1119 instruction |= ((rb.value() & 0x1f) << 11); | |
1120 emitInt(instruction); | |
1121 } | |
1122 | |
1123 /** | |
1124 * Pseudo-external assembler syntax: {@code stwux }<i>rs</i>, <i>ra</i>, <i>rb</i> | |
1125 * Example disassembly syntax: {@code stwux r0, r0, r0} | |
1126 * <p> | |
1127 * Constraint: {@code ra != R0}<br /> | |
1128 * | |
1129 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
1130 */ | |
1131 // Template#: 56, Serial#: 56 | |
1132 public void stwux(final GPR rs, final GPR ra, final GPR rb) { | |
1133 int instruction = 0x7C00016E; | |
1134 checkConstraint(ra != R0, "ra != R0"); | |
1135 instruction |= ((rs.value() & 0x1f) << 21); | |
1136 instruction |= ((ra.value() & 0x1f) << 16); | |
1137 instruction |= ((rb.value() & 0x1f) << 11); | |
1138 emitInt(instruction); | |
1139 } | |
1140 | |
1141 /** | |
1142 * Pseudo-external assembler syntax: {@code std }<i>rs</i>, <i>ds</i>, <i>ra</i> | |
1143 * Example disassembly syntax: {@code std r0, -32768(0)} | |
1144 * <p> | |
1145 * Constraint: {@code (-32768 <= ds && ds <= 32764) && ((ds % 4) == 0)}<br /> | |
1146 * Constraint: {@code ra != R0}<br /> | |
1147 * | |
1148 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
1149 */ | |
1150 // Template#: 57, Serial#: 57 | |
1151 public void std(final GPR rs, final int ds, final ZeroOrRegister ra) { | |
1152 int instruction = 0xF8000000; | |
1153 checkConstraint((-32768 <= ds && ds <= 32764) && ((ds % 4) == 0), "(-32768 <= ds && ds <= 32764) && ((ds % 4) == 0)"); | |
1154 checkConstraint(ra != R0, "ra != R0"); | |
1155 instruction |= ((rs.value() & 0x1f) << 21); | |
1156 instruction |= (((ds >> 2) & 0x3fff) << 2); | |
1157 instruction |= ((ra.value() & 0x1f) << 16); | |
1158 emitInt(instruction); | |
1159 } | |
1160 | |
1161 /** | |
1162 * Pseudo-external assembler syntax: {@code stdu }<i>rs</i>, <i>ds</i>, <i>ra</i> | |
1163 * Example disassembly syntax: {@code stdu r0, -32768(r0)} | |
1164 * <p> | |
1165 * Constraint: {@code (-32768 <= ds && ds <= 32764) && ((ds % 4) == 0)}<br /> | |
1166 * Constraint: {@code ra != R0}<br /> | |
1167 * | |
1168 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
1169 */ | |
1170 // Template#: 58, Serial#: 58 | |
1171 public void stdu(final GPR rs, final int ds, final GPR ra) { | |
1172 int instruction = 0xF8000001; | |
1173 checkConstraint((-32768 <= ds && ds <= 32764) && ((ds % 4) == 0), "(-32768 <= ds && ds <= 32764) && ((ds % 4) == 0)"); | |
1174 checkConstraint(ra != R0, "ra != R0"); | |
1175 instruction |= ((rs.value() & 0x1f) << 21); | |
1176 instruction |= (((ds >> 2) & 0x3fff) << 2); | |
1177 instruction |= ((ra.value() & 0x1f) << 16); | |
1178 emitInt(instruction); | |
1179 } | |
1180 | |
1181 /** | |
1182 * Pseudo-external assembler syntax: {@code stdx }<i>rs</i>, <i>ra</i>, <i>rb</i> | |
1183 * Example disassembly syntax: {@code stdx r0, 0, r0} | |
1184 * <p> | |
1185 * Constraint: {@code ra != R0}<br /> | |
1186 * | |
1187 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
1188 */ | |
1189 // Template#: 59, Serial#: 59 | |
1190 public void stdx(final GPR rs, final ZeroOrRegister ra, final GPR rb) { | |
1191 int instruction = 0x7C00012A; | |
1192 checkConstraint(ra != R0, "ra != R0"); | |
1193 instruction |= ((rs.value() & 0x1f) << 21); | |
1194 instruction |= ((ra.value() & 0x1f) << 16); | |
1195 instruction |= ((rb.value() & 0x1f) << 11); | |
1196 emitInt(instruction); | |
1197 } | |
1198 | |
1199 /** | |
1200 * Pseudo-external assembler syntax: {@code stdux }<i>rs</i>, <i>ra</i>, <i>rb</i> | |
1201 * Example disassembly syntax: {@code stdux r0, r0, r0} | |
1202 * <p> | |
1203 * Constraint: {@code ra != R0}<br /> | |
1204 * | |
1205 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 1]" | |
1206 */ | |
1207 // Template#: 60, Serial#: 60 | |
1208 public void stdux(final GPR rs, final GPR ra, final GPR rb) { | |
1209 int instruction = 0x7C00016A; | |
1210 checkConstraint(ra != R0, "ra != R0"); | |
1211 instruction |= ((rs.value() & 0x1f) << 21); | |
1212 instruction |= ((ra.value() & 0x1f) << 16); | |
1213 instruction |= ((rb.value() & 0x1f) << 11); | |
1214 emitInt(instruction); | |
1215 } | |
1216 | |
1217 /** | |
1218 * Pseudo-external assembler syntax: {@code lhbrx }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1219 * Example disassembly syntax: {@code lhbrx r0, 0, r0} | |
1220 * <p> | |
1221 * Constraint: {@code ra != R0}<br /> | |
1222 * | |
1223 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.4 [Book 1]" | |
1224 */ | |
1225 // Template#: 61, Serial#: 61 | |
1226 public void lhbrx(final GPR rt, final ZeroOrRegister ra, final GPR rb) { | |
1227 int instruction = 0x7C00062C; | |
1228 checkConstraint(ra != R0, "ra != R0"); | |
1229 instruction |= ((rt.value() & 0x1f) << 21); | |
1230 instruction |= ((ra.value() & 0x1f) << 16); | |
1231 instruction |= ((rb.value() & 0x1f) << 11); | |
1232 emitInt(instruction); | |
1233 } | |
1234 | |
1235 /** | |
1236 * Pseudo-external assembler syntax: {@code lwbrx }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1237 * Example disassembly syntax: {@code lwbrx r0, 0, r0} | |
1238 * <p> | |
1239 * Constraint: {@code ra != R0}<br /> | |
1240 * | |
1241 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.4 [Book 1]" | |
1242 */ | |
1243 // Template#: 62, Serial#: 62 | |
1244 public void lwbrx(final GPR rt, final ZeroOrRegister ra, final GPR rb) { | |
1245 int instruction = 0x7C00042C; | |
1246 checkConstraint(ra != R0, "ra != R0"); | |
1247 instruction |= ((rt.value() & 0x1f) << 21); | |
1248 instruction |= ((ra.value() & 0x1f) << 16); | |
1249 instruction |= ((rb.value() & 0x1f) << 11); | |
1250 emitInt(instruction); | |
1251 } | |
1252 | |
1253 /** | |
1254 * Pseudo-external assembler syntax: {@code sthbrx }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1255 * Example disassembly syntax: {@code sthbrx r0, 0, r0} | |
1256 * <p> | |
1257 * Constraint: {@code ra != R0}<br /> | |
1258 * | |
1259 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.4 [Book 1]" | |
1260 */ | |
1261 // Template#: 63, Serial#: 63 | |
1262 public void sthbrx(final GPR rt, final ZeroOrRegister ra, final GPR rb) { | |
1263 int instruction = 0x7C00072C; | |
1264 checkConstraint(ra != R0, "ra != R0"); | |
1265 instruction |= ((rt.value() & 0x1f) << 21); | |
1266 instruction |= ((ra.value() & 0x1f) << 16); | |
1267 instruction |= ((rb.value() & 0x1f) << 11); | |
1268 emitInt(instruction); | |
1269 } | |
1270 | |
1271 /** | |
1272 * Pseudo-external assembler syntax: {@code stwbrx }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1273 * Example disassembly syntax: {@code stwbrx r0, 0, r0} | |
1274 * <p> | |
1275 * Constraint: {@code ra != R0}<br /> | |
1276 * | |
1277 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.4 [Book 1]" | |
1278 */ | |
1279 // Template#: 64, Serial#: 64 | |
1280 public void stwbrx(final GPR rt, final ZeroOrRegister ra, final GPR rb) { | |
1281 int instruction = 0x7C00052C; | |
1282 checkConstraint(ra != R0, "ra != R0"); | |
1283 instruction |= ((rt.value() & 0x1f) << 21); | |
1284 instruction |= ((ra.value() & 0x1f) << 16); | |
1285 instruction |= ((rb.value() & 0x1f) << 11); | |
1286 emitInt(instruction); | |
1287 } | |
1288 | |
1289 /** | |
1290 * Pseudo-external assembler syntax: {@code lmw }<i>rt</i>, <i>d</i>, <i>ra</i> | |
1291 * Example disassembly syntax: {@code lmw r0, -32768(0)} | |
1292 * <p> | |
1293 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
1294 * Constraint: {@code ra != R0}<br /> | |
1295 * Constraint: {@code ra.value() < rt.value()}<br /> | |
1296 * | |
1297 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.5 [Book 1]" | |
1298 */ | |
1299 // Template#: 65, Serial#: 65 | |
1300 public void lmw(final GPR rt, final int d, final ZeroOrRegister ra) { | |
1301 int instruction = 0xB8000000; | |
1302 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
1303 checkConstraint(ra != R0, "ra != R0"); | |
1304 checkConstraint(ra.value() < rt.value(), "ra.value() < rt.value()"); | |
1305 instruction |= ((rt.value() & 0x1f) << 21); | |
1306 instruction |= (d & 0xffff); | |
1307 instruction |= ((ra.value() & 0x1f) << 16); | |
1308 emitInt(instruction); | |
1309 } | |
1310 | |
1311 /** | |
1312 * Pseudo-external assembler syntax: {@code stmw }<i>rs</i>, <i>d</i>, <i>ra</i> | |
1313 * Example disassembly syntax: {@code stmw r0, -32768(0)} | |
1314 * <p> | |
1315 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
1316 * Constraint: {@code ra != R0}<br /> | |
1317 * | |
1318 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.5 [Book 1]" | |
1319 */ | |
1320 // Template#: 66, Serial#: 66 | |
1321 public void stmw(final GPR rs, final int d, final ZeroOrRegister ra) { | |
1322 int instruction = 0xBC000000; | |
1323 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
1324 checkConstraint(ra != R0, "ra != R0"); | |
1325 instruction |= ((rs.value() & 0x1f) << 21); | |
1326 instruction |= (d & 0xffff); | |
1327 instruction |= ((ra.value() & 0x1f) << 16); | |
1328 emitInt(instruction); | |
1329 } | |
1330 | |
1331 /** | |
1332 * Pseudo-external assembler syntax: {@code lswi }<i>rt</i>, <i>ra</i>, <i>nb</i> | |
1333 * Example disassembly syntax: {@code lswi r0, 0, 0x0} | |
1334 * <p> | |
1335 * Constraint: {@code ra != R0}<br /> | |
1336 * Constraint: {@code 0 <= nb && nb <= 31}<br /> | |
1337 * Constraint: {@code ra.isOutsideRegisterRange(rt, nb)}<br /> | |
1338 * | |
1339 * @see com.sun.max.asm.ppc.ZeroOrRegister#isOutsideRegisterRange | |
1340 * | |
1341 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.6 [Book 1]" | |
1342 */ | |
1343 // Template#: 67, Serial#: 67 | |
1344 public void lswi(final GPR rt, final ZeroOrRegister ra, final int nb) { | |
1345 int instruction = 0x7C0004AA; | |
1346 checkConstraint(ra != R0, "ra != R0"); | |
1347 checkConstraint(0 <= nb && nb <= 31, "0 <= nb && nb <= 31"); | |
1348 checkConstraint(ra.isOutsideRegisterRange(rt, nb), "ra.isOutsideRegisterRange(rt, nb)"); | |
1349 instruction |= ((rt.value() & 0x1f) << 21); | |
1350 instruction |= ((ra.value() & 0x1f) << 16); | |
1351 instruction |= ((nb & 0x1f) << 11); | |
1352 emitInt(instruction); | |
1353 } | |
1354 | |
1355 /** | |
1356 * Pseudo-external assembler syntax: {@code lswx }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1357 * Example disassembly syntax: {@code lswx r0, 0, r0} | |
1358 * <p> | |
1359 * Constraint: {@code ra != R0}<br /> | |
1360 * Constraint: {@code rt.value() != ra.value()}<br /> | |
1361 * Constraint: {@code rt.value() != rb.value()}<br /> | |
1362 * | |
1363 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.6 [Book 1]" | |
1364 */ | |
1365 // Template#: 68, Serial#: 68 | |
1366 public void lswx(final GPR rt, final ZeroOrRegister ra, final GPR rb) { | |
1367 int instruction = 0x7C00042A; | |
1368 checkConstraint(ra != R0, "ra != R0"); | |
1369 checkConstraint(rt.value() != ra.value(), "rt.value() != ra.value()"); | |
1370 checkConstraint(rt.value() != rb.value(), "rt.value() != rb.value()"); | |
1371 instruction |= ((rt.value() & 0x1f) << 21); | |
1372 instruction |= ((ra.value() & 0x1f) << 16); | |
1373 instruction |= ((rb.value() & 0x1f) << 11); | |
1374 emitInt(instruction); | |
1375 } | |
1376 | |
1377 /** | |
1378 * Pseudo-external assembler syntax: {@code stswi }<i>rs</i>, <i>ra</i>, <i>nb</i> | |
1379 * Example disassembly syntax: {@code stswi r0, 0, 0x0} | |
1380 * <p> | |
1381 * Constraint: {@code ra != R0}<br /> | |
1382 * Constraint: {@code 0 <= nb && nb <= 31}<br /> | |
1383 * | |
1384 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.6 [Book 1]" | |
1385 */ | |
1386 // Template#: 69, Serial#: 69 | |
1387 public void stswi(final GPR rs, final ZeroOrRegister ra, final int nb) { | |
1388 int instruction = 0x7C0005AA; | |
1389 checkConstraint(ra != R0, "ra != R0"); | |
1390 checkConstraint(0 <= nb && nb <= 31, "0 <= nb && nb <= 31"); | |
1391 instruction |= ((rs.value() & 0x1f) << 21); | |
1392 instruction |= ((ra.value() & 0x1f) << 16); | |
1393 instruction |= ((nb & 0x1f) << 11); | |
1394 emitInt(instruction); | |
1395 } | |
1396 | |
1397 /** | |
1398 * Pseudo-external assembler syntax: {@code stswx }<i>rs</i>, <i>ra</i>, <i>rb</i> | |
1399 * Example disassembly syntax: {@code stswx r0, 0, r0} | |
1400 * <p> | |
1401 * Constraint: {@code ra != R0}<br /> | |
1402 * | |
1403 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.6 [Book 1]" | |
1404 */ | |
1405 // Template#: 70, Serial#: 70 | |
1406 public void stswx(final GPR rs, final ZeroOrRegister ra, final GPR rb) { | |
1407 int instruction = 0x7C00052A; | |
1408 checkConstraint(ra != R0, "ra != R0"); | |
1409 instruction |= ((rs.value() & 0x1f) << 21); | |
1410 instruction |= ((ra.value() & 0x1f) << 16); | |
1411 instruction |= ((rb.value() & 0x1f) << 11); | |
1412 emitInt(instruction); | |
1413 } | |
1414 | |
1415 /** | |
1416 * Pseudo-external assembler syntax: {@code addi }<i>rt</i>, <i>ra</i>, <i>si</i> | |
1417 * Example disassembly syntax: {@code addi r0, 0, -32768} | |
1418 * <p> | |
1419 * Constraint: {@code ra != R0}<br /> | |
1420 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
1421 * | |
1422 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1423 */ | |
1424 // Template#: 71, Serial#: 71 | |
1425 public void addi(final GPR rt, final ZeroOrRegister ra, final int si) { | |
1426 int instruction = 0x38000000; | |
1427 checkConstraint(ra != R0, "ra != R0"); | |
1428 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
1429 instruction |= ((rt.value() & 0x1f) << 21); | |
1430 instruction |= ((ra.value() & 0x1f) << 16); | |
1431 instruction |= (si & 0xffff); | |
1432 emitInt(instruction); | |
1433 } | |
1434 | |
1435 /** | |
1436 * Pseudo-external assembler syntax: {@code addis }<i>rt</i>, <i>ra</i>, <i>sis</i> | |
1437 * Example disassembly syntax: {@code addis r0, 0, 0x0} | |
1438 * <p> | |
1439 * Constraint: {@code ra != R0}<br /> | |
1440 * Constraint: {@code -32768 <= sis && sis <= 65535}<br /> | |
1441 * | |
1442 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1443 */ | |
1444 // Template#: 72, Serial#: 72 | |
1445 public void addis(final GPR rt, final ZeroOrRegister ra, final int sis) { | |
1446 int instruction = 0x3C000000; | |
1447 checkConstraint(ra != R0, "ra != R0"); | |
1448 checkConstraint(-32768 <= sis && sis <= 65535, "-32768 <= sis && sis <= 65535"); | |
1449 instruction |= ((rt.value() & 0x1f) << 21); | |
1450 instruction |= ((ra.value() & 0x1f) << 16); | |
1451 instruction |= (sis & 0xffff); | |
1452 emitInt(instruction); | |
1453 } | |
1454 | |
1455 /** | |
1456 * Pseudo-external assembler syntax: {@code add }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1457 * Example disassembly syntax: {@code add r0, r0, r0} | |
1458 * | |
1459 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1460 */ | |
1461 // Template#: 73, Serial#: 73 | |
1462 public void add(final GPR rt, final GPR ra, final GPR rb) { | |
1463 int instruction = 0x7C000214; | |
1464 instruction |= ((rt.value() & 0x1f) << 21); | |
1465 instruction |= ((ra.value() & 0x1f) << 16); | |
1466 instruction |= ((rb.value() & 0x1f) << 11); | |
1467 emitInt(instruction); | |
1468 } | |
1469 | |
1470 /** | |
1471 * Pseudo-external assembler syntax: {@code add. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1472 * Example disassembly syntax: {@code add. r0, r0, r0} | |
1473 * | |
1474 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1475 */ | |
1476 // Template#: 74, Serial#: 74 | |
1477 public void add_(final GPR rt, final GPR ra, final GPR rb) { | |
1478 int instruction = 0x7C000215; | |
1479 instruction |= ((rt.value() & 0x1f) << 21); | |
1480 instruction |= ((ra.value() & 0x1f) << 16); | |
1481 instruction |= ((rb.value() & 0x1f) << 11); | |
1482 emitInt(instruction); | |
1483 } | |
1484 | |
1485 /** | |
1486 * Pseudo-external assembler syntax: {@code addo }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1487 * Example disassembly syntax: {@code addo r0, r0, r0} | |
1488 * | |
1489 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1490 */ | |
1491 // Template#: 75, Serial#: 75 | |
1492 public void addo(final GPR rt, final GPR ra, final GPR rb) { | |
1493 int instruction = 0x7C000614; | |
1494 instruction |= ((rt.value() & 0x1f) << 21); | |
1495 instruction |= ((ra.value() & 0x1f) << 16); | |
1496 instruction |= ((rb.value() & 0x1f) << 11); | |
1497 emitInt(instruction); | |
1498 } | |
1499 | |
1500 /** | |
1501 * Pseudo-external assembler syntax: {@code addo. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1502 * Example disassembly syntax: {@code addo. r0, r0, r0} | |
1503 * | |
1504 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1505 */ | |
1506 // Template#: 76, Serial#: 76 | |
1507 public void addo_(final GPR rt, final GPR ra, final GPR rb) { | |
1508 int instruction = 0x7C000615; | |
1509 instruction |= ((rt.value() & 0x1f) << 21); | |
1510 instruction |= ((ra.value() & 0x1f) << 16); | |
1511 instruction |= ((rb.value() & 0x1f) << 11); | |
1512 emitInt(instruction); | |
1513 } | |
1514 | |
1515 /** | |
1516 * Pseudo-external assembler syntax: {@code subf }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1517 * Example disassembly syntax: {@code subf r0, r0, r0} | |
1518 * | |
1519 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1520 */ | |
1521 // Template#: 77, Serial#: 77 | |
1522 public void subf(final GPR rt, final GPR ra, final GPR rb) { | |
1523 int instruction = 0x7C000050; | |
1524 instruction |= ((rt.value() & 0x1f) << 21); | |
1525 instruction |= ((ra.value() & 0x1f) << 16); | |
1526 instruction |= ((rb.value() & 0x1f) << 11); | |
1527 emitInt(instruction); | |
1528 } | |
1529 | |
1530 /** | |
1531 * Pseudo-external assembler syntax: {@code subf. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1532 * Example disassembly syntax: {@code subf. r0, r0, r0} | |
1533 * | |
1534 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1535 */ | |
1536 // Template#: 78, Serial#: 78 | |
1537 public void subf_(final GPR rt, final GPR ra, final GPR rb) { | |
1538 int instruction = 0x7C000051; | |
1539 instruction |= ((rt.value() & 0x1f) << 21); | |
1540 instruction |= ((ra.value() & 0x1f) << 16); | |
1541 instruction |= ((rb.value() & 0x1f) << 11); | |
1542 emitInt(instruction); | |
1543 } | |
1544 | |
1545 /** | |
1546 * Pseudo-external assembler syntax: {@code subfo }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1547 * Example disassembly syntax: {@code subfo r0, r0, r0} | |
1548 * | |
1549 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1550 */ | |
1551 // Template#: 79, Serial#: 79 | |
1552 public void subfo(final GPR rt, final GPR ra, final GPR rb) { | |
1553 int instruction = 0x7C000450; | |
1554 instruction |= ((rt.value() & 0x1f) << 21); | |
1555 instruction |= ((ra.value() & 0x1f) << 16); | |
1556 instruction |= ((rb.value() & 0x1f) << 11); | |
1557 emitInt(instruction); | |
1558 } | |
1559 | |
1560 /** | |
1561 * Pseudo-external assembler syntax: {@code subfo. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1562 * Example disassembly syntax: {@code subfo. r0, r0, r0} | |
1563 * | |
1564 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1565 */ | |
1566 // Template#: 80, Serial#: 80 | |
1567 public void subfo_(final GPR rt, final GPR ra, final GPR rb) { | |
1568 int instruction = 0x7C000451; | |
1569 instruction |= ((rt.value() & 0x1f) << 21); | |
1570 instruction |= ((ra.value() & 0x1f) << 16); | |
1571 instruction |= ((rb.value() & 0x1f) << 11); | |
1572 emitInt(instruction); | |
1573 } | |
1574 | |
1575 /** | |
1576 * Pseudo-external assembler syntax: {@code addic }<i>rt</i>, <i>ra</i>, <i>si</i> | |
1577 * Example disassembly syntax: {@code addic r0, r0, -32768} | |
1578 * <p> | |
1579 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
1580 * | |
1581 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1582 */ | |
1583 // Template#: 81, Serial#: 81 | |
1584 public void addic(final GPR rt, final GPR ra, final int si) { | |
1585 int instruction = 0x30000000; | |
1586 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
1587 instruction |= ((rt.value() & 0x1f) << 21); | |
1588 instruction |= ((ra.value() & 0x1f) << 16); | |
1589 instruction |= (si & 0xffff); | |
1590 emitInt(instruction); | |
1591 } | |
1592 | |
1593 /** | |
1594 * Pseudo-external assembler syntax: {@code addic. }<i>rt</i>, <i>ra</i>, <i>si</i> | |
1595 * Example disassembly syntax: {@code addic. r0, r0, -32768} | |
1596 * <p> | |
1597 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
1598 * | |
1599 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1600 */ | |
1601 // Template#: 82, Serial#: 82 | |
1602 public void addic_(final GPR rt, final GPR ra, final int si) { | |
1603 int instruction = 0x34000000; | |
1604 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
1605 instruction |= ((rt.value() & 0x1f) << 21); | |
1606 instruction |= ((ra.value() & 0x1f) << 16); | |
1607 instruction |= (si & 0xffff); | |
1608 emitInt(instruction); | |
1609 } | |
1610 | |
1611 /** | |
1612 * Pseudo-external assembler syntax: {@code subfic }<i>rt</i>, <i>ra</i>, <i>si</i> | |
1613 * Example disassembly syntax: {@code subfic r0, r0, -32768} | |
1614 * <p> | |
1615 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
1616 * | |
1617 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1618 */ | |
1619 // Template#: 83, Serial#: 83 | |
1620 public void subfic(final GPR rt, final GPR ra, final int si) { | |
1621 int instruction = 0x20000000; | |
1622 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
1623 instruction |= ((rt.value() & 0x1f) << 21); | |
1624 instruction |= ((ra.value() & 0x1f) << 16); | |
1625 instruction |= (si & 0xffff); | |
1626 emitInt(instruction); | |
1627 } | |
1628 | |
1629 /** | |
1630 * Pseudo-external assembler syntax: {@code addc }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1631 * Example disassembly syntax: {@code addc r0, r0, r0} | |
1632 * | |
1633 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1634 */ | |
1635 // Template#: 84, Serial#: 84 | |
1636 public void addc(final GPR rt, final GPR ra, final GPR rb) { | |
1637 int instruction = 0x7C000014; | |
1638 instruction |= ((rt.value() & 0x1f) << 21); | |
1639 instruction |= ((ra.value() & 0x1f) << 16); | |
1640 instruction |= ((rb.value() & 0x1f) << 11); | |
1641 emitInt(instruction); | |
1642 } | |
1643 | |
1644 /** | |
1645 * Pseudo-external assembler syntax: {@code addc. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1646 * Example disassembly syntax: {@code addc. r0, r0, r0} | |
1647 * | |
1648 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1649 */ | |
1650 // Template#: 85, Serial#: 85 | |
1651 public void addc_(final GPR rt, final GPR ra, final GPR rb) { | |
1652 int instruction = 0x7C000015; | |
1653 instruction |= ((rt.value() & 0x1f) << 21); | |
1654 instruction |= ((ra.value() & 0x1f) << 16); | |
1655 instruction |= ((rb.value() & 0x1f) << 11); | |
1656 emitInt(instruction); | |
1657 } | |
1658 | |
1659 /** | |
1660 * Pseudo-external assembler syntax: {@code addco }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1661 * Example disassembly syntax: {@code addco r0, r0, r0} | |
1662 * | |
1663 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1664 */ | |
1665 // Template#: 86, Serial#: 86 | |
1666 public void addco(final GPR rt, final GPR ra, final GPR rb) { | |
1667 int instruction = 0x7C000414; | |
1668 instruction |= ((rt.value() & 0x1f) << 21); | |
1669 instruction |= ((ra.value() & 0x1f) << 16); | |
1670 instruction |= ((rb.value() & 0x1f) << 11); | |
1671 emitInt(instruction); | |
1672 } | |
1673 | |
1674 /** | |
1675 * Pseudo-external assembler syntax: {@code addco. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1676 * Example disassembly syntax: {@code addco. r0, r0, r0} | |
1677 * | |
1678 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1679 */ | |
1680 // Template#: 87, Serial#: 87 | |
1681 public void addco_(final GPR rt, final GPR ra, final GPR rb) { | |
1682 int instruction = 0x7C000415; | |
1683 instruction |= ((rt.value() & 0x1f) << 21); | |
1684 instruction |= ((ra.value() & 0x1f) << 16); | |
1685 instruction |= ((rb.value() & 0x1f) << 11); | |
1686 emitInt(instruction); | |
1687 } | |
1688 | |
1689 /** | |
1690 * Pseudo-external assembler syntax: {@code subfc }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1691 * Example disassembly syntax: {@code subfc r0, r0, r0} | |
1692 * | |
1693 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1694 */ | |
1695 // Template#: 88, Serial#: 88 | |
1696 public void subfc(final GPR rt, final GPR ra, final GPR rb) { | |
1697 int instruction = 0x7C000010; | |
1698 instruction |= ((rt.value() & 0x1f) << 21); | |
1699 instruction |= ((ra.value() & 0x1f) << 16); | |
1700 instruction |= ((rb.value() & 0x1f) << 11); | |
1701 emitInt(instruction); | |
1702 } | |
1703 | |
1704 /** | |
1705 * Pseudo-external assembler syntax: {@code subfc. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1706 * Example disassembly syntax: {@code subfc. r0, r0, r0} | |
1707 * | |
1708 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1709 */ | |
1710 // Template#: 89, Serial#: 89 | |
1711 public void subfc_(final GPR rt, final GPR ra, final GPR rb) { | |
1712 int instruction = 0x7C000011; | |
1713 instruction |= ((rt.value() & 0x1f) << 21); | |
1714 instruction |= ((ra.value() & 0x1f) << 16); | |
1715 instruction |= ((rb.value() & 0x1f) << 11); | |
1716 emitInt(instruction); | |
1717 } | |
1718 | |
1719 /** | |
1720 * Pseudo-external assembler syntax: {@code subfco }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1721 * Example disassembly syntax: {@code subfco r0, r0, r0} | |
1722 * | |
1723 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1724 */ | |
1725 // Template#: 90, Serial#: 90 | |
1726 public void subfco(final GPR rt, final GPR ra, final GPR rb) { | |
1727 int instruction = 0x7C000410; | |
1728 instruction |= ((rt.value() & 0x1f) << 21); | |
1729 instruction |= ((ra.value() & 0x1f) << 16); | |
1730 instruction |= ((rb.value() & 0x1f) << 11); | |
1731 emitInt(instruction); | |
1732 } | |
1733 | |
1734 /** | |
1735 * Pseudo-external assembler syntax: {@code subfco. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1736 * Example disassembly syntax: {@code subfco. r0, r0, r0} | |
1737 * | |
1738 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1739 */ | |
1740 // Template#: 91, Serial#: 91 | |
1741 public void subfco_(final GPR rt, final GPR ra, final GPR rb) { | |
1742 int instruction = 0x7C000411; | |
1743 instruction |= ((rt.value() & 0x1f) << 21); | |
1744 instruction |= ((ra.value() & 0x1f) << 16); | |
1745 instruction |= ((rb.value() & 0x1f) << 11); | |
1746 emitInt(instruction); | |
1747 } | |
1748 | |
1749 /** | |
1750 * Pseudo-external assembler syntax: {@code adde }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1751 * Example disassembly syntax: {@code adde r0, r0, r0} | |
1752 * | |
1753 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1754 */ | |
1755 // Template#: 92, Serial#: 92 | |
1756 public void adde(final GPR rt, final GPR ra, final GPR rb) { | |
1757 int instruction = 0x7C000114; | |
1758 instruction |= ((rt.value() & 0x1f) << 21); | |
1759 instruction |= ((ra.value() & 0x1f) << 16); | |
1760 instruction |= ((rb.value() & 0x1f) << 11); | |
1761 emitInt(instruction); | |
1762 } | |
1763 | |
1764 /** | |
1765 * Pseudo-external assembler syntax: {@code adde. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1766 * Example disassembly syntax: {@code adde. r0, r0, r0} | |
1767 * | |
1768 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1769 */ | |
1770 // Template#: 93, Serial#: 93 | |
1771 public void adde_(final GPR rt, final GPR ra, final GPR rb) { | |
1772 int instruction = 0x7C000115; | |
1773 instruction |= ((rt.value() & 0x1f) << 21); | |
1774 instruction |= ((ra.value() & 0x1f) << 16); | |
1775 instruction |= ((rb.value() & 0x1f) << 11); | |
1776 emitInt(instruction); | |
1777 } | |
1778 | |
1779 /** | |
1780 * Pseudo-external assembler syntax: {@code addeo }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1781 * Example disassembly syntax: {@code addeo r0, r0, r0} | |
1782 * | |
1783 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1784 */ | |
1785 // Template#: 94, Serial#: 94 | |
1786 public void addeo(final GPR rt, final GPR ra, final GPR rb) { | |
1787 int instruction = 0x7C000514; | |
1788 instruction |= ((rt.value() & 0x1f) << 21); | |
1789 instruction |= ((ra.value() & 0x1f) << 16); | |
1790 instruction |= ((rb.value() & 0x1f) << 11); | |
1791 emitInt(instruction); | |
1792 } | |
1793 | |
1794 /** | |
1795 * Pseudo-external assembler syntax: {@code addeo. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1796 * Example disassembly syntax: {@code addeo. r0, r0, r0} | |
1797 * | |
1798 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1799 */ | |
1800 // Template#: 95, Serial#: 95 | |
1801 public void addeo_(final GPR rt, final GPR ra, final GPR rb) { | |
1802 int instruction = 0x7C000515; | |
1803 instruction |= ((rt.value() & 0x1f) << 21); | |
1804 instruction |= ((ra.value() & 0x1f) << 16); | |
1805 instruction |= ((rb.value() & 0x1f) << 11); | |
1806 emitInt(instruction); | |
1807 } | |
1808 | |
1809 /** | |
1810 * Pseudo-external assembler syntax: {@code subfe }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1811 * Example disassembly syntax: {@code subfe r0, r0, r0} | |
1812 * | |
1813 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1814 */ | |
1815 // Template#: 96, Serial#: 96 | |
1816 public void subfe(final GPR rt, final GPR ra, final GPR rb) { | |
1817 int instruction = 0x7C000110; | |
1818 instruction |= ((rt.value() & 0x1f) << 21); | |
1819 instruction |= ((ra.value() & 0x1f) << 16); | |
1820 instruction |= ((rb.value() & 0x1f) << 11); | |
1821 emitInt(instruction); | |
1822 } | |
1823 | |
1824 /** | |
1825 * Pseudo-external assembler syntax: {@code subfe. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1826 * Example disassembly syntax: {@code subfe. r0, r0, r0} | |
1827 * | |
1828 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1829 */ | |
1830 // Template#: 97, Serial#: 97 | |
1831 public void subfe_(final GPR rt, final GPR ra, final GPR rb) { | |
1832 int instruction = 0x7C000111; | |
1833 instruction |= ((rt.value() & 0x1f) << 21); | |
1834 instruction |= ((ra.value() & 0x1f) << 16); | |
1835 instruction |= ((rb.value() & 0x1f) << 11); | |
1836 emitInt(instruction); | |
1837 } | |
1838 | |
1839 /** | |
1840 * Pseudo-external assembler syntax: {@code subfeo }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1841 * Example disassembly syntax: {@code subfeo r0, r0, r0} | |
1842 * | |
1843 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1844 */ | |
1845 // Template#: 98, Serial#: 98 | |
1846 public void subfeo(final GPR rt, final GPR ra, final GPR rb) { | |
1847 int instruction = 0x7C000510; | |
1848 instruction |= ((rt.value() & 0x1f) << 21); | |
1849 instruction |= ((ra.value() & 0x1f) << 16); | |
1850 instruction |= ((rb.value() & 0x1f) << 11); | |
1851 emitInt(instruction); | |
1852 } | |
1853 | |
1854 /** | |
1855 * Pseudo-external assembler syntax: {@code subfeo. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
1856 * Example disassembly syntax: {@code subfeo. r0, r0, r0} | |
1857 * | |
1858 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1859 */ | |
1860 // Template#: 99, Serial#: 99 | |
1861 public void subfeo_(final GPR rt, final GPR ra, final GPR rb) { | |
1862 int instruction = 0x7C000511; | |
1863 instruction |= ((rt.value() & 0x1f) << 21); | |
1864 instruction |= ((ra.value() & 0x1f) << 16); | |
1865 instruction |= ((rb.value() & 0x1f) << 11); | |
1866 emitInt(instruction); | |
1867 } | |
1868 | |
1869 /** | |
1870 * Pseudo-external assembler syntax: {@code addme }<i>rt</i>, <i>ra</i> | |
1871 * Example disassembly syntax: {@code addme r0, r0} | |
1872 * | |
1873 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1874 */ | |
1875 // Template#: 100, Serial#: 100 | |
1876 public void addme(final GPR rt, final GPR ra) { | |
1877 int instruction = 0x7C0001D4; | |
1878 instruction |= ((rt.value() & 0x1f) << 21); | |
1879 instruction |= ((ra.value() & 0x1f) << 16); | |
1880 emitInt(instruction); | |
1881 } | |
1882 | |
1883 /** | |
1884 * Pseudo-external assembler syntax: {@code addme. }<i>rt</i>, <i>ra</i> | |
1885 * Example disassembly syntax: {@code addme. r0, r0} | |
1886 * | |
1887 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1888 */ | |
1889 // Template#: 101, Serial#: 101 | |
1890 public void addme_(final GPR rt, final GPR ra) { | |
1891 int instruction = 0x7C0001D5; | |
1892 instruction |= ((rt.value() & 0x1f) << 21); | |
1893 instruction |= ((ra.value() & 0x1f) << 16); | |
1894 emitInt(instruction); | |
1895 } | |
1896 | |
1897 /** | |
1898 * Pseudo-external assembler syntax: {@code addmeo }<i>rt</i>, <i>ra</i> | |
1899 * Example disassembly syntax: {@code addmeo r0, r0} | |
1900 * | |
1901 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1902 */ | |
1903 // Template#: 102, Serial#: 102 | |
1904 public void addmeo(final GPR rt, final GPR ra) { | |
1905 int instruction = 0x7C0005D4; | |
1906 instruction |= ((rt.value() & 0x1f) << 21); | |
1907 instruction |= ((ra.value() & 0x1f) << 16); | |
1908 emitInt(instruction); | |
1909 } | |
1910 | |
1911 /** | |
1912 * Pseudo-external assembler syntax: {@code addmeo. }<i>rt</i>, <i>ra</i> | |
1913 * Example disassembly syntax: {@code addmeo. r0, r0} | |
1914 * | |
1915 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1916 */ | |
1917 // Template#: 103, Serial#: 103 | |
1918 public void addmeo_(final GPR rt, final GPR ra) { | |
1919 int instruction = 0x7C0005D5; | |
1920 instruction |= ((rt.value() & 0x1f) << 21); | |
1921 instruction |= ((ra.value() & 0x1f) << 16); | |
1922 emitInt(instruction); | |
1923 } | |
1924 | |
1925 /** | |
1926 * Pseudo-external assembler syntax: {@code subfme }<i>rt</i>, <i>ra</i> | |
1927 * Example disassembly syntax: {@code subfme r0, r0} | |
1928 * | |
1929 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1930 */ | |
1931 // Template#: 104, Serial#: 104 | |
1932 public void subfme(final GPR rt, final GPR ra) { | |
1933 int instruction = 0x7C0001D0; | |
1934 instruction |= ((rt.value() & 0x1f) << 21); | |
1935 instruction |= ((ra.value() & 0x1f) << 16); | |
1936 emitInt(instruction); | |
1937 } | |
1938 | |
1939 /** | |
1940 * Pseudo-external assembler syntax: {@code subfme. }<i>rt</i>, <i>ra</i> | |
1941 * Example disassembly syntax: {@code subfme. r0, r0} | |
1942 * | |
1943 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1944 */ | |
1945 // Template#: 105, Serial#: 105 | |
1946 public void subfme_(final GPR rt, final GPR ra) { | |
1947 int instruction = 0x7C0001D1; | |
1948 instruction |= ((rt.value() & 0x1f) << 21); | |
1949 instruction |= ((ra.value() & 0x1f) << 16); | |
1950 emitInt(instruction); | |
1951 } | |
1952 | |
1953 /** | |
1954 * Pseudo-external assembler syntax: {@code subfmeo }<i>rt</i>, <i>ra</i> | |
1955 * Example disassembly syntax: {@code subfmeo r0, r0} | |
1956 * | |
1957 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1958 */ | |
1959 // Template#: 106, Serial#: 106 | |
1960 public void subfmeo(final GPR rt, final GPR ra) { | |
1961 int instruction = 0x7C0005D0; | |
1962 instruction |= ((rt.value() & 0x1f) << 21); | |
1963 instruction |= ((ra.value() & 0x1f) << 16); | |
1964 emitInt(instruction); | |
1965 } | |
1966 | |
1967 /** | |
1968 * Pseudo-external assembler syntax: {@code subfmeo. }<i>rt</i>, <i>ra</i> | |
1969 * Example disassembly syntax: {@code subfmeo. r0, r0} | |
1970 * | |
1971 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1972 */ | |
1973 // Template#: 107, Serial#: 107 | |
1974 public void subfmeo_(final GPR rt, final GPR ra) { | |
1975 int instruction = 0x7C0005D1; | |
1976 instruction |= ((rt.value() & 0x1f) << 21); | |
1977 instruction |= ((ra.value() & 0x1f) << 16); | |
1978 emitInt(instruction); | |
1979 } | |
1980 | |
1981 /** | |
1982 * Pseudo-external assembler syntax: {@code addze }<i>rt</i>, <i>ra</i> | |
1983 * Example disassembly syntax: {@code addze r0, r0} | |
1984 * | |
1985 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
1986 */ | |
1987 // Template#: 108, Serial#: 108 | |
1988 public void addze(final GPR rt, final GPR ra) { | |
1989 int instruction = 0x7C000194; | |
1990 instruction |= ((rt.value() & 0x1f) << 21); | |
1991 instruction |= ((ra.value() & 0x1f) << 16); | |
1992 emitInt(instruction); | |
1993 } | |
1994 | |
1995 /** | |
1996 * Pseudo-external assembler syntax: {@code addze. }<i>rt</i>, <i>ra</i> | |
1997 * Example disassembly syntax: {@code addze. r0, r0} | |
1998 * | |
1999 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2000 */ | |
2001 // Template#: 109, Serial#: 109 | |
2002 public void addze_(final GPR rt, final GPR ra) { | |
2003 int instruction = 0x7C000195; | |
2004 instruction |= ((rt.value() & 0x1f) << 21); | |
2005 instruction |= ((ra.value() & 0x1f) << 16); | |
2006 emitInt(instruction); | |
2007 } | |
2008 | |
2009 /** | |
2010 * Pseudo-external assembler syntax: {@code addzeo }<i>rt</i>, <i>ra</i> | |
2011 * Example disassembly syntax: {@code addzeo r0, r0} | |
2012 * | |
2013 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2014 */ | |
2015 // Template#: 110, Serial#: 110 | |
2016 public void addzeo(final GPR rt, final GPR ra) { | |
2017 int instruction = 0x7C000594; | |
2018 instruction |= ((rt.value() & 0x1f) << 21); | |
2019 instruction |= ((ra.value() & 0x1f) << 16); | |
2020 emitInt(instruction); | |
2021 } | |
2022 | |
2023 /** | |
2024 * Pseudo-external assembler syntax: {@code addzeo. }<i>rt</i>, <i>ra</i> | |
2025 * Example disassembly syntax: {@code addzeo. r0, r0} | |
2026 * | |
2027 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2028 */ | |
2029 // Template#: 111, Serial#: 111 | |
2030 public void addzeo_(final GPR rt, final GPR ra) { | |
2031 int instruction = 0x7C000595; | |
2032 instruction |= ((rt.value() & 0x1f) << 21); | |
2033 instruction |= ((ra.value() & 0x1f) << 16); | |
2034 emitInt(instruction); | |
2035 } | |
2036 | |
2037 /** | |
2038 * Pseudo-external assembler syntax: {@code subfze }<i>rt</i>, <i>ra</i> | |
2039 * Example disassembly syntax: {@code subfze r0, r0} | |
2040 * | |
2041 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2042 */ | |
2043 // Template#: 112, Serial#: 112 | |
2044 public void subfze(final GPR rt, final GPR ra) { | |
2045 int instruction = 0x7C000190; | |
2046 instruction |= ((rt.value() & 0x1f) << 21); | |
2047 instruction |= ((ra.value() & 0x1f) << 16); | |
2048 emitInt(instruction); | |
2049 } | |
2050 | |
2051 /** | |
2052 * Pseudo-external assembler syntax: {@code subfze. }<i>rt</i>, <i>ra</i> | |
2053 * Example disassembly syntax: {@code subfze. r0, r0} | |
2054 * | |
2055 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2056 */ | |
2057 // Template#: 113, Serial#: 113 | |
2058 public void subfze_(final GPR rt, final GPR ra) { | |
2059 int instruction = 0x7C000191; | |
2060 instruction |= ((rt.value() & 0x1f) << 21); | |
2061 instruction |= ((ra.value() & 0x1f) << 16); | |
2062 emitInt(instruction); | |
2063 } | |
2064 | |
2065 /** | |
2066 * Pseudo-external assembler syntax: {@code subfzeo }<i>rt</i>, <i>ra</i> | |
2067 * Example disassembly syntax: {@code subfzeo r0, r0} | |
2068 * | |
2069 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2070 */ | |
2071 // Template#: 114, Serial#: 114 | |
2072 public void subfzeo(final GPR rt, final GPR ra) { | |
2073 int instruction = 0x7C000590; | |
2074 instruction |= ((rt.value() & 0x1f) << 21); | |
2075 instruction |= ((ra.value() & 0x1f) << 16); | |
2076 emitInt(instruction); | |
2077 } | |
2078 | |
2079 /** | |
2080 * Pseudo-external assembler syntax: {@code subfzeo. }<i>rt</i>, <i>ra</i> | |
2081 * Example disassembly syntax: {@code subfzeo. r0, r0} | |
2082 * | |
2083 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2084 */ | |
2085 // Template#: 115, Serial#: 115 | |
2086 public void subfzeo_(final GPR rt, final GPR ra) { | |
2087 int instruction = 0x7C000591; | |
2088 instruction |= ((rt.value() & 0x1f) << 21); | |
2089 instruction |= ((ra.value() & 0x1f) << 16); | |
2090 emitInt(instruction); | |
2091 } | |
2092 | |
2093 /** | |
2094 * Pseudo-external assembler syntax: {@code neg }<i>rt</i>, <i>ra</i> | |
2095 * Example disassembly syntax: {@code neg r0, r0} | |
2096 * | |
2097 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2098 */ | |
2099 // Template#: 116, Serial#: 116 | |
2100 public void neg(final GPR rt, final GPR ra) { | |
2101 int instruction = 0x7C0000D0; | |
2102 instruction |= ((rt.value() & 0x1f) << 21); | |
2103 instruction |= ((ra.value() & 0x1f) << 16); | |
2104 emitInt(instruction); | |
2105 } | |
2106 | |
2107 /** | |
2108 * Pseudo-external assembler syntax: {@code neg. }<i>rt</i>, <i>ra</i> | |
2109 * Example disassembly syntax: {@code neg. r0, r0} | |
2110 * | |
2111 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2112 */ | |
2113 // Template#: 117, Serial#: 117 | |
2114 public void neg_(final GPR rt, final GPR ra) { | |
2115 int instruction = 0x7C0000D1; | |
2116 instruction |= ((rt.value() & 0x1f) << 21); | |
2117 instruction |= ((ra.value() & 0x1f) << 16); | |
2118 emitInt(instruction); | |
2119 } | |
2120 | |
2121 /** | |
2122 * Pseudo-external assembler syntax: {@code nego }<i>rt</i>, <i>ra</i> | |
2123 * Example disassembly syntax: {@code nego r0, r0} | |
2124 * | |
2125 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2126 */ | |
2127 // Template#: 118, Serial#: 118 | |
2128 public void nego(final GPR rt, final GPR ra) { | |
2129 int instruction = 0x7C0004D0; | |
2130 instruction |= ((rt.value() & 0x1f) << 21); | |
2131 instruction |= ((ra.value() & 0x1f) << 16); | |
2132 emitInt(instruction); | |
2133 } | |
2134 | |
2135 /** | |
2136 * Pseudo-external assembler syntax: {@code nego. }<i>rt</i>, <i>ra</i> | |
2137 * Example disassembly syntax: {@code nego. r0, r0} | |
2138 * | |
2139 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2140 */ | |
2141 // Template#: 119, Serial#: 119 | |
2142 public void nego_(final GPR rt, final GPR ra) { | |
2143 int instruction = 0x7C0004D1; | |
2144 instruction |= ((rt.value() & 0x1f) << 21); | |
2145 instruction |= ((ra.value() & 0x1f) << 16); | |
2146 emitInt(instruction); | |
2147 } | |
2148 | |
2149 /** | |
2150 * Pseudo-external assembler syntax: {@code mulli }<i>rt</i>, <i>ra</i>, <i>si</i> | |
2151 * Example disassembly syntax: {@code mulli r0, r0, -32768} | |
2152 * <p> | |
2153 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
2154 * | |
2155 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2156 */ | |
2157 // Template#: 120, Serial#: 120 | |
2158 public void mulli(final GPR rt, final GPR ra, final int si) { | |
2159 int instruction = 0x1C000000; | |
2160 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
2161 instruction |= ((rt.value() & 0x1f) << 21); | |
2162 instruction |= ((ra.value() & 0x1f) << 16); | |
2163 instruction |= (si & 0xffff); | |
2164 emitInt(instruction); | |
2165 } | |
2166 | |
2167 /** | |
2168 * Pseudo-external assembler syntax: {@code mulld }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2169 * Example disassembly syntax: {@code mulld r0, r0, r0} | |
2170 * | |
2171 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2172 */ | |
2173 // Template#: 121, Serial#: 121 | |
2174 public void mulld(final GPR rt, final GPR ra, final GPR rb) { | |
2175 int instruction = 0x7C0001D2; | |
2176 instruction |= ((rt.value() & 0x1f) << 21); | |
2177 instruction |= ((ra.value() & 0x1f) << 16); | |
2178 instruction |= ((rb.value() & 0x1f) << 11); | |
2179 emitInt(instruction); | |
2180 } | |
2181 | |
2182 /** | |
2183 * Pseudo-external assembler syntax: {@code mulld. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2184 * Example disassembly syntax: {@code mulld. r0, r0, r0} | |
2185 * | |
2186 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2187 */ | |
2188 // Template#: 122, Serial#: 122 | |
2189 public void mulld_(final GPR rt, final GPR ra, final GPR rb) { | |
2190 int instruction = 0x7C0001D3; | |
2191 instruction |= ((rt.value() & 0x1f) << 21); | |
2192 instruction |= ((ra.value() & 0x1f) << 16); | |
2193 instruction |= ((rb.value() & 0x1f) << 11); | |
2194 emitInt(instruction); | |
2195 } | |
2196 | |
2197 /** | |
2198 * Pseudo-external assembler syntax: {@code mulldo }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2199 * Example disassembly syntax: {@code mulldo r0, r0, r0} | |
2200 * | |
2201 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2202 */ | |
2203 // Template#: 123, Serial#: 123 | |
2204 public void mulldo(final GPR rt, final GPR ra, final GPR rb) { | |
2205 int instruction = 0x7C0005D2; | |
2206 instruction |= ((rt.value() & 0x1f) << 21); | |
2207 instruction |= ((ra.value() & 0x1f) << 16); | |
2208 instruction |= ((rb.value() & 0x1f) << 11); | |
2209 emitInt(instruction); | |
2210 } | |
2211 | |
2212 /** | |
2213 * Pseudo-external assembler syntax: {@code mulldo. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2214 * Example disassembly syntax: {@code mulldo. r0, r0, r0} | |
2215 * | |
2216 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2217 */ | |
2218 // Template#: 124, Serial#: 124 | |
2219 public void mulldo_(final GPR rt, final GPR ra, final GPR rb) { | |
2220 int instruction = 0x7C0005D3; | |
2221 instruction |= ((rt.value() & 0x1f) << 21); | |
2222 instruction |= ((ra.value() & 0x1f) << 16); | |
2223 instruction |= ((rb.value() & 0x1f) << 11); | |
2224 emitInt(instruction); | |
2225 } | |
2226 | |
2227 /** | |
2228 * Pseudo-external assembler syntax: {@code mullw }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2229 * Example disassembly syntax: {@code mullw r0, r0, r0} | |
2230 * | |
2231 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2232 */ | |
2233 // Template#: 125, Serial#: 125 | |
2234 public void mullw(final GPR rt, final GPR ra, final GPR rb) { | |
2235 int instruction = 0x7C0001D6; | |
2236 instruction |= ((rt.value() & 0x1f) << 21); | |
2237 instruction |= ((ra.value() & 0x1f) << 16); | |
2238 instruction |= ((rb.value() & 0x1f) << 11); | |
2239 emitInt(instruction); | |
2240 } | |
2241 | |
2242 /** | |
2243 * Pseudo-external assembler syntax: {@code mullw. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2244 * Example disassembly syntax: {@code mullw. r0, r0, r0} | |
2245 * | |
2246 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2247 */ | |
2248 // Template#: 126, Serial#: 126 | |
2249 public void mullw_(final GPR rt, final GPR ra, final GPR rb) { | |
2250 int instruction = 0x7C0001D7; | |
2251 instruction |= ((rt.value() & 0x1f) << 21); | |
2252 instruction |= ((ra.value() & 0x1f) << 16); | |
2253 instruction |= ((rb.value() & 0x1f) << 11); | |
2254 emitInt(instruction); | |
2255 } | |
2256 | |
2257 /** | |
2258 * Pseudo-external assembler syntax: {@code mullwo }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2259 * Example disassembly syntax: {@code mullwo r0, r0, r0} | |
2260 * | |
2261 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2262 */ | |
2263 // Template#: 127, Serial#: 127 | |
2264 public void mullwo(final GPR rt, final GPR ra, final GPR rb) { | |
2265 int instruction = 0x7C0005D6; | |
2266 instruction |= ((rt.value() & 0x1f) << 21); | |
2267 instruction |= ((ra.value() & 0x1f) << 16); | |
2268 instruction |= ((rb.value() & 0x1f) << 11); | |
2269 emitInt(instruction); | |
2270 } | |
2271 | |
2272 /** | |
2273 * Pseudo-external assembler syntax: {@code mullwo. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2274 * Example disassembly syntax: {@code mullwo. r0, r0, r0} | |
2275 * | |
2276 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2277 */ | |
2278 // Template#: 128, Serial#: 128 | |
2279 public void mullwo_(final GPR rt, final GPR ra, final GPR rb) { | |
2280 int instruction = 0x7C0005D7; | |
2281 instruction |= ((rt.value() & 0x1f) << 21); | |
2282 instruction |= ((ra.value() & 0x1f) << 16); | |
2283 instruction |= ((rb.value() & 0x1f) << 11); | |
2284 emitInt(instruction); | |
2285 } | |
2286 | |
2287 /** | |
2288 * Pseudo-external assembler syntax: {@code mulhd }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2289 * Example disassembly syntax: {@code mulhd r0, r0, r0} | |
2290 * | |
2291 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2292 */ | |
2293 // Template#: 129, Serial#: 129 | |
2294 public void mulhd(final GPR rt, final GPR ra, final GPR rb) { | |
2295 int instruction = 0x7C000092; | |
2296 instruction |= ((rt.value() & 0x1f) << 21); | |
2297 instruction |= ((ra.value() & 0x1f) << 16); | |
2298 instruction |= ((rb.value() & 0x1f) << 11); | |
2299 emitInt(instruction); | |
2300 } | |
2301 | |
2302 /** | |
2303 * Pseudo-external assembler syntax: {@code mulhd. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2304 * Example disassembly syntax: {@code mulhd. r0, r0, r0} | |
2305 * | |
2306 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2307 */ | |
2308 // Template#: 130, Serial#: 130 | |
2309 public void mulhd_(final GPR rt, final GPR ra, final GPR rb) { | |
2310 int instruction = 0x7C000093; | |
2311 instruction |= ((rt.value() & 0x1f) << 21); | |
2312 instruction |= ((ra.value() & 0x1f) << 16); | |
2313 instruction |= ((rb.value() & 0x1f) << 11); | |
2314 emitInt(instruction); | |
2315 } | |
2316 | |
2317 /** | |
2318 * Pseudo-external assembler syntax: {@code mulhw }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2319 * Example disassembly syntax: {@code mulhw r0, r0, r0} | |
2320 * | |
2321 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2322 */ | |
2323 // Template#: 131, Serial#: 131 | |
2324 public void mulhw(final GPR rt, final GPR ra, final GPR rb) { | |
2325 int instruction = 0x7C000096; | |
2326 instruction |= ((rt.value() & 0x1f) << 21); | |
2327 instruction |= ((ra.value() & 0x1f) << 16); | |
2328 instruction |= ((rb.value() & 0x1f) << 11); | |
2329 emitInt(instruction); | |
2330 } | |
2331 | |
2332 /** | |
2333 * Pseudo-external assembler syntax: {@code mulhw. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2334 * Example disassembly syntax: {@code mulhw. r0, r0, r0} | |
2335 * | |
2336 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2337 */ | |
2338 // Template#: 132, Serial#: 132 | |
2339 public void mulhw_(final GPR rt, final GPR ra, final GPR rb) { | |
2340 int instruction = 0x7C000097; | |
2341 instruction |= ((rt.value() & 0x1f) << 21); | |
2342 instruction |= ((ra.value() & 0x1f) << 16); | |
2343 instruction |= ((rb.value() & 0x1f) << 11); | |
2344 emitInt(instruction); | |
2345 } | |
2346 | |
2347 /** | |
2348 * Pseudo-external assembler syntax: {@code mulhdu }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2349 * Example disassembly syntax: {@code mulhdu r0, r0, r0} | |
2350 * | |
2351 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2352 */ | |
2353 // Template#: 133, Serial#: 133 | |
2354 public void mulhdu(final GPR rt, final GPR ra, final GPR rb) { | |
2355 int instruction = 0x7C000012; | |
2356 instruction |= ((rt.value() & 0x1f) << 21); | |
2357 instruction |= ((ra.value() & 0x1f) << 16); | |
2358 instruction |= ((rb.value() & 0x1f) << 11); | |
2359 emitInt(instruction); | |
2360 } | |
2361 | |
2362 /** | |
2363 * Pseudo-external assembler syntax: {@code mulhdu. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2364 * Example disassembly syntax: {@code mulhdu. r0, r0, r0} | |
2365 * | |
2366 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2367 */ | |
2368 // Template#: 134, Serial#: 134 | |
2369 public void mulhdu_(final GPR rt, final GPR ra, final GPR rb) { | |
2370 int instruction = 0x7C000013; | |
2371 instruction |= ((rt.value() & 0x1f) << 21); | |
2372 instruction |= ((ra.value() & 0x1f) << 16); | |
2373 instruction |= ((rb.value() & 0x1f) << 11); | |
2374 emitInt(instruction); | |
2375 } | |
2376 | |
2377 /** | |
2378 * Pseudo-external assembler syntax: {@code mulhwu }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2379 * Example disassembly syntax: {@code mulhwu r0, r0, r0} | |
2380 * | |
2381 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2382 */ | |
2383 // Template#: 135, Serial#: 135 | |
2384 public void mulhwu(final GPR rt, final GPR ra, final GPR rb) { | |
2385 int instruction = 0x7C000016; | |
2386 instruction |= ((rt.value() & 0x1f) << 21); | |
2387 instruction |= ((ra.value() & 0x1f) << 16); | |
2388 instruction |= ((rb.value() & 0x1f) << 11); | |
2389 emitInt(instruction); | |
2390 } | |
2391 | |
2392 /** | |
2393 * Pseudo-external assembler syntax: {@code mulhwu. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2394 * Example disassembly syntax: {@code mulhwu. r0, r0, r0} | |
2395 * | |
2396 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2397 */ | |
2398 // Template#: 136, Serial#: 136 | |
2399 public void mulhwu_(final GPR rt, final GPR ra, final GPR rb) { | |
2400 int instruction = 0x7C000017; | |
2401 instruction |= ((rt.value() & 0x1f) << 21); | |
2402 instruction |= ((ra.value() & 0x1f) << 16); | |
2403 instruction |= ((rb.value() & 0x1f) << 11); | |
2404 emitInt(instruction); | |
2405 } | |
2406 | |
2407 /** | |
2408 * Pseudo-external assembler syntax: {@code divd }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2409 * Example disassembly syntax: {@code divd r0, r0, r0} | |
2410 * | |
2411 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2412 */ | |
2413 // Template#: 137, Serial#: 137 | |
2414 public void divd(final GPR rt, final GPR ra, final GPR rb) { | |
2415 int instruction = 0x7C0003D2; | |
2416 instruction |= ((rt.value() & 0x1f) << 21); | |
2417 instruction |= ((ra.value() & 0x1f) << 16); | |
2418 instruction |= ((rb.value() & 0x1f) << 11); | |
2419 emitInt(instruction); | |
2420 } | |
2421 | |
2422 /** | |
2423 * Pseudo-external assembler syntax: {@code divd. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2424 * Example disassembly syntax: {@code divd. r0, r0, r0} | |
2425 * | |
2426 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2427 */ | |
2428 // Template#: 138, Serial#: 138 | |
2429 public void divd_(final GPR rt, final GPR ra, final GPR rb) { | |
2430 int instruction = 0x7C0003D3; | |
2431 instruction |= ((rt.value() & 0x1f) << 21); | |
2432 instruction |= ((ra.value() & 0x1f) << 16); | |
2433 instruction |= ((rb.value() & 0x1f) << 11); | |
2434 emitInt(instruction); | |
2435 } | |
2436 | |
2437 /** | |
2438 * Pseudo-external assembler syntax: {@code divdo }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2439 * Example disassembly syntax: {@code divdo r0, r0, r0} | |
2440 * | |
2441 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2442 */ | |
2443 // Template#: 139, Serial#: 139 | |
2444 public void divdo(final GPR rt, final GPR ra, final GPR rb) { | |
2445 int instruction = 0x7C0007D2; | |
2446 instruction |= ((rt.value() & 0x1f) << 21); | |
2447 instruction |= ((ra.value() & 0x1f) << 16); | |
2448 instruction |= ((rb.value() & 0x1f) << 11); | |
2449 emitInt(instruction); | |
2450 } | |
2451 | |
2452 /** | |
2453 * Pseudo-external assembler syntax: {@code divdo. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2454 * Example disassembly syntax: {@code divdo. r0, r0, r0} | |
2455 * | |
2456 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2457 */ | |
2458 // Template#: 140, Serial#: 140 | |
2459 public void divdo_(final GPR rt, final GPR ra, final GPR rb) { | |
2460 int instruction = 0x7C0007D3; | |
2461 instruction |= ((rt.value() & 0x1f) << 21); | |
2462 instruction |= ((ra.value() & 0x1f) << 16); | |
2463 instruction |= ((rb.value() & 0x1f) << 11); | |
2464 emitInt(instruction); | |
2465 } | |
2466 | |
2467 /** | |
2468 * Pseudo-external assembler syntax: {@code divw }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2469 * Example disassembly syntax: {@code divw r0, r0, r0} | |
2470 * | |
2471 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2472 */ | |
2473 // Template#: 141, Serial#: 141 | |
2474 public void divw(final GPR rt, final GPR ra, final GPR rb) { | |
2475 int instruction = 0x7C0003D6; | |
2476 instruction |= ((rt.value() & 0x1f) << 21); | |
2477 instruction |= ((ra.value() & 0x1f) << 16); | |
2478 instruction |= ((rb.value() & 0x1f) << 11); | |
2479 emitInt(instruction); | |
2480 } | |
2481 | |
2482 /** | |
2483 * Pseudo-external assembler syntax: {@code divw. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2484 * Example disassembly syntax: {@code divw. r0, r0, r0} | |
2485 * | |
2486 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2487 */ | |
2488 // Template#: 142, Serial#: 142 | |
2489 public void divw_(final GPR rt, final GPR ra, final GPR rb) { | |
2490 int instruction = 0x7C0003D7; | |
2491 instruction |= ((rt.value() & 0x1f) << 21); | |
2492 instruction |= ((ra.value() & 0x1f) << 16); | |
2493 instruction |= ((rb.value() & 0x1f) << 11); | |
2494 emitInt(instruction); | |
2495 } | |
2496 | |
2497 /** | |
2498 * Pseudo-external assembler syntax: {@code divwo }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2499 * Example disassembly syntax: {@code divwo r0, r0, r0} | |
2500 * | |
2501 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2502 */ | |
2503 // Template#: 143, Serial#: 143 | |
2504 public void divwo(final GPR rt, final GPR ra, final GPR rb) { | |
2505 int instruction = 0x7C0007D6; | |
2506 instruction |= ((rt.value() & 0x1f) << 21); | |
2507 instruction |= ((ra.value() & 0x1f) << 16); | |
2508 instruction |= ((rb.value() & 0x1f) << 11); | |
2509 emitInt(instruction); | |
2510 } | |
2511 | |
2512 /** | |
2513 * Pseudo-external assembler syntax: {@code divwo. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2514 * Example disassembly syntax: {@code divwo. r0, r0, r0} | |
2515 * | |
2516 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2517 */ | |
2518 // Template#: 144, Serial#: 144 | |
2519 public void divwo_(final GPR rt, final GPR ra, final GPR rb) { | |
2520 int instruction = 0x7C0007D7; | |
2521 instruction |= ((rt.value() & 0x1f) << 21); | |
2522 instruction |= ((ra.value() & 0x1f) << 16); | |
2523 instruction |= ((rb.value() & 0x1f) << 11); | |
2524 emitInt(instruction); | |
2525 } | |
2526 | |
2527 /** | |
2528 * Pseudo-external assembler syntax: {@code divdu }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2529 * Example disassembly syntax: {@code divdu r0, r0, r0} | |
2530 * | |
2531 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2532 */ | |
2533 // Template#: 145, Serial#: 145 | |
2534 public void divdu(final GPR rt, final GPR ra, final GPR rb) { | |
2535 int instruction = 0x7C000392; | |
2536 instruction |= ((rt.value() & 0x1f) << 21); | |
2537 instruction |= ((ra.value() & 0x1f) << 16); | |
2538 instruction |= ((rb.value() & 0x1f) << 11); | |
2539 emitInt(instruction); | |
2540 } | |
2541 | |
2542 /** | |
2543 * Pseudo-external assembler syntax: {@code divdu. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2544 * Example disassembly syntax: {@code divdu. r0, r0, r0} | |
2545 * | |
2546 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2547 */ | |
2548 // Template#: 146, Serial#: 146 | |
2549 public void divdu_(final GPR rt, final GPR ra, final GPR rb) { | |
2550 int instruction = 0x7C000393; | |
2551 instruction |= ((rt.value() & 0x1f) << 21); | |
2552 instruction |= ((ra.value() & 0x1f) << 16); | |
2553 instruction |= ((rb.value() & 0x1f) << 11); | |
2554 emitInt(instruction); | |
2555 } | |
2556 | |
2557 /** | |
2558 * Pseudo-external assembler syntax: {@code divduo }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2559 * Example disassembly syntax: {@code divduo r0, r0, r0} | |
2560 * | |
2561 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2562 */ | |
2563 // Template#: 147, Serial#: 147 | |
2564 public void divduo(final GPR rt, final GPR ra, final GPR rb) { | |
2565 int instruction = 0x7C000792; | |
2566 instruction |= ((rt.value() & 0x1f) << 21); | |
2567 instruction |= ((ra.value() & 0x1f) << 16); | |
2568 instruction |= ((rb.value() & 0x1f) << 11); | |
2569 emitInt(instruction); | |
2570 } | |
2571 | |
2572 /** | |
2573 * Pseudo-external assembler syntax: {@code divduo. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2574 * Example disassembly syntax: {@code divduo. r0, r0, r0} | |
2575 * | |
2576 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2577 */ | |
2578 // Template#: 148, Serial#: 148 | |
2579 public void divduo_(final GPR rt, final GPR ra, final GPR rb) { | |
2580 int instruction = 0x7C000793; | |
2581 instruction |= ((rt.value() & 0x1f) << 21); | |
2582 instruction |= ((ra.value() & 0x1f) << 16); | |
2583 instruction |= ((rb.value() & 0x1f) << 11); | |
2584 emitInt(instruction); | |
2585 } | |
2586 | |
2587 /** | |
2588 * Pseudo-external assembler syntax: {@code divwu }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2589 * Example disassembly syntax: {@code divwu r0, r0, r0} | |
2590 * | |
2591 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2592 */ | |
2593 // Template#: 149, Serial#: 149 | |
2594 public void divwu(final GPR rt, final GPR ra, final GPR rb) { | |
2595 int instruction = 0x7C000396; | |
2596 instruction |= ((rt.value() & 0x1f) << 21); | |
2597 instruction |= ((ra.value() & 0x1f) << 16); | |
2598 instruction |= ((rb.value() & 0x1f) << 11); | |
2599 emitInt(instruction); | |
2600 } | |
2601 | |
2602 /** | |
2603 * Pseudo-external assembler syntax: {@code divwu. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2604 * Example disassembly syntax: {@code divwu. r0, r0, r0} | |
2605 * | |
2606 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2607 */ | |
2608 // Template#: 150, Serial#: 150 | |
2609 public void divwu_(final GPR rt, final GPR ra, final GPR rb) { | |
2610 int instruction = 0x7C000397; | |
2611 instruction |= ((rt.value() & 0x1f) << 21); | |
2612 instruction |= ((ra.value() & 0x1f) << 16); | |
2613 instruction |= ((rb.value() & 0x1f) << 11); | |
2614 emitInt(instruction); | |
2615 } | |
2616 | |
2617 /** | |
2618 * Pseudo-external assembler syntax: {@code divwuo }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2619 * Example disassembly syntax: {@code divwuo r0, r0, r0} | |
2620 * | |
2621 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2622 */ | |
2623 // Template#: 151, Serial#: 151 | |
2624 public void divwuo(final GPR rt, final GPR ra, final GPR rb) { | |
2625 int instruction = 0x7C000796; | |
2626 instruction |= ((rt.value() & 0x1f) << 21); | |
2627 instruction |= ((ra.value() & 0x1f) << 16); | |
2628 instruction |= ((rb.value() & 0x1f) << 11); | |
2629 emitInt(instruction); | |
2630 } | |
2631 | |
2632 /** | |
2633 * Pseudo-external assembler syntax: {@code divwuo. }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
2634 * Example disassembly syntax: {@code divwuo. r0, r0, r0} | |
2635 * | |
2636 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.8 [Book 1]" | |
2637 */ | |
2638 // Template#: 152, Serial#: 152 | |
2639 public void divwuo_(final GPR rt, final GPR ra, final GPR rb) { | |
2640 int instruction = 0x7C000797; | |
2641 instruction |= ((rt.value() & 0x1f) << 21); | |
2642 instruction |= ((ra.value() & 0x1f) << 16); | |
2643 instruction |= ((rb.value() & 0x1f) << 11); | |
2644 emitInt(instruction); | |
2645 } | |
2646 | |
2647 /** | |
2648 * Pseudo-external assembler syntax: {@code cmpi }<i>bf</i>, <i>l</i>, <i>ra</i>, <i>si</i> | |
2649 * Example disassembly syntax: {@code cmpi 0, 0x0, r0, -32768} | |
2650 * <p> | |
2651 * Constraint: {@code 0 <= l && l <= 1}<br /> | |
2652 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
2653 * | |
2654 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.9 [Book 1]" | |
2655 */ | |
2656 // Template#: 153, Serial#: 153 | |
2657 public void cmpi(final CRF bf, final int l, final GPR ra, final int si) { | |
2658 int instruction = 0x2C000000; | |
2659 checkConstraint(0 <= l && l <= 1, "0 <= l && l <= 1"); | |
2660 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
2661 instruction |= ((bf.value() & 0x7) << 23); | |
2662 instruction |= ((l & 0x1) << 21); | |
2663 instruction |= ((ra.value() & 0x1f) << 16); | |
2664 instruction |= (si & 0xffff); | |
2665 emitInt(instruction); | |
2666 } | |
2667 | |
2668 /** | |
2669 * Pseudo-external assembler syntax: {@code cmp }<i>bf</i>, <i>l</i>, <i>ra</i>, <i>rb</i> | |
2670 * Example disassembly syntax: {@code cmp 0, 0x0, r0, r0} | |
2671 * <p> | |
2672 * Constraint: {@code 0 <= l && l <= 1}<br /> | |
2673 * | |
2674 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.9 [Book 1]" | |
2675 */ | |
2676 // Template#: 154, Serial#: 154 | |
2677 public void cmp(final CRF bf, final int l, final GPR ra, final GPR rb) { | |
2678 int instruction = 0x7C000000; | |
2679 checkConstraint(0 <= l && l <= 1, "0 <= l && l <= 1"); | |
2680 instruction |= ((bf.value() & 0x7) << 23); | |
2681 instruction |= ((l & 0x1) << 21); | |
2682 instruction |= ((ra.value() & 0x1f) << 16); | |
2683 instruction |= ((rb.value() & 0x1f) << 11); | |
2684 emitInt(instruction); | |
2685 } | |
2686 | |
2687 /** | |
2688 * Pseudo-external assembler syntax: {@code cmpli }<i>bf</i>, <i>l</i>, <i>ra</i>, <i>ui</i> | |
2689 * Example disassembly syntax: {@code cmpli 0, 0x0, r0, 0x0} | |
2690 * <p> | |
2691 * Constraint: {@code 0 <= l && l <= 1}<br /> | |
2692 * Constraint: {@code 0 <= ui && ui <= 65535}<br /> | |
2693 * | |
2694 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.9 [Book 1]" | |
2695 */ | |
2696 // Template#: 155, Serial#: 155 | |
2697 public void cmpli(final CRF bf, final int l, final GPR ra, final int ui) { | |
2698 int instruction = 0x28000000; | |
2699 checkConstraint(0 <= l && l <= 1, "0 <= l && l <= 1"); | |
2700 checkConstraint(0 <= ui && ui <= 65535, "0 <= ui && ui <= 65535"); | |
2701 instruction |= ((bf.value() & 0x7) << 23); | |
2702 instruction |= ((l & 0x1) << 21); | |
2703 instruction |= ((ra.value() & 0x1f) << 16); | |
2704 instruction |= (ui & 0xffff); | |
2705 emitInt(instruction); | |
2706 } | |
2707 | |
2708 /** | |
2709 * Pseudo-external assembler syntax: {@code cmpl }<i>bf</i>, <i>l</i>, <i>ra</i>, <i>rb</i> | |
2710 * Example disassembly syntax: {@code cmpl 0, 0x0, r0, r0} | |
2711 * <p> | |
2712 * Constraint: {@code 0 <= l && l <= 1}<br /> | |
2713 * | |
2714 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.9 [Book 1]" | |
2715 */ | |
2716 // Template#: 156, Serial#: 156 | |
2717 public void cmpl(final CRF bf, final int l, final GPR ra, final GPR rb) { | |
2718 int instruction = 0x7C000040; | |
2719 checkConstraint(0 <= l && l <= 1, "0 <= l && l <= 1"); | |
2720 instruction |= ((bf.value() & 0x7) << 23); | |
2721 instruction |= ((l & 0x1) << 21); | |
2722 instruction |= ((ra.value() & 0x1f) << 16); | |
2723 instruction |= ((rb.value() & 0x1f) << 11); | |
2724 emitInt(instruction); | |
2725 } | |
2726 | |
2727 /** | |
2728 * Pseudo-external assembler syntax: {@code tdi }<i>to</i>, <i>ra</i>, <i>si</i> | |
2729 * Example disassembly syntax: {@code tdi 0x0, r0, -32768} | |
2730 * <p> | |
2731 * Constraint: {@code 0 <= to && to <= 31}<br /> | |
2732 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
2733 * | |
2734 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.10 [Book 1]" | |
2735 */ | |
2736 // Template#: 157, Serial#: 157 | |
2737 public void tdi(final int to, final GPR ra, final int si) { | |
2738 int instruction = 0x08000000; | |
2739 checkConstraint(0 <= to && to <= 31, "0 <= to && to <= 31"); | |
2740 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
2741 instruction |= ((to & 0x1f) << 21); | |
2742 instruction |= ((ra.value() & 0x1f) << 16); | |
2743 instruction |= (si & 0xffff); | |
2744 emitInt(instruction); | |
2745 } | |
2746 | |
2747 /** | |
2748 * Pseudo-external assembler syntax: {@code twi }<i>to</i>, <i>ra</i>, <i>si</i> | |
2749 * Example disassembly syntax: {@code twi 0x0, r0, -32768} | |
2750 * <p> | |
2751 * Constraint: {@code 0 <= to && to <= 31}<br /> | |
2752 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
2753 * | |
2754 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.10 [Book 1]" | |
2755 */ | |
2756 // Template#: 158, Serial#: 158 | |
2757 public void twi(final int to, final GPR ra, final int si) { | |
2758 int instruction = 0x0C000000; | |
2759 checkConstraint(0 <= to && to <= 31, "0 <= to && to <= 31"); | |
2760 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
2761 instruction |= ((to & 0x1f) << 21); | |
2762 instruction |= ((ra.value() & 0x1f) << 16); | |
2763 instruction |= (si & 0xffff); | |
2764 emitInt(instruction); | |
2765 } | |
2766 | |
2767 /** | |
2768 * Pseudo-external assembler syntax: {@code td }<i>to</i>, <i>ra</i>, <i>rb</i> | |
2769 * Example disassembly syntax: {@code td 0x0, r0, r0} | |
2770 * <p> | |
2771 * Constraint: {@code 0 <= to && to <= 31}<br /> | |
2772 * | |
2773 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.10 [Book 1]" | |
2774 */ | |
2775 // Template#: 159, Serial#: 159 | |
2776 public void td(final int to, final GPR ra, final GPR rb) { | |
2777 int instruction = 0x7C000088; | |
2778 checkConstraint(0 <= to && to <= 31, "0 <= to && to <= 31"); | |
2779 instruction |= ((to & 0x1f) << 21); | |
2780 instruction |= ((ra.value() & 0x1f) << 16); | |
2781 instruction |= ((rb.value() & 0x1f) << 11); | |
2782 emitInt(instruction); | |
2783 } | |
2784 | |
2785 /** | |
2786 * Pseudo-external assembler syntax: {@code tw }<i>to</i>, <i>ra</i>, <i>rb</i> | |
2787 * Example disassembly syntax: {@code tw 0x0, r0, r0} | |
2788 * <p> | |
2789 * Constraint: {@code 0 <= to && to <= 31}<br /> | |
2790 * | |
2791 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.10 [Book 1]" | |
2792 */ | |
2793 // Template#: 160, Serial#: 160 | |
2794 public void tw(final int to, final GPR ra, final GPR rb) { | |
2795 int instruction = 0x7C000008; | |
2796 checkConstraint(0 <= to && to <= 31, "0 <= to && to <= 31"); | |
2797 instruction |= ((to & 0x1f) << 21); | |
2798 instruction |= ((ra.value() & 0x1f) << 16); | |
2799 instruction |= ((rb.value() & 0x1f) << 11); | |
2800 emitInt(instruction); | |
2801 } | |
2802 | |
2803 /** | |
2804 * Pseudo-external assembler syntax: {@code andi. }<i>ra</i>, <i>rs</i>, <i>ui</i> | |
2805 * Example disassembly syntax: {@code andi. r0, r0, 0x0} | |
2806 * <p> | |
2807 * Constraint: {@code 0 <= ui && ui <= 65535}<br /> | |
2808 * | |
2809 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
2810 */ | |
2811 // Template#: 161, Serial#: 161 | |
2812 public void andi_(final GPR ra, final GPR rs, final int ui) { | |
2813 int instruction = 0x70000000; | |
2814 checkConstraint(0 <= ui && ui <= 65535, "0 <= ui && ui <= 65535"); | |
2815 instruction |= ((ra.value() & 0x1f) << 16); | |
2816 instruction |= ((rs.value() & 0x1f) << 21); | |
2817 instruction |= (ui & 0xffff); | |
2818 emitInt(instruction); | |
2819 } | |
2820 | |
2821 /** | |
2822 * Pseudo-external assembler syntax: {@code andis. }<i>ra</i>, <i>rs</i>, <i>ui</i> | |
2823 * Example disassembly syntax: {@code andis. r0, r0, 0x0} | |
2824 * <p> | |
2825 * Constraint: {@code 0 <= ui && ui <= 65535}<br /> | |
2826 * | |
2827 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
2828 */ | |
2829 // Template#: 162, Serial#: 162 | |
2830 public void andis_(final GPR ra, final GPR rs, final int ui) { | |
2831 int instruction = 0x74000000; | |
2832 checkConstraint(0 <= ui && ui <= 65535, "0 <= ui && ui <= 65535"); | |
2833 instruction |= ((ra.value() & 0x1f) << 16); | |
2834 instruction |= ((rs.value() & 0x1f) << 21); | |
2835 instruction |= (ui & 0xffff); | |
2836 emitInt(instruction); | |
2837 } | |
2838 | |
2839 /** | |
2840 * Pseudo-external assembler syntax: {@code ori }<i>ra</i>, <i>rs</i>, <i>ui</i> | |
2841 * Example disassembly syntax: {@code ori r0, r0, 0x0} | |
2842 * <p> | |
2843 * Constraint: {@code 0 <= ui && ui <= 65535}<br /> | |
2844 * | |
2845 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
2846 */ | |
2847 // Template#: 163, Serial#: 163 | |
2848 public void ori(final GPR ra, final GPR rs, final int ui) { | |
2849 int instruction = 0x60000000; | |
2850 checkConstraint(0 <= ui && ui <= 65535, "0 <= ui && ui <= 65535"); | |
2851 instruction |= ((ra.value() & 0x1f) << 16); | |
2852 instruction |= ((rs.value() & 0x1f) << 21); | |
2853 instruction |= (ui & 0xffff); | |
2854 emitInt(instruction); | |
2855 } | |
2856 | |
2857 /** | |
2858 * Pseudo-external assembler syntax: {@code oris }<i>ra</i>, <i>rs</i>, <i>ui</i> | |
2859 * Example disassembly syntax: {@code oris r0, r0, 0x0} | |
2860 * <p> | |
2861 * Constraint: {@code 0 <= ui && ui <= 65535}<br /> | |
2862 * | |
2863 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
2864 */ | |
2865 // Template#: 164, Serial#: 164 | |
2866 public void oris(final GPR ra, final GPR rs, final int ui) { | |
2867 int instruction = 0x64000000; | |
2868 checkConstraint(0 <= ui && ui <= 65535, "0 <= ui && ui <= 65535"); | |
2869 instruction |= ((ra.value() & 0x1f) << 16); | |
2870 instruction |= ((rs.value() & 0x1f) << 21); | |
2871 instruction |= (ui & 0xffff); | |
2872 emitInt(instruction); | |
2873 } | |
2874 | |
2875 /** | |
2876 * Pseudo-external assembler syntax: {@code xori }<i>ra</i>, <i>rs</i>, <i>ui</i> | |
2877 * Example disassembly syntax: {@code xori r0, r0, 0x0} | |
2878 * <p> | |
2879 * Constraint: {@code 0 <= ui && ui <= 65535}<br /> | |
2880 * | |
2881 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
2882 */ | |
2883 // Template#: 165, Serial#: 165 | |
2884 public void xori(final GPR ra, final GPR rs, final int ui) { | |
2885 int instruction = 0x68000000; | |
2886 checkConstraint(0 <= ui && ui <= 65535, "0 <= ui && ui <= 65535"); | |
2887 instruction |= ((ra.value() & 0x1f) << 16); | |
2888 instruction |= ((rs.value() & 0x1f) << 21); | |
2889 instruction |= (ui & 0xffff); | |
2890 emitInt(instruction); | |
2891 } | |
2892 | |
2893 /** | |
2894 * Pseudo-external assembler syntax: {@code xoris }<i>ra</i>, <i>rs</i>, <i>ui</i> | |
2895 * Example disassembly syntax: {@code xoris r0, r0, 0x0} | |
2896 * <p> | |
2897 * Constraint: {@code 0 <= ui && ui <= 65535}<br /> | |
2898 * | |
2899 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
2900 */ | |
2901 // Template#: 166, Serial#: 166 | |
2902 public void xoris(final GPR ra, final GPR rs, final int ui) { | |
2903 int instruction = 0x6C000000; | |
2904 checkConstraint(0 <= ui && ui <= 65535, "0 <= ui && ui <= 65535"); | |
2905 instruction |= ((ra.value() & 0x1f) << 16); | |
2906 instruction |= ((rs.value() & 0x1f) << 21); | |
2907 instruction |= (ui & 0xffff); | |
2908 emitInt(instruction); | |
2909 } | |
2910 | |
2911 /** | |
2912 * Pseudo-external assembler syntax: {@code and }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
2913 * Example disassembly syntax: {@code and r0, r0, r0} | |
2914 * | |
2915 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
2916 */ | |
2917 // Template#: 167, Serial#: 167 | |
2918 public void and(final GPR ra, final GPR rs, final GPR rb) { | |
2919 int instruction = 0x7C000038; | |
2920 instruction |= ((ra.value() & 0x1f) << 16); | |
2921 instruction |= ((rs.value() & 0x1f) << 21); | |
2922 instruction |= ((rb.value() & 0x1f) << 11); | |
2923 emitInt(instruction); | |
2924 } | |
2925 | |
2926 /** | |
2927 * Pseudo-external assembler syntax: {@code and. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
2928 * Example disassembly syntax: {@code and. r0, r0, r0} | |
2929 * | |
2930 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
2931 */ | |
2932 // Template#: 168, Serial#: 168 | |
2933 public void and_(final GPR ra, final GPR rs, final GPR rb) { | |
2934 int instruction = 0x7C000039; | |
2935 instruction |= ((ra.value() & 0x1f) << 16); | |
2936 instruction |= ((rs.value() & 0x1f) << 21); | |
2937 instruction |= ((rb.value() & 0x1f) << 11); | |
2938 emitInt(instruction); | |
2939 } | |
2940 | |
2941 /** | |
2942 * Pseudo-external assembler syntax: {@code or }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
2943 * Example disassembly syntax: {@code or r0, r0, r0} | |
2944 * | |
2945 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
2946 */ | |
2947 // Template#: 169, Serial#: 169 | |
2948 public void or(final GPR ra, final GPR rs, final GPR rb) { | |
2949 int instruction = 0x7C000378; | |
2950 instruction |= ((ra.value() & 0x1f) << 16); | |
2951 instruction |= ((rs.value() & 0x1f) << 21); | |
2952 instruction |= ((rb.value() & 0x1f) << 11); | |
2953 emitInt(instruction); | |
2954 } | |
2955 | |
2956 /** | |
2957 * Pseudo-external assembler syntax: {@code or. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
2958 * Example disassembly syntax: {@code or. r0, r0, r0} | |
2959 * | |
2960 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
2961 */ | |
2962 // Template#: 170, Serial#: 170 | |
2963 public void or_(final GPR ra, final GPR rs, final GPR rb) { | |
2964 int instruction = 0x7C000379; | |
2965 instruction |= ((ra.value() & 0x1f) << 16); | |
2966 instruction |= ((rs.value() & 0x1f) << 21); | |
2967 instruction |= ((rb.value() & 0x1f) << 11); | |
2968 emitInt(instruction); | |
2969 } | |
2970 | |
2971 /** | |
2972 * Pseudo-external assembler syntax: {@code xor }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
2973 * Example disassembly syntax: {@code xor r0, r0, r0} | |
2974 * | |
2975 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
2976 */ | |
2977 // Template#: 171, Serial#: 171 | |
2978 public void xor(final GPR ra, final GPR rs, final GPR rb) { | |
2979 int instruction = 0x7C000278; | |
2980 instruction |= ((ra.value() & 0x1f) << 16); | |
2981 instruction |= ((rs.value() & 0x1f) << 21); | |
2982 instruction |= ((rb.value() & 0x1f) << 11); | |
2983 emitInt(instruction); | |
2984 } | |
2985 | |
2986 /** | |
2987 * Pseudo-external assembler syntax: {@code xor. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
2988 * Example disassembly syntax: {@code xor. r0, r0, r0} | |
2989 * | |
2990 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
2991 */ | |
2992 // Template#: 172, Serial#: 172 | |
2993 public void xor_(final GPR ra, final GPR rs, final GPR rb) { | |
2994 int instruction = 0x7C000279; | |
2995 instruction |= ((ra.value() & 0x1f) << 16); | |
2996 instruction |= ((rs.value() & 0x1f) << 21); | |
2997 instruction |= ((rb.value() & 0x1f) << 11); | |
2998 emitInt(instruction); | |
2999 } | |
3000 | |
3001 /** | |
3002 * Pseudo-external assembler syntax: {@code nand }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3003 * Example disassembly syntax: {@code nand r0, r0, r0} | |
3004 * | |
3005 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3006 */ | |
3007 // Template#: 173, Serial#: 173 | |
3008 public void nand(final GPR ra, final GPR rs, final GPR rb) { | |
3009 int instruction = 0x7C0003B8; | |
3010 instruction |= ((ra.value() & 0x1f) << 16); | |
3011 instruction |= ((rs.value() & 0x1f) << 21); | |
3012 instruction |= ((rb.value() & 0x1f) << 11); | |
3013 emitInt(instruction); | |
3014 } | |
3015 | |
3016 /** | |
3017 * Pseudo-external assembler syntax: {@code nand. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3018 * Example disassembly syntax: {@code nand. r0, r0, r0} | |
3019 * | |
3020 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3021 */ | |
3022 // Template#: 174, Serial#: 174 | |
3023 public void nand_(final GPR ra, final GPR rs, final GPR rb) { | |
3024 int instruction = 0x7C0003B9; | |
3025 instruction |= ((ra.value() & 0x1f) << 16); | |
3026 instruction |= ((rs.value() & 0x1f) << 21); | |
3027 instruction |= ((rb.value() & 0x1f) << 11); | |
3028 emitInt(instruction); | |
3029 } | |
3030 | |
3031 /** | |
3032 * Pseudo-external assembler syntax: {@code nor }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3033 * Example disassembly syntax: {@code nor r0, r0, r0} | |
3034 * | |
3035 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3036 */ | |
3037 // Template#: 175, Serial#: 175 | |
3038 public void nor(final GPR ra, final GPR rs, final GPR rb) { | |
3039 int instruction = 0x7C0000F8; | |
3040 instruction |= ((ra.value() & 0x1f) << 16); | |
3041 instruction |= ((rs.value() & 0x1f) << 21); | |
3042 instruction |= ((rb.value() & 0x1f) << 11); | |
3043 emitInt(instruction); | |
3044 } | |
3045 | |
3046 /** | |
3047 * Pseudo-external assembler syntax: {@code nor. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3048 * Example disassembly syntax: {@code nor. r0, r0, r0} | |
3049 * | |
3050 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3051 */ | |
3052 // Template#: 176, Serial#: 176 | |
3053 public void nor_(final GPR ra, final GPR rs, final GPR rb) { | |
3054 int instruction = 0x7C0000F9; | |
3055 instruction |= ((ra.value() & 0x1f) << 16); | |
3056 instruction |= ((rs.value() & 0x1f) << 21); | |
3057 instruction |= ((rb.value() & 0x1f) << 11); | |
3058 emitInt(instruction); | |
3059 } | |
3060 | |
3061 /** | |
3062 * Pseudo-external assembler syntax: {@code eqv }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3063 * Example disassembly syntax: {@code eqv r0, r0, r0} | |
3064 * | |
3065 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3066 */ | |
3067 // Template#: 177, Serial#: 177 | |
3068 public void eqv(final GPR ra, final GPR rs, final GPR rb) { | |
3069 int instruction = 0x7C000238; | |
3070 instruction |= ((ra.value() & 0x1f) << 16); | |
3071 instruction |= ((rs.value() & 0x1f) << 21); | |
3072 instruction |= ((rb.value() & 0x1f) << 11); | |
3073 emitInt(instruction); | |
3074 } | |
3075 | |
3076 /** | |
3077 * Pseudo-external assembler syntax: {@code eqv. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3078 * Example disassembly syntax: {@code eqv. r0, r0, r0} | |
3079 * | |
3080 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3081 */ | |
3082 // Template#: 178, Serial#: 178 | |
3083 public void eqv_(final GPR ra, final GPR rs, final GPR rb) { | |
3084 int instruction = 0x7C000239; | |
3085 instruction |= ((ra.value() & 0x1f) << 16); | |
3086 instruction |= ((rs.value() & 0x1f) << 21); | |
3087 instruction |= ((rb.value() & 0x1f) << 11); | |
3088 emitInt(instruction); | |
3089 } | |
3090 | |
3091 /** | |
3092 * Pseudo-external assembler syntax: {@code andc }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3093 * Example disassembly syntax: {@code andc r0, r0, r0} | |
3094 * | |
3095 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3096 */ | |
3097 // Template#: 179, Serial#: 179 | |
3098 public void andc(final GPR ra, final GPR rs, final GPR rb) { | |
3099 int instruction = 0x7C000078; | |
3100 instruction |= ((ra.value() & 0x1f) << 16); | |
3101 instruction |= ((rs.value() & 0x1f) << 21); | |
3102 instruction |= ((rb.value() & 0x1f) << 11); | |
3103 emitInt(instruction); | |
3104 } | |
3105 | |
3106 /** | |
3107 * Pseudo-external assembler syntax: {@code andc. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3108 * Example disassembly syntax: {@code andc. r0, r0, r0} | |
3109 * | |
3110 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3111 */ | |
3112 // Template#: 180, Serial#: 180 | |
3113 public void andc_(final GPR ra, final GPR rs, final GPR rb) { | |
3114 int instruction = 0x7C000079; | |
3115 instruction |= ((ra.value() & 0x1f) << 16); | |
3116 instruction |= ((rs.value() & 0x1f) << 21); | |
3117 instruction |= ((rb.value() & 0x1f) << 11); | |
3118 emitInt(instruction); | |
3119 } | |
3120 | |
3121 /** | |
3122 * Pseudo-external assembler syntax: {@code orc }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3123 * Example disassembly syntax: {@code orc r0, r0, r0} | |
3124 * | |
3125 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3126 */ | |
3127 // Template#: 181, Serial#: 181 | |
3128 public void orc(final GPR ra, final GPR rs, final GPR rb) { | |
3129 int instruction = 0x7C000338; | |
3130 instruction |= ((ra.value() & 0x1f) << 16); | |
3131 instruction |= ((rs.value() & 0x1f) << 21); | |
3132 instruction |= ((rb.value() & 0x1f) << 11); | |
3133 emitInt(instruction); | |
3134 } | |
3135 | |
3136 /** | |
3137 * Pseudo-external assembler syntax: {@code orc. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3138 * Example disassembly syntax: {@code orc. r0, r0, r0} | |
3139 * | |
3140 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3141 */ | |
3142 // Template#: 182, Serial#: 182 | |
3143 public void orc_(final GPR ra, final GPR rs, final GPR rb) { | |
3144 int instruction = 0x7C000339; | |
3145 instruction |= ((ra.value() & 0x1f) << 16); | |
3146 instruction |= ((rs.value() & 0x1f) << 21); | |
3147 instruction |= ((rb.value() & 0x1f) << 11); | |
3148 emitInt(instruction); | |
3149 } | |
3150 | |
3151 /** | |
3152 * Pseudo-external assembler syntax: {@code extsb }<i>ra</i>, <i>rs</i> | |
3153 * Example disassembly syntax: {@code extsb r0, r0} | |
3154 * | |
3155 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3156 */ | |
3157 // Template#: 183, Serial#: 183 | |
3158 public void extsb(final GPR ra, final GPR rs) { | |
3159 int instruction = 0x7C000774; | |
3160 instruction |= ((ra.value() & 0x1f) << 16); | |
3161 instruction |= ((rs.value() & 0x1f) << 21); | |
3162 emitInt(instruction); | |
3163 } | |
3164 | |
3165 /** | |
3166 * Pseudo-external assembler syntax: {@code extsb. }<i>ra</i>, <i>rs</i> | |
3167 * Example disassembly syntax: {@code extsb. r0, r0} | |
3168 * | |
3169 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3170 */ | |
3171 // Template#: 184, Serial#: 184 | |
3172 public void extsb_(final GPR ra, final GPR rs) { | |
3173 int instruction = 0x7C000775; | |
3174 instruction |= ((ra.value() & 0x1f) << 16); | |
3175 instruction |= ((rs.value() & 0x1f) << 21); | |
3176 emitInt(instruction); | |
3177 } | |
3178 | |
3179 /** | |
3180 * Pseudo-external assembler syntax: {@code extsh }<i>ra</i>, <i>rs</i> | |
3181 * Example disassembly syntax: {@code extsh r0, r0} | |
3182 * | |
3183 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3184 */ | |
3185 // Template#: 185, Serial#: 185 | |
3186 public void extsh(final GPR ra, final GPR rs) { | |
3187 int instruction = 0x7C000734; | |
3188 instruction |= ((ra.value() & 0x1f) << 16); | |
3189 instruction |= ((rs.value() & 0x1f) << 21); | |
3190 emitInt(instruction); | |
3191 } | |
3192 | |
3193 /** | |
3194 * Pseudo-external assembler syntax: {@code extsh. }<i>ra</i>, <i>rs</i> | |
3195 * Example disassembly syntax: {@code extsh. r0, r0} | |
3196 * | |
3197 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3198 */ | |
3199 // Template#: 186, Serial#: 186 | |
3200 public void extsh_(final GPR ra, final GPR rs) { | |
3201 int instruction = 0x7C000735; | |
3202 instruction |= ((ra.value() & 0x1f) << 16); | |
3203 instruction |= ((rs.value() & 0x1f) << 21); | |
3204 emitInt(instruction); | |
3205 } | |
3206 | |
3207 /** | |
3208 * Pseudo-external assembler syntax: {@code extsw }<i>ra</i>, <i>rs</i> | |
3209 * Example disassembly syntax: {@code extsw r0, r0} | |
3210 * | |
3211 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3212 */ | |
3213 // Template#: 187, Serial#: 187 | |
3214 public void extsw(final GPR ra, final GPR rs) { | |
3215 int instruction = 0x7C0007B4; | |
3216 instruction |= ((ra.value() & 0x1f) << 16); | |
3217 instruction |= ((rs.value() & 0x1f) << 21); | |
3218 emitInt(instruction); | |
3219 } | |
3220 | |
3221 /** | |
3222 * Pseudo-external assembler syntax: {@code extsw. }<i>ra</i>, <i>rs</i> | |
3223 * Example disassembly syntax: {@code extsw. r0, r0} | |
3224 * | |
3225 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3226 */ | |
3227 // Template#: 188, Serial#: 188 | |
3228 public void extsw_(final GPR ra, final GPR rs) { | |
3229 int instruction = 0x7C0007B5; | |
3230 instruction |= ((ra.value() & 0x1f) << 16); | |
3231 instruction |= ((rs.value() & 0x1f) << 21); | |
3232 emitInt(instruction); | |
3233 } | |
3234 | |
3235 /** | |
3236 * Pseudo-external assembler syntax: {@code cntlzd }<i>ra</i>, <i>rs</i> | |
3237 * Example disassembly syntax: {@code cntlzd r0, r0} | |
3238 * | |
3239 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3240 */ | |
3241 // Template#: 189, Serial#: 189 | |
3242 public void cntlzd(final GPR ra, final GPR rs) { | |
3243 int instruction = 0x7C000074; | |
3244 instruction |= ((ra.value() & 0x1f) << 16); | |
3245 instruction |= ((rs.value() & 0x1f) << 21); | |
3246 emitInt(instruction); | |
3247 } | |
3248 | |
3249 /** | |
3250 * Pseudo-external assembler syntax: {@code cntlzd. }<i>ra</i>, <i>rs</i> | |
3251 * Example disassembly syntax: {@code cntlzd. r0, r0} | |
3252 * | |
3253 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3254 */ | |
3255 // Template#: 190, Serial#: 190 | |
3256 public void cntlzd_(final GPR ra, final GPR rs) { | |
3257 int instruction = 0x7C000075; | |
3258 instruction |= ((ra.value() & 0x1f) << 16); | |
3259 instruction |= ((rs.value() & 0x1f) << 21); | |
3260 emitInt(instruction); | |
3261 } | |
3262 | |
3263 /** | |
3264 * Pseudo-external assembler syntax: {@code cntlzw }<i>ra</i>, <i>rs</i> | |
3265 * Example disassembly syntax: {@code cntlzw r0, r0} | |
3266 * | |
3267 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3268 */ | |
3269 // Template#: 191, Serial#: 191 | |
3270 public void cntlzw(final GPR ra, final GPR rs) { | |
3271 int instruction = 0x7C000034; | |
3272 instruction |= ((ra.value() & 0x1f) << 16); | |
3273 instruction |= ((rs.value() & 0x1f) << 21); | |
3274 emitInt(instruction); | |
3275 } | |
3276 | |
3277 /** | |
3278 * Pseudo-external assembler syntax: {@code cntlzw. }<i>ra</i>, <i>rs</i> | |
3279 * Example disassembly syntax: {@code cntlzw. r0, r0} | |
3280 * | |
3281 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.11 [Book 1]" | |
3282 */ | |
3283 // Template#: 192, Serial#: 192 | |
3284 public void cntlzw_(final GPR ra, final GPR rs) { | |
3285 int instruction = 0x7C000035; | |
3286 instruction |= ((ra.value() & 0x1f) << 16); | |
3287 instruction |= ((rs.value() & 0x1f) << 21); | |
3288 emitInt(instruction); | |
3289 } | |
3290 | |
3291 /** | |
3292 * Pseudo-external assembler syntax: {@code rldicl }<i>ra</i>, <i>rs</i>, <i>sh</i>, <i>mb</i> | |
3293 * Example disassembly syntax: {@code rldicl r0, r0, 0x0, 0x0} | |
3294 * <p> | |
3295 * Constraint: {@code 0 <= sh && sh <= 63}<br /> | |
3296 * Constraint: {@code 0 <= mb && mb <= 63}<br /> | |
3297 * | |
3298 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3299 */ | |
3300 // Template#: 193, Serial#: 193 | |
3301 public void rldicl(final GPR ra, final GPR rs, final int sh, final int mb) { | |
3302 int instruction = 0x78000000; | |
3303 checkConstraint(0 <= sh && sh <= 63, "0 <= sh && sh <= 63"); | |
3304 checkConstraint(0 <= mb && mb <= 63, "0 <= mb && mb <= 63"); | |
3305 instruction |= ((ra.value() & 0x1f) << 16); | |
3306 instruction |= ((rs.value() & 0x1f) << 21); | |
3307 instruction |= ((sh & 0x1f) << 11) | (((sh >>> 5) & 0x1) << 1); | |
3308 instruction |= ((mb & 0x1f) << 6) | (((mb >>> 5) & 0x1) << 5); | |
3309 emitInt(instruction); | |
3310 } | |
3311 | |
3312 /** | |
3313 * Pseudo-external assembler syntax: {@code rldicl. }<i>ra</i>, <i>rs</i>, <i>sh</i>, <i>mb</i> | |
3314 * Example disassembly syntax: {@code rldicl. r0, r0, 0x0, 0x0} | |
3315 * <p> | |
3316 * Constraint: {@code 0 <= sh && sh <= 63}<br /> | |
3317 * Constraint: {@code 0 <= mb && mb <= 63}<br /> | |
3318 * | |
3319 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3320 */ | |
3321 // Template#: 194, Serial#: 194 | |
3322 public void rldicl_(final GPR ra, final GPR rs, final int sh, final int mb) { | |
3323 int instruction = 0x78000001; | |
3324 checkConstraint(0 <= sh && sh <= 63, "0 <= sh && sh <= 63"); | |
3325 checkConstraint(0 <= mb && mb <= 63, "0 <= mb && mb <= 63"); | |
3326 instruction |= ((ra.value() & 0x1f) << 16); | |
3327 instruction |= ((rs.value() & 0x1f) << 21); | |
3328 instruction |= ((sh & 0x1f) << 11) | (((sh >>> 5) & 0x1) << 1); | |
3329 instruction |= ((mb & 0x1f) << 6) | (((mb >>> 5) & 0x1) << 5); | |
3330 emitInt(instruction); | |
3331 } | |
3332 | |
3333 /** | |
3334 * Pseudo-external assembler syntax: {@code rldicr }<i>ra</i>, <i>rs</i>, <i>sh</i>, <i>me</i> | |
3335 * Example disassembly syntax: {@code rldicr r0, r0, 0x0, 0x0} | |
3336 * <p> | |
3337 * Constraint: {@code 0 <= sh && sh <= 63}<br /> | |
3338 * Constraint: {@code 0 <= me && me <= 63}<br /> | |
3339 * | |
3340 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3341 */ | |
3342 // Template#: 195, Serial#: 195 | |
3343 public void rldicr(final GPR ra, final GPR rs, final int sh, final int me) { | |
3344 int instruction = 0x78000004; | |
3345 checkConstraint(0 <= sh && sh <= 63, "0 <= sh && sh <= 63"); | |
3346 checkConstraint(0 <= me && me <= 63, "0 <= me && me <= 63"); | |
3347 instruction |= ((ra.value() & 0x1f) << 16); | |
3348 instruction |= ((rs.value() & 0x1f) << 21); | |
3349 instruction |= ((sh & 0x1f) << 11) | (((sh >>> 5) & 0x1) << 1); | |
3350 instruction |= ((me & 0x1f) << 6) | (((me >>> 5) & 0x1) << 5); | |
3351 emitInt(instruction); | |
3352 } | |
3353 | |
3354 /** | |
3355 * Pseudo-external assembler syntax: {@code rldicr. }<i>ra</i>, <i>rs</i>, <i>sh</i>, <i>me</i> | |
3356 * Example disassembly syntax: {@code rldicr. r0, r0, 0x0, 0x0} | |
3357 * <p> | |
3358 * Constraint: {@code 0 <= sh && sh <= 63}<br /> | |
3359 * Constraint: {@code 0 <= me && me <= 63}<br /> | |
3360 * | |
3361 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3362 */ | |
3363 // Template#: 196, Serial#: 196 | |
3364 public void rldicr_(final GPR ra, final GPR rs, final int sh, final int me) { | |
3365 int instruction = 0x78000005; | |
3366 checkConstraint(0 <= sh && sh <= 63, "0 <= sh && sh <= 63"); | |
3367 checkConstraint(0 <= me && me <= 63, "0 <= me && me <= 63"); | |
3368 instruction |= ((ra.value() & 0x1f) << 16); | |
3369 instruction |= ((rs.value() & 0x1f) << 21); | |
3370 instruction |= ((sh & 0x1f) << 11) | (((sh >>> 5) & 0x1) << 1); | |
3371 instruction |= ((me & 0x1f) << 6) | (((me >>> 5) & 0x1) << 5); | |
3372 emitInt(instruction); | |
3373 } | |
3374 | |
3375 /** | |
3376 * Pseudo-external assembler syntax: {@code rldic }<i>ra</i>, <i>rs</i>, <i>sh</i>, <i>mb</i> | |
3377 * Example disassembly syntax: {@code rldic r0, r0, 0x0, 0x0} | |
3378 * <p> | |
3379 * Constraint: {@code 0 <= sh && sh <= 63}<br /> | |
3380 * Constraint: {@code 0 <= mb && mb <= 63}<br /> | |
3381 * | |
3382 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3383 */ | |
3384 // Template#: 197, Serial#: 197 | |
3385 public void rldic(final GPR ra, final GPR rs, final int sh, final int mb) { | |
3386 int instruction = 0x78000008; | |
3387 checkConstraint(0 <= sh && sh <= 63, "0 <= sh && sh <= 63"); | |
3388 checkConstraint(0 <= mb && mb <= 63, "0 <= mb && mb <= 63"); | |
3389 instruction |= ((ra.value() & 0x1f) << 16); | |
3390 instruction |= ((rs.value() & 0x1f) << 21); | |
3391 instruction |= ((sh & 0x1f) << 11) | (((sh >>> 5) & 0x1) << 1); | |
3392 instruction |= ((mb & 0x1f) << 6) | (((mb >>> 5) & 0x1) << 5); | |
3393 emitInt(instruction); | |
3394 } | |
3395 | |
3396 /** | |
3397 * Pseudo-external assembler syntax: {@code rldic. }<i>ra</i>, <i>rs</i>, <i>sh</i>, <i>mb</i> | |
3398 * Example disassembly syntax: {@code rldic. r0, r0, 0x0, 0x0} | |
3399 * <p> | |
3400 * Constraint: {@code 0 <= sh && sh <= 63}<br /> | |
3401 * Constraint: {@code 0 <= mb && mb <= 63}<br /> | |
3402 * | |
3403 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3404 */ | |
3405 // Template#: 198, Serial#: 198 | |
3406 public void rldic_(final GPR ra, final GPR rs, final int sh, final int mb) { | |
3407 int instruction = 0x78000009; | |
3408 checkConstraint(0 <= sh && sh <= 63, "0 <= sh && sh <= 63"); | |
3409 checkConstraint(0 <= mb && mb <= 63, "0 <= mb && mb <= 63"); | |
3410 instruction |= ((ra.value() & 0x1f) << 16); | |
3411 instruction |= ((rs.value() & 0x1f) << 21); | |
3412 instruction |= ((sh & 0x1f) << 11) | (((sh >>> 5) & 0x1) << 1); | |
3413 instruction |= ((mb & 0x1f) << 6) | (((mb >>> 5) & 0x1) << 5); | |
3414 emitInt(instruction); | |
3415 } | |
3416 | |
3417 /** | |
3418 * Pseudo-external assembler syntax: {@code rlwinm }<i>ra</i>, <i>rs</i>, <i>sh</i>, <i>mb</i>, <i>me</i> | |
3419 * Example disassembly syntax: {@code rlwinm r0, r0, 0x0, 0x0, 0x0} | |
3420 * <p> | |
3421 * Constraint: {@code 0 <= sh && sh <= 31}<br /> | |
3422 * Constraint: {@code 0 <= mb && mb <= 31}<br /> | |
3423 * Constraint: {@code 0 <= me && me <= 31}<br /> | |
3424 * | |
3425 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3426 */ | |
3427 // Template#: 199, Serial#: 199 | |
3428 public void rlwinm(final GPR ra, final GPR rs, final int sh, final int mb, final int me) { | |
3429 int instruction = 0x54000000; | |
3430 checkConstraint(0 <= sh && sh <= 31, "0 <= sh && sh <= 31"); | |
3431 checkConstraint(0 <= mb && mb <= 31, "0 <= mb && mb <= 31"); | |
3432 checkConstraint(0 <= me && me <= 31, "0 <= me && me <= 31"); | |
3433 instruction |= ((ra.value() & 0x1f) << 16); | |
3434 instruction |= ((rs.value() & 0x1f) << 21); | |
3435 instruction |= ((sh & 0x1f) << 11); | |
3436 instruction |= ((mb & 0x1f) << 6); | |
3437 instruction |= ((me & 0x1f) << 1); | |
3438 emitInt(instruction); | |
3439 } | |
3440 | |
3441 /** | |
3442 * Pseudo-external assembler syntax: {@code rlwinm. }<i>ra</i>, <i>rs</i>, <i>sh</i>, <i>mb</i>, <i>me</i> | |
3443 * Example disassembly syntax: {@code rlwinm. r0, r0, 0x0, 0x0, 0x0} | |
3444 * <p> | |
3445 * Constraint: {@code 0 <= sh && sh <= 31}<br /> | |
3446 * Constraint: {@code 0 <= mb && mb <= 31}<br /> | |
3447 * Constraint: {@code 0 <= me && me <= 31}<br /> | |
3448 * | |
3449 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3450 */ | |
3451 // Template#: 200, Serial#: 200 | |
3452 public void rlwinm_(final GPR ra, final GPR rs, final int sh, final int mb, final int me) { | |
3453 int instruction = 0x54000001; | |
3454 checkConstraint(0 <= sh && sh <= 31, "0 <= sh && sh <= 31"); | |
3455 checkConstraint(0 <= mb && mb <= 31, "0 <= mb && mb <= 31"); | |
3456 checkConstraint(0 <= me && me <= 31, "0 <= me && me <= 31"); | |
3457 instruction |= ((ra.value() & 0x1f) << 16); | |
3458 instruction |= ((rs.value() & 0x1f) << 21); | |
3459 instruction |= ((sh & 0x1f) << 11); | |
3460 instruction |= ((mb & 0x1f) << 6); | |
3461 instruction |= ((me & 0x1f) << 1); | |
3462 emitInt(instruction); | |
3463 } | |
3464 | |
3465 /** | |
3466 * Pseudo-external assembler syntax: {@code rldcl }<i>ra</i>, <i>rs</i>, <i>rb</i>, <i>mb</i> | |
3467 * Example disassembly syntax: {@code rldcl r0, r0, r0, 0x0} | |
3468 * <p> | |
3469 * Constraint: {@code 0 <= mb && mb <= 63}<br /> | |
3470 * | |
3471 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3472 */ | |
3473 // Template#: 201, Serial#: 201 | |
3474 public void rldcl(final GPR ra, final GPR rs, final GPR rb, final int mb) { | |
3475 int instruction = 0x78000010; | |
3476 checkConstraint(0 <= mb && mb <= 63, "0 <= mb && mb <= 63"); | |
3477 instruction |= ((ra.value() & 0x1f) << 16); | |
3478 instruction |= ((rs.value() & 0x1f) << 21); | |
3479 instruction |= ((rb.value() & 0x1f) << 11); | |
3480 instruction |= ((mb & 0x1f) << 6) | (((mb >>> 5) & 0x1) << 5); | |
3481 emitInt(instruction); | |
3482 } | |
3483 | |
3484 /** | |
3485 * Pseudo-external assembler syntax: {@code rldcl. }<i>ra</i>, <i>rs</i>, <i>rb</i>, <i>mb</i> | |
3486 * Example disassembly syntax: {@code rldcl. r0, r0, r0, 0x0} | |
3487 * <p> | |
3488 * Constraint: {@code 0 <= mb && mb <= 63}<br /> | |
3489 * | |
3490 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3491 */ | |
3492 // Template#: 202, Serial#: 202 | |
3493 public void rldcl_(final GPR ra, final GPR rs, final GPR rb, final int mb) { | |
3494 int instruction = 0x78000011; | |
3495 checkConstraint(0 <= mb && mb <= 63, "0 <= mb && mb <= 63"); | |
3496 instruction |= ((ra.value() & 0x1f) << 16); | |
3497 instruction |= ((rs.value() & 0x1f) << 21); | |
3498 instruction |= ((rb.value() & 0x1f) << 11); | |
3499 instruction |= ((mb & 0x1f) << 6) | (((mb >>> 5) & 0x1) << 5); | |
3500 emitInt(instruction); | |
3501 } | |
3502 | |
3503 /** | |
3504 * Pseudo-external assembler syntax: {@code rldcr }<i>ra</i>, <i>rs</i>, <i>rb</i>, <i>me</i> | |
3505 * Example disassembly syntax: {@code rldcr r0, r0, r0, 0x0} | |
3506 * <p> | |
3507 * Constraint: {@code 0 <= me && me <= 63}<br /> | |
3508 * | |
3509 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3510 */ | |
3511 // Template#: 203, Serial#: 203 | |
3512 public void rldcr(final GPR ra, final GPR rs, final GPR rb, final int me) { | |
3513 int instruction = 0x78000012; | |
3514 checkConstraint(0 <= me && me <= 63, "0 <= me && me <= 63"); | |
3515 instruction |= ((ra.value() & 0x1f) << 16); | |
3516 instruction |= ((rs.value() & 0x1f) << 21); | |
3517 instruction |= ((rb.value() & 0x1f) << 11); | |
3518 instruction |= ((me & 0x1f) << 6) | (((me >>> 5) & 0x1) << 5); | |
3519 emitInt(instruction); | |
3520 } | |
3521 | |
3522 /** | |
3523 * Pseudo-external assembler syntax: {@code rldcr. }<i>ra</i>, <i>rs</i>, <i>rb</i>, <i>me</i> | |
3524 * Example disassembly syntax: {@code rldcr. r0, r0, r0, 0x0} | |
3525 * <p> | |
3526 * Constraint: {@code 0 <= me && me <= 63}<br /> | |
3527 * | |
3528 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3529 */ | |
3530 // Template#: 204, Serial#: 204 | |
3531 public void rldcr_(final GPR ra, final GPR rs, final GPR rb, final int me) { | |
3532 int instruction = 0x78000013; | |
3533 checkConstraint(0 <= me && me <= 63, "0 <= me && me <= 63"); | |
3534 instruction |= ((ra.value() & 0x1f) << 16); | |
3535 instruction |= ((rs.value() & 0x1f) << 21); | |
3536 instruction |= ((rb.value() & 0x1f) << 11); | |
3537 instruction |= ((me & 0x1f) << 6) | (((me >>> 5) & 0x1) << 5); | |
3538 emitInt(instruction); | |
3539 } | |
3540 | |
3541 /** | |
3542 * Pseudo-external assembler syntax: {@code rlwnm }<i>ra</i>, <i>rs</i>, <i>rb</i>, <i>mb</i>, <i>me</i> | |
3543 * Example disassembly syntax: {@code rlwnm r0, r0, r0, 0x0, 0x0} | |
3544 * <p> | |
3545 * Constraint: {@code 0 <= mb && mb <= 31}<br /> | |
3546 * Constraint: {@code 0 <= me && me <= 31}<br /> | |
3547 * | |
3548 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3549 */ | |
3550 // Template#: 205, Serial#: 205 | |
3551 public void rlwnm(final GPR ra, final GPR rs, final GPR rb, final int mb, final int me) { | |
3552 int instruction = 0x5C000000; | |
3553 checkConstraint(0 <= mb && mb <= 31, "0 <= mb && mb <= 31"); | |
3554 checkConstraint(0 <= me && me <= 31, "0 <= me && me <= 31"); | |
3555 instruction |= ((ra.value() & 0x1f) << 16); | |
3556 instruction |= ((rs.value() & 0x1f) << 21); | |
3557 instruction |= ((rb.value() & 0x1f) << 11); | |
3558 instruction |= ((mb & 0x1f) << 6); | |
3559 instruction |= ((me & 0x1f) << 1); | |
3560 emitInt(instruction); | |
3561 } | |
3562 | |
3563 /** | |
3564 * Pseudo-external assembler syntax: {@code rlwnm. }<i>ra</i>, <i>rs</i>, <i>rb</i>, <i>mb</i>, <i>me</i> | |
3565 * Example disassembly syntax: {@code rlwnm. r0, r0, r0, 0x0, 0x0} | |
3566 * <p> | |
3567 * Constraint: {@code 0 <= mb && mb <= 31}<br /> | |
3568 * Constraint: {@code 0 <= me && me <= 31}<br /> | |
3569 * | |
3570 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3571 */ | |
3572 // Template#: 206, Serial#: 206 | |
3573 public void rlwnm_(final GPR ra, final GPR rs, final GPR rb, final int mb, final int me) { | |
3574 int instruction = 0x5C000001; | |
3575 checkConstraint(0 <= mb && mb <= 31, "0 <= mb && mb <= 31"); | |
3576 checkConstraint(0 <= me && me <= 31, "0 <= me && me <= 31"); | |
3577 instruction |= ((ra.value() & 0x1f) << 16); | |
3578 instruction |= ((rs.value() & 0x1f) << 21); | |
3579 instruction |= ((rb.value() & 0x1f) << 11); | |
3580 instruction |= ((mb & 0x1f) << 6); | |
3581 instruction |= ((me & 0x1f) << 1); | |
3582 emitInt(instruction); | |
3583 } | |
3584 | |
3585 /** | |
3586 * Pseudo-external assembler syntax: {@code rldimi }<i>ra</i>, <i>rs</i>, <i>sh</i>, <i>mb</i> | |
3587 * Example disassembly syntax: {@code rldimi r0, r0, 0x0, 0x0} | |
3588 * <p> | |
3589 * Constraint: {@code 0 <= sh && sh <= 63}<br /> | |
3590 * Constraint: {@code 0 <= mb && mb <= 63}<br /> | |
3591 * | |
3592 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3593 */ | |
3594 // Template#: 207, Serial#: 207 | |
3595 public void rldimi(final GPR ra, final GPR rs, final int sh, final int mb) { | |
3596 int instruction = 0x7800000C; | |
3597 checkConstraint(0 <= sh && sh <= 63, "0 <= sh && sh <= 63"); | |
3598 checkConstraint(0 <= mb && mb <= 63, "0 <= mb && mb <= 63"); | |
3599 instruction |= ((ra.value() & 0x1f) << 16); | |
3600 instruction |= ((rs.value() & 0x1f) << 21); | |
3601 instruction |= ((sh & 0x1f) << 11) | (((sh >>> 5) & 0x1) << 1); | |
3602 instruction |= ((mb & 0x1f) << 6) | (((mb >>> 5) & 0x1) << 5); | |
3603 emitInt(instruction); | |
3604 } | |
3605 | |
3606 /** | |
3607 * Pseudo-external assembler syntax: {@code rldimi. }<i>ra</i>, <i>rs</i>, <i>sh</i>, <i>mb</i> | |
3608 * Example disassembly syntax: {@code rldimi. r0, r0, 0x0, 0x0} | |
3609 * <p> | |
3610 * Constraint: {@code 0 <= sh && sh <= 63}<br /> | |
3611 * Constraint: {@code 0 <= mb && mb <= 63}<br /> | |
3612 * | |
3613 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3614 */ | |
3615 // Template#: 208, Serial#: 208 | |
3616 public void rldimi_(final GPR ra, final GPR rs, final int sh, final int mb) { | |
3617 int instruction = 0x7800000D; | |
3618 checkConstraint(0 <= sh && sh <= 63, "0 <= sh && sh <= 63"); | |
3619 checkConstraint(0 <= mb && mb <= 63, "0 <= mb && mb <= 63"); | |
3620 instruction |= ((ra.value() & 0x1f) << 16); | |
3621 instruction |= ((rs.value() & 0x1f) << 21); | |
3622 instruction |= ((sh & 0x1f) << 11) | (((sh >>> 5) & 0x1) << 1); | |
3623 instruction |= ((mb & 0x1f) << 6) | (((mb >>> 5) & 0x1) << 5); | |
3624 emitInt(instruction); | |
3625 } | |
3626 | |
3627 /** | |
3628 * Pseudo-external assembler syntax: {@code rlwimi }<i>ra</i>, <i>rs</i>, <i>sh</i>, <i>mb</i>, <i>me</i> | |
3629 * Example disassembly syntax: {@code rlwimi r0, r0, 0x0, 0x0, 0x0} | |
3630 * <p> | |
3631 * Constraint: {@code 0 <= sh && sh <= 31}<br /> | |
3632 * Constraint: {@code 0 <= mb && mb <= 31}<br /> | |
3633 * Constraint: {@code 0 <= me && me <= 31}<br /> | |
3634 * | |
3635 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3636 */ | |
3637 // Template#: 209, Serial#: 209 | |
3638 public void rlwimi(final GPR ra, final GPR rs, final int sh, final int mb, final int me) { | |
3639 int instruction = 0x50000000; | |
3640 checkConstraint(0 <= sh && sh <= 31, "0 <= sh && sh <= 31"); | |
3641 checkConstraint(0 <= mb && mb <= 31, "0 <= mb && mb <= 31"); | |
3642 checkConstraint(0 <= me && me <= 31, "0 <= me && me <= 31"); | |
3643 instruction |= ((ra.value() & 0x1f) << 16); | |
3644 instruction |= ((rs.value() & 0x1f) << 21); | |
3645 instruction |= ((sh & 0x1f) << 11); | |
3646 instruction |= ((mb & 0x1f) << 6); | |
3647 instruction |= ((me & 0x1f) << 1); | |
3648 emitInt(instruction); | |
3649 } | |
3650 | |
3651 /** | |
3652 * Pseudo-external assembler syntax: {@code rlwimi. }<i>ra</i>, <i>rs</i>, <i>sh</i>, <i>mb</i>, <i>me</i> | |
3653 * Example disassembly syntax: {@code rlwimi. r0, r0, 0x0, 0x0, 0x0} | |
3654 * <p> | |
3655 * Constraint: {@code 0 <= sh && sh <= 31}<br /> | |
3656 * Constraint: {@code 0 <= mb && mb <= 31}<br /> | |
3657 * Constraint: {@code 0 <= me && me <= 31}<br /> | |
3658 * | |
3659 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12 [Book 1]" | |
3660 */ | |
3661 // Template#: 210, Serial#: 210 | |
3662 public void rlwimi_(final GPR ra, final GPR rs, final int sh, final int mb, final int me) { | |
3663 int instruction = 0x50000001; | |
3664 checkConstraint(0 <= sh && sh <= 31, "0 <= sh && sh <= 31"); | |
3665 checkConstraint(0 <= mb && mb <= 31, "0 <= mb && mb <= 31"); | |
3666 checkConstraint(0 <= me && me <= 31, "0 <= me && me <= 31"); | |
3667 instruction |= ((ra.value() & 0x1f) << 16); | |
3668 instruction |= ((rs.value() & 0x1f) << 21); | |
3669 instruction |= ((sh & 0x1f) << 11); | |
3670 instruction |= ((mb & 0x1f) << 6); | |
3671 instruction |= ((me & 0x1f) << 1); | |
3672 emitInt(instruction); | |
3673 } | |
3674 | |
3675 /** | |
3676 * Pseudo-external assembler syntax: {@code sld }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3677 * Example disassembly syntax: {@code sld r0, r0, r0} | |
3678 * | |
3679 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3680 */ | |
3681 // Template#: 211, Serial#: 211 | |
3682 public void sld(final GPR ra, final GPR rs, final GPR rb) { | |
3683 int instruction = 0x7C000036; | |
3684 instruction |= ((ra.value() & 0x1f) << 16); | |
3685 instruction |= ((rs.value() & 0x1f) << 21); | |
3686 instruction |= ((rb.value() & 0x1f) << 11); | |
3687 emitInt(instruction); | |
3688 } | |
3689 | |
3690 /** | |
3691 * Pseudo-external assembler syntax: {@code sld. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3692 * Example disassembly syntax: {@code sld. r0, r0, r0} | |
3693 * | |
3694 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3695 */ | |
3696 // Template#: 212, Serial#: 212 | |
3697 public void sld_(final GPR ra, final GPR rs, final GPR rb) { | |
3698 int instruction = 0x7C000037; | |
3699 instruction |= ((ra.value() & 0x1f) << 16); | |
3700 instruction |= ((rs.value() & 0x1f) << 21); | |
3701 instruction |= ((rb.value() & 0x1f) << 11); | |
3702 emitInt(instruction); | |
3703 } | |
3704 | |
3705 /** | |
3706 * Pseudo-external assembler syntax: {@code slw }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3707 * Example disassembly syntax: {@code slw r0, r0, r0} | |
3708 * | |
3709 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3710 */ | |
3711 // Template#: 213, Serial#: 213 | |
3712 public void slw(final GPR ra, final GPR rs, final GPR rb) { | |
3713 int instruction = 0x7C000030; | |
3714 instruction |= ((ra.value() & 0x1f) << 16); | |
3715 instruction |= ((rs.value() & 0x1f) << 21); | |
3716 instruction |= ((rb.value() & 0x1f) << 11); | |
3717 emitInt(instruction); | |
3718 } | |
3719 | |
3720 /** | |
3721 * Pseudo-external assembler syntax: {@code slw. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3722 * Example disassembly syntax: {@code slw. r0, r0, r0} | |
3723 * | |
3724 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3725 */ | |
3726 // Template#: 214, Serial#: 214 | |
3727 public void slw_(final GPR ra, final GPR rs, final GPR rb) { | |
3728 int instruction = 0x7C000031; | |
3729 instruction |= ((ra.value() & 0x1f) << 16); | |
3730 instruction |= ((rs.value() & 0x1f) << 21); | |
3731 instruction |= ((rb.value() & 0x1f) << 11); | |
3732 emitInt(instruction); | |
3733 } | |
3734 | |
3735 /** | |
3736 * Pseudo-external assembler syntax: {@code srd }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3737 * Example disassembly syntax: {@code srd r0, r0, r0} | |
3738 * | |
3739 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3740 */ | |
3741 // Template#: 215, Serial#: 215 | |
3742 public void srd(final GPR ra, final GPR rs, final GPR rb) { | |
3743 int instruction = 0x7C000436; | |
3744 instruction |= ((ra.value() & 0x1f) << 16); | |
3745 instruction |= ((rs.value() & 0x1f) << 21); | |
3746 instruction |= ((rb.value() & 0x1f) << 11); | |
3747 emitInt(instruction); | |
3748 } | |
3749 | |
3750 /** | |
3751 * Pseudo-external assembler syntax: {@code srd. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3752 * Example disassembly syntax: {@code srd. r0, r0, r0} | |
3753 * | |
3754 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3755 */ | |
3756 // Template#: 216, Serial#: 216 | |
3757 public void srd_(final GPR ra, final GPR rs, final GPR rb) { | |
3758 int instruction = 0x7C000437; | |
3759 instruction |= ((ra.value() & 0x1f) << 16); | |
3760 instruction |= ((rs.value() & 0x1f) << 21); | |
3761 instruction |= ((rb.value() & 0x1f) << 11); | |
3762 emitInt(instruction); | |
3763 } | |
3764 | |
3765 /** | |
3766 * Pseudo-external assembler syntax: {@code srw }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3767 * Example disassembly syntax: {@code srw r0, r0, r0} | |
3768 * | |
3769 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3770 */ | |
3771 // Template#: 217, Serial#: 217 | |
3772 public void srw(final GPR ra, final GPR rs, final GPR rb) { | |
3773 int instruction = 0x7C000430; | |
3774 instruction |= ((ra.value() & 0x1f) << 16); | |
3775 instruction |= ((rs.value() & 0x1f) << 21); | |
3776 instruction |= ((rb.value() & 0x1f) << 11); | |
3777 emitInt(instruction); | |
3778 } | |
3779 | |
3780 /** | |
3781 * Pseudo-external assembler syntax: {@code srw. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3782 * Example disassembly syntax: {@code srw. r0, r0, r0} | |
3783 * | |
3784 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3785 */ | |
3786 // Template#: 218, Serial#: 218 | |
3787 public void srw_(final GPR ra, final GPR rs, final GPR rb) { | |
3788 int instruction = 0x7C000431; | |
3789 instruction |= ((ra.value() & 0x1f) << 16); | |
3790 instruction |= ((rs.value() & 0x1f) << 21); | |
3791 instruction |= ((rb.value() & 0x1f) << 11); | |
3792 emitInt(instruction); | |
3793 } | |
3794 | |
3795 /** | |
3796 * Pseudo-external assembler syntax: {@code sradi }<i>ra</i>, <i>rs</i>, <i>sh</i> | |
3797 * Example disassembly syntax: {@code sradi r0, r0, 0x0} | |
3798 * <p> | |
3799 * Constraint: {@code 0 <= sh && sh <= 63}<br /> | |
3800 * | |
3801 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3802 */ | |
3803 // Template#: 219, Serial#: 219 | |
3804 public void sradi(final GPR ra, final GPR rs, final int sh) { | |
3805 int instruction = 0x7C000674; | |
3806 checkConstraint(0 <= sh && sh <= 63, "0 <= sh && sh <= 63"); | |
3807 instruction |= ((ra.value() & 0x1f) << 16); | |
3808 instruction |= ((rs.value() & 0x1f) << 21); | |
3809 instruction |= ((sh & 0x1f) << 11) | (((sh >>> 5) & 0x1) << 1); | |
3810 emitInt(instruction); | |
3811 } | |
3812 | |
3813 /** | |
3814 * Pseudo-external assembler syntax: {@code sradi. }<i>ra</i>, <i>rs</i>, <i>sh</i> | |
3815 * Example disassembly syntax: {@code sradi. r0, r0, 0x0} | |
3816 * <p> | |
3817 * Constraint: {@code 0 <= sh && sh <= 63}<br /> | |
3818 * | |
3819 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3820 */ | |
3821 // Template#: 220, Serial#: 220 | |
3822 public void sradi_(final GPR ra, final GPR rs, final int sh) { | |
3823 int instruction = 0x7C000675; | |
3824 checkConstraint(0 <= sh && sh <= 63, "0 <= sh && sh <= 63"); | |
3825 instruction |= ((ra.value() & 0x1f) << 16); | |
3826 instruction |= ((rs.value() & 0x1f) << 21); | |
3827 instruction |= ((sh & 0x1f) << 11) | (((sh >>> 5) & 0x1) << 1); | |
3828 emitInt(instruction); | |
3829 } | |
3830 | |
3831 /** | |
3832 * Pseudo-external assembler syntax: {@code srawi }<i>ra</i>, <i>rs</i>, <i>sh</i> | |
3833 * Example disassembly syntax: {@code srawi r0, r0, 0x0} | |
3834 * <p> | |
3835 * Constraint: {@code 0 <= sh && sh <= 31}<br /> | |
3836 * | |
3837 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3838 */ | |
3839 // Template#: 221, Serial#: 221 | |
3840 public void srawi(final GPR ra, final GPR rs, final int sh) { | |
3841 int instruction = 0x7C000670; | |
3842 checkConstraint(0 <= sh && sh <= 31, "0 <= sh && sh <= 31"); | |
3843 instruction |= ((ra.value() & 0x1f) << 16); | |
3844 instruction |= ((rs.value() & 0x1f) << 21); | |
3845 instruction |= ((sh & 0x1f) << 11); | |
3846 emitInt(instruction); | |
3847 } | |
3848 | |
3849 /** | |
3850 * Pseudo-external assembler syntax: {@code srawi. }<i>ra</i>, <i>rs</i>, <i>sh</i> | |
3851 * Example disassembly syntax: {@code srawi. r0, r0, 0x0} | |
3852 * <p> | |
3853 * Constraint: {@code 0 <= sh && sh <= 31}<br /> | |
3854 * | |
3855 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3856 */ | |
3857 // Template#: 222, Serial#: 222 | |
3858 public void srawi_(final GPR ra, final GPR rs, final int sh) { | |
3859 int instruction = 0x7C000671; | |
3860 checkConstraint(0 <= sh && sh <= 31, "0 <= sh && sh <= 31"); | |
3861 instruction |= ((ra.value() & 0x1f) << 16); | |
3862 instruction |= ((rs.value() & 0x1f) << 21); | |
3863 instruction |= ((sh & 0x1f) << 11); | |
3864 emitInt(instruction); | |
3865 } | |
3866 | |
3867 /** | |
3868 * Pseudo-external assembler syntax: {@code srad }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3869 * Example disassembly syntax: {@code srad r0, r0, r0} | |
3870 * | |
3871 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3872 */ | |
3873 // Template#: 223, Serial#: 223 | |
3874 public void srad(final GPR ra, final GPR rs, final GPR rb) { | |
3875 int instruction = 0x7C000634; | |
3876 instruction |= ((ra.value() & 0x1f) << 16); | |
3877 instruction |= ((rs.value() & 0x1f) << 21); | |
3878 instruction |= ((rb.value() & 0x1f) << 11); | |
3879 emitInt(instruction); | |
3880 } | |
3881 | |
3882 /** | |
3883 * Pseudo-external assembler syntax: {@code srad. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3884 * Example disassembly syntax: {@code srad. r0, r0, r0} | |
3885 * | |
3886 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3887 */ | |
3888 // Template#: 224, Serial#: 224 | |
3889 public void srad_(final GPR ra, final GPR rs, final GPR rb) { | |
3890 int instruction = 0x7C000635; | |
3891 instruction |= ((ra.value() & 0x1f) << 16); | |
3892 instruction |= ((rs.value() & 0x1f) << 21); | |
3893 instruction |= ((rb.value() & 0x1f) << 11); | |
3894 emitInt(instruction); | |
3895 } | |
3896 | |
3897 /** | |
3898 * Pseudo-external assembler syntax: {@code sraw }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3899 * Example disassembly syntax: {@code sraw r0, r0, r0} | |
3900 * | |
3901 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3902 */ | |
3903 // Template#: 225, Serial#: 225 | |
3904 public void sraw(final GPR ra, final GPR rs, final GPR rb) { | |
3905 int instruction = 0x7C000630; | |
3906 instruction |= ((ra.value() & 0x1f) << 16); | |
3907 instruction |= ((rs.value() & 0x1f) << 21); | |
3908 instruction |= ((rb.value() & 0x1f) << 11); | |
3909 emitInt(instruction); | |
3910 } | |
3911 | |
3912 /** | |
3913 * Pseudo-external assembler syntax: {@code sraw. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
3914 * Example disassembly syntax: {@code sraw. r0, r0, r0} | |
3915 * | |
3916 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.12.2 [Book 1]" | |
3917 */ | |
3918 // Template#: 226, Serial#: 226 | |
3919 public void sraw_(final GPR ra, final GPR rs, final GPR rb) { | |
3920 int instruction = 0x7C000631; | |
3921 instruction |= ((ra.value() & 0x1f) << 16); | |
3922 instruction |= ((rs.value() & 0x1f) << 21); | |
3923 instruction |= ((rb.value() & 0x1f) << 11); | |
3924 emitInt(instruction); | |
3925 } | |
3926 | |
3927 /** | |
3928 * Pseudo-external assembler syntax: {@code mtspr }<i>spr</i>, <i>rs</i> | |
3929 * Example disassembly syntax: {@code mtspr 0x0, r0} | |
3930 * <p> | |
3931 * Constraint: {@code 0 <= spr && spr <= 1023}<br /> | |
3932 * | |
3933 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.13 [Book 1]" | |
3934 */ | |
3935 // Template#: 227, Serial#: 227 | |
3936 public void mtspr(final int spr, final GPR rs) { | |
3937 int instruction = 0x7C0003A6; | |
3938 checkConstraint(0 <= spr && spr <= 1023, "0 <= spr && spr <= 1023"); | |
3939 instruction |= ((spr & 0x1f) << 16) | (((spr >>> 5) & 0x1f) << 11); | |
3940 instruction |= ((rs.value() & 0x1f) << 21); | |
3941 emitInt(instruction); | |
3942 } | |
3943 | |
3944 /** | |
3945 * Pseudo-external assembler syntax: {@code mfspr }<i>rt</i>, <i>spr</i> | |
3946 * Example disassembly syntax: {@code mfspr r0, 0x0} | |
3947 * <p> | |
3948 * Constraint: {@code 0 <= spr && spr <= 1023}<br /> | |
3949 * | |
3950 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.13 [Book 1]" | |
3951 */ | |
3952 // Template#: 228, Serial#: 228 | |
3953 public void mfspr(final GPR rt, final int spr) { | |
3954 int instruction = 0x7C0002A6; | |
3955 checkConstraint(0 <= spr && spr <= 1023, "0 <= spr && spr <= 1023"); | |
3956 instruction |= ((rt.value() & 0x1f) << 21); | |
3957 instruction |= ((spr & 0x1f) << 16) | (((spr >>> 5) & 0x1f) << 11); | |
3958 emitInt(instruction); | |
3959 } | |
3960 | |
3961 /** | |
3962 * Pseudo-external assembler syntax: {@code mtcrf }<i>fxm</i>, <i>rs</i> | |
3963 * Example disassembly syntax: {@code mtcrf 0x0, r0} | |
3964 * <p> | |
3965 * Constraint: {@code 0 <= fxm && fxm <= 255}<br /> | |
3966 * | |
3967 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.13 [Book 1]" | |
3968 */ | |
3969 // Template#: 229, Serial#: 229 | |
3970 public void mtcrf(final int fxm, final GPR rs) { | |
3971 int instruction = 0x7C000120; | |
3972 checkConstraint(0 <= fxm && fxm <= 255, "0 <= fxm && fxm <= 255"); | |
3973 instruction |= ((fxm & 0xff) << 12); | |
3974 instruction |= ((rs.value() & 0x1f) << 21); | |
3975 emitInt(instruction); | |
3976 } | |
3977 | |
3978 /** | |
3979 * Pseudo-external assembler syntax: {@code mfcr }<i>rt</i> | |
3980 * Example disassembly syntax: {@code mfcr r0} | |
3981 * | |
3982 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.13 [Book 1]" | |
3983 */ | |
3984 // Template#: 230, Serial#: 230 | |
3985 public void mfcr(final GPR rt) { | |
3986 int instruction = 0x7C000026; | |
3987 instruction |= ((rt.value() & 0x1f) << 21); | |
3988 emitInt(instruction); | |
3989 } | |
3990 | |
3991 /** | |
3992 * Pseudo-external assembler syntax: {@code lfs }<i>frt</i>, <i>d</i>, <i>ra</i> | |
3993 * Example disassembly syntax: {@code lfs f0, -32768(0)} | |
3994 * <p> | |
3995 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
3996 * Constraint: {@code ra != R0}<br /> | |
3997 * | |
3998 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.2 [Book 1]" | |
3999 */ | |
4000 // Template#: 231, Serial#: 231 | |
4001 public void lfs(final FPR frt, final int d, final ZeroOrRegister ra) { | |
4002 int instruction = 0xC0000000; | |
4003 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
4004 checkConstraint(ra != R0, "ra != R0"); | |
4005 instruction |= ((frt.value() & 0x1f) << 21); | |
4006 instruction |= (d & 0xffff); | |
4007 instruction |= ((ra.value() & 0x1f) << 16); | |
4008 emitInt(instruction); | |
4009 } | |
4010 | |
4011 /** | |
4012 * Pseudo-external assembler syntax: {@code lfsx }<i>frt</i>, <i>ra</i>, <i>rb</i> | |
4013 * Example disassembly syntax: {@code lfsx f0, 0, r0} | |
4014 * <p> | |
4015 * Constraint: {@code ra != R0}<br /> | |
4016 * | |
4017 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.2 [Book 1]" | |
4018 */ | |
4019 // Template#: 232, Serial#: 232 | |
4020 public void lfsx(final FPR frt, final ZeroOrRegister ra, final GPR rb) { | |
4021 int instruction = 0x7C00042E; | |
4022 checkConstraint(ra != R0, "ra != R0"); | |
4023 instruction |= ((frt.value() & 0x1f) << 21); | |
4024 instruction |= ((ra.value() & 0x1f) << 16); | |
4025 instruction |= ((rb.value() & 0x1f) << 11); | |
4026 emitInt(instruction); | |
4027 } | |
4028 | |
4029 /** | |
4030 * Pseudo-external assembler syntax: {@code lfsu }<i>frt</i>, <i>d</i>, <i>ra</i> | |
4031 * Example disassembly syntax: {@code lfsu f0, -32768(r0)} | |
4032 * <p> | |
4033 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
4034 * Constraint: {@code ra != R0}<br /> | |
4035 * | |
4036 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.2 [Book 1]" | |
4037 */ | |
4038 // Template#: 233, Serial#: 233 | |
4039 public void lfsu(final FPR frt, final int d, final GPR ra) { | |
4040 int instruction = 0xC4000000; | |
4041 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
4042 checkConstraint(ra != R0, "ra != R0"); | |
4043 instruction |= ((frt.value() & 0x1f) << 21); | |
4044 instruction |= (d & 0xffff); | |
4045 instruction |= ((ra.value() & 0x1f) << 16); | |
4046 emitInt(instruction); | |
4047 } | |
4048 | |
4049 /** | |
4050 * Pseudo-external assembler syntax: {@code lfsux }<i>frt</i>, <i>ra</i>, <i>rb</i> | |
4051 * Example disassembly syntax: {@code lfsux f0, r0, r0} | |
4052 * <p> | |
4053 * Constraint: {@code ra != R0}<br /> | |
4054 * | |
4055 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.2 [Book 1]" | |
4056 */ | |
4057 // Template#: 234, Serial#: 234 | |
4058 public void lfsux(final FPR frt, final GPR ra, final GPR rb) { | |
4059 int instruction = 0x7C00046E; | |
4060 checkConstraint(ra != R0, "ra != R0"); | |
4061 instruction |= ((frt.value() & 0x1f) << 21); | |
4062 instruction |= ((ra.value() & 0x1f) << 16); | |
4063 instruction |= ((rb.value() & 0x1f) << 11); | |
4064 emitInt(instruction); | |
4065 } | |
4066 | |
4067 /** | |
4068 * Pseudo-external assembler syntax: {@code lfd }<i>frt</i>, <i>d</i>, <i>ra</i> | |
4069 * Example disassembly syntax: {@code lfd f0, -32768(0)} | |
4070 * <p> | |
4071 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
4072 * Constraint: {@code ra != R0}<br /> | |
4073 * | |
4074 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.2 [Book 1]" | |
4075 */ | |
4076 // Template#: 235, Serial#: 235 | |
4077 public void lfd(final FPR frt, final int d, final ZeroOrRegister ra) { | |
4078 int instruction = 0xC8000000; | |
4079 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
4080 checkConstraint(ra != R0, "ra != R0"); | |
4081 instruction |= ((frt.value() & 0x1f) << 21); | |
4082 instruction |= (d & 0xffff); | |
4083 instruction |= ((ra.value() & 0x1f) << 16); | |
4084 emitInt(instruction); | |
4085 } | |
4086 | |
4087 /** | |
4088 * Pseudo-external assembler syntax: {@code lfdx }<i>frt</i>, <i>ra</i>, <i>rb</i> | |
4089 * Example disassembly syntax: {@code lfdx f0, 0, r0} | |
4090 * <p> | |
4091 * Constraint: {@code ra != R0}<br /> | |
4092 * | |
4093 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.2 [Book 1]" | |
4094 */ | |
4095 // Template#: 236, Serial#: 236 | |
4096 public void lfdx(final FPR frt, final ZeroOrRegister ra, final GPR rb) { | |
4097 int instruction = 0x7C0004AE; | |
4098 checkConstraint(ra != R0, "ra != R0"); | |
4099 instruction |= ((frt.value() & 0x1f) << 21); | |
4100 instruction |= ((ra.value() & 0x1f) << 16); | |
4101 instruction |= ((rb.value() & 0x1f) << 11); | |
4102 emitInt(instruction); | |
4103 } | |
4104 | |
4105 /** | |
4106 * Pseudo-external assembler syntax: {@code lfdu }<i>frt</i>, <i>d</i>, <i>ra</i> | |
4107 * Example disassembly syntax: {@code lfdu f0, -32768(r0)} | |
4108 * <p> | |
4109 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
4110 * Constraint: {@code ra != R0}<br /> | |
4111 * | |
4112 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.2 [Book 1]" | |
4113 */ | |
4114 // Template#: 237, Serial#: 237 | |
4115 public void lfdu(final FPR frt, final int d, final GPR ra) { | |
4116 int instruction = 0xCC000000; | |
4117 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
4118 checkConstraint(ra != R0, "ra != R0"); | |
4119 instruction |= ((frt.value() & 0x1f) << 21); | |
4120 instruction |= (d & 0xffff); | |
4121 instruction |= ((ra.value() & 0x1f) << 16); | |
4122 emitInt(instruction); | |
4123 } | |
4124 | |
4125 /** | |
4126 * Pseudo-external assembler syntax: {@code lfdux }<i>frt</i>, <i>ra</i>, <i>rb</i> | |
4127 * Example disassembly syntax: {@code lfdux f0, r0, r0} | |
4128 * <p> | |
4129 * Constraint: {@code ra != R0}<br /> | |
4130 * | |
4131 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.2 [Book 1]" | |
4132 */ | |
4133 // Template#: 238, Serial#: 238 | |
4134 public void lfdux(final FPR frt, final GPR ra, final GPR rb) { | |
4135 int instruction = 0x7C0004EE; | |
4136 checkConstraint(ra != R0, "ra != R0"); | |
4137 instruction |= ((frt.value() & 0x1f) << 21); | |
4138 instruction |= ((ra.value() & 0x1f) << 16); | |
4139 instruction |= ((rb.value() & 0x1f) << 11); | |
4140 emitInt(instruction); | |
4141 } | |
4142 | |
4143 /** | |
4144 * Pseudo-external assembler syntax: {@code stfs }<i>frs</i>, <i>d</i>, <i>ra</i> | |
4145 * Example disassembly syntax: {@code stfs f0, -32768(0)} | |
4146 * <p> | |
4147 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
4148 * Constraint: {@code ra != R0}<br /> | |
4149 * | |
4150 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.3 [Book 1]" | |
4151 */ | |
4152 // Template#: 239, Serial#: 239 | |
4153 public void stfs(final FPR frs, final int d, final ZeroOrRegister ra) { | |
4154 int instruction = 0xD0000000; | |
4155 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
4156 checkConstraint(ra != R0, "ra != R0"); | |
4157 instruction |= ((frs.value() & 0x1f) << 21); | |
4158 instruction |= (d & 0xffff); | |
4159 instruction |= ((ra.value() & 0x1f) << 16); | |
4160 emitInt(instruction); | |
4161 } | |
4162 | |
4163 /** | |
4164 * Pseudo-external assembler syntax: {@code stfsx }<i>frs</i>, <i>ra</i>, <i>rb</i> | |
4165 * Example disassembly syntax: {@code stfsx f0, 0, r0} | |
4166 * <p> | |
4167 * Constraint: {@code ra != R0}<br /> | |
4168 * | |
4169 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.3 [Book 1]" | |
4170 */ | |
4171 // Template#: 240, Serial#: 240 | |
4172 public void stfsx(final FPR frs, final ZeroOrRegister ra, final GPR rb) { | |
4173 int instruction = 0x7C00052E; | |
4174 checkConstraint(ra != R0, "ra != R0"); | |
4175 instruction |= ((frs.value() & 0x1f) << 21); | |
4176 instruction |= ((ra.value() & 0x1f) << 16); | |
4177 instruction |= ((rb.value() & 0x1f) << 11); | |
4178 emitInt(instruction); | |
4179 } | |
4180 | |
4181 /** | |
4182 * Pseudo-external assembler syntax: {@code stfsu }<i>frs</i>, <i>d</i>, <i>ra</i> | |
4183 * Example disassembly syntax: {@code stfsu f0, -32768(r0)} | |
4184 * <p> | |
4185 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
4186 * Constraint: {@code ra != R0}<br /> | |
4187 * | |
4188 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.3 [Book 1]" | |
4189 */ | |
4190 // Template#: 241, Serial#: 241 | |
4191 public void stfsu(final FPR frs, final int d, final GPR ra) { | |
4192 int instruction = 0xD4000000; | |
4193 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
4194 checkConstraint(ra != R0, "ra != R0"); | |
4195 instruction |= ((frs.value() & 0x1f) << 21); | |
4196 instruction |= (d & 0xffff); | |
4197 instruction |= ((ra.value() & 0x1f) << 16); | |
4198 emitInt(instruction); | |
4199 } | |
4200 | |
4201 /** | |
4202 * Pseudo-external assembler syntax: {@code stfsux }<i>frs</i>, <i>ra</i>, <i>rb</i> | |
4203 * Example disassembly syntax: {@code stfsux f0, r0, r0} | |
4204 * <p> | |
4205 * Constraint: {@code ra != R0}<br /> | |
4206 * | |
4207 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.3 [Book 1]" | |
4208 */ | |
4209 // Template#: 242, Serial#: 242 | |
4210 public void stfsux(final FPR frs, final GPR ra, final GPR rb) { | |
4211 int instruction = 0x7C00056E; | |
4212 checkConstraint(ra != R0, "ra != R0"); | |
4213 instruction |= ((frs.value() & 0x1f) << 21); | |
4214 instruction |= ((ra.value() & 0x1f) << 16); | |
4215 instruction |= ((rb.value() & 0x1f) << 11); | |
4216 emitInt(instruction); | |
4217 } | |
4218 | |
4219 /** | |
4220 * Pseudo-external assembler syntax: {@code stfd }<i>frs</i>, <i>d</i>, <i>ra</i> | |
4221 * Example disassembly syntax: {@code stfd f0, -32768(0)} | |
4222 * <p> | |
4223 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
4224 * Constraint: {@code ra != R0}<br /> | |
4225 * | |
4226 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.3 [Book 1]" | |
4227 */ | |
4228 // Template#: 243, Serial#: 243 | |
4229 public void stfd(final FPR frs, final int d, final ZeroOrRegister ra) { | |
4230 int instruction = 0xD8000000; | |
4231 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
4232 checkConstraint(ra != R0, "ra != R0"); | |
4233 instruction |= ((frs.value() & 0x1f) << 21); | |
4234 instruction |= (d & 0xffff); | |
4235 instruction |= ((ra.value() & 0x1f) << 16); | |
4236 emitInt(instruction); | |
4237 } | |
4238 | |
4239 /** | |
4240 * Pseudo-external assembler syntax: {@code stfdx }<i>frs</i>, <i>ra</i>, <i>rb</i> | |
4241 * Example disassembly syntax: {@code stfdx f0, 0, r0} | |
4242 * <p> | |
4243 * Constraint: {@code ra != R0}<br /> | |
4244 * | |
4245 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.3 [Book 1]" | |
4246 */ | |
4247 // Template#: 244, Serial#: 244 | |
4248 public void stfdx(final FPR frs, final ZeroOrRegister ra, final GPR rb) { | |
4249 int instruction = 0x7C0005AE; | |
4250 checkConstraint(ra != R0, "ra != R0"); | |
4251 instruction |= ((frs.value() & 0x1f) << 21); | |
4252 instruction |= ((ra.value() & 0x1f) << 16); | |
4253 instruction |= ((rb.value() & 0x1f) << 11); | |
4254 emitInt(instruction); | |
4255 } | |
4256 | |
4257 /** | |
4258 * Pseudo-external assembler syntax: {@code stfdu }<i>frs</i>, <i>d</i>, <i>ra</i> | |
4259 * Example disassembly syntax: {@code stfdu f0, -32768(r0)} | |
4260 * <p> | |
4261 * Constraint: {@code -32768 <= d && d <= 32767}<br /> | |
4262 * Constraint: {@code ra != R0}<br /> | |
4263 * | |
4264 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.3 [Book 1]" | |
4265 */ | |
4266 // Template#: 245, Serial#: 245 | |
4267 public void stfdu(final FPR frs, final int d, final GPR ra) { | |
4268 int instruction = 0xDC000000; | |
4269 checkConstraint(-32768 <= d && d <= 32767, "-32768 <= d && d <= 32767"); | |
4270 checkConstraint(ra != R0, "ra != R0"); | |
4271 instruction |= ((frs.value() & 0x1f) << 21); | |
4272 instruction |= (d & 0xffff); | |
4273 instruction |= ((ra.value() & 0x1f) << 16); | |
4274 emitInt(instruction); | |
4275 } | |
4276 | |
4277 /** | |
4278 * Pseudo-external assembler syntax: {@code stfdux }<i>frs</i>, <i>ra</i>, <i>rb</i> | |
4279 * Example disassembly syntax: {@code stfdux f0, r0, r0} | |
4280 * <p> | |
4281 * Constraint: {@code ra != R0}<br /> | |
4282 * | |
4283 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.3 [Book 1]" | |
4284 */ | |
4285 // Template#: 246, Serial#: 246 | |
4286 public void stfdux(final FPR frs, final GPR ra, final GPR rb) { | |
4287 int instruction = 0x7C0005EE; | |
4288 checkConstraint(ra != R0, "ra != R0"); | |
4289 instruction |= ((frs.value() & 0x1f) << 21); | |
4290 instruction |= ((ra.value() & 0x1f) << 16); | |
4291 instruction |= ((rb.value() & 0x1f) << 11); | |
4292 emitInt(instruction); | |
4293 } | |
4294 | |
4295 /** | |
4296 * Pseudo-external assembler syntax: {@code fmr }<i>frt</i>, <i>frb</i> | |
4297 * Example disassembly syntax: {@code fmr f0, f0} | |
4298 * | |
4299 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.4 [Book 1]" | |
4300 */ | |
4301 // Template#: 247, Serial#: 247 | |
4302 public void fmr(final FPR frt, final FPR frb) { | |
4303 int instruction = 0xFC000090; | |
4304 instruction |= ((frt.value() & 0x1f) << 21); | |
4305 instruction |= ((frb.value() & 0x1f) << 11); | |
4306 emitInt(instruction); | |
4307 } | |
4308 | |
4309 /** | |
4310 * Pseudo-external assembler syntax: {@code fmr. }<i>frt</i>, <i>frb</i> | |
4311 * Example disassembly syntax: {@code fmr. f0, f0} | |
4312 * | |
4313 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.4 [Book 1]" | |
4314 */ | |
4315 // Template#: 248, Serial#: 248 | |
4316 public void fmr_(final FPR frt, final FPR frb) { | |
4317 int instruction = 0xFC000091; | |
4318 instruction |= ((frt.value() & 0x1f) << 21); | |
4319 instruction |= ((frb.value() & 0x1f) << 11); | |
4320 emitInt(instruction); | |
4321 } | |
4322 | |
4323 /** | |
4324 * Pseudo-external assembler syntax: {@code fneg }<i>frt</i>, <i>frb</i> | |
4325 * Example disassembly syntax: {@code fneg f0, f0} | |
4326 * | |
4327 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.4 [Book 1]" | |
4328 */ | |
4329 // Template#: 249, Serial#: 249 | |
4330 public void fneg(final FPR frt, final FPR frb) { | |
4331 int instruction = 0xFC000050; | |
4332 instruction |= ((frt.value() & 0x1f) << 21); | |
4333 instruction |= ((frb.value() & 0x1f) << 11); | |
4334 emitInt(instruction); | |
4335 } | |
4336 | |
4337 /** | |
4338 * Pseudo-external assembler syntax: {@code fneg. }<i>frt</i>, <i>frb</i> | |
4339 * Example disassembly syntax: {@code fneg. f0, f0} | |
4340 * | |
4341 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.4 [Book 1]" | |
4342 */ | |
4343 // Template#: 250, Serial#: 250 | |
4344 public void fneg_(final FPR frt, final FPR frb) { | |
4345 int instruction = 0xFC000051; | |
4346 instruction |= ((frt.value() & 0x1f) << 21); | |
4347 instruction |= ((frb.value() & 0x1f) << 11); | |
4348 emitInt(instruction); | |
4349 } | |
4350 | |
4351 /** | |
4352 * Pseudo-external assembler syntax: {@code fabs }<i>frt</i>, <i>frb</i> | |
4353 * Example disassembly syntax: {@code fabs f0, f0} | |
4354 * | |
4355 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.4 [Book 1]" | |
4356 */ | |
4357 // Template#: 251, Serial#: 251 | |
4358 public void fabs(final FPR frt, final FPR frb) { | |
4359 int instruction = 0xFC000210; | |
4360 instruction |= ((frt.value() & 0x1f) << 21); | |
4361 instruction |= ((frb.value() & 0x1f) << 11); | |
4362 emitInt(instruction); | |
4363 } | |
4364 | |
4365 /** | |
4366 * Pseudo-external assembler syntax: {@code fabs. }<i>frt</i>, <i>frb</i> | |
4367 * Example disassembly syntax: {@code fabs. f0, f0} | |
4368 * | |
4369 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.4 [Book 1]" | |
4370 */ | |
4371 // Template#: 252, Serial#: 252 | |
4372 public void fabs_(final FPR frt, final FPR frb) { | |
4373 int instruction = 0xFC000211; | |
4374 instruction |= ((frt.value() & 0x1f) << 21); | |
4375 instruction |= ((frb.value() & 0x1f) << 11); | |
4376 emitInt(instruction); | |
4377 } | |
4378 | |
4379 /** | |
4380 * Pseudo-external assembler syntax: {@code fnabs }<i>frt</i>, <i>frb</i> | |
4381 * Example disassembly syntax: {@code fnabs f0, f0} | |
4382 * | |
4383 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.4 [Book 1]" | |
4384 */ | |
4385 // Template#: 253, Serial#: 253 | |
4386 public void fnabs(final FPR frt, final FPR frb) { | |
4387 int instruction = 0xFC000110; | |
4388 instruction |= ((frt.value() & 0x1f) << 21); | |
4389 instruction |= ((frb.value() & 0x1f) << 11); | |
4390 emitInt(instruction); | |
4391 } | |
4392 | |
4393 /** | |
4394 * Pseudo-external assembler syntax: {@code fnabs. }<i>frt</i>, <i>frb</i> | |
4395 * Example disassembly syntax: {@code fnabs. f0, f0} | |
4396 * | |
4397 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.4 [Book 1]" | |
4398 */ | |
4399 // Template#: 254, Serial#: 254 | |
4400 public void fnabs_(final FPR frt, final FPR frb) { | |
4401 int instruction = 0xFC000111; | |
4402 instruction |= ((frt.value() & 0x1f) << 21); | |
4403 instruction |= ((frb.value() & 0x1f) << 11); | |
4404 emitInt(instruction); | |
4405 } | |
4406 | |
4407 /** | |
4408 * Pseudo-external assembler syntax: {@code fadd }<i>frt</i>, <i>fra</i>, <i>frb</i> | |
4409 * Example disassembly syntax: {@code fadd f0, f0, f0} | |
4410 * | |
4411 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4412 */ | |
4413 // Template#: 255, Serial#: 255 | |
4414 public void fadd(final FPR frt, final FPR fra, final FPR frb) { | |
4415 int instruction = 0xFC00002A; | |
4416 instruction |= ((frt.value() & 0x1f) << 21); | |
4417 instruction |= ((fra.value() & 0x1f) << 16); | |
4418 instruction |= ((frb.value() & 0x1f) << 11); | |
4419 emitInt(instruction); | |
4420 } | |
4421 | |
4422 /** | |
4423 * Pseudo-external assembler syntax: {@code fadd. }<i>frt</i>, <i>fra</i>, <i>frb</i> | |
4424 * Example disassembly syntax: {@code fadd. f0, f0, f0} | |
4425 * | |
4426 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4427 */ | |
4428 // Template#: 256, Serial#: 256 | |
4429 public void fadd_(final FPR frt, final FPR fra, final FPR frb) { | |
4430 int instruction = 0xFC00002B; | |
4431 instruction |= ((frt.value() & 0x1f) << 21); | |
4432 instruction |= ((fra.value() & 0x1f) << 16); | |
4433 instruction |= ((frb.value() & 0x1f) << 11); | |
4434 emitInt(instruction); | |
4435 } | |
4436 | |
4437 /** | |
4438 * Pseudo-external assembler syntax: {@code fadds }<i>frt</i>, <i>fra</i>, <i>frb</i> | |
4439 * Example disassembly syntax: {@code fadds f0, f0, f0} | |
4440 * | |
4441 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4442 */ | |
4443 // Template#: 257, Serial#: 257 | |
4444 public void fadds(final FPR frt, final FPR fra, final FPR frb) { | |
4445 int instruction = 0xEC00002A; | |
4446 instruction |= ((frt.value() & 0x1f) << 21); | |
4447 instruction |= ((fra.value() & 0x1f) << 16); | |
4448 instruction |= ((frb.value() & 0x1f) << 11); | |
4449 emitInt(instruction); | |
4450 } | |
4451 | |
4452 /** | |
4453 * Pseudo-external assembler syntax: {@code fadds. }<i>frt</i>, <i>fra</i>, <i>frb</i> | |
4454 * Example disassembly syntax: {@code fadds. f0, f0, f0} | |
4455 * | |
4456 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4457 */ | |
4458 // Template#: 258, Serial#: 258 | |
4459 public void fadds_(final FPR frt, final FPR fra, final FPR frb) { | |
4460 int instruction = 0xEC00002B; | |
4461 instruction |= ((frt.value() & 0x1f) << 21); | |
4462 instruction |= ((fra.value() & 0x1f) << 16); | |
4463 instruction |= ((frb.value() & 0x1f) << 11); | |
4464 emitInt(instruction); | |
4465 } | |
4466 | |
4467 /** | |
4468 * Pseudo-external assembler syntax: {@code fsub }<i>frt</i>, <i>fra</i>, <i>frb</i> | |
4469 * Example disassembly syntax: {@code fsub f0, f0, f0} | |
4470 * | |
4471 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4472 */ | |
4473 // Template#: 259, Serial#: 259 | |
4474 public void fsub(final FPR frt, final FPR fra, final FPR frb) { | |
4475 int instruction = 0xFC000028; | |
4476 instruction |= ((frt.value() & 0x1f) << 21); | |
4477 instruction |= ((fra.value() & 0x1f) << 16); | |
4478 instruction |= ((frb.value() & 0x1f) << 11); | |
4479 emitInt(instruction); | |
4480 } | |
4481 | |
4482 /** | |
4483 * Pseudo-external assembler syntax: {@code fsub. }<i>frt</i>, <i>fra</i>, <i>frb</i> | |
4484 * Example disassembly syntax: {@code fsub. f0, f0, f0} | |
4485 * | |
4486 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4487 */ | |
4488 // Template#: 260, Serial#: 260 | |
4489 public void fsub_(final FPR frt, final FPR fra, final FPR frb) { | |
4490 int instruction = 0xFC000029; | |
4491 instruction |= ((frt.value() & 0x1f) << 21); | |
4492 instruction |= ((fra.value() & 0x1f) << 16); | |
4493 instruction |= ((frb.value() & 0x1f) << 11); | |
4494 emitInt(instruction); | |
4495 } | |
4496 | |
4497 /** | |
4498 * Pseudo-external assembler syntax: {@code fsubs }<i>frt</i>, <i>fra</i>, <i>frb</i> | |
4499 * Example disassembly syntax: {@code fsubs f0, f0, f0} | |
4500 * | |
4501 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4502 */ | |
4503 // Template#: 261, Serial#: 261 | |
4504 public void fsubs(final FPR frt, final FPR fra, final FPR frb) { | |
4505 int instruction = 0xEC000028; | |
4506 instruction |= ((frt.value() & 0x1f) << 21); | |
4507 instruction |= ((fra.value() & 0x1f) << 16); | |
4508 instruction |= ((frb.value() & 0x1f) << 11); | |
4509 emitInt(instruction); | |
4510 } | |
4511 | |
4512 /** | |
4513 * Pseudo-external assembler syntax: {@code fsubs. }<i>frt</i>, <i>fra</i>, <i>frb</i> | |
4514 * Example disassembly syntax: {@code fsubs. f0, f0, f0} | |
4515 * | |
4516 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4517 */ | |
4518 // Template#: 262, Serial#: 262 | |
4519 public void fsubs_(final FPR frt, final FPR fra, final FPR frb) { | |
4520 int instruction = 0xEC000029; | |
4521 instruction |= ((frt.value() & 0x1f) << 21); | |
4522 instruction |= ((fra.value() & 0x1f) << 16); | |
4523 instruction |= ((frb.value() & 0x1f) << 11); | |
4524 emitInt(instruction); | |
4525 } | |
4526 | |
4527 /** | |
4528 * Pseudo-external assembler syntax: {@code fmul }<i>frt</i>, <i>fra</i>, <i>frc</i> | |
4529 * Example disassembly syntax: {@code fmul f0, f0, f0} | |
4530 * | |
4531 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4532 */ | |
4533 // Template#: 263, Serial#: 263 | |
4534 public void fmul(final FPR frt, final FPR fra, final FPR frc) { | |
4535 int instruction = 0xFC000032; | |
4536 instruction |= ((frt.value() & 0x1f) << 21); | |
4537 instruction |= ((fra.value() & 0x1f) << 16); | |
4538 instruction |= ((frc.value() & 0x1f) << 6); | |
4539 emitInt(instruction); | |
4540 } | |
4541 | |
4542 /** | |
4543 * Pseudo-external assembler syntax: {@code fmul. }<i>frt</i>, <i>fra</i>, <i>frc</i> | |
4544 * Example disassembly syntax: {@code fmul. f0, f0, f0} | |
4545 * | |
4546 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4547 */ | |
4548 // Template#: 264, Serial#: 264 | |
4549 public void fmul_(final FPR frt, final FPR fra, final FPR frc) { | |
4550 int instruction = 0xFC000033; | |
4551 instruction |= ((frt.value() & 0x1f) << 21); | |
4552 instruction |= ((fra.value() & 0x1f) << 16); | |
4553 instruction |= ((frc.value() & 0x1f) << 6); | |
4554 emitInt(instruction); | |
4555 } | |
4556 | |
4557 /** | |
4558 * Pseudo-external assembler syntax: {@code fmuls }<i>frt</i>, <i>fra</i>, <i>frc</i> | |
4559 * Example disassembly syntax: {@code fmuls f0, f0, f0} | |
4560 * | |
4561 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4562 */ | |
4563 // Template#: 265, Serial#: 265 | |
4564 public void fmuls(final FPR frt, final FPR fra, final FPR frc) { | |
4565 int instruction = 0xEC000032; | |
4566 instruction |= ((frt.value() & 0x1f) << 21); | |
4567 instruction |= ((fra.value() & 0x1f) << 16); | |
4568 instruction |= ((frc.value() & 0x1f) << 6); | |
4569 emitInt(instruction); | |
4570 } | |
4571 | |
4572 /** | |
4573 * Pseudo-external assembler syntax: {@code fmuls. }<i>frt</i>, <i>fra</i>, <i>frc</i> | |
4574 * Example disassembly syntax: {@code fmuls. f0, f0, f0} | |
4575 * | |
4576 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4577 */ | |
4578 // Template#: 266, Serial#: 266 | |
4579 public void fmuls_(final FPR frt, final FPR fra, final FPR frc) { | |
4580 int instruction = 0xEC000033; | |
4581 instruction |= ((frt.value() & 0x1f) << 21); | |
4582 instruction |= ((fra.value() & 0x1f) << 16); | |
4583 instruction |= ((frc.value() & 0x1f) << 6); | |
4584 emitInt(instruction); | |
4585 } | |
4586 | |
4587 /** | |
4588 * Pseudo-external assembler syntax: {@code fdiv }<i>frt</i>, <i>fra</i>, <i>frb</i> | |
4589 * Example disassembly syntax: {@code fdiv f0, f0, f0} | |
4590 * | |
4591 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4592 */ | |
4593 // Template#: 267, Serial#: 267 | |
4594 public void fdiv(final FPR frt, final FPR fra, final FPR frb) { | |
4595 int instruction = 0xFC000024; | |
4596 instruction |= ((frt.value() & 0x1f) << 21); | |
4597 instruction |= ((fra.value() & 0x1f) << 16); | |
4598 instruction |= ((frb.value() & 0x1f) << 11); | |
4599 emitInt(instruction); | |
4600 } | |
4601 | |
4602 /** | |
4603 * Pseudo-external assembler syntax: {@code fdiv. }<i>frt</i>, <i>fra</i>, <i>frb</i> | |
4604 * Example disassembly syntax: {@code fdiv. f0, f0, f0} | |
4605 * | |
4606 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4607 */ | |
4608 // Template#: 268, Serial#: 268 | |
4609 public void fdiv_(final FPR frt, final FPR fra, final FPR frb) { | |
4610 int instruction = 0xFC000025; | |
4611 instruction |= ((frt.value() & 0x1f) << 21); | |
4612 instruction |= ((fra.value() & 0x1f) << 16); | |
4613 instruction |= ((frb.value() & 0x1f) << 11); | |
4614 emitInt(instruction); | |
4615 } | |
4616 | |
4617 /** | |
4618 * Pseudo-external assembler syntax: {@code fdivs }<i>frt</i>, <i>fra</i>, <i>frb</i> | |
4619 * Example disassembly syntax: {@code fdivs f0, f0, f0} | |
4620 * | |
4621 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4622 */ | |
4623 // Template#: 269, Serial#: 269 | |
4624 public void fdivs(final FPR frt, final FPR fra, final FPR frb) { | |
4625 int instruction = 0xEC000024; | |
4626 instruction |= ((frt.value() & 0x1f) << 21); | |
4627 instruction |= ((fra.value() & 0x1f) << 16); | |
4628 instruction |= ((frb.value() & 0x1f) << 11); | |
4629 emitInt(instruction); | |
4630 } | |
4631 | |
4632 /** | |
4633 * Pseudo-external assembler syntax: {@code fdivs. }<i>frt</i>, <i>fra</i>, <i>frb</i> | |
4634 * Example disassembly syntax: {@code fdivs. f0, f0, f0} | |
4635 * | |
4636 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4637 */ | |
4638 // Template#: 270, Serial#: 270 | |
4639 public void fdivs_(final FPR frt, final FPR fra, final FPR frb) { | |
4640 int instruction = 0xEC000025; | |
4641 instruction |= ((frt.value() & 0x1f) << 21); | |
4642 instruction |= ((fra.value() & 0x1f) << 16); | |
4643 instruction |= ((frb.value() & 0x1f) << 11); | |
4644 emitInt(instruction); | |
4645 } | |
4646 | |
4647 /** | |
4648 * Pseudo-external assembler syntax: {@code fmadd }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4649 * Example disassembly syntax: {@code fmadd f0, f0, f0, f0} | |
4650 * | |
4651 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4652 */ | |
4653 // Template#: 271, Serial#: 271 | |
4654 public void fmadd(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4655 int instruction = 0xFC00003A; | |
4656 instruction |= ((frt.value() & 0x1f) << 21); | |
4657 instruction |= ((fra.value() & 0x1f) << 16); | |
4658 instruction |= ((frc.value() & 0x1f) << 6); | |
4659 instruction |= ((frb.value() & 0x1f) << 11); | |
4660 emitInt(instruction); | |
4661 } | |
4662 | |
4663 /** | |
4664 * Pseudo-external assembler syntax: {@code fmadd. }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4665 * Example disassembly syntax: {@code fmadd. f0, f0, f0, f0} | |
4666 * | |
4667 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4668 */ | |
4669 // Template#: 272, Serial#: 272 | |
4670 public void fmadd_(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4671 int instruction = 0xFC00003B; | |
4672 instruction |= ((frt.value() & 0x1f) << 21); | |
4673 instruction |= ((fra.value() & 0x1f) << 16); | |
4674 instruction |= ((frc.value() & 0x1f) << 6); | |
4675 instruction |= ((frb.value() & 0x1f) << 11); | |
4676 emitInt(instruction); | |
4677 } | |
4678 | |
4679 /** | |
4680 * Pseudo-external assembler syntax: {@code fmadds }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4681 * Example disassembly syntax: {@code fmadds f0, f0, f0, f0} | |
4682 * | |
4683 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4684 */ | |
4685 // Template#: 273, Serial#: 273 | |
4686 public void fmadds(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4687 int instruction = 0xEC00003A; | |
4688 instruction |= ((frt.value() & 0x1f) << 21); | |
4689 instruction |= ((fra.value() & 0x1f) << 16); | |
4690 instruction |= ((frc.value() & 0x1f) << 6); | |
4691 instruction |= ((frb.value() & 0x1f) << 11); | |
4692 emitInt(instruction); | |
4693 } | |
4694 | |
4695 /** | |
4696 * Pseudo-external assembler syntax: {@code fmadds. }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4697 * Example disassembly syntax: {@code fmadds. f0, f0, f0, f0} | |
4698 * | |
4699 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4700 */ | |
4701 // Template#: 274, Serial#: 274 | |
4702 public void fmadds_(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4703 int instruction = 0xEC00003B; | |
4704 instruction |= ((frt.value() & 0x1f) << 21); | |
4705 instruction |= ((fra.value() & 0x1f) << 16); | |
4706 instruction |= ((frc.value() & 0x1f) << 6); | |
4707 instruction |= ((frb.value() & 0x1f) << 11); | |
4708 emitInt(instruction); | |
4709 } | |
4710 | |
4711 /** | |
4712 * Pseudo-external assembler syntax: {@code fmsub }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4713 * Example disassembly syntax: {@code fmsub f0, f0, f0, f0} | |
4714 * | |
4715 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4716 */ | |
4717 // Template#: 275, Serial#: 275 | |
4718 public void fmsub(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4719 int instruction = 0xFC000038; | |
4720 instruction |= ((frt.value() & 0x1f) << 21); | |
4721 instruction |= ((fra.value() & 0x1f) << 16); | |
4722 instruction |= ((frc.value() & 0x1f) << 6); | |
4723 instruction |= ((frb.value() & 0x1f) << 11); | |
4724 emitInt(instruction); | |
4725 } | |
4726 | |
4727 /** | |
4728 * Pseudo-external assembler syntax: {@code fmsub. }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4729 * Example disassembly syntax: {@code fmsub. f0, f0, f0, f0} | |
4730 * | |
4731 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4732 */ | |
4733 // Template#: 276, Serial#: 276 | |
4734 public void fmsub_(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4735 int instruction = 0xFC000039; | |
4736 instruction |= ((frt.value() & 0x1f) << 21); | |
4737 instruction |= ((fra.value() & 0x1f) << 16); | |
4738 instruction |= ((frc.value() & 0x1f) << 6); | |
4739 instruction |= ((frb.value() & 0x1f) << 11); | |
4740 emitInt(instruction); | |
4741 } | |
4742 | |
4743 /** | |
4744 * Pseudo-external assembler syntax: {@code fmsubs }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4745 * Example disassembly syntax: {@code fmsubs f0, f0, f0, f0} | |
4746 * | |
4747 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4748 */ | |
4749 // Template#: 277, Serial#: 277 | |
4750 public void fmsubs(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4751 int instruction = 0xEC000038; | |
4752 instruction |= ((frt.value() & 0x1f) << 21); | |
4753 instruction |= ((fra.value() & 0x1f) << 16); | |
4754 instruction |= ((frc.value() & 0x1f) << 6); | |
4755 instruction |= ((frb.value() & 0x1f) << 11); | |
4756 emitInt(instruction); | |
4757 } | |
4758 | |
4759 /** | |
4760 * Pseudo-external assembler syntax: {@code fmsubs. }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4761 * Example disassembly syntax: {@code fmsubs. f0, f0, f0, f0} | |
4762 * | |
4763 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4764 */ | |
4765 // Template#: 278, Serial#: 278 | |
4766 public void fmsubs_(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4767 int instruction = 0xEC000039; | |
4768 instruction |= ((frt.value() & 0x1f) << 21); | |
4769 instruction |= ((fra.value() & 0x1f) << 16); | |
4770 instruction |= ((frc.value() & 0x1f) << 6); | |
4771 instruction |= ((frb.value() & 0x1f) << 11); | |
4772 emitInt(instruction); | |
4773 } | |
4774 | |
4775 /** | |
4776 * Pseudo-external assembler syntax: {@code fnmadd }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4777 * Example disassembly syntax: {@code fnmadd f0, f0, f0, f0} | |
4778 * | |
4779 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4780 */ | |
4781 // Template#: 279, Serial#: 279 | |
4782 public void fnmadd(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4783 int instruction = 0xFC00003E; | |
4784 instruction |= ((frt.value() & 0x1f) << 21); | |
4785 instruction |= ((fra.value() & 0x1f) << 16); | |
4786 instruction |= ((frc.value() & 0x1f) << 6); | |
4787 instruction |= ((frb.value() & 0x1f) << 11); | |
4788 emitInt(instruction); | |
4789 } | |
4790 | |
4791 /** | |
4792 * Pseudo-external assembler syntax: {@code fnmadd. }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4793 * Example disassembly syntax: {@code fnmadd. f0, f0, f0, f0} | |
4794 * | |
4795 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4796 */ | |
4797 // Template#: 280, Serial#: 280 | |
4798 public void fnmadd_(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4799 int instruction = 0xFC00003F; | |
4800 instruction |= ((frt.value() & 0x1f) << 21); | |
4801 instruction |= ((fra.value() & 0x1f) << 16); | |
4802 instruction |= ((frc.value() & 0x1f) << 6); | |
4803 instruction |= ((frb.value() & 0x1f) << 11); | |
4804 emitInt(instruction); | |
4805 } | |
4806 | |
4807 /** | |
4808 * Pseudo-external assembler syntax: {@code fnmadds }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4809 * Example disassembly syntax: {@code fnmadds f0, f0, f0, f0} | |
4810 * | |
4811 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4812 */ | |
4813 // Template#: 281, Serial#: 281 | |
4814 public void fnmadds(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4815 int instruction = 0xEC00003E; | |
4816 instruction |= ((frt.value() & 0x1f) << 21); | |
4817 instruction |= ((fra.value() & 0x1f) << 16); | |
4818 instruction |= ((frc.value() & 0x1f) << 6); | |
4819 instruction |= ((frb.value() & 0x1f) << 11); | |
4820 emitInt(instruction); | |
4821 } | |
4822 | |
4823 /** | |
4824 * Pseudo-external assembler syntax: {@code fnmadds. }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4825 * Example disassembly syntax: {@code fnmadds. f0, f0, f0, f0} | |
4826 * | |
4827 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4828 */ | |
4829 // Template#: 282, Serial#: 282 | |
4830 public void fnmadds_(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4831 int instruction = 0xEC00003F; | |
4832 instruction |= ((frt.value() & 0x1f) << 21); | |
4833 instruction |= ((fra.value() & 0x1f) << 16); | |
4834 instruction |= ((frc.value() & 0x1f) << 6); | |
4835 instruction |= ((frb.value() & 0x1f) << 11); | |
4836 emitInt(instruction); | |
4837 } | |
4838 | |
4839 /** | |
4840 * Pseudo-external assembler syntax: {@code fnmsub }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4841 * Example disassembly syntax: {@code fnmsub f0, f0, f0, f0} | |
4842 * | |
4843 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4844 */ | |
4845 // Template#: 283, Serial#: 283 | |
4846 public void fnmsub(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4847 int instruction = 0xFC00003C; | |
4848 instruction |= ((frt.value() & 0x1f) << 21); | |
4849 instruction |= ((fra.value() & 0x1f) << 16); | |
4850 instruction |= ((frc.value() & 0x1f) << 6); | |
4851 instruction |= ((frb.value() & 0x1f) << 11); | |
4852 emitInt(instruction); | |
4853 } | |
4854 | |
4855 /** | |
4856 * Pseudo-external assembler syntax: {@code fnmsub. }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4857 * Example disassembly syntax: {@code fnmsub. f0, f0, f0, f0} | |
4858 * | |
4859 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4860 */ | |
4861 // Template#: 284, Serial#: 284 | |
4862 public void fnmsub_(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4863 int instruction = 0xFC00003D; | |
4864 instruction |= ((frt.value() & 0x1f) << 21); | |
4865 instruction |= ((fra.value() & 0x1f) << 16); | |
4866 instruction |= ((frc.value() & 0x1f) << 6); | |
4867 instruction |= ((frb.value() & 0x1f) << 11); | |
4868 emitInt(instruction); | |
4869 } | |
4870 | |
4871 /** | |
4872 * Pseudo-external assembler syntax: {@code fnmsubs }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4873 * Example disassembly syntax: {@code fnmsubs f0, f0, f0, f0} | |
4874 * | |
4875 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4876 */ | |
4877 // Template#: 285, Serial#: 285 | |
4878 public void fnmsubs(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4879 int instruction = 0xEC00003C; | |
4880 instruction |= ((frt.value() & 0x1f) << 21); | |
4881 instruction |= ((fra.value() & 0x1f) << 16); | |
4882 instruction |= ((frc.value() & 0x1f) << 6); | |
4883 instruction |= ((frb.value() & 0x1f) << 11); | |
4884 emitInt(instruction); | |
4885 } | |
4886 | |
4887 /** | |
4888 * Pseudo-external assembler syntax: {@code fnmsubs. }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
4889 * Example disassembly syntax: {@code fnmsubs. f0, f0, f0, f0} | |
4890 * | |
4891 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.5 [Book 1]" | |
4892 */ | |
4893 // Template#: 286, Serial#: 286 | |
4894 public void fnmsubs_(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
4895 int instruction = 0xEC00003D; | |
4896 instruction |= ((frt.value() & 0x1f) << 21); | |
4897 instruction |= ((fra.value() & 0x1f) << 16); | |
4898 instruction |= ((frc.value() & 0x1f) << 6); | |
4899 instruction |= ((frb.value() & 0x1f) << 11); | |
4900 emitInt(instruction); | |
4901 } | |
4902 | |
4903 /** | |
4904 * Pseudo-external assembler syntax: {@code frsp }<i>frt</i>, <i>frb</i> | |
4905 * Example disassembly syntax: {@code frsp f0, f0} | |
4906 * | |
4907 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.6 [Book 1]" | |
4908 */ | |
4909 // Template#: 287, Serial#: 287 | |
4910 public void frsp(final FPR frt, final FPR frb) { | |
4911 int instruction = 0xFC000018; | |
4912 instruction |= ((frt.value() & 0x1f) << 21); | |
4913 instruction |= ((frb.value() & 0x1f) << 11); | |
4914 emitInt(instruction); | |
4915 } | |
4916 | |
4917 /** | |
4918 * Pseudo-external assembler syntax: {@code frsp. }<i>frt</i>, <i>frb</i> | |
4919 * Example disassembly syntax: {@code frsp. f0, f0} | |
4920 * | |
4921 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.6 [Book 1]" | |
4922 */ | |
4923 // Template#: 288, Serial#: 288 | |
4924 public void frsp_(final FPR frt, final FPR frb) { | |
4925 int instruction = 0xFC000019; | |
4926 instruction |= ((frt.value() & 0x1f) << 21); | |
4927 instruction |= ((frb.value() & 0x1f) << 11); | |
4928 emitInt(instruction); | |
4929 } | |
4930 | |
4931 /** | |
4932 * Pseudo-external assembler syntax: {@code fctid }<i>frt</i>, <i>frb</i> | |
4933 * Example disassembly syntax: {@code fctid f0, f0} | |
4934 * | |
4935 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.6 [Book 1]" | |
4936 */ | |
4937 // Template#: 289, Serial#: 289 | |
4938 public void fctid(final FPR frt, final FPR frb) { | |
4939 int instruction = 0xFC00065C; | |
4940 instruction |= ((frt.value() & 0x1f) << 21); | |
4941 instruction |= ((frb.value() & 0x1f) << 11); | |
4942 emitInt(instruction); | |
4943 } | |
4944 | |
4945 /** | |
4946 * Pseudo-external assembler syntax: {@code fctid. }<i>frt</i>, <i>frb</i> | |
4947 * Example disassembly syntax: {@code fctid. f0, f0} | |
4948 * | |
4949 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.6 [Book 1]" | |
4950 */ | |
4951 // Template#: 290, Serial#: 290 | |
4952 public void fctid_(final FPR frt, final FPR frb) { | |
4953 int instruction = 0xFC00065D; | |
4954 instruction |= ((frt.value() & 0x1f) << 21); | |
4955 instruction |= ((frb.value() & 0x1f) << 11); | |
4956 emitInt(instruction); | |
4957 } | |
4958 | |
4959 /** | |
4960 * Pseudo-external assembler syntax: {@code fctidz }<i>frt</i>, <i>frb</i> | |
4961 * Example disassembly syntax: {@code fctidz f0, f0} | |
4962 * | |
4963 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.6 [Book 1]" | |
4964 */ | |
4965 // Template#: 291, Serial#: 291 | |
4966 public void fctidz(final FPR frt, final FPR frb) { | |
4967 int instruction = 0xFC00065E; | |
4968 instruction |= ((frt.value() & 0x1f) << 21); | |
4969 instruction |= ((frb.value() & 0x1f) << 11); | |
4970 emitInt(instruction); | |
4971 } | |
4972 | |
4973 /** | |
4974 * Pseudo-external assembler syntax: {@code fctidz. }<i>frt</i>, <i>frb</i> | |
4975 * Example disassembly syntax: {@code fctidz. f0, f0} | |
4976 * | |
4977 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.6 [Book 1]" | |
4978 */ | |
4979 // Template#: 292, Serial#: 292 | |
4980 public void fctidz_(final FPR frt, final FPR frb) { | |
4981 int instruction = 0xFC00065F; | |
4982 instruction |= ((frt.value() & 0x1f) << 21); | |
4983 instruction |= ((frb.value() & 0x1f) << 11); | |
4984 emitInt(instruction); | |
4985 } | |
4986 | |
4987 /** | |
4988 * Pseudo-external assembler syntax: {@code fctiw }<i>frt</i>, <i>frb</i> | |
4989 * Example disassembly syntax: {@code fctiw f0, f0} | |
4990 * | |
4991 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.6 [Book 1]" | |
4992 */ | |
4993 // Template#: 293, Serial#: 293 | |
4994 public void fctiw(final FPR frt, final FPR frb) { | |
4995 int instruction = 0xFC00001C; | |
4996 instruction |= ((frt.value() & 0x1f) << 21); | |
4997 instruction |= ((frb.value() & 0x1f) << 11); | |
4998 emitInt(instruction); | |
4999 } | |
5000 | |
5001 /** | |
5002 * Pseudo-external assembler syntax: {@code fctiw. }<i>frt</i>, <i>frb</i> | |
5003 * Example disassembly syntax: {@code fctiw. f0, f0} | |
5004 * | |
5005 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.6 [Book 1]" | |
5006 */ | |
5007 // Template#: 294, Serial#: 294 | |
5008 public void fctiw_(final FPR frt, final FPR frb) { | |
5009 int instruction = 0xFC00001D; | |
5010 instruction |= ((frt.value() & 0x1f) << 21); | |
5011 instruction |= ((frb.value() & 0x1f) << 11); | |
5012 emitInt(instruction); | |
5013 } | |
5014 | |
5015 /** | |
5016 * Pseudo-external assembler syntax: {@code fctiwz }<i>frt</i>, <i>frb</i> | |
5017 * Example disassembly syntax: {@code fctiwz f0, f0} | |
5018 * | |
5019 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.6 [Book 1]" | |
5020 */ | |
5021 // Template#: 295, Serial#: 295 | |
5022 public void fctiwz(final FPR frt, final FPR frb) { | |
5023 int instruction = 0xFC00001E; | |
5024 instruction |= ((frt.value() & 0x1f) << 21); | |
5025 instruction |= ((frb.value() & 0x1f) << 11); | |
5026 emitInt(instruction); | |
5027 } | |
5028 | |
5029 /** | |
5030 * Pseudo-external assembler syntax: {@code fctiwz. }<i>frt</i>, <i>frb</i> | |
5031 * Example disassembly syntax: {@code fctiwz. f0, f0} | |
5032 * | |
5033 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.6 [Book 1]" | |
5034 */ | |
5035 // Template#: 296, Serial#: 296 | |
5036 public void fctiwz_(final FPR frt, final FPR frb) { | |
5037 int instruction = 0xFC00001F; | |
5038 instruction |= ((frt.value() & 0x1f) << 21); | |
5039 instruction |= ((frb.value() & 0x1f) << 11); | |
5040 emitInt(instruction); | |
5041 } | |
5042 | |
5043 /** | |
5044 * Pseudo-external assembler syntax: {@code fcfid }<i>frt</i>, <i>frb</i> | |
5045 * Example disassembly syntax: {@code fcfid f0, f0} | |
5046 * | |
5047 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.6 [Book 1]" | |
5048 */ | |
5049 // Template#: 297, Serial#: 297 | |
5050 public void fcfid(final FPR frt, final FPR frb) { | |
5051 int instruction = 0xFC00069C; | |
5052 instruction |= ((frt.value() & 0x1f) << 21); | |
5053 instruction |= ((frb.value() & 0x1f) << 11); | |
5054 emitInt(instruction); | |
5055 } | |
5056 | |
5057 /** | |
5058 * Pseudo-external assembler syntax: {@code fcfid. }<i>frt</i>, <i>frb</i> | |
5059 * Example disassembly syntax: {@code fcfid. f0, f0} | |
5060 * | |
5061 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.6 [Book 1]" | |
5062 */ | |
5063 // Template#: 298, Serial#: 298 | |
5064 public void fcfid_(final FPR frt, final FPR frb) { | |
5065 int instruction = 0xFC00069D; | |
5066 instruction |= ((frt.value() & 0x1f) << 21); | |
5067 instruction |= ((frb.value() & 0x1f) << 11); | |
5068 emitInt(instruction); | |
5069 } | |
5070 | |
5071 /** | |
5072 * Pseudo-external assembler syntax: {@code fcmpu }<i>bf</i>, <i>fra</i>, <i>frb</i> | |
5073 * Example disassembly syntax: {@code fcmpu 0, f0, f0} | |
5074 * | |
5075 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.7 [Book 1]" | |
5076 */ | |
5077 // Template#: 299, Serial#: 299 | |
5078 public void fcmpu(final CRF bf, final FPR fra, final FPR frb) { | |
5079 int instruction = 0xFC000000; | |
5080 instruction |= ((bf.value() & 0x7) << 23); | |
5081 instruction |= ((fra.value() & 0x1f) << 16); | |
5082 instruction |= ((frb.value() & 0x1f) << 11); | |
5083 emitInt(instruction); | |
5084 } | |
5085 | |
5086 /** | |
5087 * Pseudo-external assembler syntax: {@code fcmpo }<i>bf</i>, <i>fra</i>, <i>frb</i> | |
5088 * Example disassembly syntax: {@code fcmpo 0, f0, f0} | |
5089 * | |
5090 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.7 [Book 1]" | |
5091 */ | |
5092 // Template#: 300, Serial#: 300 | |
5093 public void fcmpo(final CRF bf, final FPR fra, final FPR frb) { | |
5094 int instruction = 0xFC000040; | |
5095 instruction |= ((bf.value() & 0x7) << 23); | |
5096 instruction |= ((fra.value() & 0x1f) << 16); | |
5097 instruction |= ((frb.value() & 0x1f) << 11); | |
5098 emitInt(instruction); | |
5099 } | |
5100 | |
5101 /** | |
5102 * Pseudo-external assembler syntax: {@code mffs }<i>frt</i> | |
5103 * Example disassembly syntax: {@code mffs f0} | |
5104 * | |
5105 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.8 [Book 1]" | |
5106 */ | |
5107 // Template#: 301, Serial#: 301 | |
5108 public void mffs(final FPR frt) { | |
5109 int instruction = 0xFC00048E; | |
5110 instruction |= ((frt.value() & 0x1f) << 21); | |
5111 emitInt(instruction); | |
5112 } | |
5113 | |
5114 /** | |
5115 * Pseudo-external assembler syntax: {@code mffs. }<i>frt</i> | |
5116 * Example disassembly syntax: {@code mffs. f0} | |
5117 * | |
5118 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.8 [Book 1]" | |
5119 */ | |
5120 // Template#: 302, Serial#: 302 | |
5121 public void mffs_(final FPR frt) { | |
5122 int instruction = 0xFC00048F; | |
5123 instruction |= ((frt.value() & 0x1f) << 21); | |
5124 emitInt(instruction); | |
5125 } | |
5126 | |
5127 /** | |
5128 * Pseudo-external assembler syntax: {@code mcrfs }<i>bf</i>, <i>bfa</i> | |
5129 * Example disassembly syntax: {@code mcrfs 0, 0} | |
5130 * | |
5131 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.8 [Book 1]" | |
5132 */ | |
5133 // Template#: 303, Serial#: 303 | |
5134 public void mcrfs(final CRF bf, final CRF bfa) { | |
5135 int instruction = 0xFC000080; | |
5136 instruction |= ((bf.value() & 0x7) << 23); | |
5137 instruction |= ((bfa.value() & 0x7) << 18); | |
5138 emitInt(instruction); | |
5139 } | |
5140 | |
5141 /** | |
5142 * Pseudo-external assembler syntax: {@code mtfsfi }<i>bf</i>, <i>u</i> | |
5143 * Example disassembly syntax: {@code mtfsfi 0, 0x0} | |
5144 * <p> | |
5145 * Constraint: {@code 0 <= u && u <= 15}<br /> | |
5146 * | |
5147 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.8 [Book 1]" | |
5148 */ | |
5149 // Template#: 304, Serial#: 304 | |
5150 public void mtfsfi(final CRF bf, final int u) { | |
5151 int instruction = 0xFC00010C; | |
5152 checkConstraint(0 <= u && u <= 15, "0 <= u && u <= 15"); | |
5153 instruction |= ((bf.value() & 0x7) << 23); | |
5154 instruction |= ((u & 0xf) << 12); | |
5155 emitInt(instruction); | |
5156 } | |
5157 | |
5158 /** | |
5159 * Pseudo-external assembler syntax: {@code mtfsfi. }<i>bf</i>, <i>u</i> | |
5160 * Example disassembly syntax: {@code mtfsfi. 0, 0x0} | |
5161 * <p> | |
5162 * Constraint: {@code 0 <= u && u <= 15}<br /> | |
5163 * | |
5164 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.8 [Book 1]" | |
5165 */ | |
5166 // Template#: 305, Serial#: 305 | |
5167 public void mtfsfi_(final CRF bf, final int u) { | |
5168 int instruction = 0xFC00010D; | |
5169 checkConstraint(0 <= u && u <= 15, "0 <= u && u <= 15"); | |
5170 instruction |= ((bf.value() & 0x7) << 23); | |
5171 instruction |= ((u & 0xf) << 12); | |
5172 emitInt(instruction); | |
5173 } | |
5174 | |
5175 /** | |
5176 * Pseudo-external assembler syntax: {@code mtfsf }<i>flm</i>, <i>frb</i> | |
5177 * Example disassembly syntax: {@code mtfsf 0x0, f0} | |
5178 * <p> | |
5179 * Constraint: {@code 0 <= flm && flm <= 255}<br /> | |
5180 * | |
5181 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.8 [Book 1]" | |
5182 */ | |
5183 // Template#: 306, Serial#: 306 | |
5184 public void mtfsf(final int flm, final FPR frb) { | |
5185 int instruction = 0xFC00058E; | |
5186 checkConstraint(0 <= flm && flm <= 255, "0 <= flm && flm <= 255"); | |
5187 instruction |= ((flm & 0xff) << 17); | |
5188 instruction |= ((frb.value() & 0x1f) << 11); | |
5189 emitInt(instruction); | |
5190 } | |
5191 | |
5192 /** | |
5193 * Pseudo-external assembler syntax: {@code mtfsf. }<i>flm</i>, <i>frb</i> | |
5194 * Example disassembly syntax: {@code mtfsf. 0x0, f0} | |
5195 * <p> | |
5196 * Constraint: {@code 0 <= flm && flm <= 255}<br /> | |
5197 * | |
5198 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.8 [Book 1]" | |
5199 */ | |
5200 // Template#: 307, Serial#: 307 | |
5201 public void mtfsf_(final int flm, final FPR frb) { | |
5202 int instruction = 0xFC00058F; | |
5203 checkConstraint(0 <= flm && flm <= 255, "0 <= flm && flm <= 255"); | |
5204 instruction |= ((flm & 0xff) << 17); | |
5205 instruction |= ((frb.value() & 0x1f) << 11); | |
5206 emitInt(instruction); | |
5207 } | |
5208 | |
5209 /** | |
5210 * Pseudo-external assembler syntax: {@code mtfsb0 }<i>bt</i> | |
5211 * Example disassembly syntax: {@code mtfsb0 0x0} | |
5212 * <p> | |
5213 * Constraint: {@code 0 <= bt && bt <= 31}<br /> | |
5214 * | |
5215 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.8 [Book 1]" | |
5216 */ | |
5217 // Template#: 308, Serial#: 308 | |
5218 public void mtfsb0(final int bt) { | |
5219 int instruction = 0xFC00008C; | |
5220 checkConstraint(0 <= bt && bt <= 31, "0 <= bt && bt <= 31"); | |
5221 instruction |= ((bt & 0x1f) << 21); | |
5222 emitInt(instruction); | |
5223 } | |
5224 | |
5225 /** | |
5226 * Pseudo-external assembler syntax: {@code mtfsb0. }<i>bt</i> | |
5227 * Example disassembly syntax: {@code mtfsb0. 0x0} | |
5228 * <p> | |
5229 * Constraint: {@code 0 <= bt && bt <= 31}<br /> | |
5230 * | |
5231 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.8 [Book 1]" | |
5232 */ | |
5233 // Template#: 309, Serial#: 309 | |
5234 public void mtfsb0_(final int bt) { | |
5235 int instruction = 0xFC00008D; | |
5236 checkConstraint(0 <= bt && bt <= 31, "0 <= bt && bt <= 31"); | |
5237 instruction |= ((bt & 0x1f) << 21); | |
5238 emitInt(instruction); | |
5239 } | |
5240 | |
5241 /** | |
5242 * Pseudo-external assembler syntax: {@code mtfsb1 }<i>bt</i> | |
5243 * Example disassembly syntax: {@code mtfsb1 0x0} | |
5244 * <p> | |
5245 * Constraint: {@code 0 <= bt && bt <= 31}<br /> | |
5246 * | |
5247 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.8 [Book 1]" | |
5248 */ | |
5249 // Template#: 310, Serial#: 310 | |
5250 public void mtfsb1(final int bt) { | |
5251 int instruction = 0xFC00004C; | |
5252 checkConstraint(0 <= bt && bt <= 31, "0 <= bt && bt <= 31"); | |
5253 instruction |= ((bt & 0x1f) << 21); | |
5254 emitInt(instruction); | |
5255 } | |
5256 | |
5257 /** | |
5258 * Pseudo-external assembler syntax: {@code mtfsb1. }<i>bt</i> | |
5259 * Example disassembly syntax: {@code mtfsb1. 0x0} | |
5260 * <p> | |
5261 * Constraint: {@code 0 <= bt && bt <= 31}<br /> | |
5262 * | |
5263 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 4.6.8 [Book 1]" | |
5264 */ | |
5265 // Template#: 311, Serial#: 311 | |
5266 public void mtfsb1_(final int bt) { | |
5267 int instruction = 0xFC00004D; | |
5268 checkConstraint(0 <= bt && bt <= 31, "0 <= bt && bt <= 31"); | |
5269 instruction |= ((bt & 0x1f) << 21); | |
5270 emitInt(instruction); | |
5271 } | |
5272 | |
5273 /** | |
5274 * Pseudo-external assembler syntax: {@code mtocrf }<i>fxm</i>, <i>rs</i> | |
5275 * Example disassembly syntax: {@code mtocrf 0x0, r0} | |
5276 * <p> | |
5277 * Constraint: {@code 0 <= fxm && fxm <= 255}<br /> | |
5278 * | |
5279 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.1.1 [Book 1]" | |
5280 */ | |
5281 // Template#: 312, Serial#: 312 | |
5282 public void mtocrf(final int fxm, final GPR rs) { | |
5283 int instruction = 0x7C100120; | |
5284 checkConstraint(0 <= fxm && fxm <= 255, "0 <= fxm && fxm <= 255"); | |
5285 instruction |= ((fxm & 0xff) << 12); | |
5286 instruction |= ((rs.value() & 0x1f) << 21); | |
5287 emitInt(instruction); | |
5288 } | |
5289 | |
5290 /** | |
5291 * Pseudo-external assembler syntax: {@code mfocrf }<i>rt</i>, <i>fxm</i> | |
5292 * Example disassembly syntax: {@code mfocrf r0, 0x0} | |
5293 * <p> | |
5294 * Constraint: {@code 0 <= fxm && fxm <= 255}<br /> | |
5295 * Constraint: {@code CRF.isExactlyOneCRFSelected(fxm)}<br /> | |
5296 * | |
5297 * @see com.sun.max.asm.ppc.CRF#isExactlyOneCRFSelected | |
5298 * | |
5299 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.1.1 [Book 1]" | |
5300 */ | |
5301 // Template#: 313, Serial#: 313 | |
5302 public void mfocrf(final GPR rt, final int fxm) { | |
5303 int instruction = 0x7C100026; | |
5304 checkConstraint(0 <= fxm && fxm <= 255, "0 <= fxm && fxm <= 255"); | |
5305 checkConstraint(CRF.isExactlyOneCRFSelected(fxm), "CRF.isExactlyOneCRFSelected(fxm)"); | |
5306 instruction |= ((rt.value() & 0x1f) << 21); | |
5307 instruction |= ((fxm & 0xff) << 12); | |
5308 emitInt(instruction); | |
5309 } | |
5310 | |
5311 /** | |
5312 * Pseudo-external assembler syntax: {@code fsqrt }<i>frt</i>, <i>frb</i> | |
5313 * Example disassembly syntax: {@code fsqrt f0, f0} | |
5314 * | |
5315 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.2.1 [Book 1]" | |
5316 */ | |
5317 // Template#: 314, Serial#: 314 | |
5318 public void fsqrt(final FPR frt, final FPR frb) { | |
5319 int instruction = 0xFC00002C; | |
5320 instruction |= ((frt.value() & 0x1f) << 21); | |
5321 instruction |= ((frb.value() & 0x1f) << 11); | |
5322 emitInt(instruction); | |
5323 } | |
5324 | |
5325 /** | |
5326 * Pseudo-external assembler syntax: {@code fsqrt. }<i>frt</i>, <i>frb</i> | |
5327 * Example disassembly syntax: {@code fsqrt. f0, f0} | |
5328 * | |
5329 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.2.1 [Book 1]" | |
5330 */ | |
5331 // Template#: 315, Serial#: 315 | |
5332 public void fsqrt_(final FPR frt, final FPR frb) { | |
5333 int instruction = 0xFC00002D; | |
5334 instruction |= ((frt.value() & 0x1f) << 21); | |
5335 instruction |= ((frb.value() & 0x1f) << 11); | |
5336 emitInt(instruction); | |
5337 } | |
5338 | |
5339 /** | |
5340 * Pseudo-external assembler syntax: {@code fsqrts }<i>frt</i>, <i>frb</i> | |
5341 * Example disassembly syntax: {@code fsqrts f0, f0} | |
5342 * | |
5343 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.2.1 [Book 1]" | |
5344 */ | |
5345 // Template#: 316, Serial#: 316 | |
5346 public void fsqrts(final FPR frt, final FPR frb) { | |
5347 int instruction = 0xEC00002C; | |
5348 instruction |= ((frt.value() & 0x1f) << 21); | |
5349 instruction |= ((frb.value() & 0x1f) << 11); | |
5350 emitInt(instruction); | |
5351 } | |
5352 | |
5353 /** | |
5354 * Pseudo-external assembler syntax: {@code fsqrts. }<i>frt</i>, <i>frb</i> | |
5355 * Example disassembly syntax: {@code fsqrts. f0, f0} | |
5356 * | |
5357 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.2.1 [Book 1]" | |
5358 */ | |
5359 // Template#: 317, Serial#: 317 | |
5360 public void fsqrts_(final FPR frt, final FPR frb) { | |
5361 int instruction = 0xEC00002D; | |
5362 instruction |= ((frt.value() & 0x1f) << 21); | |
5363 instruction |= ((frb.value() & 0x1f) << 11); | |
5364 emitInt(instruction); | |
5365 } | |
5366 | |
5367 /** | |
5368 * Pseudo-external assembler syntax: {@code fre }<i>frt</i>, <i>frb</i> | |
5369 * Example disassembly syntax: {@code fre f0, f0} | |
5370 * | |
5371 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.2.1 [Book 1]" | |
5372 */ | |
5373 // Template#: 318, Serial#: 318 | |
5374 public void fre(final FPR frt, final FPR frb) { | |
5375 int instruction = 0xFC000030; | |
5376 instruction |= ((frt.value() & 0x1f) << 21); | |
5377 instruction |= ((frb.value() & 0x1f) << 11); | |
5378 emitInt(instruction); | |
5379 } | |
5380 | |
5381 /** | |
5382 * Pseudo-external assembler syntax: {@code fre. }<i>frt</i>, <i>frb</i> | |
5383 * Example disassembly syntax: {@code fre. f0, f0} | |
5384 * | |
5385 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.2.1 [Book 1]" | |
5386 */ | |
5387 // Template#: 319, Serial#: 319 | |
5388 public void fre_(final FPR frt, final FPR frb) { | |
5389 int instruction = 0xFC000031; | |
5390 instruction |= ((frt.value() & 0x1f) << 21); | |
5391 instruction |= ((frb.value() & 0x1f) << 11); | |
5392 emitInt(instruction); | |
5393 } | |
5394 | |
5395 /** | |
5396 * Pseudo-external assembler syntax: {@code fres }<i>frt</i>, <i>frb</i> | |
5397 * Example disassembly syntax: {@code fres f0, f0} | |
5398 * | |
5399 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.2.1 [Book 1]" | |
5400 */ | |
5401 // Template#: 320, Serial#: 320 | |
5402 public void fres(final FPR frt, final FPR frb) { | |
5403 int instruction = 0xEC000030; | |
5404 instruction |= ((frt.value() & 0x1f) << 21); | |
5405 instruction |= ((frb.value() & 0x1f) << 11); | |
5406 emitInt(instruction); | |
5407 } | |
5408 | |
5409 /** | |
5410 * Pseudo-external assembler syntax: {@code fres. }<i>frt</i>, <i>frb</i> | |
5411 * Example disassembly syntax: {@code fres. f0, f0} | |
5412 * | |
5413 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.2.1 [Book 1]" | |
5414 */ | |
5415 // Template#: 321, Serial#: 321 | |
5416 public void fres_(final FPR frt, final FPR frb) { | |
5417 int instruction = 0xEC000031; | |
5418 instruction |= ((frt.value() & 0x1f) << 21); | |
5419 instruction |= ((frb.value() & 0x1f) << 11); | |
5420 emitInt(instruction); | |
5421 } | |
5422 | |
5423 /** | |
5424 * Pseudo-external assembler syntax: {@code frsqrte }<i>frt</i>, <i>frb</i> | |
5425 * Example disassembly syntax: {@code frsqrte f0, f0} | |
5426 * | |
5427 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.2.1 [Book 1]" | |
5428 */ | |
5429 // Template#: 322, Serial#: 322 | |
5430 public void frsqrte(final FPR frt, final FPR frb) { | |
5431 int instruction = 0xFC000034; | |
5432 instruction |= ((frt.value() & 0x1f) << 21); | |
5433 instruction |= ((frb.value() & 0x1f) << 11); | |
5434 emitInt(instruction); | |
5435 } | |
5436 | |
5437 /** | |
5438 * Pseudo-external assembler syntax: {@code frsqrte. }<i>frt</i>, <i>frb</i> | |
5439 * Example disassembly syntax: {@code frsqrte. f0, f0} | |
5440 * | |
5441 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.2.1 [Book 1]" | |
5442 */ | |
5443 // Template#: 323, Serial#: 323 | |
5444 public void frsqrte_(final FPR frt, final FPR frb) { | |
5445 int instruction = 0xFC000035; | |
5446 instruction |= ((frt.value() & 0x1f) << 21); | |
5447 instruction |= ((frb.value() & 0x1f) << 11); | |
5448 emitInt(instruction); | |
5449 } | |
5450 | |
5451 /** | |
5452 * Pseudo-external assembler syntax: {@code frsqrtes }<i>frt</i>, <i>frb</i> | |
5453 * Example disassembly syntax: {@code frsqrtes f0, f0} | |
5454 * | |
5455 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.2.1 [Book 1]" | |
5456 */ | |
5457 // Template#: 324, Serial#: 324 | |
5458 public void frsqrtes(final FPR frt, final FPR frb) { | |
5459 int instruction = 0xEC000034; | |
5460 instruction |= ((frt.value() & 0x1f) << 21); | |
5461 instruction |= ((frb.value() & 0x1f) << 11); | |
5462 emitInt(instruction); | |
5463 } | |
5464 | |
5465 /** | |
5466 * Pseudo-external assembler syntax: {@code frsqrtes. }<i>frt</i>, <i>frb</i> | |
5467 * Example disassembly syntax: {@code frsqrtes. f0, f0} | |
5468 * | |
5469 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.2.1 [Book 1]" | |
5470 */ | |
5471 // Template#: 325, Serial#: 325 | |
5472 public void frsqrtes_(final FPR frt, final FPR frb) { | |
5473 int instruction = 0xEC000035; | |
5474 instruction |= ((frt.value() & 0x1f) << 21); | |
5475 instruction |= ((frb.value() & 0x1f) << 11); | |
5476 emitInt(instruction); | |
5477 } | |
5478 | |
5479 /** | |
5480 * Pseudo-external assembler syntax: {@code fsel }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
5481 * Example disassembly syntax: {@code fsel f0, f0, f0, f0} | |
5482 * | |
5483 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.2.2 [Book 1]" | |
5484 */ | |
5485 // Template#: 326, Serial#: 326 | |
5486 public void fsel(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
5487 int instruction = 0xFC00002E; | |
5488 instruction |= ((frt.value() & 0x1f) << 21); | |
5489 instruction |= ((fra.value() & 0x1f) << 16); | |
5490 instruction |= ((frc.value() & 0x1f) << 6); | |
5491 instruction |= ((frb.value() & 0x1f) << 11); | |
5492 emitInt(instruction); | |
5493 } | |
5494 | |
5495 /** | |
5496 * Pseudo-external assembler syntax: {@code fsel. }<i>frt</i>, <i>fra</i>, <i>frc</i>, <i>frb</i> | |
5497 * Example disassembly syntax: {@code fsel. f0, f0, f0, f0} | |
5498 * | |
5499 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 5.2.2 [Book 1]" | |
5500 */ | |
5501 // Template#: 327, Serial#: 327 | |
5502 public void fsel_(final FPR frt, final FPR fra, final FPR frc, final FPR frb) { | |
5503 int instruction = 0xFC00002F; | |
5504 instruction |= ((frt.value() & 0x1f) << 21); | |
5505 instruction |= ((fra.value() & 0x1f) << 16); | |
5506 instruction |= ((frc.value() & 0x1f) << 6); | |
5507 instruction |= ((frb.value() & 0x1f) << 11); | |
5508 emitInt(instruction); | |
5509 } | |
5510 | |
5511 /** | |
5512 * Pseudo-external assembler syntax: {@code mcrxr }<i>bf</i> | |
5513 * Example disassembly syntax: {@code mcrxr 0} | |
5514 * | |
5515 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 6.1 [Book 1]" | |
5516 */ | |
5517 // Template#: 328, Serial#: 328 | |
5518 public void mcrxr(final CRF bf) { | |
5519 int instruction = 0x7C000400; | |
5520 instruction |= ((bf.value() & 0x7) << 23); | |
5521 emitInt(instruction); | |
5522 } | |
5523 | |
5524 /** | |
5525 * Pseudo-external assembler syntax: {@code icbi }<i>ra</i>, <i>rb</i> | |
5526 * Example disassembly syntax: {@code icbi 0, r0} | |
5527 * <p> | |
5528 * Constraint: {@code ra != R0}<br /> | |
5529 * | |
5530 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.2.1 [Book 2]" | |
5531 */ | |
5532 // Template#: 329, Serial#: 329 | |
5533 public void icbi(final ZeroOrRegister ra, final GPR rb) { | |
5534 int instruction = 0x7C0007AC; | |
5535 checkConstraint(ra != R0, "ra != R0"); | |
5536 instruction |= ((ra.value() & 0x1f) << 16); | |
5537 instruction |= ((rb.value() & 0x1f) << 11); | |
5538 emitInt(instruction); | |
5539 } | |
5540 | |
5541 /** | |
5542 * Pseudo-external assembler syntax: {@code dcbt }<i>ra</i>, <i>rb</i> | |
5543 * Example disassembly syntax: {@code dcbt 0, r0} | |
5544 * <p> | |
5545 * Constraint: {@code ra != R0}<br /> | |
5546 * | |
5547 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.2.2 [Book 2]" | |
5548 */ | |
5549 // Template#: 330, Serial#: 330 | |
5550 public void dcbt(final ZeroOrRegister ra, final GPR rb) { | |
5551 int instruction = 0x7C00022C; | |
5552 checkConstraint(ra != R0, "ra != R0"); | |
5553 instruction |= ((ra.value() & 0x1f) << 16); | |
5554 instruction |= ((rb.value() & 0x1f) << 11); | |
5555 emitInt(instruction); | |
5556 } | |
5557 | |
5558 /** | |
5559 * Pseudo-external assembler syntax: {@code dcbtst }<i>ra</i>, <i>rb</i> | |
5560 * Example disassembly syntax: {@code dcbtst 0, r0} | |
5561 * <p> | |
5562 * Constraint: {@code ra != R0}<br /> | |
5563 * | |
5564 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.2.2 [Book 2]" | |
5565 */ | |
5566 // Template#: 331, Serial#: 331 | |
5567 public void dcbtst(final ZeroOrRegister ra, final GPR rb) { | |
5568 int instruction = 0x7C0001EC; | |
5569 checkConstraint(ra != R0, "ra != R0"); | |
5570 instruction |= ((ra.value() & 0x1f) << 16); | |
5571 instruction |= ((rb.value() & 0x1f) << 11); | |
5572 emitInt(instruction); | |
5573 } | |
5574 | |
5575 /** | |
5576 * Pseudo-external assembler syntax: {@code dcbz }<i>ra</i>, <i>rb</i> | |
5577 * Example disassembly syntax: {@code dcbz 0, r0} | |
5578 * <p> | |
5579 * Constraint: {@code ra != R0}<br /> | |
5580 * | |
5581 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.2.2 [Book 2]" | |
5582 */ | |
5583 // Template#: 332, Serial#: 332 | |
5584 public void dcbz(final ZeroOrRegister ra, final GPR rb) { | |
5585 int instruction = 0x7C0007EC; | |
5586 checkConstraint(ra != R0, "ra != R0"); | |
5587 instruction |= ((ra.value() & 0x1f) << 16); | |
5588 instruction |= ((rb.value() & 0x1f) << 11); | |
5589 emitInt(instruction); | |
5590 } | |
5591 | |
5592 /** | |
5593 * Pseudo-external assembler syntax: {@code dcbst }<i>ra</i>, <i>rb</i> | |
5594 * Example disassembly syntax: {@code dcbst 0, r0} | |
5595 * <p> | |
5596 * Constraint: {@code ra != R0}<br /> | |
5597 * | |
5598 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.2.2 [Book 2]" | |
5599 */ | |
5600 // Template#: 333, Serial#: 333 | |
5601 public void dcbst(final ZeroOrRegister ra, final GPR rb) { | |
5602 int instruction = 0x7C00006C; | |
5603 checkConstraint(ra != R0, "ra != R0"); | |
5604 instruction |= ((ra.value() & 0x1f) << 16); | |
5605 instruction |= ((rb.value() & 0x1f) << 11); | |
5606 emitInt(instruction); | |
5607 } | |
5608 | |
5609 /** | |
5610 * Pseudo-external assembler syntax: {@code dcbf }<i>ra</i>, <i>rb</i> | |
5611 * Example disassembly syntax: {@code dcbf 0, r0} | |
5612 * <p> | |
5613 * Constraint: {@code ra != R0}<br /> | |
5614 * | |
5615 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.2.2 [Book 2]" | |
5616 */ | |
5617 // Template#: 334, Serial#: 334 | |
5618 public void dcbf(final ZeroOrRegister ra, final GPR rb) { | |
5619 int instruction = 0x7C0000AC; | |
5620 checkConstraint(ra != R0, "ra != R0"); | |
5621 instruction |= ((ra.value() & 0x1f) << 16); | |
5622 instruction |= ((rb.value() & 0x1f) << 11); | |
5623 emitInt(instruction); | |
5624 } | |
5625 | |
5626 /** | |
5627 * Pseudo-external assembler syntax: {@code isync } | |
5628 * Example disassembly syntax: {@code isync } | |
5629 * | |
5630 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.1 [Book 2]" | |
5631 */ | |
5632 // Template#: 335, Serial#: 335 | |
5633 public void isync() { | |
5634 int instruction = 0x4C00012C; | |
5635 emitInt(instruction); | |
5636 } | |
5637 | |
5638 /** | |
5639 * Pseudo-external assembler syntax: {@code lwarx }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
5640 * Example disassembly syntax: {@code lwarx r0, 0, r0} | |
5641 * <p> | |
5642 * Constraint: {@code ra != R0}<br /> | |
5643 * | |
5644 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 2]" | |
5645 */ | |
5646 // Template#: 336, Serial#: 336 | |
5647 public void lwarx(final GPR rt, final ZeroOrRegister ra, final GPR rb) { | |
5648 int instruction = 0x7C000028; | |
5649 checkConstraint(ra != R0, "ra != R0"); | |
5650 instruction |= ((rt.value() & 0x1f) << 21); | |
5651 instruction |= ((ra.value() & 0x1f) << 16); | |
5652 instruction |= ((rb.value() & 0x1f) << 11); | |
5653 emitInt(instruction); | |
5654 } | |
5655 | |
5656 /** | |
5657 * Pseudo-external assembler syntax: {@code ldarx }<i>rt</i>, <i>ra</i>, <i>rb</i> | |
5658 * Example disassembly syntax: {@code ldarx r0, 0, r0} | |
5659 * <p> | |
5660 * Constraint: {@code ra != R0}<br /> | |
5661 * | |
5662 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 2]" | |
5663 */ | |
5664 // Template#: 337, Serial#: 337 | |
5665 public void ldarx(final GPR rt, final ZeroOrRegister ra, final GPR rb) { | |
5666 int instruction = 0x7C0000A8; | |
5667 checkConstraint(ra != R0, "ra != R0"); | |
5668 instruction |= ((rt.value() & 0x1f) << 21); | |
5669 instruction |= ((ra.value() & 0x1f) << 16); | |
5670 instruction |= ((rb.value() & 0x1f) << 11); | |
5671 emitInt(instruction); | |
5672 } | |
5673 | |
5674 /** | |
5675 * Pseudo-external assembler syntax: {@code stwcx. }<i>rs</i>, <i>ra</i>, <i>rb</i> | |
5676 * Example disassembly syntax: {@code stwcx. r0, 0, r0} | |
5677 * <p> | |
5678 * Constraint: {@code ra != R0}<br /> | |
5679 * | |
5680 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 2]" | |
5681 */ | |
5682 // Template#: 338, Serial#: 338 | |
5683 public void stwcx(final GPR rs, final ZeroOrRegister ra, final GPR rb) { | |
5684 int instruction = 0x7C00012D; | |
5685 checkConstraint(ra != R0, "ra != R0"); | |
5686 instruction |= ((rs.value() & 0x1f) << 21); | |
5687 instruction |= ((ra.value() & 0x1f) << 16); | |
5688 instruction |= ((rb.value() & 0x1f) << 11); | |
5689 emitInt(instruction); | |
5690 } | |
5691 | |
5692 /** | |
5693 * Pseudo-external assembler syntax: {@code stdcx. }<i>rs</i>, <i>ra</i>, <i>rb</i> | |
5694 * Example disassembly syntax: {@code stdcx. r0, 0, r0} | |
5695 * <p> | |
5696 * Constraint: {@code ra != R0}<br /> | |
5697 * | |
5698 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.2 [Book 2]" | |
5699 */ | |
5700 // Template#: 339, Serial#: 339 | |
5701 public void stdcx(final GPR rs, final ZeroOrRegister ra, final GPR rb) { | |
5702 int instruction = 0x7C0001AD; | |
5703 checkConstraint(ra != R0, "ra != R0"); | |
5704 instruction |= ((rs.value() & 0x1f) << 21); | |
5705 instruction |= ((ra.value() & 0x1f) << 16); | |
5706 instruction |= ((rb.value() & 0x1f) << 11); | |
5707 emitInt(instruction); | |
5708 } | |
5709 | |
5710 /** | |
5711 * Pseudo-external assembler syntax: {@code sync } | |
5712 * Example disassembly syntax: {@code sync } | |
5713 * | |
5714 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 2]" | |
5715 */ | |
5716 // Template#: 340, Serial#: 340 | |
5717 public void sync() { | |
5718 int instruction = 0x7C0004AC; | |
5719 emitInt(instruction); | |
5720 } | |
5721 | |
5722 /** | |
5723 * Pseudo-external assembler syntax: {@code eieio } | |
5724 * Example disassembly syntax: {@code eieio } | |
5725 * | |
5726 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section 3.3.3 [Book 2]" | |
5727 */ | |
5728 // Template#: 341, Serial#: 341 | |
5729 public void eieio() { | |
5730 int instruction = 0x7C0006AC; | |
5731 emitInt(instruction); | |
5732 } | |
5733 | |
5734 /** | |
5735 * Pseudo-external assembler syntax: {@code bt{++|--} }<i>bi</i>, <i>bd</i> | |
5736 * Example disassembly syntax: {@code bt 0x0, L1: -32768} | |
5737 * <p> | |
5738 * This is a synthetic instruction equivalent to: {@code bc(CRTrue | prediction, bi, bd)} | |
5739 * <p> | |
5740 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
5741 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
5742 * | |
5743 * @see #bc(BOOperand, int, int) | |
5744 * | |
5745 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
5746 */ | |
5747 // Template#: 342, Serial#: 342 | |
5748 public void bt(final int bi, final int bd, final BranchPredictionBits prediction) { | |
5749 int instruction = 0x41800000; | |
5750 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
5751 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
5752 instruction |= ((bi & 0x1f) << 16); | |
5753 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
5754 instruction |= ((prediction.value() & 0x3) << 21); | |
5755 emitInt(instruction); | |
5756 } | |
5757 | |
5758 /** | |
5759 * Pseudo-external assembler syntax: {@code bta{++|--} }<i>bi</i>, <i>bd</i> | |
5760 * Example disassembly syntax: {@code bta 0x0, L1: -32768} | |
5761 * <p> | |
5762 * This is a synthetic instruction equivalent to: {@code bca(CRTrue | prediction, bi, bd)} | |
5763 * <p> | |
5764 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
5765 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
5766 * | |
5767 * @see #bca(BOOperand, int, int) | |
5768 * | |
5769 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
5770 */ | |
5771 // Template#: 343, Serial#: 343 | |
5772 public void bta(final int bi, final int bd, final BranchPredictionBits prediction) { | |
5773 int instruction = 0x41800002; | |
5774 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
5775 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
5776 instruction |= ((bi & 0x1f) << 16); | |
5777 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
5778 instruction |= ((prediction.value() & 0x3) << 21); | |
5779 emitInt(instruction); | |
5780 } | |
5781 | |
5782 /** | |
5783 * Pseudo-external assembler syntax: {@code btl{++|--} }<i>bi</i>, <i>bd</i> | |
5784 * Example disassembly syntax: {@code btl 0x0, L1: -32768} | |
5785 * <p> | |
5786 * This is a synthetic instruction equivalent to: {@code bcl(CRTrue | prediction, bi, bd)} | |
5787 * <p> | |
5788 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
5789 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
5790 * | |
5791 * @see #bcl(BOOperand, int, int) | |
5792 * | |
5793 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
5794 */ | |
5795 // Template#: 344, Serial#: 344 | |
5796 public void btl(final int bi, final int bd, final BranchPredictionBits prediction) { | |
5797 int instruction = 0x41800001; | |
5798 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
5799 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
5800 instruction |= ((bi & 0x1f) << 16); | |
5801 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
5802 instruction |= ((prediction.value() & 0x3) << 21); | |
5803 emitInt(instruction); | |
5804 } | |
5805 | |
5806 /** | |
5807 * Pseudo-external assembler syntax: {@code btla{++|--} }<i>bi</i>, <i>bd</i> | |
5808 * Example disassembly syntax: {@code btla 0x0, L1: -32768} | |
5809 * <p> | |
5810 * This is a synthetic instruction equivalent to: {@code bcla(CRTrue | prediction, bi, bd)} | |
5811 * <p> | |
5812 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
5813 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
5814 * | |
5815 * @see #bcla(BOOperand, int, int) | |
5816 * | |
5817 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
5818 */ | |
5819 // Template#: 345, Serial#: 345 | |
5820 public void btla(final int bi, final int bd, final BranchPredictionBits prediction) { | |
5821 int instruction = 0x41800003; | |
5822 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
5823 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
5824 instruction |= ((bi & 0x1f) << 16); | |
5825 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
5826 instruction |= ((prediction.value() & 0x3) << 21); | |
5827 emitInt(instruction); | |
5828 } | |
5829 | |
5830 /** | |
5831 * Pseudo-external assembler syntax: {@code bf{++|--} }<i>bi</i>, <i>bd</i> | |
5832 * Example disassembly syntax: {@code bf 0x0, L1: -32768} | |
5833 * <p> | |
5834 * This is a synthetic instruction equivalent to: {@code bc(CRFalse | prediction, bi, bd)} | |
5835 * <p> | |
5836 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
5837 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
5838 * | |
5839 * @see #bc(BOOperand, int, int) | |
5840 * | |
5841 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
5842 */ | |
5843 // Template#: 346, Serial#: 346 | |
5844 public void bf(final int bi, final int bd, final BranchPredictionBits prediction) { | |
5845 int instruction = 0x40800000; | |
5846 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
5847 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
5848 instruction |= ((bi & 0x1f) << 16); | |
5849 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
5850 instruction |= ((prediction.value() & 0x3) << 21); | |
5851 emitInt(instruction); | |
5852 } | |
5853 | |
5854 /** | |
5855 * Pseudo-external assembler syntax: {@code bfa{++|--} }<i>bi</i>, <i>bd</i> | |
5856 * Example disassembly syntax: {@code bfa 0x0, L1: -32768} | |
5857 * <p> | |
5858 * This is a synthetic instruction equivalent to: {@code bca(CRFalse | prediction, bi, bd)} | |
5859 * <p> | |
5860 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
5861 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
5862 * | |
5863 * @see #bca(BOOperand, int, int) | |
5864 * | |
5865 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
5866 */ | |
5867 // Template#: 347, Serial#: 347 | |
5868 public void bfa(final int bi, final int bd, final BranchPredictionBits prediction) { | |
5869 int instruction = 0x40800002; | |
5870 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
5871 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
5872 instruction |= ((bi & 0x1f) << 16); | |
5873 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
5874 instruction |= ((prediction.value() & 0x3) << 21); | |
5875 emitInt(instruction); | |
5876 } | |
5877 | |
5878 /** | |
5879 * Pseudo-external assembler syntax: {@code bfl{++|--} }<i>bi</i>, <i>bd</i> | |
5880 * Example disassembly syntax: {@code bfl 0x0, L1: -32768} | |
5881 * <p> | |
5882 * This is a synthetic instruction equivalent to: {@code bcl(CRFalse | prediction, bi, bd)} | |
5883 * <p> | |
5884 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
5885 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
5886 * | |
5887 * @see #bcl(BOOperand, int, int) | |
5888 * | |
5889 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
5890 */ | |
5891 // Template#: 348, Serial#: 348 | |
5892 public void bfl(final int bi, final int bd, final BranchPredictionBits prediction) { | |
5893 int instruction = 0x40800001; | |
5894 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
5895 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
5896 instruction |= ((bi & 0x1f) << 16); | |
5897 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
5898 instruction |= ((prediction.value() & 0x3) << 21); | |
5899 emitInt(instruction); | |
5900 } | |
5901 | |
5902 /** | |
5903 * Pseudo-external assembler syntax: {@code bfla{++|--} }<i>bi</i>, <i>bd</i> | |
5904 * Example disassembly syntax: {@code bfla 0x0, L1: -32768} | |
5905 * <p> | |
5906 * This is a synthetic instruction equivalent to: {@code bcla(CRFalse | prediction, bi, bd)} | |
5907 * <p> | |
5908 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
5909 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
5910 * | |
5911 * @see #bcla(BOOperand, int, int) | |
5912 * | |
5913 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
5914 */ | |
5915 // Template#: 349, Serial#: 349 | |
5916 public void bfla(final int bi, final int bd, final BranchPredictionBits prediction) { | |
5917 int instruction = 0x40800003; | |
5918 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
5919 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
5920 instruction |= ((bi & 0x1f) << 16); | |
5921 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
5922 instruction |= ((prediction.value() & 0x3) << 21); | |
5923 emitInt(instruction); | |
5924 } | |
5925 | |
5926 /** | |
5927 * Pseudo-external assembler syntax: {@code bdnz{++|--} }<i>bd</i> | |
5928 * Example disassembly syntax: {@code bdnz L1: -32768} | |
5929 * <p> | |
5930 * This is a synthetic instruction equivalent to: {@code bc(CTRNonZero | (prediction & 0x1) | (((prediction >>> 1) & 0x1) << 3), 0, bd)} | |
5931 * <p> | |
5932 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
5933 * | |
5934 * @see #bc(BOOperand, int, int) | |
5935 * | |
5936 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
5937 */ | |
5938 // Template#: 350, Serial#: 350 | |
5939 public void bdnz(final int bd, final BranchPredictionBits prediction) { | |
5940 int instruction = 0x42000000; | |
5941 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
5942 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
5943 instruction |= ((prediction.value() & 0x1) << 21) | (((prediction.value() >>> 1) & 0x1) << 24); | |
5944 emitInt(instruction); | |
5945 } | |
5946 | |
5947 /** | |
5948 * Pseudo-external assembler syntax: {@code bdnza{++|--} }<i>bd</i> | |
5949 * Example disassembly syntax: {@code bdnza L1: -32768} | |
5950 * <p> | |
5951 * This is a synthetic instruction equivalent to: {@code bca(CTRNonZero | (prediction & 0x1) | (((prediction >>> 1) & 0x1) << 3), 0, bd)} | |
5952 * <p> | |
5953 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
5954 * | |
5955 * @see #bca(BOOperand, int, int) | |
5956 * | |
5957 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
5958 */ | |
5959 // Template#: 351, Serial#: 351 | |
5960 public void bdnza(final int bd, final BranchPredictionBits prediction) { | |
5961 int instruction = 0x42000002; | |
5962 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
5963 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
5964 instruction |= ((prediction.value() & 0x1) << 21) | (((prediction.value() >>> 1) & 0x1) << 24); | |
5965 emitInt(instruction); | |
5966 } | |
5967 | |
5968 /** | |
5969 * Pseudo-external assembler syntax: {@code bdnzl{++|--} }<i>bd</i> | |
5970 * Example disassembly syntax: {@code bdnzl L1: -32768} | |
5971 * <p> | |
5972 * This is a synthetic instruction equivalent to: {@code bcl(CTRNonZero | (prediction & 0x1) | (((prediction >>> 1) & 0x1) << 3), 0, bd)} | |
5973 * <p> | |
5974 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
5975 * | |
5976 * @see #bcl(BOOperand, int, int) | |
5977 * | |
5978 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
5979 */ | |
5980 // Template#: 352, Serial#: 352 | |
5981 public void bdnzl(final int bd, final BranchPredictionBits prediction) { | |
5982 int instruction = 0x42000001; | |
5983 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
5984 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
5985 instruction |= ((prediction.value() & 0x1) << 21) | (((prediction.value() >>> 1) & 0x1) << 24); | |
5986 emitInt(instruction); | |
5987 } | |
5988 | |
5989 /** | |
5990 * Pseudo-external assembler syntax: {@code bdnzla{++|--} }<i>bd</i> | |
5991 * Example disassembly syntax: {@code bdnzla L1: -32768} | |
5992 * <p> | |
5993 * This is a synthetic instruction equivalent to: {@code bcla(CTRNonZero | (prediction & 0x1) | (((prediction >>> 1) & 0x1) << 3), 0, bd)} | |
5994 * <p> | |
5995 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
5996 * | |
5997 * @see #bcla(BOOperand, int, int) | |
5998 * | |
5999 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6000 */ | |
6001 // Template#: 353, Serial#: 353 | |
6002 public void bdnzla(final int bd, final BranchPredictionBits prediction) { | |
6003 int instruction = 0x42000003; | |
6004 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6005 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6006 instruction |= ((prediction.value() & 0x1) << 21) | (((prediction.value() >>> 1) & 0x1) << 24); | |
6007 emitInt(instruction); | |
6008 } | |
6009 | |
6010 /** | |
6011 * Pseudo-external assembler syntax: {@code bdz{++|--} }<i>bd</i> | |
6012 * Example disassembly syntax: {@code bdz L1: -32768} | |
6013 * <p> | |
6014 * This is a synthetic instruction equivalent to: {@code bc(CTRZero | (prediction & 0x1) | (((prediction >>> 1) & 0x1) << 3), 0, bd)} | |
6015 * <p> | |
6016 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6017 * | |
6018 * @see #bc(BOOperand, int, int) | |
6019 * | |
6020 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6021 */ | |
6022 // Template#: 354, Serial#: 354 | |
6023 public void bdz(final int bd, final BranchPredictionBits prediction) { | |
6024 int instruction = 0x42400000; | |
6025 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6026 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6027 instruction |= ((prediction.value() & 0x1) << 21) | (((prediction.value() >>> 1) & 0x1) << 24); | |
6028 emitInt(instruction); | |
6029 } | |
6030 | |
6031 /** | |
6032 * Pseudo-external assembler syntax: {@code bdza{++|--} }<i>bd</i> | |
6033 * Example disassembly syntax: {@code bdza L1: -32768} | |
6034 * <p> | |
6035 * This is a synthetic instruction equivalent to: {@code bca(CTRZero | (prediction & 0x1) | (((prediction >>> 1) & 0x1) << 3), 0, bd)} | |
6036 * <p> | |
6037 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6038 * | |
6039 * @see #bca(BOOperand, int, int) | |
6040 * | |
6041 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6042 */ | |
6043 // Template#: 355, Serial#: 355 | |
6044 public void bdza(final int bd, final BranchPredictionBits prediction) { | |
6045 int instruction = 0x42400002; | |
6046 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6047 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6048 instruction |= ((prediction.value() & 0x1) << 21) | (((prediction.value() >>> 1) & 0x1) << 24); | |
6049 emitInt(instruction); | |
6050 } | |
6051 | |
6052 /** | |
6053 * Pseudo-external assembler syntax: {@code bdzl{++|--} }<i>bd</i> | |
6054 * Example disassembly syntax: {@code bdzl L1: -32768} | |
6055 * <p> | |
6056 * This is a synthetic instruction equivalent to: {@code bcl(CTRZero | (prediction & 0x1) | (((prediction >>> 1) & 0x1) << 3), 0, bd)} | |
6057 * <p> | |
6058 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6059 * | |
6060 * @see #bcl(BOOperand, int, int) | |
6061 * | |
6062 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6063 */ | |
6064 // Template#: 356, Serial#: 356 | |
6065 public void bdzl(final int bd, final BranchPredictionBits prediction) { | |
6066 int instruction = 0x42400001; | |
6067 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6068 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6069 instruction |= ((prediction.value() & 0x1) << 21) | (((prediction.value() >>> 1) & 0x1) << 24); | |
6070 emitInt(instruction); | |
6071 } | |
6072 | |
6073 /** | |
6074 * Pseudo-external assembler syntax: {@code bdzla{++|--} }<i>bd</i> | |
6075 * Example disassembly syntax: {@code bdzla L1: -32768} | |
6076 * <p> | |
6077 * This is a synthetic instruction equivalent to: {@code bcla(CTRZero | (prediction & 0x1) | (((prediction >>> 1) & 0x1) << 3), 0, bd)} | |
6078 * <p> | |
6079 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6080 * | |
6081 * @see #bcla(BOOperand, int, int) | |
6082 * | |
6083 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6084 */ | |
6085 // Template#: 357, Serial#: 357 | |
6086 public void bdzla(final int bd, final BranchPredictionBits prediction) { | |
6087 int instruction = 0x42400003; | |
6088 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6089 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6090 instruction |= ((prediction.value() & 0x1) << 21) | (((prediction.value() >>> 1) & 0x1) << 24); | |
6091 emitInt(instruction); | |
6092 } | |
6093 | |
6094 /** | |
6095 * Pseudo-external assembler syntax: {@code bdnzt }<i>bi</i>, <i>bd</i> | |
6096 * Example disassembly syntax: {@code bdnzt 0x0, L1: -32768} | |
6097 * <p> | |
6098 * This is a synthetic instruction equivalent to: {@code bc(CTRNonZero_CRTrue, bi, bd)} | |
6099 * <p> | |
6100 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6101 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6102 * | |
6103 * @see #bc(BOOperand, int, int) | |
6104 * | |
6105 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6106 */ | |
6107 // Template#: 358, Serial#: 358 | |
6108 public void bdnzt(final int bi, final int bd) { | |
6109 int instruction = 0x41000000; | |
6110 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6111 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6112 instruction |= ((bi & 0x1f) << 16); | |
6113 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6114 emitInt(instruction); | |
6115 } | |
6116 | |
6117 /** | |
6118 * Pseudo-external assembler syntax: {@code bdnzta }<i>bi</i>, <i>bd</i> | |
6119 * Example disassembly syntax: {@code bdnzta 0x0, L1: -32768} | |
6120 * <p> | |
6121 * This is a synthetic instruction equivalent to: {@code bca(CTRNonZero_CRTrue, bi, bd)} | |
6122 * <p> | |
6123 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6124 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6125 * | |
6126 * @see #bca(BOOperand, int, int) | |
6127 * | |
6128 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6129 */ | |
6130 // Template#: 359, Serial#: 359 | |
6131 public void bdnzta(final int bi, final int bd) { | |
6132 int instruction = 0x41000002; | |
6133 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6134 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6135 instruction |= ((bi & 0x1f) << 16); | |
6136 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6137 emitInt(instruction); | |
6138 } | |
6139 | |
6140 /** | |
6141 * Pseudo-external assembler syntax: {@code bdnztl }<i>bi</i>, <i>bd</i> | |
6142 * Example disassembly syntax: {@code bdnztl 0x0, L1: -32768} | |
6143 * <p> | |
6144 * This is a synthetic instruction equivalent to: {@code bcl(CTRNonZero_CRTrue, bi, bd)} | |
6145 * <p> | |
6146 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6147 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6148 * | |
6149 * @see #bcl(BOOperand, int, int) | |
6150 * | |
6151 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6152 */ | |
6153 // Template#: 360, Serial#: 360 | |
6154 public void bdnztl(final int bi, final int bd) { | |
6155 int instruction = 0x41000001; | |
6156 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6157 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6158 instruction |= ((bi & 0x1f) << 16); | |
6159 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6160 emitInt(instruction); | |
6161 } | |
6162 | |
6163 /** | |
6164 * Pseudo-external assembler syntax: {@code bdnztla }<i>bi</i>, <i>bd</i> | |
6165 * Example disassembly syntax: {@code bdnztla 0x0, L1: -32768} | |
6166 * <p> | |
6167 * This is a synthetic instruction equivalent to: {@code bcla(CTRNonZero_CRTrue, bi, bd)} | |
6168 * <p> | |
6169 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6170 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6171 * | |
6172 * @see #bcla(BOOperand, int, int) | |
6173 * | |
6174 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6175 */ | |
6176 // Template#: 361, Serial#: 361 | |
6177 public void bdnztla(final int bi, final int bd) { | |
6178 int instruction = 0x41000003; | |
6179 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6180 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6181 instruction |= ((bi & 0x1f) << 16); | |
6182 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6183 emitInt(instruction); | |
6184 } | |
6185 | |
6186 /** | |
6187 * Pseudo-external assembler syntax: {@code bdnzf }<i>bi</i>, <i>bd</i> | |
6188 * Example disassembly syntax: {@code bdnzf 0x0, L1: -32768} | |
6189 * <p> | |
6190 * This is a synthetic instruction equivalent to: {@code bc(CTRNonZero_CRFalse, bi, bd)} | |
6191 * <p> | |
6192 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6193 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6194 * | |
6195 * @see #bc(BOOperand, int, int) | |
6196 * | |
6197 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6198 */ | |
6199 // Template#: 362, Serial#: 362 | |
6200 public void bdnzf(final int bi, final int bd) { | |
6201 int instruction = 0x40000000; | |
6202 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6203 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6204 instruction |= ((bi & 0x1f) << 16); | |
6205 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6206 emitInt(instruction); | |
6207 } | |
6208 | |
6209 /** | |
6210 * Pseudo-external assembler syntax: {@code bdnzfa }<i>bi</i>, <i>bd</i> | |
6211 * Example disassembly syntax: {@code bdnzfa 0x0, L1: -32768} | |
6212 * <p> | |
6213 * This is a synthetic instruction equivalent to: {@code bca(CTRNonZero_CRFalse, bi, bd)} | |
6214 * <p> | |
6215 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6216 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6217 * | |
6218 * @see #bca(BOOperand, int, int) | |
6219 * | |
6220 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6221 */ | |
6222 // Template#: 363, Serial#: 363 | |
6223 public void bdnzfa(final int bi, final int bd) { | |
6224 int instruction = 0x40000002; | |
6225 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6226 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6227 instruction |= ((bi & 0x1f) << 16); | |
6228 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6229 emitInt(instruction); | |
6230 } | |
6231 | |
6232 /** | |
6233 * Pseudo-external assembler syntax: {@code bdnzfl }<i>bi</i>, <i>bd</i> | |
6234 * Example disassembly syntax: {@code bdnzfl 0x0, L1: -32768} | |
6235 * <p> | |
6236 * This is a synthetic instruction equivalent to: {@code bcl(CTRNonZero_CRFalse, bi, bd)} | |
6237 * <p> | |
6238 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6239 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6240 * | |
6241 * @see #bcl(BOOperand, int, int) | |
6242 * | |
6243 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6244 */ | |
6245 // Template#: 364, Serial#: 364 | |
6246 public void bdnzfl(final int bi, final int bd) { | |
6247 int instruction = 0x40000001; | |
6248 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6249 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6250 instruction |= ((bi & 0x1f) << 16); | |
6251 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6252 emitInt(instruction); | |
6253 } | |
6254 | |
6255 /** | |
6256 * Pseudo-external assembler syntax: {@code bdnzfla }<i>bi</i>, <i>bd</i> | |
6257 * Example disassembly syntax: {@code bdnzfla 0x0, L1: -32768} | |
6258 * <p> | |
6259 * This is a synthetic instruction equivalent to: {@code bcla(CTRNonZero_CRFalse, bi, bd)} | |
6260 * <p> | |
6261 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6262 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6263 * | |
6264 * @see #bcla(BOOperand, int, int) | |
6265 * | |
6266 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6267 */ | |
6268 // Template#: 365, Serial#: 365 | |
6269 public void bdnzfla(final int bi, final int bd) { | |
6270 int instruction = 0x40000003; | |
6271 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6272 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6273 instruction |= ((bi & 0x1f) << 16); | |
6274 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6275 emitInt(instruction); | |
6276 } | |
6277 | |
6278 /** | |
6279 * Pseudo-external assembler syntax: {@code bdzt }<i>bi</i>, <i>bd</i> | |
6280 * Example disassembly syntax: {@code bdzt 0x0, L1: -32768} | |
6281 * <p> | |
6282 * This is a synthetic instruction equivalent to: {@code bc(CTRZero_CRTrue, bi, bd)} | |
6283 * <p> | |
6284 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6285 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6286 * | |
6287 * @see #bc(BOOperand, int, int) | |
6288 * | |
6289 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6290 */ | |
6291 // Template#: 366, Serial#: 366 | |
6292 public void bdzt(final int bi, final int bd) { | |
6293 int instruction = 0x41400000; | |
6294 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6295 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6296 instruction |= ((bi & 0x1f) << 16); | |
6297 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6298 emitInt(instruction); | |
6299 } | |
6300 | |
6301 /** | |
6302 * Pseudo-external assembler syntax: {@code bdzta }<i>bi</i>, <i>bd</i> | |
6303 * Example disassembly syntax: {@code bdzta 0x0, L1: -32768} | |
6304 * <p> | |
6305 * This is a synthetic instruction equivalent to: {@code bca(CTRZero_CRTrue, bi, bd)} | |
6306 * <p> | |
6307 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6308 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6309 * | |
6310 * @see #bca(BOOperand, int, int) | |
6311 * | |
6312 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6313 */ | |
6314 // Template#: 367, Serial#: 367 | |
6315 public void bdzta(final int bi, final int bd) { | |
6316 int instruction = 0x41400002; | |
6317 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6318 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6319 instruction |= ((bi & 0x1f) << 16); | |
6320 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6321 emitInt(instruction); | |
6322 } | |
6323 | |
6324 /** | |
6325 * Pseudo-external assembler syntax: {@code bdztl }<i>bi</i>, <i>bd</i> | |
6326 * Example disassembly syntax: {@code bdztl 0x0, L1: -32768} | |
6327 * <p> | |
6328 * This is a synthetic instruction equivalent to: {@code bcl(CTRZero_CRTrue, bi, bd)} | |
6329 * <p> | |
6330 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6331 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6332 * | |
6333 * @see #bcl(BOOperand, int, int) | |
6334 * | |
6335 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6336 */ | |
6337 // Template#: 368, Serial#: 368 | |
6338 public void bdztl(final int bi, final int bd) { | |
6339 int instruction = 0x41400001; | |
6340 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6341 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6342 instruction |= ((bi & 0x1f) << 16); | |
6343 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6344 emitInt(instruction); | |
6345 } | |
6346 | |
6347 /** | |
6348 * Pseudo-external assembler syntax: {@code bdztla }<i>bi</i>, <i>bd</i> | |
6349 * Example disassembly syntax: {@code bdztla 0x0, L1: -32768} | |
6350 * <p> | |
6351 * This is a synthetic instruction equivalent to: {@code bcla(CTRZero_CRTrue, bi, bd)} | |
6352 * <p> | |
6353 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6354 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6355 * | |
6356 * @see #bcla(BOOperand, int, int) | |
6357 * | |
6358 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6359 */ | |
6360 // Template#: 369, Serial#: 369 | |
6361 public void bdztla(final int bi, final int bd) { | |
6362 int instruction = 0x41400003; | |
6363 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6364 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6365 instruction |= ((bi & 0x1f) << 16); | |
6366 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6367 emitInt(instruction); | |
6368 } | |
6369 | |
6370 /** | |
6371 * Pseudo-external assembler syntax: {@code bdzf }<i>bi</i>, <i>bd</i> | |
6372 * Example disassembly syntax: {@code bdzf 0x0, L1: -32768} | |
6373 * <p> | |
6374 * This is a synthetic instruction equivalent to: {@code bc(CTRZero_CRFalse, bi, bd)} | |
6375 * <p> | |
6376 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6377 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6378 * | |
6379 * @see #bc(BOOperand, int, int) | |
6380 * | |
6381 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6382 */ | |
6383 // Template#: 370, Serial#: 370 | |
6384 public void bdzf(final int bi, final int bd) { | |
6385 int instruction = 0x40400000; | |
6386 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6387 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6388 instruction |= ((bi & 0x1f) << 16); | |
6389 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6390 emitInt(instruction); | |
6391 } | |
6392 | |
6393 /** | |
6394 * Pseudo-external assembler syntax: {@code bdzfa }<i>bi</i>, <i>bd</i> | |
6395 * Example disassembly syntax: {@code bdzfa 0x0, L1: -32768} | |
6396 * <p> | |
6397 * This is a synthetic instruction equivalent to: {@code bca(CTRZero_CRFalse, bi, bd)} | |
6398 * <p> | |
6399 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6400 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6401 * | |
6402 * @see #bca(BOOperand, int, int) | |
6403 * | |
6404 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6405 */ | |
6406 // Template#: 371, Serial#: 371 | |
6407 public void bdzfa(final int bi, final int bd) { | |
6408 int instruction = 0x40400002; | |
6409 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6410 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6411 instruction |= ((bi & 0x1f) << 16); | |
6412 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6413 emitInt(instruction); | |
6414 } | |
6415 | |
6416 /** | |
6417 * Pseudo-external assembler syntax: {@code bdzfl }<i>bi</i>, <i>bd</i> | |
6418 * Example disassembly syntax: {@code bdzfl 0x0, L1: -32768} | |
6419 * <p> | |
6420 * This is a synthetic instruction equivalent to: {@code bcl(CTRZero_CRFalse, bi, bd)} | |
6421 * <p> | |
6422 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6423 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6424 * | |
6425 * @see #bcl(BOOperand, int, int) | |
6426 * | |
6427 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6428 */ | |
6429 // Template#: 372, Serial#: 372 | |
6430 public void bdzfl(final int bi, final int bd) { | |
6431 int instruction = 0x40400001; | |
6432 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6433 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6434 instruction |= ((bi & 0x1f) << 16); | |
6435 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6436 emitInt(instruction); | |
6437 } | |
6438 | |
6439 /** | |
6440 * Pseudo-external assembler syntax: {@code bdzfla }<i>bi</i>, <i>bd</i> | |
6441 * Example disassembly syntax: {@code bdzfla 0x0, L1: -32768} | |
6442 * <p> | |
6443 * This is a synthetic instruction equivalent to: {@code bcla(CTRZero_CRFalse, bi, bd)} | |
6444 * <p> | |
6445 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6446 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6447 * | |
6448 * @see #bcla(BOOperand, int, int) | |
6449 * | |
6450 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6451 */ | |
6452 // Template#: 373, Serial#: 373 | |
6453 public void bdzfla(final int bi, final int bd) { | |
6454 int instruction = 0x40400003; | |
6455 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6456 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6457 instruction |= ((bi & 0x1f) << 16); | |
6458 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6459 emitInt(instruction); | |
6460 } | |
6461 | |
6462 /** | |
6463 * Pseudo-external assembler syntax: {@code blr } | |
6464 * Example disassembly syntax: {@code blr } | |
6465 * <p> | |
6466 * This is a synthetic instruction equivalent to: {@code bclr(Always, 0, 0)} | |
6467 * | |
6468 * @see #bclr(BOOperand, int, int) | |
6469 * | |
6470 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6471 */ | |
6472 // Template#: 374, Serial#: 374 | |
6473 public void blr() { | |
6474 int instruction = 0x4E800020; | |
6475 emitInt(instruction); | |
6476 } | |
6477 | |
6478 /** | |
6479 * Pseudo-external assembler syntax: {@code blrl } | |
6480 * Example disassembly syntax: {@code blrl } | |
6481 * <p> | |
6482 * This is a synthetic instruction equivalent to: {@code bclrl(Always, 0, 0)} | |
6483 * | |
6484 * @see #bclrl(BOOperand, int, int) | |
6485 * | |
6486 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6487 */ | |
6488 // Template#: 375, Serial#: 375 | |
6489 public void blrl() { | |
6490 int instruction = 0x4E800021; | |
6491 emitInt(instruction); | |
6492 } | |
6493 | |
6494 /** | |
6495 * Pseudo-external assembler syntax: {@code btlr{++|--} }<i>bi</i> | |
6496 * Example disassembly syntax: {@code btlr 0x0} | |
6497 * <p> | |
6498 * This is a synthetic instruction equivalent to: {@code bclr(CRTrue | prediction, bi, 0)} | |
6499 * <p> | |
6500 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6501 * | |
6502 * @see #bclr(BOOperand, int, int) | |
6503 * | |
6504 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6505 */ | |
6506 // Template#: 376, Serial#: 376 | |
6507 public void btlr(final int bi, final BranchPredictionBits prediction) { | |
6508 int instruction = 0x4D800020; | |
6509 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6510 instruction |= ((bi & 0x1f) << 16); | |
6511 instruction |= ((prediction.value() & 0x3) << 21); | |
6512 emitInt(instruction); | |
6513 } | |
6514 | |
6515 /** | |
6516 * Pseudo-external assembler syntax: {@code btlrl{++|--} }<i>bi</i> | |
6517 * Example disassembly syntax: {@code btlrl 0x0} | |
6518 * <p> | |
6519 * This is a synthetic instruction equivalent to: {@code bclrl(CRTrue | prediction, bi, 0)} | |
6520 * <p> | |
6521 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6522 * | |
6523 * @see #bclrl(BOOperand, int, int) | |
6524 * | |
6525 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6526 */ | |
6527 // Template#: 377, Serial#: 377 | |
6528 public void btlrl(final int bi, final BranchPredictionBits prediction) { | |
6529 int instruction = 0x4D800021; | |
6530 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6531 instruction |= ((bi & 0x1f) << 16); | |
6532 instruction |= ((prediction.value() & 0x3) << 21); | |
6533 emitInt(instruction); | |
6534 } | |
6535 | |
6536 /** | |
6537 * Pseudo-external assembler syntax: {@code bflr{++|--} }<i>bi</i> | |
6538 * Example disassembly syntax: {@code bflr 0x0} | |
6539 * <p> | |
6540 * This is a synthetic instruction equivalent to: {@code bclr(CRFalse | prediction, bi, 0)} | |
6541 * <p> | |
6542 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6543 * | |
6544 * @see #bclr(BOOperand, int, int) | |
6545 * | |
6546 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6547 */ | |
6548 // Template#: 378, Serial#: 378 | |
6549 public void bflr(final int bi, final BranchPredictionBits prediction) { | |
6550 int instruction = 0x4C800020; | |
6551 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6552 instruction |= ((bi & 0x1f) << 16); | |
6553 instruction |= ((prediction.value() & 0x3) << 21); | |
6554 emitInt(instruction); | |
6555 } | |
6556 | |
6557 /** | |
6558 * Pseudo-external assembler syntax: {@code bflrl{++|--} }<i>bi</i> | |
6559 * Example disassembly syntax: {@code bflrl 0x0} | |
6560 * <p> | |
6561 * This is a synthetic instruction equivalent to: {@code bclrl(CRFalse | prediction, bi, 0)} | |
6562 * <p> | |
6563 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6564 * | |
6565 * @see #bclrl(BOOperand, int, int) | |
6566 * | |
6567 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6568 */ | |
6569 // Template#: 379, Serial#: 379 | |
6570 public void bflrl(final int bi, final BranchPredictionBits prediction) { | |
6571 int instruction = 0x4C800021; | |
6572 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6573 instruction |= ((bi & 0x1f) << 16); | |
6574 instruction |= ((prediction.value() & 0x3) << 21); | |
6575 emitInt(instruction); | |
6576 } | |
6577 | |
6578 /** | |
6579 * Pseudo-external assembler syntax: {@code bdnzlr{++|--} } | |
6580 * Example disassembly syntax: {@code bdnzlr } | |
6581 * <p> | |
6582 * This is a synthetic instruction equivalent to: {@code bclr(CTRNonZero | (prediction & 0x1) | (((prediction >>> 1) & 0x1) << 3), 0, 0)} | |
6583 * | |
6584 * @see #bclr(BOOperand, int, int) | |
6585 * | |
6586 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6587 */ | |
6588 // Template#: 380, Serial#: 380 | |
6589 public void bdnzlr(final BranchPredictionBits prediction) { | |
6590 int instruction = 0x4E000020; | |
6591 instruction |= ((prediction.value() & 0x1) << 21) | (((prediction.value() >>> 1) & 0x1) << 24); | |
6592 emitInt(instruction); | |
6593 } | |
6594 | |
6595 /** | |
6596 * Pseudo-external assembler syntax: {@code bdnzlrl{++|--} } | |
6597 * Example disassembly syntax: {@code bdnzlrl } | |
6598 * <p> | |
6599 * This is a synthetic instruction equivalent to: {@code bclrl(CTRNonZero | (prediction & 0x1) | (((prediction >>> 1) & 0x1) << 3), 0, 0)} | |
6600 * | |
6601 * @see #bclrl(BOOperand, int, int) | |
6602 * | |
6603 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6604 */ | |
6605 // Template#: 381, Serial#: 381 | |
6606 public void bdnzlrl(final BranchPredictionBits prediction) { | |
6607 int instruction = 0x4E000021; | |
6608 instruction |= ((prediction.value() & 0x1) << 21) | (((prediction.value() >>> 1) & 0x1) << 24); | |
6609 emitInt(instruction); | |
6610 } | |
6611 | |
6612 /** | |
6613 * Pseudo-external assembler syntax: {@code bdzlr{++|--} } | |
6614 * Example disassembly syntax: {@code bdzlr } | |
6615 * <p> | |
6616 * This is a synthetic instruction equivalent to: {@code bclr(CTRZero | (prediction & 0x1) | (((prediction >>> 1) & 0x1) << 3), 0, 0)} | |
6617 * | |
6618 * @see #bclr(BOOperand, int, int) | |
6619 * | |
6620 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6621 */ | |
6622 // Template#: 382, Serial#: 382 | |
6623 public void bdzlr(final BranchPredictionBits prediction) { | |
6624 int instruction = 0x4E400020; | |
6625 instruction |= ((prediction.value() & 0x1) << 21) | (((prediction.value() >>> 1) & 0x1) << 24); | |
6626 emitInt(instruction); | |
6627 } | |
6628 | |
6629 /** | |
6630 * Pseudo-external assembler syntax: {@code bdzlrl{++|--} } | |
6631 * Example disassembly syntax: {@code bdzlrl } | |
6632 * <p> | |
6633 * This is a synthetic instruction equivalent to: {@code bclrl(CTRZero | (prediction & 0x1) | (((prediction >>> 1) & 0x1) << 3), 0, 0)} | |
6634 * | |
6635 * @see #bclrl(BOOperand, int, int) | |
6636 * | |
6637 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6638 */ | |
6639 // Template#: 383, Serial#: 383 | |
6640 public void bdzlrl(final BranchPredictionBits prediction) { | |
6641 int instruction = 0x4E400021; | |
6642 instruction |= ((prediction.value() & 0x1) << 21) | (((prediction.value() >>> 1) & 0x1) << 24); | |
6643 emitInt(instruction); | |
6644 } | |
6645 | |
6646 /** | |
6647 * Pseudo-external assembler syntax: {@code bdnztlr }<i>bi</i> | |
6648 * Example disassembly syntax: {@code bdnztlr 0x0} | |
6649 * <p> | |
6650 * This is a synthetic instruction equivalent to: {@code bclr(CTRNonZero_CRTrue, bi, 0)} | |
6651 * <p> | |
6652 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6653 * | |
6654 * @see #bclr(BOOperand, int, int) | |
6655 * | |
6656 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6657 */ | |
6658 // Template#: 384, Serial#: 384 | |
6659 public void bdnztlr(final int bi) { | |
6660 int instruction = 0x4D000020; | |
6661 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6662 instruction |= ((bi & 0x1f) << 16); | |
6663 emitInt(instruction); | |
6664 } | |
6665 | |
6666 /** | |
6667 * Pseudo-external assembler syntax: {@code bdnztlrl }<i>bi</i> | |
6668 * Example disassembly syntax: {@code bdnztlrl 0x0} | |
6669 * <p> | |
6670 * This is a synthetic instruction equivalent to: {@code bclrl(CTRNonZero_CRTrue, bi, 0)} | |
6671 * <p> | |
6672 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6673 * | |
6674 * @see #bclrl(BOOperand, int, int) | |
6675 * | |
6676 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6677 */ | |
6678 // Template#: 385, Serial#: 385 | |
6679 public void bdnztlrl(final int bi) { | |
6680 int instruction = 0x4D000021; | |
6681 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6682 instruction |= ((bi & 0x1f) << 16); | |
6683 emitInt(instruction); | |
6684 } | |
6685 | |
6686 /** | |
6687 * Pseudo-external assembler syntax: {@code bdnzflr }<i>bi</i> | |
6688 * Example disassembly syntax: {@code bdnzflr 0x0} | |
6689 * <p> | |
6690 * This is a synthetic instruction equivalent to: {@code bclr(CTRNonZero_CRFalse, bi, 0)} | |
6691 * <p> | |
6692 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6693 * | |
6694 * @see #bclr(BOOperand, int, int) | |
6695 * | |
6696 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6697 */ | |
6698 // Template#: 386, Serial#: 386 | |
6699 public void bdnzflr(final int bi) { | |
6700 int instruction = 0x4C000020; | |
6701 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6702 instruction |= ((bi & 0x1f) << 16); | |
6703 emitInt(instruction); | |
6704 } | |
6705 | |
6706 /** | |
6707 * Pseudo-external assembler syntax: {@code bdnzflrl }<i>bi</i> | |
6708 * Example disassembly syntax: {@code bdnzflrl 0x0} | |
6709 * <p> | |
6710 * This is a synthetic instruction equivalent to: {@code bclrl(CTRNonZero_CRFalse, bi, 0)} | |
6711 * <p> | |
6712 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6713 * | |
6714 * @see #bclrl(BOOperand, int, int) | |
6715 * | |
6716 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6717 */ | |
6718 // Template#: 387, Serial#: 387 | |
6719 public void bdnzflrl(final int bi) { | |
6720 int instruction = 0x4C000021; | |
6721 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6722 instruction |= ((bi & 0x1f) << 16); | |
6723 emitInt(instruction); | |
6724 } | |
6725 | |
6726 /** | |
6727 * Pseudo-external assembler syntax: {@code bdztlr }<i>bi</i> | |
6728 * Example disassembly syntax: {@code bdztlr 0x0} | |
6729 * <p> | |
6730 * This is a synthetic instruction equivalent to: {@code bclr(CTRZero_CRTrue, bi, 0)} | |
6731 * <p> | |
6732 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6733 * | |
6734 * @see #bclr(BOOperand, int, int) | |
6735 * | |
6736 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6737 */ | |
6738 // Template#: 388, Serial#: 388 | |
6739 public void bdztlr(final int bi) { | |
6740 int instruction = 0x4D400020; | |
6741 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6742 instruction |= ((bi & 0x1f) << 16); | |
6743 emitInt(instruction); | |
6744 } | |
6745 | |
6746 /** | |
6747 * Pseudo-external assembler syntax: {@code bdztlrl }<i>bi</i> | |
6748 * Example disassembly syntax: {@code bdztlrl 0x0} | |
6749 * <p> | |
6750 * This is a synthetic instruction equivalent to: {@code bclrl(CTRZero_CRTrue, bi, 0)} | |
6751 * <p> | |
6752 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6753 * | |
6754 * @see #bclrl(BOOperand, int, int) | |
6755 * | |
6756 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6757 */ | |
6758 // Template#: 389, Serial#: 389 | |
6759 public void bdztlrl(final int bi) { | |
6760 int instruction = 0x4D400021; | |
6761 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6762 instruction |= ((bi & 0x1f) << 16); | |
6763 emitInt(instruction); | |
6764 } | |
6765 | |
6766 /** | |
6767 * Pseudo-external assembler syntax: {@code bdzflr }<i>bi</i> | |
6768 * Example disassembly syntax: {@code bdzflr 0x0} | |
6769 * <p> | |
6770 * This is a synthetic instruction equivalent to: {@code bclr(CTRZero_CRFalse, bi, 0)} | |
6771 * <p> | |
6772 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6773 * | |
6774 * @see #bclr(BOOperand, int, int) | |
6775 * | |
6776 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6777 */ | |
6778 // Template#: 390, Serial#: 390 | |
6779 public void bdzflr(final int bi) { | |
6780 int instruction = 0x4C400020; | |
6781 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6782 instruction |= ((bi & 0x1f) << 16); | |
6783 emitInt(instruction); | |
6784 } | |
6785 | |
6786 /** | |
6787 * Pseudo-external assembler syntax: {@code bdzflrl }<i>bi</i> | |
6788 * Example disassembly syntax: {@code bdzflrl 0x0} | |
6789 * <p> | |
6790 * This is a synthetic instruction equivalent to: {@code bclrl(CTRZero_CRFalse, bi, 0)} | |
6791 * <p> | |
6792 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6793 * | |
6794 * @see #bclrl(BOOperand, int, int) | |
6795 * | |
6796 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6797 */ | |
6798 // Template#: 391, Serial#: 391 | |
6799 public void bdzflrl(final int bi) { | |
6800 int instruction = 0x4C400021; | |
6801 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6802 instruction |= ((bi & 0x1f) << 16); | |
6803 emitInt(instruction); | |
6804 } | |
6805 | |
6806 /** | |
6807 * Pseudo-external assembler syntax: {@code bctr } | |
6808 * Example disassembly syntax: {@code bctr } | |
6809 * <p> | |
6810 * This is a synthetic instruction equivalent to: {@code bcctr(Always, 0, 0)} | |
6811 * | |
6812 * @see #bcctr(BOOperand, int, int) | |
6813 * | |
6814 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6815 */ | |
6816 // Template#: 392, Serial#: 392 | |
6817 public void bctr() { | |
6818 int instruction = 0x4E800420; | |
6819 emitInt(instruction); | |
6820 } | |
6821 | |
6822 /** | |
6823 * Pseudo-external assembler syntax: {@code bctrl } | |
6824 * Example disassembly syntax: {@code bctrl } | |
6825 * <p> | |
6826 * This is a synthetic instruction equivalent to: {@code bcctrl(Always, 0, 0)} | |
6827 * | |
6828 * @see #bcctrl(BOOperand, int, int) | |
6829 * | |
6830 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6831 */ | |
6832 // Template#: 393, Serial#: 393 | |
6833 public void bctrl() { | |
6834 int instruction = 0x4E800421; | |
6835 emitInt(instruction); | |
6836 } | |
6837 | |
6838 /** | |
6839 * Pseudo-external assembler syntax: {@code btctr{++|--} }<i>bi</i> | |
6840 * Example disassembly syntax: {@code btctr 0x0} | |
6841 * <p> | |
6842 * This is a synthetic instruction equivalent to: {@code bcctr(CRTrue | prediction, bi, 0)} | |
6843 * <p> | |
6844 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6845 * | |
6846 * @see #bcctr(BOOperand, int, int) | |
6847 * | |
6848 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6849 */ | |
6850 // Template#: 394, Serial#: 394 | |
6851 public void btctr(final int bi, final BranchPredictionBits prediction) { | |
6852 int instruction = 0x4D800420; | |
6853 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6854 instruction |= ((bi & 0x1f) << 16); | |
6855 instruction |= ((prediction.value() & 0x3) << 21); | |
6856 emitInt(instruction); | |
6857 } | |
6858 | |
6859 /** | |
6860 * Pseudo-external assembler syntax: {@code btctrl{++|--} }<i>bi</i> | |
6861 * Example disassembly syntax: {@code btctrl 0x0} | |
6862 * <p> | |
6863 * This is a synthetic instruction equivalent to: {@code bcctrl(CRTrue | prediction, bi, 0)} | |
6864 * <p> | |
6865 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6866 * | |
6867 * @see #bcctrl(BOOperand, int, int) | |
6868 * | |
6869 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6870 */ | |
6871 // Template#: 395, Serial#: 395 | |
6872 public void btctrl(final int bi, final BranchPredictionBits prediction) { | |
6873 int instruction = 0x4D800421; | |
6874 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6875 instruction |= ((bi & 0x1f) << 16); | |
6876 instruction |= ((prediction.value() & 0x3) << 21); | |
6877 emitInt(instruction); | |
6878 } | |
6879 | |
6880 /** | |
6881 * Pseudo-external assembler syntax: {@code bfctr{++|--} }<i>bi</i> | |
6882 * Example disassembly syntax: {@code bfctr 0x0} | |
6883 * <p> | |
6884 * This is a synthetic instruction equivalent to: {@code bcctr(CRFalse | prediction, bi, 0)} | |
6885 * <p> | |
6886 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6887 * | |
6888 * @see #bcctr(BOOperand, int, int) | |
6889 * | |
6890 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6891 */ | |
6892 // Template#: 396, Serial#: 396 | |
6893 public void bfctr(final int bi, final BranchPredictionBits prediction) { | |
6894 int instruction = 0x4C800420; | |
6895 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6896 instruction |= ((bi & 0x1f) << 16); | |
6897 instruction |= ((prediction.value() & 0x3) << 21); | |
6898 emitInt(instruction); | |
6899 } | |
6900 | |
6901 /** | |
6902 * Pseudo-external assembler syntax: {@code bfctrl{++|--} }<i>bi</i> | |
6903 * Example disassembly syntax: {@code bfctrl 0x0} | |
6904 * <p> | |
6905 * This is a synthetic instruction equivalent to: {@code bcctrl(CRFalse | prediction, bi, 0)} | |
6906 * <p> | |
6907 * Constraint: {@code 0 <= bi && bi <= 31}<br /> | |
6908 * | |
6909 * @see #bcctrl(BOOperand, int, int) | |
6910 * | |
6911 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.2 [Book 1]" | |
6912 */ | |
6913 // Template#: 397, Serial#: 397 | |
6914 public void bfctrl(final int bi, final BranchPredictionBits prediction) { | |
6915 int instruction = 0x4C800421; | |
6916 checkConstraint(0 <= bi && bi <= 31, "0 <= bi && bi <= 31"); | |
6917 instruction |= ((bi & 0x1f) << 16); | |
6918 instruction |= ((prediction.value() & 0x3) << 21); | |
6919 emitInt(instruction); | |
6920 } | |
6921 | |
6922 /** | |
6923 * Pseudo-external assembler syntax: {@code blt{++|--} }<i>crf</i>, <i>bd</i> | |
6924 * Example disassembly syntax: {@code blt cr0, L1: -32768} | |
6925 * <p> | |
6926 * This is a synthetic instruction equivalent to: {@code bc(CRTrue | prediction, (crf * 4), bd)} | |
6927 * <p> | |
6928 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6929 * | |
6930 * @see #bc(BOOperand, int, int) | |
6931 * | |
6932 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
6933 */ | |
6934 // Template#: 398, Serial#: 398 | |
6935 public void blt(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
6936 int instruction = 0x41800000; | |
6937 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6938 instruction |= ((crf.value() & 0x7) << 18); | |
6939 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6940 instruction |= ((prediction.value() & 0x3) << 21); | |
6941 emitInt(instruction); | |
6942 } | |
6943 | |
6944 /** | |
6945 * Pseudo-external assembler syntax: {@code blta{++|--} }<i>crf</i>, <i>bd</i> | |
6946 * Example disassembly syntax: {@code blta cr0, L1: -32768} | |
6947 * <p> | |
6948 * This is a synthetic instruction equivalent to: {@code bca(CRTrue | prediction, (crf * 4), bd)} | |
6949 * <p> | |
6950 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6951 * | |
6952 * @see #bca(BOOperand, int, int) | |
6953 * | |
6954 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
6955 */ | |
6956 // Template#: 399, Serial#: 399 | |
6957 public void blta(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
6958 int instruction = 0x41800002; | |
6959 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6960 instruction |= ((crf.value() & 0x7) << 18); | |
6961 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6962 instruction |= ((prediction.value() & 0x3) << 21); | |
6963 emitInt(instruction); | |
6964 } | |
6965 | |
6966 /** | |
6967 * Pseudo-external assembler syntax: {@code bltl{++|--} }<i>crf</i>, <i>bd</i> | |
6968 * Example disassembly syntax: {@code bltl cr0, L1: -32768} | |
6969 * <p> | |
6970 * This is a synthetic instruction equivalent to: {@code bcl(CRTrue | prediction, (crf * 4), bd)} | |
6971 * <p> | |
6972 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6973 * | |
6974 * @see #bcl(BOOperand, int, int) | |
6975 * | |
6976 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
6977 */ | |
6978 // Template#: 400, Serial#: 400 | |
6979 public void bltl(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
6980 int instruction = 0x41800001; | |
6981 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
6982 instruction |= ((crf.value() & 0x7) << 18); | |
6983 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
6984 instruction |= ((prediction.value() & 0x3) << 21); | |
6985 emitInt(instruction); | |
6986 } | |
6987 | |
6988 /** | |
6989 * Pseudo-external assembler syntax: {@code bltla{++|--} }<i>crf</i>, <i>bd</i> | |
6990 * Example disassembly syntax: {@code bltla cr0, L1: -32768} | |
6991 * <p> | |
6992 * This is a synthetic instruction equivalent to: {@code bcla(CRTrue | prediction, (crf * 4), bd)} | |
6993 * <p> | |
6994 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
6995 * | |
6996 * @see #bcla(BOOperand, int, int) | |
6997 * | |
6998 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
6999 */ | |
7000 // Template#: 401, Serial#: 401 | |
7001 public void bltla(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7002 int instruction = 0x41800003; | |
7003 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7004 instruction |= ((crf.value() & 0x7) << 18); | |
7005 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7006 instruction |= ((prediction.value() & 0x3) << 21); | |
7007 emitInt(instruction); | |
7008 } | |
7009 | |
7010 /** | |
7011 * Pseudo-external assembler syntax: {@code ble{++|--} }<i>crf</i>, <i>bd</i> | |
7012 * Example disassembly syntax: {@code ble cr0, L1: -32768} | |
7013 * <p> | |
7014 * This is a synthetic instruction equivalent to: {@code bc(CRFalse | prediction, 1 | (crf * 4), bd)} | |
7015 * <p> | |
7016 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7017 * | |
7018 * @see #bc(BOOperand, int, int) | |
7019 * | |
7020 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7021 */ | |
7022 // Template#: 402, Serial#: 402 | |
7023 public void ble(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7024 int instruction = 0x40810000; | |
7025 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7026 instruction |= ((crf.value() & 0x7) << 18); | |
7027 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7028 instruction |= ((prediction.value() & 0x3) << 21); | |
7029 emitInt(instruction); | |
7030 } | |
7031 | |
7032 /** | |
7033 * Pseudo-external assembler syntax: {@code blea{++|--} }<i>crf</i>, <i>bd</i> | |
7034 * Example disassembly syntax: {@code blea cr0, L1: -32768} | |
7035 * <p> | |
7036 * This is a synthetic instruction equivalent to: {@code bca(CRFalse | prediction, 1 | (crf * 4), bd)} | |
7037 * <p> | |
7038 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7039 * | |
7040 * @see #bca(BOOperand, int, int) | |
7041 * | |
7042 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7043 */ | |
7044 // Template#: 403, Serial#: 403 | |
7045 public void blea(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7046 int instruction = 0x40810002; | |
7047 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7048 instruction |= ((crf.value() & 0x7) << 18); | |
7049 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7050 instruction |= ((prediction.value() & 0x3) << 21); | |
7051 emitInt(instruction); | |
7052 } | |
7053 | |
7054 /** | |
7055 * Pseudo-external assembler syntax: {@code blel{++|--} }<i>crf</i>, <i>bd</i> | |
7056 * Example disassembly syntax: {@code blel cr0, L1: -32768} | |
7057 * <p> | |
7058 * This is a synthetic instruction equivalent to: {@code bcl(CRFalse | prediction, 1 | (crf * 4), bd)} | |
7059 * <p> | |
7060 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7061 * | |
7062 * @see #bcl(BOOperand, int, int) | |
7063 * | |
7064 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7065 */ | |
7066 // Template#: 404, Serial#: 404 | |
7067 public void blel(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7068 int instruction = 0x40810001; | |
7069 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7070 instruction |= ((crf.value() & 0x7) << 18); | |
7071 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7072 instruction |= ((prediction.value() & 0x3) << 21); | |
7073 emitInt(instruction); | |
7074 } | |
7075 | |
7076 /** | |
7077 * Pseudo-external assembler syntax: {@code blela{++|--} }<i>crf</i>, <i>bd</i> | |
7078 * Example disassembly syntax: {@code blela cr0, L1: -32768} | |
7079 * <p> | |
7080 * This is a synthetic instruction equivalent to: {@code bcla(CRFalse | prediction, 1 | (crf * 4), bd)} | |
7081 * <p> | |
7082 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7083 * | |
7084 * @see #bcla(BOOperand, int, int) | |
7085 * | |
7086 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7087 */ | |
7088 // Template#: 405, Serial#: 405 | |
7089 public void blela(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7090 int instruction = 0x40810003; | |
7091 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7092 instruction |= ((crf.value() & 0x7) << 18); | |
7093 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7094 instruction |= ((prediction.value() & 0x3) << 21); | |
7095 emitInt(instruction); | |
7096 } | |
7097 | |
7098 /** | |
7099 * Pseudo-external assembler syntax: {@code beq{++|--} }<i>crf</i>, <i>bd</i> | |
7100 * Example disassembly syntax: {@code beq cr0, L1: -32768} | |
7101 * <p> | |
7102 * This is a synthetic instruction equivalent to: {@code bc(CRTrue | prediction, 2 | (crf * 4), bd)} | |
7103 * <p> | |
7104 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7105 * | |
7106 * @see #bc(BOOperand, int, int) | |
7107 * | |
7108 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7109 */ | |
7110 // Template#: 406, Serial#: 406 | |
7111 public void beq(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7112 int instruction = 0x41820000; | |
7113 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7114 instruction |= ((crf.value() & 0x7) << 18); | |
7115 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7116 instruction |= ((prediction.value() & 0x3) << 21); | |
7117 emitInt(instruction); | |
7118 } | |
7119 | |
7120 /** | |
7121 * Pseudo-external assembler syntax: {@code beqa{++|--} }<i>crf</i>, <i>bd</i> | |
7122 * Example disassembly syntax: {@code beqa cr0, L1: -32768} | |
7123 * <p> | |
7124 * This is a synthetic instruction equivalent to: {@code bca(CRTrue | prediction, 2 | (crf * 4), bd)} | |
7125 * <p> | |
7126 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7127 * | |
7128 * @see #bca(BOOperand, int, int) | |
7129 * | |
7130 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7131 */ | |
7132 // Template#: 407, Serial#: 407 | |
7133 public void beqa(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7134 int instruction = 0x41820002; | |
7135 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7136 instruction |= ((crf.value() & 0x7) << 18); | |
7137 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7138 instruction |= ((prediction.value() & 0x3) << 21); | |
7139 emitInt(instruction); | |
7140 } | |
7141 | |
7142 /** | |
7143 * Pseudo-external assembler syntax: {@code beql{++|--} }<i>crf</i>, <i>bd</i> | |
7144 * Example disassembly syntax: {@code beql cr0, L1: -32768} | |
7145 * <p> | |
7146 * This is a synthetic instruction equivalent to: {@code bcl(CRTrue | prediction, 2 | (crf * 4), bd)} | |
7147 * <p> | |
7148 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7149 * | |
7150 * @see #bcl(BOOperand, int, int) | |
7151 * | |
7152 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7153 */ | |
7154 // Template#: 408, Serial#: 408 | |
7155 public void beql(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7156 int instruction = 0x41820001; | |
7157 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7158 instruction |= ((crf.value() & 0x7) << 18); | |
7159 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7160 instruction |= ((prediction.value() & 0x3) << 21); | |
7161 emitInt(instruction); | |
7162 } | |
7163 | |
7164 /** | |
7165 * Pseudo-external assembler syntax: {@code beqla{++|--} }<i>crf</i>, <i>bd</i> | |
7166 * Example disassembly syntax: {@code beqla cr0, L1: -32768} | |
7167 * <p> | |
7168 * This is a synthetic instruction equivalent to: {@code bcla(CRTrue | prediction, 2 | (crf * 4), bd)} | |
7169 * <p> | |
7170 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7171 * | |
7172 * @see #bcla(BOOperand, int, int) | |
7173 * | |
7174 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7175 */ | |
7176 // Template#: 409, Serial#: 409 | |
7177 public void beqla(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7178 int instruction = 0x41820003; | |
7179 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7180 instruction |= ((crf.value() & 0x7) << 18); | |
7181 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7182 instruction |= ((prediction.value() & 0x3) << 21); | |
7183 emitInt(instruction); | |
7184 } | |
7185 | |
7186 /** | |
7187 * Pseudo-external assembler syntax: {@code bge{++|--} }<i>crf</i>, <i>bd</i> | |
7188 * Example disassembly syntax: {@code bge cr0, L1: -32768} | |
7189 * <p> | |
7190 * This is a synthetic instruction equivalent to: {@code bc(CRFalse | prediction, (crf * 4), bd)} | |
7191 * <p> | |
7192 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7193 * | |
7194 * @see #bc(BOOperand, int, int) | |
7195 * | |
7196 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7197 */ | |
7198 // Template#: 410, Serial#: 410 | |
7199 public void bge(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7200 int instruction = 0x40800000; | |
7201 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7202 instruction |= ((crf.value() & 0x7) << 18); | |
7203 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7204 instruction |= ((prediction.value() & 0x3) << 21); | |
7205 emitInt(instruction); | |
7206 } | |
7207 | |
7208 /** | |
7209 * Pseudo-external assembler syntax: {@code bgea{++|--} }<i>crf</i>, <i>bd</i> | |
7210 * Example disassembly syntax: {@code bgea cr0, L1: -32768} | |
7211 * <p> | |
7212 * This is a synthetic instruction equivalent to: {@code bca(CRFalse | prediction, (crf * 4), bd)} | |
7213 * <p> | |
7214 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7215 * | |
7216 * @see #bca(BOOperand, int, int) | |
7217 * | |
7218 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7219 */ | |
7220 // Template#: 411, Serial#: 411 | |
7221 public void bgea(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7222 int instruction = 0x40800002; | |
7223 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7224 instruction |= ((crf.value() & 0x7) << 18); | |
7225 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7226 instruction |= ((prediction.value() & 0x3) << 21); | |
7227 emitInt(instruction); | |
7228 } | |
7229 | |
7230 /** | |
7231 * Pseudo-external assembler syntax: {@code bgel{++|--} }<i>crf</i>, <i>bd</i> | |
7232 * Example disassembly syntax: {@code bgel cr0, L1: -32768} | |
7233 * <p> | |
7234 * This is a synthetic instruction equivalent to: {@code bcl(CRFalse | prediction, (crf * 4), bd)} | |
7235 * <p> | |
7236 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7237 * | |
7238 * @see #bcl(BOOperand, int, int) | |
7239 * | |
7240 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7241 */ | |
7242 // Template#: 412, Serial#: 412 | |
7243 public void bgel(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7244 int instruction = 0x40800001; | |
7245 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7246 instruction |= ((crf.value() & 0x7) << 18); | |
7247 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7248 instruction |= ((prediction.value() & 0x3) << 21); | |
7249 emitInt(instruction); | |
7250 } | |
7251 | |
7252 /** | |
7253 * Pseudo-external assembler syntax: {@code bgela{++|--} }<i>crf</i>, <i>bd</i> | |
7254 * Example disassembly syntax: {@code bgela cr0, L1: -32768} | |
7255 * <p> | |
7256 * This is a synthetic instruction equivalent to: {@code bcla(CRFalse | prediction, (crf * 4), bd)} | |
7257 * <p> | |
7258 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7259 * | |
7260 * @see #bcla(BOOperand, int, int) | |
7261 * | |
7262 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7263 */ | |
7264 // Template#: 413, Serial#: 413 | |
7265 public void bgela(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7266 int instruction = 0x40800003; | |
7267 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7268 instruction |= ((crf.value() & 0x7) << 18); | |
7269 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7270 instruction |= ((prediction.value() & 0x3) << 21); | |
7271 emitInt(instruction); | |
7272 } | |
7273 | |
7274 /** | |
7275 * Pseudo-external assembler syntax: {@code bgt{++|--} }<i>crf</i>, <i>bd</i> | |
7276 * Example disassembly syntax: {@code bgt cr0, L1: -32768} | |
7277 * <p> | |
7278 * This is a synthetic instruction equivalent to: {@code bc(CRTrue | prediction, 1 | (crf * 4), bd)} | |
7279 * <p> | |
7280 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7281 * | |
7282 * @see #bc(BOOperand, int, int) | |
7283 * | |
7284 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7285 */ | |
7286 // Template#: 414, Serial#: 414 | |
7287 public void bgt(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7288 int instruction = 0x41810000; | |
7289 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7290 instruction |= ((crf.value() & 0x7) << 18); | |
7291 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7292 instruction |= ((prediction.value() & 0x3) << 21); | |
7293 emitInt(instruction); | |
7294 } | |
7295 | |
7296 /** | |
7297 * Pseudo-external assembler syntax: {@code bgta{++|--} }<i>crf</i>, <i>bd</i> | |
7298 * Example disassembly syntax: {@code bgta cr0, L1: -32768} | |
7299 * <p> | |
7300 * This is a synthetic instruction equivalent to: {@code bca(CRTrue | prediction, 1 | (crf * 4), bd)} | |
7301 * <p> | |
7302 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7303 * | |
7304 * @see #bca(BOOperand, int, int) | |
7305 * | |
7306 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7307 */ | |
7308 // Template#: 415, Serial#: 415 | |
7309 public void bgta(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7310 int instruction = 0x41810002; | |
7311 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7312 instruction |= ((crf.value() & 0x7) << 18); | |
7313 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7314 instruction |= ((prediction.value() & 0x3) << 21); | |
7315 emitInt(instruction); | |
7316 } | |
7317 | |
7318 /** | |
7319 * Pseudo-external assembler syntax: {@code bgtl{++|--} }<i>crf</i>, <i>bd</i> | |
7320 * Example disassembly syntax: {@code bgtl cr0, L1: -32768} | |
7321 * <p> | |
7322 * This is a synthetic instruction equivalent to: {@code bcl(CRTrue | prediction, 1 | (crf * 4), bd)} | |
7323 * <p> | |
7324 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7325 * | |
7326 * @see #bcl(BOOperand, int, int) | |
7327 * | |
7328 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7329 */ | |
7330 // Template#: 416, Serial#: 416 | |
7331 public void bgtl(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7332 int instruction = 0x41810001; | |
7333 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7334 instruction |= ((crf.value() & 0x7) << 18); | |
7335 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7336 instruction |= ((prediction.value() & 0x3) << 21); | |
7337 emitInt(instruction); | |
7338 } | |
7339 | |
7340 /** | |
7341 * Pseudo-external assembler syntax: {@code bgtla{++|--} }<i>crf</i>, <i>bd</i> | |
7342 * Example disassembly syntax: {@code bgtla cr0, L1: -32768} | |
7343 * <p> | |
7344 * This is a synthetic instruction equivalent to: {@code bcla(CRTrue | prediction, 1 | (crf * 4), bd)} | |
7345 * <p> | |
7346 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7347 * | |
7348 * @see #bcla(BOOperand, int, int) | |
7349 * | |
7350 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7351 */ | |
7352 // Template#: 417, Serial#: 417 | |
7353 public void bgtla(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7354 int instruction = 0x41810003; | |
7355 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7356 instruction |= ((crf.value() & 0x7) << 18); | |
7357 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7358 instruction |= ((prediction.value() & 0x3) << 21); | |
7359 emitInt(instruction); | |
7360 } | |
7361 | |
7362 /** | |
7363 * Pseudo-external assembler syntax: {@code bnl{++|--} }<i>crf</i>, <i>bd</i> | |
7364 * Example disassembly syntax: {@code bnl cr0, L1: -32768} | |
7365 * <p> | |
7366 * This is a synthetic instruction equivalent to: {@code bc(CRFalse | prediction, (crf * 4), bd)} | |
7367 * <p> | |
7368 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7369 * | |
7370 * @see #bc(BOOperand, int, int) | |
7371 * | |
7372 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7373 */ | |
7374 // Template#: 418, Serial#: 418 | |
7375 public void bnl(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7376 int instruction = 0x40800000; | |
7377 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7378 instruction |= ((crf.value() & 0x7) << 18); | |
7379 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7380 instruction |= ((prediction.value() & 0x3) << 21); | |
7381 emitInt(instruction); | |
7382 } | |
7383 | |
7384 /** | |
7385 * Pseudo-external assembler syntax: {@code bnla{++|--} }<i>crf</i>, <i>bd</i> | |
7386 * Example disassembly syntax: {@code bnla cr0, L1: -32768} | |
7387 * <p> | |
7388 * This is a synthetic instruction equivalent to: {@code bca(CRFalse | prediction, (crf * 4), bd)} | |
7389 * <p> | |
7390 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7391 * | |
7392 * @see #bca(BOOperand, int, int) | |
7393 * | |
7394 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7395 */ | |
7396 // Template#: 419, Serial#: 419 | |
7397 public void bnla(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7398 int instruction = 0x40800002; | |
7399 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7400 instruction |= ((crf.value() & 0x7) << 18); | |
7401 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7402 instruction |= ((prediction.value() & 0x3) << 21); | |
7403 emitInt(instruction); | |
7404 } | |
7405 | |
7406 /** | |
7407 * Pseudo-external assembler syntax: {@code bnll{++|--} }<i>crf</i>, <i>bd</i> | |
7408 * Example disassembly syntax: {@code bnll cr0, L1: -32768} | |
7409 * <p> | |
7410 * This is a synthetic instruction equivalent to: {@code bcl(CRFalse | prediction, (crf * 4), bd)} | |
7411 * <p> | |
7412 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7413 * | |
7414 * @see #bcl(BOOperand, int, int) | |
7415 * | |
7416 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7417 */ | |
7418 // Template#: 420, Serial#: 420 | |
7419 public void bnll(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7420 int instruction = 0x40800001; | |
7421 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7422 instruction |= ((crf.value() & 0x7) << 18); | |
7423 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7424 instruction |= ((prediction.value() & 0x3) << 21); | |
7425 emitInt(instruction); | |
7426 } | |
7427 | |
7428 /** | |
7429 * Pseudo-external assembler syntax: {@code bnlla{++|--} }<i>crf</i>, <i>bd</i> | |
7430 * Example disassembly syntax: {@code bnlla cr0, L1: -32768} | |
7431 * <p> | |
7432 * This is a synthetic instruction equivalent to: {@code bcla(CRFalse | prediction, (crf * 4), bd)} | |
7433 * <p> | |
7434 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7435 * | |
7436 * @see #bcla(BOOperand, int, int) | |
7437 * | |
7438 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7439 */ | |
7440 // Template#: 421, Serial#: 421 | |
7441 public void bnlla(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7442 int instruction = 0x40800003; | |
7443 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7444 instruction |= ((crf.value() & 0x7) << 18); | |
7445 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7446 instruction |= ((prediction.value() & 0x3) << 21); | |
7447 emitInt(instruction); | |
7448 } | |
7449 | |
7450 /** | |
7451 * Pseudo-external assembler syntax: {@code bne{++|--} }<i>crf</i>, <i>bd</i> | |
7452 * Example disassembly syntax: {@code bne cr0, L1: -32768} | |
7453 * <p> | |
7454 * This is a synthetic instruction equivalent to: {@code bc(CRFalse | prediction, 2 | (crf * 4), bd)} | |
7455 * <p> | |
7456 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7457 * | |
7458 * @see #bc(BOOperand, int, int) | |
7459 * | |
7460 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7461 */ | |
7462 // Template#: 422, Serial#: 422 | |
7463 public void bne(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7464 int instruction = 0x40820000; | |
7465 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7466 instruction |= ((crf.value() & 0x7) << 18); | |
7467 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7468 instruction |= ((prediction.value() & 0x3) << 21); | |
7469 emitInt(instruction); | |
7470 } | |
7471 | |
7472 /** | |
7473 * Pseudo-external assembler syntax: {@code bnea{++|--} }<i>crf</i>, <i>bd</i> | |
7474 * Example disassembly syntax: {@code bnea cr0, L1: -32768} | |
7475 * <p> | |
7476 * This is a synthetic instruction equivalent to: {@code bca(CRFalse | prediction, 2 | (crf * 4), bd)} | |
7477 * <p> | |
7478 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7479 * | |
7480 * @see #bca(BOOperand, int, int) | |
7481 * | |
7482 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7483 */ | |
7484 // Template#: 423, Serial#: 423 | |
7485 public void bnea(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7486 int instruction = 0x40820002; | |
7487 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7488 instruction |= ((crf.value() & 0x7) << 18); | |
7489 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7490 instruction |= ((prediction.value() & 0x3) << 21); | |
7491 emitInt(instruction); | |
7492 } | |
7493 | |
7494 /** | |
7495 * Pseudo-external assembler syntax: {@code bnel{++|--} }<i>crf</i>, <i>bd</i> | |
7496 * Example disassembly syntax: {@code bnel cr0, L1: -32768} | |
7497 * <p> | |
7498 * This is a synthetic instruction equivalent to: {@code bcl(CRFalse | prediction, 2 | (crf * 4), bd)} | |
7499 * <p> | |
7500 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7501 * | |
7502 * @see #bcl(BOOperand, int, int) | |
7503 * | |
7504 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7505 */ | |
7506 // Template#: 424, Serial#: 424 | |
7507 public void bnel(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7508 int instruction = 0x40820001; | |
7509 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7510 instruction |= ((crf.value() & 0x7) << 18); | |
7511 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7512 instruction |= ((prediction.value() & 0x3) << 21); | |
7513 emitInt(instruction); | |
7514 } | |
7515 | |
7516 /** | |
7517 * Pseudo-external assembler syntax: {@code bnela{++|--} }<i>crf</i>, <i>bd</i> | |
7518 * Example disassembly syntax: {@code bnela cr0, L1: -32768} | |
7519 * <p> | |
7520 * This is a synthetic instruction equivalent to: {@code bcla(CRFalse | prediction, 2 | (crf * 4), bd)} | |
7521 * <p> | |
7522 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7523 * | |
7524 * @see #bcla(BOOperand, int, int) | |
7525 * | |
7526 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7527 */ | |
7528 // Template#: 425, Serial#: 425 | |
7529 public void bnela(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7530 int instruction = 0x40820003; | |
7531 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7532 instruction |= ((crf.value() & 0x7) << 18); | |
7533 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7534 instruction |= ((prediction.value() & 0x3) << 21); | |
7535 emitInt(instruction); | |
7536 } | |
7537 | |
7538 /** | |
7539 * Pseudo-external assembler syntax: {@code bng{++|--} }<i>crf</i>, <i>bd</i> | |
7540 * Example disassembly syntax: {@code bng cr0, L1: -32768} | |
7541 * <p> | |
7542 * This is a synthetic instruction equivalent to: {@code bc(CRFalse | prediction, 1 | (crf * 4), bd)} | |
7543 * <p> | |
7544 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7545 * | |
7546 * @see #bc(BOOperand, int, int) | |
7547 * | |
7548 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7549 */ | |
7550 // Template#: 426, Serial#: 426 | |
7551 public void bng(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7552 int instruction = 0x40810000; | |
7553 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7554 instruction |= ((crf.value() & 0x7) << 18); | |
7555 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7556 instruction |= ((prediction.value() & 0x3) << 21); | |
7557 emitInt(instruction); | |
7558 } | |
7559 | |
7560 /** | |
7561 * Pseudo-external assembler syntax: {@code bnga{++|--} }<i>crf</i>, <i>bd</i> | |
7562 * Example disassembly syntax: {@code bnga cr0, L1: -32768} | |
7563 * <p> | |
7564 * This is a synthetic instruction equivalent to: {@code bca(CRFalse | prediction, 1 | (crf * 4), bd)} | |
7565 * <p> | |
7566 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7567 * | |
7568 * @see #bca(BOOperand, int, int) | |
7569 * | |
7570 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7571 */ | |
7572 // Template#: 427, Serial#: 427 | |
7573 public void bnga(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7574 int instruction = 0x40810002; | |
7575 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7576 instruction |= ((crf.value() & 0x7) << 18); | |
7577 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7578 instruction |= ((prediction.value() & 0x3) << 21); | |
7579 emitInt(instruction); | |
7580 } | |
7581 | |
7582 /** | |
7583 * Pseudo-external assembler syntax: {@code bngl{++|--} }<i>crf</i>, <i>bd</i> | |
7584 * Example disassembly syntax: {@code bngl cr0, L1: -32768} | |
7585 * <p> | |
7586 * This is a synthetic instruction equivalent to: {@code bcl(CRFalse | prediction, 1 | (crf * 4), bd)} | |
7587 * <p> | |
7588 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7589 * | |
7590 * @see #bcl(BOOperand, int, int) | |
7591 * | |
7592 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7593 */ | |
7594 // Template#: 428, Serial#: 428 | |
7595 public void bngl(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7596 int instruction = 0x40810001; | |
7597 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7598 instruction |= ((crf.value() & 0x7) << 18); | |
7599 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7600 instruction |= ((prediction.value() & 0x3) << 21); | |
7601 emitInt(instruction); | |
7602 } | |
7603 | |
7604 /** | |
7605 * Pseudo-external assembler syntax: {@code bngla{++|--} }<i>crf</i>, <i>bd</i> | |
7606 * Example disassembly syntax: {@code bngla cr0, L1: -32768} | |
7607 * <p> | |
7608 * This is a synthetic instruction equivalent to: {@code bcla(CRFalse | prediction, 1 | (crf * 4), bd)} | |
7609 * <p> | |
7610 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7611 * | |
7612 * @see #bcla(BOOperand, int, int) | |
7613 * | |
7614 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7615 */ | |
7616 // Template#: 429, Serial#: 429 | |
7617 public void bngla(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7618 int instruction = 0x40810003; | |
7619 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7620 instruction |= ((crf.value() & 0x7) << 18); | |
7621 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7622 instruction |= ((prediction.value() & 0x3) << 21); | |
7623 emitInt(instruction); | |
7624 } | |
7625 | |
7626 /** | |
7627 * Pseudo-external assembler syntax: {@code bso{++|--} }<i>crf</i>, <i>bd</i> | |
7628 * Example disassembly syntax: {@code bso cr0, L1: -32768} | |
7629 * <p> | |
7630 * This is a synthetic instruction equivalent to: {@code bc(CRTrue | prediction, 3 | (crf * 4), bd)} | |
7631 * <p> | |
7632 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7633 * | |
7634 * @see #bc(BOOperand, int, int) | |
7635 * | |
7636 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7637 */ | |
7638 // Template#: 430, Serial#: 430 | |
7639 public void bso(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7640 int instruction = 0x41830000; | |
7641 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7642 instruction |= ((crf.value() & 0x7) << 18); | |
7643 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7644 instruction |= ((prediction.value() & 0x3) << 21); | |
7645 emitInt(instruction); | |
7646 } | |
7647 | |
7648 /** | |
7649 * Pseudo-external assembler syntax: {@code bsoa{++|--} }<i>crf</i>, <i>bd</i> | |
7650 * Example disassembly syntax: {@code bsoa cr0, L1: -32768} | |
7651 * <p> | |
7652 * This is a synthetic instruction equivalent to: {@code bca(CRTrue | prediction, 3 | (crf * 4), bd)} | |
7653 * <p> | |
7654 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7655 * | |
7656 * @see #bca(BOOperand, int, int) | |
7657 * | |
7658 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7659 */ | |
7660 // Template#: 431, Serial#: 431 | |
7661 public void bsoa(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7662 int instruction = 0x41830002; | |
7663 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7664 instruction |= ((crf.value() & 0x7) << 18); | |
7665 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7666 instruction |= ((prediction.value() & 0x3) << 21); | |
7667 emitInt(instruction); | |
7668 } | |
7669 | |
7670 /** | |
7671 * Pseudo-external assembler syntax: {@code bsol{++|--} }<i>crf</i>, <i>bd</i> | |
7672 * Example disassembly syntax: {@code bsol cr0, L1: -32768} | |
7673 * <p> | |
7674 * This is a synthetic instruction equivalent to: {@code bcl(CRTrue | prediction, 3 | (crf * 4), bd)} | |
7675 * <p> | |
7676 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7677 * | |
7678 * @see #bcl(BOOperand, int, int) | |
7679 * | |
7680 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7681 */ | |
7682 // Template#: 432, Serial#: 432 | |
7683 public void bsol(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7684 int instruction = 0x41830001; | |
7685 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7686 instruction |= ((crf.value() & 0x7) << 18); | |
7687 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7688 instruction |= ((prediction.value() & 0x3) << 21); | |
7689 emitInt(instruction); | |
7690 } | |
7691 | |
7692 /** | |
7693 * Pseudo-external assembler syntax: {@code bsola{++|--} }<i>crf</i>, <i>bd</i> | |
7694 * Example disassembly syntax: {@code bsola cr0, L1: -32768} | |
7695 * <p> | |
7696 * This is a synthetic instruction equivalent to: {@code bcla(CRTrue | prediction, 3 | (crf * 4), bd)} | |
7697 * <p> | |
7698 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7699 * | |
7700 * @see #bcla(BOOperand, int, int) | |
7701 * | |
7702 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7703 */ | |
7704 // Template#: 433, Serial#: 433 | |
7705 public void bsola(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7706 int instruction = 0x41830003; | |
7707 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7708 instruction |= ((crf.value() & 0x7) << 18); | |
7709 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7710 instruction |= ((prediction.value() & 0x3) << 21); | |
7711 emitInt(instruction); | |
7712 } | |
7713 | |
7714 /** | |
7715 * Pseudo-external assembler syntax: {@code bns{++|--} }<i>crf</i>, <i>bd</i> | |
7716 * Example disassembly syntax: {@code bns cr0, L1: -32768} | |
7717 * <p> | |
7718 * This is a synthetic instruction equivalent to: {@code bc(CRFalse | prediction, 3 | (crf * 4), bd)} | |
7719 * <p> | |
7720 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7721 * | |
7722 * @see #bc(BOOperand, int, int) | |
7723 * | |
7724 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7725 */ | |
7726 // Template#: 434, Serial#: 434 | |
7727 public void bns(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7728 int instruction = 0x40830000; | |
7729 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7730 instruction |= ((crf.value() & 0x7) << 18); | |
7731 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7732 instruction |= ((prediction.value() & 0x3) << 21); | |
7733 emitInt(instruction); | |
7734 } | |
7735 | |
7736 /** | |
7737 * Pseudo-external assembler syntax: {@code bnsa{++|--} }<i>crf</i>, <i>bd</i> | |
7738 * Example disassembly syntax: {@code bnsa cr0, L1: -32768} | |
7739 * <p> | |
7740 * This is a synthetic instruction equivalent to: {@code bca(CRFalse | prediction, 3 | (crf * 4), bd)} | |
7741 * <p> | |
7742 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7743 * | |
7744 * @see #bca(BOOperand, int, int) | |
7745 * | |
7746 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7747 */ | |
7748 // Template#: 435, Serial#: 435 | |
7749 public void bnsa(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7750 int instruction = 0x40830002; | |
7751 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7752 instruction |= ((crf.value() & 0x7) << 18); | |
7753 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7754 instruction |= ((prediction.value() & 0x3) << 21); | |
7755 emitInt(instruction); | |
7756 } | |
7757 | |
7758 /** | |
7759 * Pseudo-external assembler syntax: {@code bnsl{++|--} }<i>crf</i>, <i>bd</i> | |
7760 * Example disassembly syntax: {@code bnsl cr0, L1: -32768} | |
7761 * <p> | |
7762 * This is a synthetic instruction equivalent to: {@code bcl(CRFalse | prediction, 3 | (crf * 4), bd)} | |
7763 * <p> | |
7764 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7765 * | |
7766 * @see #bcl(BOOperand, int, int) | |
7767 * | |
7768 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7769 */ | |
7770 // Template#: 436, Serial#: 436 | |
7771 public void bnsl(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7772 int instruction = 0x40830001; | |
7773 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7774 instruction |= ((crf.value() & 0x7) << 18); | |
7775 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7776 instruction |= ((prediction.value() & 0x3) << 21); | |
7777 emitInt(instruction); | |
7778 } | |
7779 | |
7780 /** | |
7781 * Pseudo-external assembler syntax: {@code bnsla{++|--} }<i>crf</i>, <i>bd</i> | |
7782 * Example disassembly syntax: {@code bnsla cr0, L1: -32768} | |
7783 * <p> | |
7784 * This is a synthetic instruction equivalent to: {@code bcla(CRFalse | prediction, 3 | (crf * 4), bd)} | |
7785 * <p> | |
7786 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7787 * | |
7788 * @see #bcla(BOOperand, int, int) | |
7789 * | |
7790 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7791 */ | |
7792 // Template#: 437, Serial#: 437 | |
7793 public void bnsla(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7794 int instruction = 0x40830003; | |
7795 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7796 instruction |= ((crf.value() & 0x7) << 18); | |
7797 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7798 instruction |= ((prediction.value() & 0x3) << 21); | |
7799 emitInt(instruction); | |
7800 } | |
7801 | |
7802 /** | |
7803 * Pseudo-external assembler syntax: {@code bun{++|--} }<i>crf</i>, <i>bd</i> | |
7804 * Example disassembly syntax: {@code bun cr0, L1: -32768} | |
7805 * <p> | |
7806 * This is a synthetic instruction equivalent to: {@code bc(CRTrue | prediction, 3 | (crf * 4), bd)} | |
7807 * <p> | |
7808 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7809 * | |
7810 * @see #bc(BOOperand, int, int) | |
7811 * | |
7812 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7813 */ | |
7814 // Template#: 438, Serial#: 438 | |
7815 public void bun(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7816 int instruction = 0x41830000; | |
7817 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7818 instruction |= ((crf.value() & 0x7) << 18); | |
7819 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7820 instruction |= ((prediction.value() & 0x3) << 21); | |
7821 emitInt(instruction); | |
7822 } | |
7823 | |
7824 /** | |
7825 * Pseudo-external assembler syntax: {@code buna{++|--} }<i>crf</i>, <i>bd</i> | |
7826 * Example disassembly syntax: {@code buna cr0, L1: -32768} | |
7827 * <p> | |
7828 * This is a synthetic instruction equivalent to: {@code bca(CRTrue | prediction, 3 | (crf * 4), bd)} | |
7829 * <p> | |
7830 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7831 * | |
7832 * @see #bca(BOOperand, int, int) | |
7833 * | |
7834 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7835 */ | |
7836 // Template#: 439, Serial#: 439 | |
7837 public void buna(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7838 int instruction = 0x41830002; | |
7839 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7840 instruction |= ((crf.value() & 0x7) << 18); | |
7841 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7842 instruction |= ((prediction.value() & 0x3) << 21); | |
7843 emitInt(instruction); | |
7844 } | |
7845 | |
7846 /** | |
7847 * Pseudo-external assembler syntax: {@code bunl{++|--} }<i>crf</i>, <i>bd</i> | |
7848 * Example disassembly syntax: {@code bunl cr0, L1: -32768} | |
7849 * <p> | |
7850 * This is a synthetic instruction equivalent to: {@code bcl(CRTrue | prediction, 3 | (crf * 4), bd)} | |
7851 * <p> | |
7852 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7853 * | |
7854 * @see #bcl(BOOperand, int, int) | |
7855 * | |
7856 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7857 */ | |
7858 // Template#: 440, Serial#: 440 | |
7859 public void bunl(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7860 int instruction = 0x41830001; | |
7861 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7862 instruction |= ((crf.value() & 0x7) << 18); | |
7863 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7864 instruction |= ((prediction.value() & 0x3) << 21); | |
7865 emitInt(instruction); | |
7866 } | |
7867 | |
7868 /** | |
7869 * Pseudo-external assembler syntax: {@code bunla{++|--} }<i>crf</i>, <i>bd</i> | |
7870 * Example disassembly syntax: {@code bunla cr0, L1: -32768} | |
7871 * <p> | |
7872 * This is a synthetic instruction equivalent to: {@code bcla(CRTrue | prediction, 3 | (crf * 4), bd)} | |
7873 * <p> | |
7874 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7875 * | |
7876 * @see #bcla(BOOperand, int, int) | |
7877 * | |
7878 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7879 */ | |
7880 // Template#: 441, Serial#: 441 | |
7881 public void bunla(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7882 int instruction = 0x41830003; | |
7883 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7884 instruction |= ((crf.value() & 0x7) << 18); | |
7885 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7886 instruction |= ((prediction.value() & 0x3) << 21); | |
7887 emitInt(instruction); | |
7888 } | |
7889 | |
7890 /** | |
7891 * Pseudo-external assembler syntax: {@code bnu{++|--} }<i>crf</i>, <i>bd</i> | |
7892 * Example disassembly syntax: {@code bnu cr0, L1: -32768} | |
7893 * <p> | |
7894 * This is a synthetic instruction equivalent to: {@code bc(CRFalse | prediction, 3 | (crf * 4), bd)} | |
7895 * <p> | |
7896 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7897 * | |
7898 * @see #bc(BOOperand, int, int) | |
7899 * | |
7900 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7901 */ | |
7902 // Template#: 442, Serial#: 442 | |
7903 public void bnu(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7904 int instruction = 0x40830000; | |
7905 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7906 instruction |= ((crf.value() & 0x7) << 18); | |
7907 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7908 instruction |= ((prediction.value() & 0x3) << 21); | |
7909 emitInt(instruction); | |
7910 } | |
7911 | |
7912 /** | |
7913 * Pseudo-external assembler syntax: {@code bnua{++|--} }<i>crf</i>, <i>bd</i> | |
7914 * Example disassembly syntax: {@code bnua cr0, L1: -32768} | |
7915 * <p> | |
7916 * This is a synthetic instruction equivalent to: {@code bca(CRFalse | prediction, 3 | (crf * 4), bd)} | |
7917 * <p> | |
7918 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7919 * | |
7920 * @see #bca(BOOperand, int, int) | |
7921 * | |
7922 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7923 */ | |
7924 // Template#: 443, Serial#: 443 | |
7925 public void bnua(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7926 int instruction = 0x40830002; | |
7927 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7928 instruction |= ((crf.value() & 0x7) << 18); | |
7929 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7930 instruction |= ((prediction.value() & 0x3) << 21); | |
7931 emitInt(instruction); | |
7932 } | |
7933 | |
7934 /** | |
7935 * Pseudo-external assembler syntax: {@code bnul{++|--} }<i>crf</i>, <i>bd</i> | |
7936 * Example disassembly syntax: {@code bnul cr0, L1: -32768} | |
7937 * <p> | |
7938 * This is a synthetic instruction equivalent to: {@code bcl(CRFalse | prediction, 3 | (crf * 4), bd)} | |
7939 * <p> | |
7940 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7941 * | |
7942 * @see #bcl(BOOperand, int, int) | |
7943 * | |
7944 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7945 */ | |
7946 // Template#: 444, Serial#: 444 | |
7947 public void bnul(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7948 int instruction = 0x40830001; | |
7949 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7950 instruction |= ((crf.value() & 0x7) << 18); | |
7951 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7952 instruction |= ((prediction.value() & 0x3) << 21); | |
7953 emitInt(instruction); | |
7954 } | |
7955 | |
7956 /** | |
7957 * Pseudo-external assembler syntax: {@code bnula{++|--} }<i>crf</i>, <i>bd</i> | |
7958 * Example disassembly syntax: {@code bnula cr0, L1: -32768} | |
7959 * <p> | |
7960 * This is a synthetic instruction equivalent to: {@code bcla(CRFalse | prediction, 3 | (crf * 4), bd)} | |
7961 * <p> | |
7962 * Constraint: {@code (-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)}<br /> | |
7963 * | |
7964 * @see #bcla(BOOperand, int, int) | |
7965 * | |
7966 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7967 */ | |
7968 // Template#: 445, Serial#: 445 | |
7969 public void bnula(final CRF crf, final int bd, final BranchPredictionBits prediction) { | |
7970 int instruction = 0x40830003; | |
7971 checkConstraint((-32768 <= bd && bd <= 32764) && ((bd % 4) == 0), "(-32768 <= bd && bd <= 32764) && ((bd % 4) == 0)"); | |
7972 instruction |= ((crf.value() & 0x7) << 18); | |
7973 instruction |= (((bd >> 2) & 0x3fff) << 2); | |
7974 instruction |= ((prediction.value() & 0x3) << 21); | |
7975 emitInt(instruction); | |
7976 } | |
7977 | |
7978 /** | |
7979 * Pseudo-external assembler syntax: {@code bltlr{++|--} }<i>crf</i> | |
7980 * Example disassembly syntax: {@code bltlr cr0} | |
7981 * <p> | |
7982 * This is a synthetic instruction equivalent to: {@code bclr(CRTrue | prediction, (crf * 4), 0)} | |
7983 * | |
7984 * @see #bclr(BOOperand, int, int) | |
7985 * | |
7986 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
7987 */ | |
7988 // Template#: 446, Serial#: 446 | |
7989 public void bltlr(final CRF crf, final BranchPredictionBits prediction) { | |
7990 int instruction = 0x4D800020; | |
7991 instruction |= ((crf.value() & 0x7) << 18); | |
7992 instruction |= ((prediction.value() & 0x3) << 21); | |
7993 emitInt(instruction); | |
7994 } | |
7995 | |
7996 /** | |
7997 * Pseudo-external assembler syntax: {@code bltlrl{++|--} }<i>crf</i> | |
7998 * Example disassembly syntax: {@code bltlrl cr0} | |
7999 * <p> | |
8000 * This is a synthetic instruction equivalent to: {@code bclrl(CRTrue | prediction, (crf * 4), 0)} | |
8001 * | |
8002 * @see #bclrl(BOOperand, int, int) | |
8003 * | |
8004 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8005 */ | |
8006 // Template#: 447, Serial#: 447 | |
8007 public void bltlrl(final CRF crf, final BranchPredictionBits prediction) { | |
8008 int instruction = 0x4D800021; | |
8009 instruction |= ((crf.value() & 0x7) << 18); | |
8010 instruction |= ((prediction.value() & 0x3) << 21); | |
8011 emitInt(instruction); | |
8012 } | |
8013 | |
8014 /** | |
8015 * Pseudo-external assembler syntax: {@code blelr{++|--} }<i>crf</i> | |
8016 * Example disassembly syntax: {@code blelr cr0} | |
8017 * <p> | |
8018 * This is a synthetic instruction equivalent to: {@code bclr(CRFalse | prediction, 1 | (crf * 4), 0)} | |
8019 * | |
8020 * @see #bclr(BOOperand, int, int) | |
8021 * | |
8022 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8023 */ | |
8024 // Template#: 448, Serial#: 448 | |
8025 public void blelr(final CRF crf, final BranchPredictionBits prediction) { | |
8026 int instruction = 0x4C810020; | |
8027 instruction |= ((crf.value() & 0x7) << 18); | |
8028 instruction |= ((prediction.value() & 0x3) << 21); | |
8029 emitInt(instruction); | |
8030 } | |
8031 | |
8032 /** | |
8033 * Pseudo-external assembler syntax: {@code blelrl{++|--} }<i>crf</i> | |
8034 * Example disassembly syntax: {@code blelrl cr0} | |
8035 * <p> | |
8036 * This is a synthetic instruction equivalent to: {@code bclrl(CRFalse | prediction, 1 | (crf * 4), 0)} | |
8037 * | |
8038 * @see #bclrl(BOOperand, int, int) | |
8039 * | |
8040 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8041 */ | |
8042 // Template#: 449, Serial#: 449 | |
8043 public void blelrl(final CRF crf, final BranchPredictionBits prediction) { | |
8044 int instruction = 0x4C810021; | |
8045 instruction |= ((crf.value() & 0x7) << 18); | |
8046 instruction |= ((prediction.value() & 0x3) << 21); | |
8047 emitInt(instruction); | |
8048 } | |
8049 | |
8050 /** | |
8051 * Pseudo-external assembler syntax: {@code beqlr{++|--} }<i>crf</i> | |
8052 * Example disassembly syntax: {@code beqlr cr0} | |
8053 * <p> | |
8054 * This is a synthetic instruction equivalent to: {@code bclr(CRTrue | prediction, 2 | (crf * 4), 0)} | |
8055 * | |
8056 * @see #bclr(BOOperand, int, int) | |
8057 * | |
8058 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8059 */ | |
8060 // Template#: 450, Serial#: 450 | |
8061 public void beqlr(final CRF crf, final BranchPredictionBits prediction) { | |
8062 int instruction = 0x4D820020; | |
8063 instruction |= ((crf.value() & 0x7) << 18); | |
8064 instruction |= ((prediction.value() & 0x3) << 21); | |
8065 emitInt(instruction); | |
8066 } | |
8067 | |
8068 /** | |
8069 * Pseudo-external assembler syntax: {@code beqlrl{++|--} }<i>crf</i> | |
8070 * Example disassembly syntax: {@code beqlrl cr0} | |
8071 * <p> | |
8072 * This is a synthetic instruction equivalent to: {@code bclrl(CRTrue | prediction, 2 | (crf * 4), 0)} | |
8073 * | |
8074 * @see #bclrl(BOOperand, int, int) | |
8075 * | |
8076 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8077 */ | |
8078 // Template#: 451, Serial#: 451 | |
8079 public void beqlrl(final CRF crf, final BranchPredictionBits prediction) { | |
8080 int instruction = 0x4D820021; | |
8081 instruction |= ((crf.value() & 0x7) << 18); | |
8082 instruction |= ((prediction.value() & 0x3) << 21); | |
8083 emitInt(instruction); | |
8084 } | |
8085 | |
8086 /** | |
8087 * Pseudo-external assembler syntax: {@code bgelr{++|--} }<i>crf</i> | |
8088 * Example disassembly syntax: {@code bgelr cr0} | |
8089 * <p> | |
8090 * This is a synthetic instruction equivalent to: {@code bclr(CRFalse | prediction, (crf * 4), 0)} | |
8091 * | |
8092 * @see #bclr(BOOperand, int, int) | |
8093 * | |
8094 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8095 */ | |
8096 // Template#: 452, Serial#: 452 | |
8097 public void bgelr(final CRF crf, final BranchPredictionBits prediction) { | |
8098 int instruction = 0x4C800020; | |
8099 instruction |= ((crf.value() & 0x7) << 18); | |
8100 instruction |= ((prediction.value() & 0x3) << 21); | |
8101 emitInt(instruction); | |
8102 } | |
8103 | |
8104 /** | |
8105 * Pseudo-external assembler syntax: {@code bgelrl{++|--} }<i>crf</i> | |
8106 * Example disassembly syntax: {@code bgelrl cr0} | |
8107 * <p> | |
8108 * This is a synthetic instruction equivalent to: {@code bclrl(CRFalse | prediction, (crf * 4), 0)} | |
8109 * | |
8110 * @see #bclrl(BOOperand, int, int) | |
8111 * | |
8112 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8113 */ | |
8114 // Template#: 453, Serial#: 453 | |
8115 public void bgelrl(final CRF crf, final BranchPredictionBits prediction) { | |
8116 int instruction = 0x4C800021; | |
8117 instruction |= ((crf.value() & 0x7) << 18); | |
8118 instruction |= ((prediction.value() & 0x3) << 21); | |
8119 emitInt(instruction); | |
8120 } | |
8121 | |
8122 /** | |
8123 * Pseudo-external assembler syntax: {@code bgtlr{++|--} }<i>crf</i> | |
8124 * Example disassembly syntax: {@code bgtlr cr0} | |
8125 * <p> | |
8126 * This is a synthetic instruction equivalent to: {@code bclr(CRTrue | prediction, 1 | (crf * 4), 0)} | |
8127 * | |
8128 * @see #bclr(BOOperand, int, int) | |
8129 * | |
8130 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8131 */ | |
8132 // Template#: 454, Serial#: 454 | |
8133 public void bgtlr(final CRF crf, final BranchPredictionBits prediction) { | |
8134 int instruction = 0x4D810020; | |
8135 instruction |= ((crf.value() & 0x7) << 18); | |
8136 instruction |= ((prediction.value() & 0x3) << 21); | |
8137 emitInt(instruction); | |
8138 } | |
8139 | |
8140 /** | |
8141 * Pseudo-external assembler syntax: {@code bgtlrl{++|--} }<i>crf</i> | |
8142 * Example disassembly syntax: {@code bgtlrl cr0} | |
8143 * <p> | |
8144 * This is a synthetic instruction equivalent to: {@code bclrl(CRTrue | prediction, 1 | (crf * 4), 0)} | |
8145 * | |
8146 * @see #bclrl(BOOperand, int, int) | |
8147 * | |
8148 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8149 */ | |
8150 // Template#: 455, Serial#: 455 | |
8151 public void bgtlrl(final CRF crf, final BranchPredictionBits prediction) { | |
8152 int instruction = 0x4D810021; | |
8153 instruction |= ((crf.value() & 0x7) << 18); | |
8154 instruction |= ((prediction.value() & 0x3) << 21); | |
8155 emitInt(instruction); | |
8156 } | |
8157 | |
8158 /** | |
8159 * Pseudo-external assembler syntax: {@code bnllr{++|--} }<i>crf</i> | |
8160 * Example disassembly syntax: {@code bnllr cr0} | |
8161 * <p> | |
8162 * This is a synthetic instruction equivalent to: {@code bclr(CRFalse | prediction, (crf * 4), 0)} | |
8163 * | |
8164 * @see #bclr(BOOperand, int, int) | |
8165 * | |
8166 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8167 */ | |
8168 // Template#: 456, Serial#: 456 | |
8169 public void bnllr(final CRF crf, final BranchPredictionBits prediction) { | |
8170 int instruction = 0x4C800020; | |
8171 instruction |= ((crf.value() & 0x7) << 18); | |
8172 instruction |= ((prediction.value() & 0x3) << 21); | |
8173 emitInt(instruction); | |
8174 } | |
8175 | |
8176 /** | |
8177 * Pseudo-external assembler syntax: {@code bnllrl{++|--} }<i>crf</i> | |
8178 * Example disassembly syntax: {@code bnllrl cr0} | |
8179 * <p> | |
8180 * This is a synthetic instruction equivalent to: {@code bclrl(CRFalse | prediction, (crf * 4), 0)} | |
8181 * | |
8182 * @see #bclrl(BOOperand, int, int) | |
8183 * | |
8184 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8185 */ | |
8186 // Template#: 457, Serial#: 457 | |
8187 public void bnllrl(final CRF crf, final BranchPredictionBits prediction) { | |
8188 int instruction = 0x4C800021; | |
8189 instruction |= ((crf.value() & 0x7) << 18); | |
8190 instruction |= ((prediction.value() & 0x3) << 21); | |
8191 emitInt(instruction); | |
8192 } | |
8193 | |
8194 /** | |
8195 * Pseudo-external assembler syntax: {@code bnelr{++|--} }<i>crf</i> | |
8196 * Example disassembly syntax: {@code bnelr cr0} | |
8197 * <p> | |
8198 * This is a synthetic instruction equivalent to: {@code bclr(CRFalse | prediction, 2 | (crf * 4), 0)} | |
8199 * | |
8200 * @see #bclr(BOOperand, int, int) | |
8201 * | |
8202 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8203 */ | |
8204 // Template#: 458, Serial#: 458 | |
8205 public void bnelr(final CRF crf, final BranchPredictionBits prediction) { | |
8206 int instruction = 0x4C820020; | |
8207 instruction |= ((crf.value() & 0x7) << 18); | |
8208 instruction |= ((prediction.value() & 0x3) << 21); | |
8209 emitInt(instruction); | |
8210 } | |
8211 | |
8212 /** | |
8213 * Pseudo-external assembler syntax: {@code bnelrl{++|--} }<i>crf</i> | |
8214 * Example disassembly syntax: {@code bnelrl cr0} | |
8215 * <p> | |
8216 * This is a synthetic instruction equivalent to: {@code bclrl(CRFalse | prediction, 2 | (crf * 4), 0)} | |
8217 * | |
8218 * @see #bclrl(BOOperand, int, int) | |
8219 * | |
8220 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8221 */ | |
8222 // Template#: 459, Serial#: 459 | |
8223 public void bnelrl(final CRF crf, final BranchPredictionBits prediction) { | |
8224 int instruction = 0x4C820021; | |
8225 instruction |= ((crf.value() & 0x7) << 18); | |
8226 instruction |= ((prediction.value() & 0x3) << 21); | |
8227 emitInt(instruction); | |
8228 } | |
8229 | |
8230 /** | |
8231 * Pseudo-external assembler syntax: {@code bnglr{++|--} }<i>crf</i> | |
8232 * Example disassembly syntax: {@code bnglr cr0} | |
8233 * <p> | |
8234 * This is a synthetic instruction equivalent to: {@code bclr(CRFalse | prediction, 1 | (crf * 4), 0)} | |
8235 * | |
8236 * @see #bclr(BOOperand, int, int) | |
8237 * | |
8238 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8239 */ | |
8240 // Template#: 460, Serial#: 460 | |
8241 public void bnglr(final CRF crf, final BranchPredictionBits prediction) { | |
8242 int instruction = 0x4C810020; | |
8243 instruction |= ((crf.value() & 0x7) << 18); | |
8244 instruction |= ((prediction.value() & 0x3) << 21); | |
8245 emitInt(instruction); | |
8246 } | |
8247 | |
8248 /** | |
8249 * Pseudo-external assembler syntax: {@code bnglrl{++|--} }<i>crf</i> | |
8250 * Example disassembly syntax: {@code bnglrl cr0} | |
8251 * <p> | |
8252 * This is a synthetic instruction equivalent to: {@code bclrl(CRFalse | prediction, 1 | (crf * 4), 0)} | |
8253 * | |
8254 * @see #bclrl(BOOperand, int, int) | |
8255 * | |
8256 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8257 */ | |
8258 // Template#: 461, Serial#: 461 | |
8259 public void bnglrl(final CRF crf, final BranchPredictionBits prediction) { | |
8260 int instruction = 0x4C810021; | |
8261 instruction |= ((crf.value() & 0x7) << 18); | |
8262 instruction |= ((prediction.value() & 0x3) << 21); | |
8263 emitInt(instruction); | |
8264 } | |
8265 | |
8266 /** | |
8267 * Pseudo-external assembler syntax: {@code bsolr{++|--} }<i>crf</i> | |
8268 * Example disassembly syntax: {@code bsolr cr0} | |
8269 * <p> | |
8270 * This is a synthetic instruction equivalent to: {@code bclr(CRTrue | prediction, 3 | (crf * 4), 0)} | |
8271 * | |
8272 * @see #bclr(BOOperand, int, int) | |
8273 * | |
8274 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8275 */ | |
8276 // Template#: 462, Serial#: 462 | |
8277 public void bsolr(final CRF crf, final BranchPredictionBits prediction) { | |
8278 int instruction = 0x4D830020; | |
8279 instruction |= ((crf.value() & 0x7) << 18); | |
8280 instruction |= ((prediction.value() & 0x3) << 21); | |
8281 emitInt(instruction); | |
8282 } | |
8283 | |
8284 /** | |
8285 * Pseudo-external assembler syntax: {@code bsolrl{++|--} }<i>crf</i> | |
8286 * Example disassembly syntax: {@code bsolrl cr0} | |
8287 * <p> | |
8288 * This is a synthetic instruction equivalent to: {@code bclrl(CRTrue | prediction, 3 | (crf * 4), 0)} | |
8289 * | |
8290 * @see #bclrl(BOOperand, int, int) | |
8291 * | |
8292 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8293 */ | |
8294 // Template#: 463, Serial#: 463 | |
8295 public void bsolrl(final CRF crf, final BranchPredictionBits prediction) { | |
8296 int instruction = 0x4D830021; | |
8297 instruction |= ((crf.value() & 0x7) << 18); | |
8298 instruction |= ((prediction.value() & 0x3) << 21); | |
8299 emitInt(instruction); | |
8300 } | |
8301 | |
8302 /** | |
8303 * Pseudo-external assembler syntax: {@code bnslr{++|--} }<i>crf</i> | |
8304 * Example disassembly syntax: {@code bnslr cr0} | |
8305 * <p> | |
8306 * This is a synthetic instruction equivalent to: {@code bclr(CRFalse | prediction, 3 | (crf * 4), 0)} | |
8307 * | |
8308 * @see #bclr(BOOperand, int, int) | |
8309 * | |
8310 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8311 */ | |
8312 // Template#: 464, Serial#: 464 | |
8313 public void bnslr(final CRF crf, final BranchPredictionBits prediction) { | |
8314 int instruction = 0x4C830020; | |
8315 instruction |= ((crf.value() & 0x7) << 18); | |
8316 instruction |= ((prediction.value() & 0x3) << 21); | |
8317 emitInt(instruction); | |
8318 } | |
8319 | |
8320 /** | |
8321 * Pseudo-external assembler syntax: {@code bnslrl{++|--} }<i>crf</i> | |
8322 * Example disassembly syntax: {@code bnslrl cr0} | |
8323 * <p> | |
8324 * This is a synthetic instruction equivalent to: {@code bclrl(CRFalse | prediction, 3 | (crf * 4), 0)} | |
8325 * | |
8326 * @see #bclrl(BOOperand, int, int) | |
8327 * | |
8328 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8329 */ | |
8330 // Template#: 465, Serial#: 465 | |
8331 public void bnslrl(final CRF crf, final BranchPredictionBits prediction) { | |
8332 int instruction = 0x4C830021; | |
8333 instruction |= ((crf.value() & 0x7) << 18); | |
8334 instruction |= ((prediction.value() & 0x3) << 21); | |
8335 emitInt(instruction); | |
8336 } | |
8337 | |
8338 /** | |
8339 * Pseudo-external assembler syntax: {@code bunlr{++|--} }<i>crf</i> | |
8340 * Example disassembly syntax: {@code bunlr cr0} | |
8341 * <p> | |
8342 * This is a synthetic instruction equivalent to: {@code bclr(CRTrue | prediction, 3 | (crf * 4), 0)} | |
8343 * | |
8344 * @see #bclr(BOOperand, int, int) | |
8345 * | |
8346 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8347 */ | |
8348 // Template#: 466, Serial#: 466 | |
8349 public void bunlr(final CRF crf, final BranchPredictionBits prediction) { | |
8350 int instruction = 0x4D830020; | |
8351 instruction |= ((crf.value() & 0x7) << 18); | |
8352 instruction |= ((prediction.value() & 0x3) << 21); | |
8353 emitInt(instruction); | |
8354 } | |
8355 | |
8356 /** | |
8357 * Pseudo-external assembler syntax: {@code bunlrl{++|--} }<i>crf</i> | |
8358 * Example disassembly syntax: {@code bunlrl cr0} | |
8359 * <p> | |
8360 * This is a synthetic instruction equivalent to: {@code bclrl(CRTrue | prediction, 3 | (crf * 4), 0)} | |
8361 * | |
8362 * @see #bclrl(BOOperand, int, int) | |
8363 * | |
8364 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8365 */ | |
8366 // Template#: 467, Serial#: 467 | |
8367 public void bunlrl(final CRF crf, final BranchPredictionBits prediction) { | |
8368 int instruction = 0x4D830021; | |
8369 instruction |= ((crf.value() & 0x7) << 18); | |
8370 instruction |= ((prediction.value() & 0x3) << 21); | |
8371 emitInt(instruction); | |
8372 } | |
8373 | |
8374 /** | |
8375 * Pseudo-external assembler syntax: {@code bnulr{++|--} }<i>crf</i> | |
8376 * Example disassembly syntax: {@code bnulr cr0} | |
8377 * <p> | |
8378 * This is a synthetic instruction equivalent to: {@code bclr(CRFalse | prediction, 3 | (crf * 4), 0)} | |
8379 * | |
8380 * @see #bclr(BOOperand, int, int) | |
8381 * | |
8382 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8383 */ | |
8384 // Template#: 468, Serial#: 468 | |
8385 public void bnulr(final CRF crf, final BranchPredictionBits prediction) { | |
8386 int instruction = 0x4C830020; | |
8387 instruction |= ((crf.value() & 0x7) << 18); | |
8388 instruction |= ((prediction.value() & 0x3) << 21); | |
8389 emitInt(instruction); | |
8390 } | |
8391 | |
8392 /** | |
8393 * Pseudo-external assembler syntax: {@code bnulrl{++|--} }<i>crf</i> | |
8394 * Example disassembly syntax: {@code bnulrl cr0} | |
8395 * <p> | |
8396 * This is a synthetic instruction equivalent to: {@code bclrl(CRFalse | prediction, 3 | (crf * 4), 0)} | |
8397 * | |
8398 * @see #bclrl(BOOperand, int, int) | |
8399 * | |
8400 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8401 */ | |
8402 // Template#: 469, Serial#: 469 | |
8403 public void bnulrl(final CRF crf, final BranchPredictionBits prediction) { | |
8404 int instruction = 0x4C830021; | |
8405 instruction |= ((crf.value() & 0x7) << 18); | |
8406 instruction |= ((prediction.value() & 0x3) << 21); | |
8407 emitInt(instruction); | |
8408 } | |
8409 | |
8410 /** | |
8411 * Pseudo-external assembler syntax: {@code bltctr{++|--} }<i>crf</i> | |
8412 * Example disassembly syntax: {@code bltctr cr0} | |
8413 * <p> | |
8414 * This is a synthetic instruction equivalent to: {@code bcctr(CRTrue | prediction, (crf * 4), 0)} | |
8415 * | |
8416 * @see #bcctr(BOOperand, int, int) | |
8417 * | |
8418 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8419 */ | |
8420 // Template#: 470, Serial#: 470 | |
8421 public void bltctr(final CRF crf, final BranchPredictionBits prediction) { | |
8422 int instruction = 0x4D800420; | |
8423 instruction |= ((crf.value() & 0x7) << 18); | |
8424 instruction |= ((prediction.value() & 0x3) << 21); | |
8425 emitInt(instruction); | |
8426 } | |
8427 | |
8428 /** | |
8429 * Pseudo-external assembler syntax: {@code bltctrl{++|--} }<i>crf</i> | |
8430 * Example disassembly syntax: {@code bltctrl cr0} | |
8431 * <p> | |
8432 * This is a synthetic instruction equivalent to: {@code bcctrl(CRTrue | prediction, (crf * 4), 0)} | |
8433 * | |
8434 * @see #bcctrl(BOOperand, int, int) | |
8435 * | |
8436 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8437 */ | |
8438 // Template#: 471, Serial#: 471 | |
8439 public void bltctrl(final CRF crf, final BranchPredictionBits prediction) { | |
8440 int instruction = 0x4D800421; | |
8441 instruction |= ((crf.value() & 0x7) << 18); | |
8442 instruction |= ((prediction.value() & 0x3) << 21); | |
8443 emitInt(instruction); | |
8444 } | |
8445 | |
8446 /** | |
8447 * Pseudo-external assembler syntax: {@code blectr{++|--} }<i>crf</i> | |
8448 * Example disassembly syntax: {@code blectr cr0} | |
8449 * <p> | |
8450 * This is a synthetic instruction equivalent to: {@code bcctr(CRFalse | prediction, 1 | (crf * 4), 0)} | |
8451 * | |
8452 * @see #bcctr(BOOperand, int, int) | |
8453 * | |
8454 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8455 */ | |
8456 // Template#: 472, Serial#: 472 | |
8457 public void blectr(final CRF crf, final BranchPredictionBits prediction) { | |
8458 int instruction = 0x4C810420; | |
8459 instruction |= ((crf.value() & 0x7) << 18); | |
8460 instruction |= ((prediction.value() & 0x3) << 21); | |
8461 emitInt(instruction); | |
8462 } | |
8463 | |
8464 /** | |
8465 * Pseudo-external assembler syntax: {@code blectrl{++|--} }<i>crf</i> | |
8466 * Example disassembly syntax: {@code blectrl cr0} | |
8467 * <p> | |
8468 * This is a synthetic instruction equivalent to: {@code bcctrl(CRFalse | prediction, 1 | (crf * 4), 0)} | |
8469 * | |
8470 * @see #bcctrl(BOOperand, int, int) | |
8471 * | |
8472 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8473 */ | |
8474 // Template#: 473, Serial#: 473 | |
8475 public void blectrl(final CRF crf, final BranchPredictionBits prediction) { | |
8476 int instruction = 0x4C810421; | |
8477 instruction |= ((crf.value() & 0x7) << 18); | |
8478 instruction |= ((prediction.value() & 0x3) << 21); | |
8479 emitInt(instruction); | |
8480 } | |
8481 | |
8482 /** | |
8483 * Pseudo-external assembler syntax: {@code beqctr{++|--} }<i>crf</i> | |
8484 * Example disassembly syntax: {@code beqctr cr0} | |
8485 * <p> | |
8486 * This is a synthetic instruction equivalent to: {@code bcctr(CRTrue | prediction, 2 | (crf * 4), 0)} | |
8487 * | |
8488 * @see #bcctr(BOOperand, int, int) | |
8489 * | |
8490 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8491 */ | |
8492 // Template#: 474, Serial#: 474 | |
8493 public void beqctr(final CRF crf, final BranchPredictionBits prediction) { | |
8494 int instruction = 0x4D820420; | |
8495 instruction |= ((crf.value() & 0x7) << 18); | |
8496 instruction |= ((prediction.value() & 0x3) << 21); | |
8497 emitInt(instruction); | |
8498 } | |
8499 | |
8500 /** | |
8501 * Pseudo-external assembler syntax: {@code beqctrl{++|--} }<i>crf</i> | |
8502 * Example disassembly syntax: {@code beqctrl cr0} | |
8503 * <p> | |
8504 * This is a synthetic instruction equivalent to: {@code bcctrl(CRTrue | prediction, 2 | (crf * 4), 0)} | |
8505 * | |
8506 * @see #bcctrl(BOOperand, int, int) | |
8507 * | |
8508 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8509 */ | |
8510 // Template#: 475, Serial#: 475 | |
8511 public void beqctrl(final CRF crf, final BranchPredictionBits prediction) { | |
8512 int instruction = 0x4D820421; | |
8513 instruction |= ((crf.value() & 0x7) << 18); | |
8514 instruction |= ((prediction.value() & 0x3) << 21); | |
8515 emitInt(instruction); | |
8516 } | |
8517 | |
8518 /** | |
8519 * Pseudo-external assembler syntax: {@code bgectr{++|--} }<i>crf</i> | |
8520 * Example disassembly syntax: {@code bgectr cr0} | |
8521 * <p> | |
8522 * This is a synthetic instruction equivalent to: {@code bcctr(CRFalse | prediction, (crf * 4), 0)} | |
8523 * | |
8524 * @see #bcctr(BOOperand, int, int) | |
8525 * | |
8526 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8527 */ | |
8528 // Template#: 476, Serial#: 476 | |
8529 public void bgectr(final CRF crf, final BranchPredictionBits prediction) { | |
8530 int instruction = 0x4C800420; | |
8531 instruction |= ((crf.value() & 0x7) << 18); | |
8532 instruction |= ((prediction.value() & 0x3) << 21); | |
8533 emitInt(instruction); | |
8534 } | |
8535 | |
8536 /** | |
8537 * Pseudo-external assembler syntax: {@code bgectrl{++|--} }<i>crf</i> | |
8538 * Example disassembly syntax: {@code bgectrl cr0} | |
8539 * <p> | |
8540 * This is a synthetic instruction equivalent to: {@code bcctrl(CRFalse | prediction, (crf * 4), 0)} | |
8541 * | |
8542 * @see #bcctrl(BOOperand, int, int) | |
8543 * | |
8544 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8545 */ | |
8546 // Template#: 477, Serial#: 477 | |
8547 public void bgectrl(final CRF crf, final BranchPredictionBits prediction) { | |
8548 int instruction = 0x4C800421; | |
8549 instruction |= ((crf.value() & 0x7) << 18); | |
8550 instruction |= ((prediction.value() & 0x3) << 21); | |
8551 emitInt(instruction); | |
8552 } | |
8553 | |
8554 /** | |
8555 * Pseudo-external assembler syntax: {@code bgtctr{++|--} }<i>crf</i> | |
8556 * Example disassembly syntax: {@code bgtctr cr0} | |
8557 * <p> | |
8558 * This is a synthetic instruction equivalent to: {@code bcctr(CRTrue | prediction, 1 | (crf * 4), 0)} | |
8559 * | |
8560 * @see #bcctr(BOOperand, int, int) | |
8561 * | |
8562 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8563 */ | |
8564 // Template#: 478, Serial#: 478 | |
8565 public void bgtctr(final CRF crf, final BranchPredictionBits prediction) { | |
8566 int instruction = 0x4D810420; | |
8567 instruction |= ((crf.value() & 0x7) << 18); | |
8568 instruction |= ((prediction.value() & 0x3) << 21); | |
8569 emitInt(instruction); | |
8570 } | |
8571 | |
8572 /** | |
8573 * Pseudo-external assembler syntax: {@code bgtctrl{++|--} }<i>crf</i> | |
8574 * Example disassembly syntax: {@code bgtctrl cr0} | |
8575 * <p> | |
8576 * This is a synthetic instruction equivalent to: {@code bcctrl(CRTrue | prediction, 1 | (crf * 4), 0)} | |
8577 * | |
8578 * @see #bcctrl(BOOperand, int, int) | |
8579 * | |
8580 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8581 */ | |
8582 // Template#: 479, Serial#: 479 | |
8583 public void bgtctrl(final CRF crf, final BranchPredictionBits prediction) { | |
8584 int instruction = 0x4D810421; | |
8585 instruction |= ((crf.value() & 0x7) << 18); | |
8586 instruction |= ((prediction.value() & 0x3) << 21); | |
8587 emitInt(instruction); | |
8588 } | |
8589 | |
8590 /** | |
8591 * Pseudo-external assembler syntax: {@code bnlctr{++|--} }<i>crf</i> | |
8592 * Example disassembly syntax: {@code bnlctr cr0} | |
8593 * <p> | |
8594 * This is a synthetic instruction equivalent to: {@code bcctr(CRFalse | prediction, (crf * 4), 0)} | |
8595 * | |
8596 * @see #bcctr(BOOperand, int, int) | |
8597 * | |
8598 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8599 */ | |
8600 // Template#: 480, Serial#: 480 | |
8601 public void bnlctr(final CRF crf, final BranchPredictionBits prediction) { | |
8602 int instruction = 0x4C800420; | |
8603 instruction |= ((crf.value() & 0x7) << 18); | |
8604 instruction |= ((prediction.value() & 0x3) << 21); | |
8605 emitInt(instruction); | |
8606 } | |
8607 | |
8608 /** | |
8609 * Pseudo-external assembler syntax: {@code bnlctrl{++|--} }<i>crf</i> | |
8610 * Example disassembly syntax: {@code bnlctrl cr0} | |
8611 * <p> | |
8612 * This is a synthetic instruction equivalent to: {@code bcctrl(CRFalse | prediction, (crf * 4), 0)} | |
8613 * | |
8614 * @see #bcctrl(BOOperand, int, int) | |
8615 * | |
8616 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8617 */ | |
8618 // Template#: 481, Serial#: 481 | |
8619 public void bnlctrl(final CRF crf, final BranchPredictionBits prediction) { | |
8620 int instruction = 0x4C800421; | |
8621 instruction |= ((crf.value() & 0x7) << 18); | |
8622 instruction |= ((prediction.value() & 0x3) << 21); | |
8623 emitInt(instruction); | |
8624 } | |
8625 | |
8626 /** | |
8627 * Pseudo-external assembler syntax: {@code bnectr{++|--} }<i>crf</i> | |
8628 * Example disassembly syntax: {@code bnectr cr0} | |
8629 * <p> | |
8630 * This is a synthetic instruction equivalent to: {@code bcctr(CRFalse | prediction, 2 | (crf * 4), 0)} | |
8631 * | |
8632 * @see #bcctr(BOOperand, int, int) | |
8633 * | |
8634 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8635 */ | |
8636 // Template#: 482, Serial#: 482 | |
8637 public void bnectr(final CRF crf, final BranchPredictionBits prediction) { | |
8638 int instruction = 0x4C820420; | |
8639 instruction |= ((crf.value() & 0x7) << 18); | |
8640 instruction |= ((prediction.value() & 0x3) << 21); | |
8641 emitInt(instruction); | |
8642 } | |
8643 | |
8644 /** | |
8645 * Pseudo-external assembler syntax: {@code bnectrl{++|--} }<i>crf</i> | |
8646 * Example disassembly syntax: {@code bnectrl cr0} | |
8647 * <p> | |
8648 * This is a synthetic instruction equivalent to: {@code bcctrl(CRFalse | prediction, 2 | (crf * 4), 0)} | |
8649 * | |
8650 * @see #bcctrl(BOOperand, int, int) | |
8651 * | |
8652 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8653 */ | |
8654 // Template#: 483, Serial#: 483 | |
8655 public void bnectrl(final CRF crf, final BranchPredictionBits prediction) { | |
8656 int instruction = 0x4C820421; | |
8657 instruction |= ((crf.value() & 0x7) << 18); | |
8658 instruction |= ((prediction.value() & 0x3) << 21); | |
8659 emitInt(instruction); | |
8660 } | |
8661 | |
8662 /** | |
8663 * Pseudo-external assembler syntax: {@code bngctr{++|--} }<i>crf</i> | |
8664 * Example disassembly syntax: {@code bngctr cr0} | |
8665 * <p> | |
8666 * This is a synthetic instruction equivalent to: {@code bcctr(CRFalse | prediction, 1 | (crf * 4), 0)} | |
8667 * | |
8668 * @see #bcctr(BOOperand, int, int) | |
8669 * | |
8670 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8671 */ | |
8672 // Template#: 484, Serial#: 484 | |
8673 public void bngctr(final CRF crf, final BranchPredictionBits prediction) { | |
8674 int instruction = 0x4C810420; | |
8675 instruction |= ((crf.value() & 0x7) << 18); | |
8676 instruction |= ((prediction.value() & 0x3) << 21); | |
8677 emitInt(instruction); | |
8678 } | |
8679 | |
8680 /** | |
8681 * Pseudo-external assembler syntax: {@code bngctrl{++|--} }<i>crf</i> | |
8682 * Example disassembly syntax: {@code bngctrl cr0} | |
8683 * <p> | |
8684 * This is a synthetic instruction equivalent to: {@code bcctrl(CRFalse | prediction, 1 | (crf * 4), 0)} | |
8685 * | |
8686 * @see #bcctrl(BOOperand, int, int) | |
8687 * | |
8688 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8689 */ | |
8690 // Template#: 485, Serial#: 485 | |
8691 public void bngctrl(final CRF crf, final BranchPredictionBits prediction) { | |
8692 int instruction = 0x4C810421; | |
8693 instruction |= ((crf.value() & 0x7) << 18); | |
8694 instruction |= ((prediction.value() & 0x3) << 21); | |
8695 emitInt(instruction); | |
8696 } | |
8697 | |
8698 /** | |
8699 * Pseudo-external assembler syntax: {@code bsoctr{++|--} }<i>crf</i> | |
8700 * Example disassembly syntax: {@code bsoctr cr0} | |
8701 * <p> | |
8702 * This is a synthetic instruction equivalent to: {@code bcctr(CRTrue | prediction, 3 | (crf * 4), 0)} | |
8703 * | |
8704 * @see #bcctr(BOOperand, int, int) | |
8705 * | |
8706 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8707 */ | |
8708 // Template#: 486, Serial#: 486 | |
8709 public void bsoctr(final CRF crf, final BranchPredictionBits prediction) { | |
8710 int instruction = 0x4D830420; | |
8711 instruction |= ((crf.value() & 0x7) << 18); | |
8712 instruction |= ((prediction.value() & 0x3) << 21); | |
8713 emitInt(instruction); | |
8714 } | |
8715 | |
8716 /** | |
8717 * Pseudo-external assembler syntax: {@code bsoctrl{++|--} }<i>crf</i> | |
8718 * Example disassembly syntax: {@code bsoctrl cr0} | |
8719 * <p> | |
8720 * This is a synthetic instruction equivalent to: {@code bcctrl(CRTrue | prediction, 3 | (crf * 4), 0)} | |
8721 * | |
8722 * @see #bcctrl(BOOperand, int, int) | |
8723 * | |
8724 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8725 */ | |
8726 // Template#: 487, Serial#: 487 | |
8727 public void bsoctrl(final CRF crf, final BranchPredictionBits prediction) { | |
8728 int instruction = 0x4D830421; | |
8729 instruction |= ((crf.value() & 0x7) << 18); | |
8730 instruction |= ((prediction.value() & 0x3) << 21); | |
8731 emitInt(instruction); | |
8732 } | |
8733 | |
8734 /** | |
8735 * Pseudo-external assembler syntax: {@code bnsctr{++|--} }<i>crf</i> | |
8736 * Example disassembly syntax: {@code bnsctr cr0} | |
8737 * <p> | |
8738 * This is a synthetic instruction equivalent to: {@code bcctr(CRFalse | prediction, 3 | (crf * 4), 0)} | |
8739 * | |
8740 * @see #bcctr(BOOperand, int, int) | |
8741 * | |
8742 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8743 */ | |
8744 // Template#: 488, Serial#: 488 | |
8745 public void bnsctr(final CRF crf, final BranchPredictionBits prediction) { | |
8746 int instruction = 0x4C830420; | |
8747 instruction |= ((crf.value() & 0x7) << 18); | |
8748 instruction |= ((prediction.value() & 0x3) << 21); | |
8749 emitInt(instruction); | |
8750 } | |
8751 | |
8752 /** | |
8753 * Pseudo-external assembler syntax: {@code bnsctrl{++|--} }<i>crf</i> | |
8754 * Example disassembly syntax: {@code bnsctrl cr0} | |
8755 * <p> | |
8756 * This is a synthetic instruction equivalent to: {@code bcctrl(CRFalse | prediction, 3 | (crf * 4), 0)} | |
8757 * | |
8758 * @see #bcctrl(BOOperand, int, int) | |
8759 * | |
8760 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8761 */ | |
8762 // Template#: 489, Serial#: 489 | |
8763 public void bnsctrl(final CRF crf, final BranchPredictionBits prediction) { | |
8764 int instruction = 0x4C830421; | |
8765 instruction |= ((crf.value() & 0x7) << 18); | |
8766 instruction |= ((prediction.value() & 0x3) << 21); | |
8767 emitInt(instruction); | |
8768 } | |
8769 | |
8770 /** | |
8771 * Pseudo-external assembler syntax: {@code bunctr{++|--} }<i>crf</i> | |
8772 * Example disassembly syntax: {@code bunctr cr0} | |
8773 * <p> | |
8774 * This is a synthetic instruction equivalent to: {@code bcctr(CRTrue | prediction, 3 | (crf * 4), 0)} | |
8775 * | |
8776 * @see #bcctr(BOOperand, int, int) | |
8777 * | |
8778 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8779 */ | |
8780 // Template#: 490, Serial#: 490 | |
8781 public void bunctr(final CRF crf, final BranchPredictionBits prediction) { | |
8782 int instruction = 0x4D830420; | |
8783 instruction |= ((crf.value() & 0x7) << 18); | |
8784 instruction |= ((prediction.value() & 0x3) << 21); | |
8785 emitInt(instruction); | |
8786 } | |
8787 | |
8788 /** | |
8789 * Pseudo-external assembler syntax: {@code bunctrl{++|--} }<i>crf</i> | |
8790 * Example disassembly syntax: {@code bunctrl cr0} | |
8791 * <p> | |
8792 * This is a synthetic instruction equivalent to: {@code bcctrl(CRTrue | prediction, 3 | (crf * 4), 0)} | |
8793 * | |
8794 * @see #bcctrl(BOOperand, int, int) | |
8795 * | |
8796 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8797 */ | |
8798 // Template#: 491, Serial#: 491 | |
8799 public void bunctrl(final CRF crf, final BranchPredictionBits prediction) { | |
8800 int instruction = 0x4D830421; | |
8801 instruction |= ((crf.value() & 0x7) << 18); | |
8802 instruction |= ((prediction.value() & 0x3) << 21); | |
8803 emitInt(instruction); | |
8804 } | |
8805 | |
8806 /** | |
8807 * Pseudo-external assembler syntax: {@code bnuctr{++|--} }<i>crf</i> | |
8808 * Example disassembly syntax: {@code bnuctr cr0} | |
8809 * <p> | |
8810 * This is a synthetic instruction equivalent to: {@code bcctr(CRFalse | prediction, 3 | (crf * 4), 0)} | |
8811 * | |
8812 * @see #bcctr(BOOperand, int, int) | |
8813 * | |
8814 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8815 */ | |
8816 // Template#: 492, Serial#: 492 | |
8817 public void bnuctr(final CRF crf, final BranchPredictionBits prediction) { | |
8818 int instruction = 0x4C830420; | |
8819 instruction |= ((crf.value() & 0x7) << 18); | |
8820 instruction |= ((prediction.value() & 0x3) << 21); | |
8821 emitInt(instruction); | |
8822 } | |
8823 | |
8824 /** | |
8825 * Pseudo-external assembler syntax: {@code bnuctrl{++|--} }<i>crf</i> | |
8826 * Example disassembly syntax: {@code bnuctrl cr0} | |
8827 * <p> | |
8828 * This is a synthetic instruction equivalent to: {@code bcctrl(CRFalse | prediction, 3 | (crf * 4), 0)} | |
8829 * | |
8830 * @see #bcctrl(BOOperand, int, int) | |
8831 * | |
8832 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.2.3 [Book 1]" | |
8833 */ | |
8834 // Template#: 493, Serial#: 493 | |
8835 public void bnuctrl(final CRF crf, final BranchPredictionBits prediction) { | |
8836 int instruction = 0x4C830421; | |
8837 instruction |= ((crf.value() & 0x7) << 18); | |
8838 instruction |= ((prediction.value() & 0x3) << 21); | |
8839 emitInt(instruction); | |
8840 } | |
8841 | |
8842 /** | |
8843 * Pseudo-external assembler syntax: {@code crset }<i>ba</i> | |
8844 * Example disassembly syntax: {@code crset 0x0} | |
8845 * <p> | |
8846 * This is a synthetic instruction equivalent to: {@code creqv(ba, ba, ba)} | |
8847 * <p> | |
8848 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
8849 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
8850 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
8851 * | |
8852 * @see #creqv(int, int, int) | |
8853 * | |
8854 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.3 [Book 1]" | |
8855 */ | |
8856 // Template#: 494, Serial#: 494 | |
8857 public void crset(final int ba) { | |
8858 int instruction = 0x4C000242; | |
8859 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
8860 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
8861 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
8862 instruction |= ((ba & 0x1f) << 21); | |
8863 instruction |= ((ba & 0x1f) << 16); | |
8864 instruction |= ((ba & 0x1f) << 11); | |
8865 emitInt(instruction); | |
8866 } | |
8867 | |
8868 /** | |
8869 * Pseudo-external assembler syntax: {@code crclr }<i>ba</i> | |
8870 * Example disassembly syntax: {@code crclr 0x0} | |
8871 * <p> | |
8872 * This is a synthetic instruction equivalent to: {@code crxor(ba, ba, ba)} | |
8873 * <p> | |
8874 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
8875 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
8876 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
8877 * | |
8878 * @see #crxor(int, int, int) | |
8879 * | |
8880 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.3 [Book 1]" | |
8881 */ | |
8882 // Template#: 495, Serial#: 495 | |
8883 public void crclr(final int ba) { | |
8884 int instruction = 0x4C000182; | |
8885 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
8886 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
8887 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
8888 instruction |= ((ba & 0x1f) << 21); | |
8889 instruction |= ((ba & 0x1f) << 16); | |
8890 instruction |= ((ba & 0x1f) << 11); | |
8891 emitInt(instruction); | |
8892 } | |
8893 | |
8894 /** | |
8895 * Pseudo-external assembler syntax: {@code crmove }<i>bt</i>, <i>ba</i> | |
8896 * Example disassembly syntax: {@code crmove 0x0, 0x0} | |
8897 * <p> | |
8898 * This is a synthetic instruction equivalent to: {@code cror(bt, ba, ba)} | |
8899 * <p> | |
8900 * Constraint: {@code 0 <= bt && bt <= 31}<br /> | |
8901 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
8902 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
8903 * | |
8904 * @see #cror(int, int, int) | |
8905 * | |
8906 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.3 [Book 1]" | |
8907 */ | |
8908 // Template#: 496, Serial#: 496 | |
8909 public void crmove(final int bt, final int ba) { | |
8910 int instruction = 0x4C000382; | |
8911 checkConstraint(0 <= bt && bt <= 31, "0 <= bt && bt <= 31"); | |
8912 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
8913 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
8914 instruction |= ((bt & 0x1f) << 21); | |
8915 instruction |= ((ba & 0x1f) << 16); | |
8916 instruction |= ((ba & 0x1f) << 11); | |
8917 emitInt(instruction); | |
8918 } | |
8919 | |
8920 /** | |
8921 * Pseudo-external assembler syntax: {@code crnot }<i>bt</i>, <i>ba</i> | |
8922 * Example disassembly syntax: {@code crnot 0x0, 0x0} | |
8923 * <p> | |
8924 * This is a synthetic instruction equivalent to: {@code crnor(bt, ba, ba)} | |
8925 * <p> | |
8926 * Constraint: {@code 0 <= bt && bt <= 31}<br /> | |
8927 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
8928 * Constraint: {@code 0 <= ba && ba <= 31}<br /> | |
8929 * | |
8930 * @see #crnor(int, int, int) | |
8931 * | |
8932 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.3 [Book 1]" | |
8933 */ | |
8934 // Template#: 497, Serial#: 497 | |
8935 public void crnot(final int bt, final int ba) { | |
8936 int instruction = 0x4C000042; | |
8937 checkConstraint(0 <= bt && bt <= 31, "0 <= bt && bt <= 31"); | |
8938 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
8939 checkConstraint(0 <= ba && ba <= 31, "0 <= ba && ba <= 31"); | |
8940 instruction |= ((bt & 0x1f) << 21); | |
8941 instruction |= ((ba & 0x1f) << 16); | |
8942 instruction |= ((ba & 0x1f) << 11); | |
8943 emitInt(instruction); | |
8944 } | |
8945 | |
8946 /** | |
8947 * Pseudo-external assembler syntax: {@code subi }<i>rt</i>, <i>ra</i>, <i>val</i> | |
8948 * Example disassembly syntax: {@code subi r0, 0, 0xffff8000} | |
8949 * <p> | |
8950 * This is a synthetic instruction equivalent to: {@code addi(rt, ra, -val)} | |
8951 * <p> | |
8952 * Constraint: {@code ra != R0}<br /> | |
8953 * Constraint: {@code -32768 <= -val && -val <= 32767}<br /> | |
8954 * | |
8955 * @see #addi(GPR, ZeroOrRegister, int) | |
8956 * | |
8957 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.4.1 [Book 1]" | |
8958 */ | |
8959 // Template#: 498, Serial#: 498 | |
8960 public void subi(final GPR rt, final ZeroOrRegister ra, final int val) { | |
8961 int instruction = 0x38000000; | |
8962 checkConstraint(ra != R0, "ra != R0"); | |
8963 checkConstraint(-32768 <= -val && -val <= 32767, "-32768 <= -val && -val <= 32767"); | |
8964 instruction |= ((rt.value() & 0x1f) << 21); | |
8965 instruction |= ((ra.value() & 0x1f) << 16); | |
8966 instruction |= (-val & 0xffff); | |
8967 emitInt(instruction); | |
8968 } | |
8969 | |
8970 /** | |
8971 * Pseudo-external assembler syntax: {@code subis }<i>rt</i>, <i>ra</i>, <i>val</i> | |
8972 * Example disassembly syntax: {@code subis r0, 0, 0xffff8000} | |
8973 * <p> | |
8974 * This is a synthetic instruction equivalent to: {@code addis(rt, ra, -val)} | |
8975 * <p> | |
8976 * Constraint: {@code ra != R0}<br /> | |
8977 * Constraint: {@code -32768 <= -val && -val <= 32767}<br /> | |
8978 * | |
8979 * @see #addis(GPR, ZeroOrRegister, int) | |
8980 * | |
8981 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.4.1 [Book 1]" | |
8982 */ | |
8983 // Template#: 499, Serial#: 499 | |
8984 public void subis(final GPR rt, final ZeroOrRegister ra, final int val) { | |
8985 int instruction = 0x3C000000; | |
8986 checkConstraint(ra != R0, "ra != R0"); | |
8987 checkConstraint(-32768 <= -val && -val <= 32767, "-32768 <= -val && -val <= 32767"); | |
8988 instruction |= ((rt.value() & 0x1f) << 21); | |
8989 instruction |= ((ra.value() & 0x1f) << 16); | |
8990 instruction |= (-val & 0xffff); | |
8991 emitInt(instruction); | |
8992 } | |
8993 | |
8994 /** | |
8995 * Pseudo-external assembler syntax: {@code subic }<i>rt</i>, <i>ra</i>, <i>val</i> | |
8996 * Example disassembly syntax: {@code subic r0, r0, 0xffff8000} | |
8997 * <p> | |
8998 * This is a synthetic instruction equivalent to: {@code addic(rt, ra, -val)} | |
8999 * <p> | |
9000 * Constraint: {@code -32768 <= -val && -val <= 32767}<br /> | |
9001 * | |
9002 * @see #addic(GPR, GPR, int) | |
9003 * | |
9004 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.4.1 [Book 1]" | |
9005 */ | |
9006 // Template#: 500, Serial#: 500 | |
9007 public void subic(final GPR rt, final GPR ra, final int val) { | |
9008 int instruction = 0x30000000; | |
9009 checkConstraint(-32768 <= -val && -val <= 32767, "-32768 <= -val && -val <= 32767"); | |
9010 instruction |= ((rt.value() & 0x1f) << 21); | |
9011 instruction |= ((ra.value() & 0x1f) << 16); | |
9012 instruction |= (-val & 0xffff); | |
9013 emitInt(instruction); | |
9014 } | |
9015 | |
9016 /** | |
9017 * Pseudo-external assembler syntax: {@code subic. }<i>rt</i>, <i>ra</i>, <i>val</i> | |
9018 * Example disassembly syntax: {@code subic. r0, r0, 0xffff8000} | |
9019 * <p> | |
9020 * This is a synthetic instruction equivalent to: {@code addic_(rt, ra, -val)} | |
9021 * <p> | |
9022 * Constraint: {@code -32768 <= -val && -val <= 32767}<br /> | |
9023 * | |
9024 * @see #addic_(GPR, GPR, int) | |
9025 * | |
9026 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.4.1 [Book 1]" | |
9027 */ | |
9028 // Template#: 501, Serial#: 501 | |
9029 public void subic_(final GPR rt, final GPR ra, final int val) { | |
9030 int instruction = 0x34000000; | |
9031 checkConstraint(-32768 <= -val && -val <= 32767, "-32768 <= -val && -val <= 32767"); | |
9032 instruction |= ((rt.value() & 0x1f) << 21); | |
9033 instruction |= ((ra.value() & 0x1f) << 16); | |
9034 instruction |= (-val & 0xffff); | |
9035 emitInt(instruction); | |
9036 } | |
9037 | |
9038 /** | |
9039 * Pseudo-external assembler syntax: {@code sub }<i>rt</i>, <i>rb</i>, <i>ra</i> | |
9040 * Example disassembly syntax: {@code sub r0, r0, r0} | |
9041 * <p> | |
9042 * This is a synthetic instruction equivalent to: {@code subf(rt, ra, rb)} | |
9043 * | |
9044 * @see #subf(GPR, GPR, GPR) | |
9045 * | |
9046 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.4.2 [Book 1]" | |
9047 */ | |
9048 // Template#: 502, Serial#: 502 | |
9049 public void sub(final GPR rt, final GPR rb, final GPR ra) { | |
9050 int instruction = 0x7C000050; | |
9051 instruction |= ((rt.value() & 0x1f) << 21); | |
9052 instruction |= ((rb.value() & 0x1f) << 11); | |
9053 instruction |= ((ra.value() & 0x1f) << 16); | |
9054 emitInt(instruction); | |
9055 } | |
9056 | |
9057 /** | |
9058 * Pseudo-external assembler syntax: {@code sub. }<i>rt</i>, <i>rb</i>, <i>ra</i> | |
9059 * Example disassembly syntax: {@code sub. r0, r0, r0} | |
9060 * <p> | |
9061 * This is a synthetic instruction equivalent to: {@code subf_(rt, ra, rb)} | |
9062 * | |
9063 * @see #subf_(GPR, GPR, GPR) | |
9064 * | |
9065 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.4.2 [Book 1]" | |
9066 */ | |
9067 // Template#: 503, Serial#: 503 | |
9068 public void sub_(final GPR rt, final GPR rb, final GPR ra) { | |
9069 int instruction = 0x7C000051; | |
9070 instruction |= ((rt.value() & 0x1f) << 21); | |
9071 instruction |= ((rb.value() & 0x1f) << 11); | |
9072 instruction |= ((ra.value() & 0x1f) << 16); | |
9073 emitInt(instruction); | |
9074 } | |
9075 | |
9076 /** | |
9077 * Pseudo-external assembler syntax: {@code subo }<i>rt</i>, <i>rb</i>, <i>ra</i> | |
9078 * Example disassembly syntax: {@code subo r0, r0, r0} | |
9079 * <p> | |
9080 * This is a synthetic instruction equivalent to: {@code subfo(rt, ra, rb)} | |
9081 * | |
9082 * @see #subfo(GPR, GPR, GPR) | |
9083 * | |
9084 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.4.2 [Book 1]" | |
9085 */ | |
9086 // Template#: 504, Serial#: 504 | |
9087 public void subo(final GPR rt, final GPR rb, final GPR ra) { | |
9088 int instruction = 0x7C000450; | |
9089 instruction |= ((rt.value() & 0x1f) << 21); | |
9090 instruction |= ((rb.value() & 0x1f) << 11); | |
9091 instruction |= ((ra.value() & 0x1f) << 16); | |
9092 emitInt(instruction); | |
9093 } | |
9094 | |
9095 /** | |
9096 * Pseudo-external assembler syntax: {@code subo. }<i>rt</i>, <i>rb</i>, <i>ra</i> | |
9097 * Example disassembly syntax: {@code subo. r0, r0, r0} | |
9098 * <p> | |
9099 * This is a synthetic instruction equivalent to: {@code subfo_(rt, ra, rb)} | |
9100 * | |
9101 * @see #subfo_(GPR, GPR, GPR) | |
9102 * | |
9103 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.4.2 [Book 1]" | |
9104 */ | |
9105 // Template#: 505, Serial#: 505 | |
9106 public void subo_(final GPR rt, final GPR rb, final GPR ra) { | |
9107 int instruction = 0x7C000451; | |
9108 instruction |= ((rt.value() & 0x1f) << 21); | |
9109 instruction |= ((rb.value() & 0x1f) << 11); | |
9110 instruction |= ((ra.value() & 0x1f) << 16); | |
9111 emitInt(instruction); | |
9112 } | |
9113 | |
9114 /** | |
9115 * Pseudo-external assembler syntax: {@code subc }<i>rt</i>, <i>rb</i>, <i>ra</i> | |
9116 * Example disassembly syntax: {@code subc r0, r0, r0} | |
9117 * <p> | |
9118 * This is a synthetic instruction equivalent to: {@code subfc(rt, ra, rb)} | |
9119 * | |
9120 * @see #subfc(GPR, GPR, GPR) | |
9121 * | |
9122 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.4.2 [Book 1]" | |
9123 */ | |
9124 // Template#: 506, Serial#: 506 | |
9125 public void subc(final GPR rt, final GPR rb, final GPR ra) { | |
9126 int instruction = 0x7C000010; | |
9127 instruction |= ((rt.value() & 0x1f) << 21); | |
9128 instruction |= ((rb.value() & 0x1f) << 11); | |
9129 instruction |= ((ra.value() & 0x1f) << 16); | |
9130 emitInt(instruction); | |
9131 } | |
9132 | |
9133 /** | |
9134 * Pseudo-external assembler syntax: {@code subc. }<i>rt</i>, <i>rb</i>, <i>ra</i> | |
9135 * Example disassembly syntax: {@code subc. r0, r0, r0} | |
9136 * <p> | |
9137 * This is a synthetic instruction equivalent to: {@code subfc_(rt, ra, rb)} | |
9138 * | |
9139 * @see #subfc_(GPR, GPR, GPR) | |
9140 * | |
9141 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.4.2 [Book 1]" | |
9142 */ | |
9143 // Template#: 507, Serial#: 507 | |
9144 public void subc_(final GPR rt, final GPR rb, final GPR ra) { | |
9145 int instruction = 0x7C000011; | |
9146 instruction |= ((rt.value() & 0x1f) << 21); | |
9147 instruction |= ((rb.value() & 0x1f) << 11); | |
9148 instruction |= ((ra.value() & 0x1f) << 16); | |
9149 emitInt(instruction); | |
9150 } | |
9151 | |
9152 /** | |
9153 * Pseudo-external assembler syntax: {@code subco }<i>rt</i>, <i>rb</i>, <i>ra</i> | |
9154 * Example disassembly syntax: {@code subco r0, r0, r0} | |
9155 * <p> | |
9156 * This is a synthetic instruction equivalent to: {@code subfco(rt, ra, rb)} | |
9157 * | |
9158 * @see #subfco(GPR, GPR, GPR) | |
9159 * | |
9160 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.4.2 [Book 1]" | |
9161 */ | |
9162 // Template#: 508, Serial#: 508 | |
9163 public void subco(final GPR rt, final GPR rb, final GPR ra) { | |
9164 int instruction = 0x7C000410; | |
9165 instruction |= ((rt.value() & 0x1f) << 21); | |
9166 instruction |= ((rb.value() & 0x1f) << 11); | |
9167 instruction |= ((ra.value() & 0x1f) << 16); | |
9168 emitInt(instruction); | |
9169 } | |
9170 | |
9171 /** | |
9172 * Pseudo-external assembler syntax: {@code subco. }<i>rt</i>, <i>rb</i>, <i>ra</i> | |
9173 * Example disassembly syntax: {@code subco. r0, r0, r0} | |
9174 * <p> | |
9175 * This is a synthetic instruction equivalent to: {@code subfco_(rt, ra, rb)} | |
9176 * | |
9177 * @see #subfco_(GPR, GPR, GPR) | |
9178 * | |
9179 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.4.2 [Book 1]" | |
9180 */ | |
9181 // Template#: 509, Serial#: 509 | |
9182 public void subco_(final GPR rt, final GPR rb, final GPR ra) { | |
9183 int instruction = 0x7C000411; | |
9184 instruction |= ((rt.value() & 0x1f) << 21); | |
9185 instruction |= ((rb.value() & 0x1f) << 11); | |
9186 instruction |= ((ra.value() & 0x1f) << 16); | |
9187 emitInt(instruction); | |
9188 } | |
9189 | |
9190 /** | |
9191 * Pseudo-external assembler syntax: {@code cmpdi }<i>bf</i>, <i>ra</i>, <i>si</i> | |
9192 * Example disassembly syntax: {@code cmpdi 0, r0, -32768} | |
9193 * <p> | |
9194 * This is a synthetic instruction equivalent to: {@code cmpi(bf, 1, ra, si)} | |
9195 * <p> | |
9196 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9197 * | |
9198 * @see #cmpi(CRF, int, GPR, int) | |
9199 * | |
9200 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.1 [Book 1]" | |
9201 */ | |
9202 // Template#: 510, Serial#: 510 | |
9203 public void cmpdi(final CRF bf, final GPR ra, final int si) { | |
9204 int instruction = 0x2C200000; | |
9205 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9206 instruction |= ((bf.value() & 0x7) << 23); | |
9207 instruction |= ((ra.value() & 0x1f) << 16); | |
9208 instruction |= (si & 0xffff); | |
9209 emitInt(instruction); | |
9210 } | |
9211 | |
9212 /** | |
9213 * Pseudo-external assembler syntax: {@code cmpdi }<i>ra</i>, <i>si</i> | |
9214 * Example disassembly syntax: {@code cmpdi r0, -32768} | |
9215 * <p> | |
9216 * This is a synthetic instruction equivalent to: {@code cmpi(CR0, 1, ra, si)} | |
9217 * <p> | |
9218 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9219 * | |
9220 * @see #cmpi(CRF, int, GPR, int) | |
9221 * | |
9222 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.1 [Book 1]" | |
9223 */ | |
9224 // Template#: 511, Serial#: 511 | |
9225 public void cmpdi(final GPR ra, final int si) { | |
9226 int instruction = 0x2C200000; | |
9227 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9228 instruction |= ((ra.value() & 0x1f) << 16); | |
9229 instruction |= (si & 0xffff); | |
9230 emitInt(instruction); | |
9231 } | |
9232 | |
9233 /** | |
9234 * Pseudo-external assembler syntax: {@code cmpd }<i>bf</i>, <i>ra</i>, <i>rb</i> | |
9235 * Example disassembly syntax: {@code cmpd 0, r0, r0} | |
9236 * <p> | |
9237 * This is a synthetic instruction equivalent to: {@code cmp(bf, 1, ra, rb)} | |
9238 * | |
9239 * @see #cmp(CRF, int, GPR, GPR) | |
9240 * | |
9241 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.1 [Book 1]" | |
9242 */ | |
9243 // Template#: 512, Serial#: 512 | |
9244 public void cmpd(final CRF bf, final GPR ra, final GPR rb) { | |
9245 int instruction = 0x7C200000; | |
9246 instruction |= ((bf.value() & 0x7) << 23); | |
9247 instruction |= ((ra.value() & 0x1f) << 16); | |
9248 instruction |= ((rb.value() & 0x1f) << 11); | |
9249 emitInt(instruction); | |
9250 } | |
9251 | |
9252 /** | |
9253 * Pseudo-external assembler syntax: {@code cmpd }<i>ra</i>, <i>rb</i> | |
9254 * Example disassembly syntax: {@code cmpd r0, r0} | |
9255 * <p> | |
9256 * This is a synthetic instruction equivalent to: {@code cmp(CR0, 1, ra, rb)} | |
9257 * | |
9258 * @see #cmp(CRF, int, GPR, GPR) | |
9259 * | |
9260 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.1 [Book 1]" | |
9261 */ | |
9262 // Template#: 513, Serial#: 513 | |
9263 public void cmpd(final GPR ra, final GPR rb) { | |
9264 int instruction = 0x7C200000; | |
9265 instruction |= ((ra.value() & 0x1f) << 16); | |
9266 instruction |= ((rb.value() & 0x1f) << 11); | |
9267 emitInt(instruction); | |
9268 } | |
9269 | |
9270 /** | |
9271 * Pseudo-external assembler syntax: {@code cmpldi }<i>bf</i>, <i>ra</i>, <i>ui</i> | |
9272 * Example disassembly syntax: {@code cmpldi 0, r0, 0x0} | |
9273 * <p> | |
9274 * This is a synthetic instruction equivalent to: {@code cmpli(bf, 1, ra, ui)} | |
9275 * <p> | |
9276 * Constraint: {@code 0 <= ui && ui <= 65535}<br /> | |
9277 * | |
9278 * @see #cmpli(CRF, int, GPR, int) | |
9279 * | |
9280 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.1 [Book 1]" | |
9281 */ | |
9282 // Template#: 514, Serial#: 514 | |
9283 public void cmpldi(final CRF bf, final GPR ra, final int ui) { | |
9284 int instruction = 0x28200000; | |
9285 checkConstraint(0 <= ui && ui <= 65535, "0 <= ui && ui <= 65535"); | |
9286 instruction |= ((bf.value() & 0x7) << 23); | |
9287 instruction |= ((ra.value() & 0x1f) << 16); | |
9288 instruction |= (ui & 0xffff); | |
9289 emitInt(instruction); | |
9290 } | |
9291 | |
9292 /** | |
9293 * Pseudo-external assembler syntax: {@code cmpldi }<i>ra</i>, <i>ui</i> | |
9294 * Example disassembly syntax: {@code cmpldi r0, 0x0} | |
9295 * <p> | |
9296 * This is a synthetic instruction equivalent to: {@code cmpli(CR0, 1, ra, ui)} | |
9297 * <p> | |
9298 * Constraint: {@code 0 <= ui && ui <= 65535}<br /> | |
9299 * | |
9300 * @see #cmpli(CRF, int, GPR, int) | |
9301 * | |
9302 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.1 [Book 1]" | |
9303 */ | |
9304 // Template#: 515, Serial#: 515 | |
9305 public void cmpldi(final GPR ra, final int ui) { | |
9306 int instruction = 0x28200000; | |
9307 checkConstraint(0 <= ui && ui <= 65535, "0 <= ui && ui <= 65535"); | |
9308 instruction |= ((ra.value() & 0x1f) << 16); | |
9309 instruction |= (ui & 0xffff); | |
9310 emitInt(instruction); | |
9311 } | |
9312 | |
9313 /** | |
9314 * Pseudo-external assembler syntax: {@code cmpld }<i>bf</i>, <i>ra</i>, <i>rb</i> | |
9315 * Example disassembly syntax: {@code cmpld 0, r0, r0} | |
9316 * <p> | |
9317 * This is a synthetic instruction equivalent to: {@code cmpl(bf, 1, ra, rb)} | |
9318 * | |
9319 * @see #cmpl(CRF, int, GPR, GPR) | |
9320 * | |
9321 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.1 [Book 1]" | |
9322 */ | |
9323 // Template#: 516, Serial#: 516 | |
9324 public void cmpld(final CRF bf, final GPR ra, final GPR rb) { | |
9325 int instruction = 0x7C200040; | |
9326 instruction |= ((bf.value() & 0x7) << 23); | |
9327 instruction |= ((ra.value() & 0x1f) << 16); | |
9328 instruction |= ((rb.value() & 0x1f) << 11); | |
9329 emitInt(instruction); | |
9330 } | |
9331 | |
9332 /** | |
9333 * Pseudo-external assembler syntax: {@code cmpld }<i>ra</i>, <i>rb</i> | |
9334 * Example disassembly syntax: {@code cmpld r0, r0} | |
9335 * <p> | |
9336 * This is a synthetic instruction equivalent to: {@code cmpl(CR0, 1, ra, rb)} | |
9337 * | |
9338 * @see #cmpl(CRF, int, GPR, GPR) | |
9339 * | |
9340 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.1 [Book 1]" | |
9341 */ | |
9342 // Template#: 517, Serial#: 517 | |
9343 public void cmpld(final GPR ra, final GPR rb) { | |
9344 int instruction = 0x7C200040; | |
9345 instruction |= ((ra.value() & 0x1f) << 16); | |
9346 instruction |= ((rb.value() & 0x1f) << 11); | |
9347 emitInt(instruction); | |
9348 } | |
9349 | |
9350 /** | |
9351 * Pseudo-external assembler syntax: {@code cmpwi }<i>bf</i>, <i>ra</i>, <i>si</i> | |
9352 * Example disassembly syntax: {@code cmpwi 0, r0, -32768} | |
9353 * <p> | |
9354 * This is a synthetic instruction equivalent to: {@code cmpi(bf, 0, ra, si)} | |
9355 * <p> | |
9356 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9357 * | |
9358 * @see #cmpi(CRF, int, GPR, int) | |
9359 * | |
9360 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.2 [Book 1]" | |
9361 */ | |
9362 // Template#: 518, Serial#: 518 | |
9363 public void cmpwi(final CRF bf, final GPR ra, final int si) { | |
9364 int instruction = 0x2C000000; | |
9365 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9366 instruction |= ((bf.value() & 0x7) << 23); | |
9367 instruction |= ((ra.value() & 0x1f) << 16); | |
9368 instruction |= (si & 0xffff); | |
9369 emitInt(instruction); | |
9370 } | |
9371 | |
9372 /** | |
9373 * Pseudo-external assembler syntax: {@code cmpwi }<i>ra</i>, <i>si</i> | |
9374 * Example disassembly syntax: {@code cmpwi r0, -32768} | |
9375 * <p> | |
9376 * This is a synthetic instruction equivalent to: {@code cmpi(CR0, 0, ra, si)} | |
9377 * <p> | |
9378 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9379 * | |
9380 * @see #cmpi(CRF, int, GPR, int) | |
9381 * | |
9382 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.2 [Book 1]" | |
9383 */ | |
9384 // Template#: 519, Serial#: 519 | |
9385 public void cmpwi(final GPR ra, final int si) { | |
9386 int instruction = 0x2C000000; | |
9387 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9388 instruction |= ((ra.value() & 0x1f) << 16); | |
9389 instruction |= (si & 0xffff); | |
9390 emitInt(instruction); | |
9391 } | |
9392 | |
9393 /** | |
9394 * Pseudo-external assembler syntax: {@code cmpw }<i>bf</i>, <i>ra</i>, <i>rb</i> | |
9395 * Example disassembly syntax: {@code cmpw 0, r0, r0} | |
9396 * <p> | |
9397 * This is a synthetic instruction equivalent to: {@code cmp(bf, 0, ra, rb)} | |
9398 * | |
9399 * @see #cmp(CRF, int, GPR, GPR) | |
9400 * | |
9401 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.2 [Book 1]" | |
9402 */ | |
9403 // Template#: 520, Serial#: 520 | |
9404 public void cmpw(final CRF bf, final GPR ra, final GPR rb) { | |
9405 int instruction = 0x7C000000; | |
9406 instruction |= ((bf.value() & 0x7) << 23); | |
9407 instruction |= ((ra.value() & 0x1f) << 16); | |
9408 instruction |= ((rb.value() & 0x1f) << 11); | |
9409 emitInt(instruction); | |
9410 } | |
9411 | |
9412 /** | |
9413 * Pseudo-external assembler syntax: {@code cmpw }<i>ra</i>, <i>rb</i> | |
9414 * Example disassembly syntax: {@code cmpw r0, r0} | |
9415 * <p> | |
9416 * This is a synthetic instruction equivalent to: {@code cmp(CR0, 0, ra, rb)} | |
9417 * | |
9418 * @see #cmp(CRF, int, GPR, GPR) | |
9419 * | |
9420 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.2 [Book 1]" | |
9421 */ | |
9422 // Template#: 521, Serial#: 521 | |
9423 public void cmpw(final GPR ra, final GPR rb) { | |
9424 int instruction = 0x7C000000; | |
9425 instruction |= ((ra.value() & 0x1f) << 16); | |
9426 instruction |= ((rb.value() & 0x1f) << 11); | |
9427 emitInt(instruction); | |
9428 } | |
9429 | |
9430 /** | |
9431 * Pseudo-external assembler syntax: {@code cmplwi }<i>bf</i>, <i>ra</i>, <i>ui</i> | |
9432 * Example disassembly syntax: {@code cmplwi 0, r0, 0x0} | |
9433 * <p> | |
9434 * This is a synthetic instruction equivalent to: {@code cmpli(bf, 0, ra, ui)} | |
9435 * <p> | |
9436 * Constraint: {@code 0 <= ui && ui <= 65535}<br /> | |
9437 * | |
9438 * @see #cmpli(CRF, int, GPR, int) | |
9439 * | |
9440 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.2 [Book 1]" | |
9441 */ | |
9442 // Template#: 522, Serial#: 522 | |
9443 public void cmplwi(final CRF bf, final GPR ra, final int ui) { | |
9444 int instruction = 0x28000000; | |
9445 checkConstraint(0 <= ui && ui <= 65535, "0 <= ui && ui <= 65535"); | |
9446 instruction |= ((bf.value() & 0x7) << 23); | |
9447 instruction |= ((ra.value() & 0x1f) << 16); | |
9448 instruction |= (ui & 0xffff); | |
9449 emitInt(instruction); | |
9450 } | |
9451 | |
9452 /** | |
9453 * Pseudo-external assembler syntax: {@code cmplwi }<i>ra</i>, <i>ui</i> | |
9454 * Example disassembly syntax: {@code cmplwi r0, 0x0} | |
9455 * <p> | |
9456 * This is a synthetic instruction equivalent to: {@code cmpli(CR0, 0, ra, ui)} | |
9457 * <p> | |
9458 * Constraint: {@code 0 <= ui && ui <= 65535}<br /> | |
9459 * | |
9460 * @see #cmpli(CRF, int, GPR, int) | |
9461 * | |
9462 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.2 [Book 1]" | |
9463 */ | |
9464 // Template#: 523, Serial#: 523 | |
9465 public void cmplwi(final GPR ra, final int ui) { | |
9466 int instruction = 0x28000000; | |
9467 checkConstraint(0 <= ui && ui <= 65535, "0 <= ui && ui <= 65535"); | |
9468 instruction |= ((ra.value() & 0x1f) << 16); | |
9469 instruction |= (ui & 0xffff); | |
9470 emitInt(instruction); | |
9471 } | |
9472 | |
9473 /** | |
9474 * Pseudo-external assembler syntax: {@code cmplw }<i>bf</i>, <i>ra</i>, <i>rb</i> | |
9475 * Example disassembly syntax: {@code cmplw 0, r0, r0} | |
9476 * <p> | |
9477 * This is a synthetic instruction equivalent to: {@code cmpl(bf, 0, ra, rb)} | |
9478 * | |
9479 * @see #cmpl(CRF, int, GPR, GPR) | |
9480 * | |
9481 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.2 [Book 1]" | |
9482 */ | |
9483 // Template#: 524, Serial#: 524 | |
9484 public void cmplw(final CRF bf, final GPR ra, final GPR rb) { | |
9485 int instruction = 0x7C000040; | |
9486 instruction |= ((bf.value() & 0x7) << 23); | |
9487 instruction |= ((ra.value() & 0x1f) << 16); | |
9488 instruction |= ((rb.value() & 0x1f) << 11); | |
9489 emitInt(instruction); | |
9490 } | |
9491 | |
9492 /** | |
9493 * Pseudo-external assembler syntax: {@code cmplw }<i>ra</i>, <i>rb</i> | |
9494 * Example disassembly syntax: {@code cmplw r0, r0} | |
9495 * <p> | |
9496 * This is a synthetic instruction equivalent to: {@code cmpl(CR0, 0, ra, rb)} | |
9497 * | |
9498 * @see #cmpl(CRF, int, GPR, GPR) | |
9499 * | |
9500 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.5.2 [Book 1]" | |
9501 */ | |
9502 // Template#: 525, Serial#: 525 | |
9503 public void cmplw(final GPR ra, final GPR rb) { | |
9504 int instruction = 0x7C000040; | |
9505 instruction |= ((ra.value() & 0x1f) << 16); | |
9506 instruction |= ((rb.value() & 0x1f) << 11); | |
9507 emitInt(instruction); | |
9508 } | |
9509 | |
9510 /** | |
9511 * Pseudo-external assembler syntax: {@code twlti }<i>ra</i>, <i>si</i> | |
9512 * Example disassembly syntax: {@code twlti r0, -32768} | |
9513 * <p> | |
9514 * This is a synthetic instruction equivalent to: {@code twi(16, ra, si)} | |
9515 * <p> | |
9516 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9517 * | |
9518 * @see #twi(int, GPR, int) | |
9519 * | |
9520 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9521 */ | |
9522 // Template#: 526, Serial#: 526 | |
9523 public void twlti(final GPR ra, final int si) { | |
9524 int instruction = 0x0E000000; | |
9525 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9526 instruction |= ((ra.value() & 0x1f) << 16); | |
9527 instruction |= (si & 0xffff); | |
9528 emitInt(instruction); | |
9529 } | |
9530 | |
9531 /** | |
9532 * Pseudo-external assembler syntax: {@code twlei }<i>ra</i>, <i>si</i> | |
9533 * Example disassembly syntax: {@code twlei r0, -32768} | |
9534 * <p> | |
9535 * This is a synthetic instruction equivalent to: {@code twi(20, ra, si)} | |
9536 * <p> | |
9537 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9538 * | |
9539 * @see #twi(int, GPR, int) | |
9540 * | |
9541 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9542 */ | |
9543 // Template#: 527, Serial#: 527 | |
9544 public void twlei(final GPR ra, final int si) { | |
9545 int instruction = 0x0E800000; | |
9546 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9547 instruction |= ((ra.value() & 0x1f) << 16); | |
9548 instruction |= (si & 0xffff); | |
9549 emitInt(instruction); | |
9550 } | |
9551 | |
9552 /** | |
9553 * Pseudo-external assembler syntax: {@code tweqi }<i>ra</i>, <i>si</i> | |
9554 * Example disassembly syntax: {@code tweqi r0, -32768} | |
9555 * <p> | |
9556 * This is a synthetic instruction equivalent to: {@code twi(4, ra, si)} | |
9557 * <p> | |
9558 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9559 * | |
9560 * @see #twi(int, GPR, int) | |
9561 * | |
9562 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9563 */ | |
9564 // Template#: 528, Serial#: 528 | |
9565 public void tweqi(final GPR ra, final int si) { | |
9566 int instruction = 0x0C800000; | |
9567 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9568 instruction |= ((ra.value() & 0x1f) << 16); | |
9569 instruction |= (si & 0xffff); | |
9570 emitInt(instruction); | |
9571 } | |
9572 | |
9573 /** | |
9574 * Pseudo-external assembler syntax: {@code twgei }<i>ra</i>, <i>si</i> | |
9575 * Example disassembly syntax: {@code twgei r0, -32768} | |
9576 * <p> | |
9577 * This is a synthetic instruction equivalent to: {@code twi(12, ra, si)} | |
9578 * <p> | |
9579 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9580 * | |
9581 * @see #twi(int, GPR, int) | |
9582 * | |
9583 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9584 */ | |
9585 // Template#: 529, Serial#: 529 | |
9586 public void twgei(final GPR ra, final int si) { | |
9587 int instruction = 0x0D800000; | |
9588 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9589 instruction |= ((ra.value() & 0x1f) << 16); | |
9590 instruction |= (si & 0xffff); | |
9591 emitInt(instruction); | |
9592 } | |
9593 | |
9594 /** | |
9595 * Pseudo-external assembler syntax: {@code twgti }<i>ra</i>, <i>si</i> | |
9596 * Example disassembly syntax: {@code twgti r0, -32768} | |
9597 * <p> | |
9598 * This is a synthetic instruction equivalent to: {@code twi(8, ra, si)} | |
9599 * <p> | |
9600 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9601 * | |
9602 * @see #twi(int, GPR, int) | |
9603 * | |
9604 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9605 */ | |
9606 // Template#: 530, Serial#: 530 | |
9607 public void twgti(final GPR ra, final int si) { | |
9608 int instruction = 0x0D000000; | |
9609 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9610 instruction |= ((ra.value() & 0x1f) << 16); | |
9611 instruction |= (si & 0xffff); | |
9612 emitInt(instruction); | |
9613 } | |
9614 | |
9615 /** | |
9616 * Pseudo-external assembler syntax: {@code twnli }<i>ra</i>, <i>si</i> | |
9617 * Example disassembly syntax: {@code twnli r0, -32768} | |
9618 * <p> | |
9619 * This is a synthetic instruction equivalent to: {@code twi(12, ra, si)} | |
9620 * <p> | |
9621 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9622 * | |
9623 * @see #twi(int, GPR, int) | |
9624 * | |
9625 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9626 */ | |
9627 // Template#: 531, Serial#: 531 | |
9628 public void twnli(final GPR ra, final int si) { | |
9629 int instruction = 0x0D800000; | |
9630 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9631 instruction |= ((ra.value() & 0x1f) << 16); | |
9632 instruction |= (si & 0xffff); | |
9633 emitInt(instruction); | |
9634 } | |
9635 | |
9636 /** | |
9637 * Pseudo-external assembler syntax: {@code twnei }<i>ra</i>, <i>si</i> | |
9638 * Example disassembly syntax: {@code twnei r0, -32768} | |
9639 * <p> | |
9640 * This is a synthetic instruction equivalent to: {@code twi(24, ra, si)} | |
9641 * <p> | |
9642 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9643 * | |
9644 * @see #twi(int, GPR, int) | |
9645 * | |
9646 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9647 */ | |
9648 // Template#: 532, Serial#: 532 | |
9649 public void twnei(final GPR ra, final int si) { | |
9650 int instruction = 0x0F000000; | |
9651 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9652 instruction |= ((ra.value() & 0x1f) << 16); | |
9653 instruction |= (si & 0xffff); | |
9654 emitInt(instruction); | |
9655 } | |
9656 | |
9657 /** | |
9658 * Pseudo-external assembler syntax: {@code twngi }<i>ra</i>, <i>si</i> | |
9659 * Example disassembly syntax: {@code twngi r0, -32768} | |
9660 * <p> | |
9661 * This is a synthetic instruction equivalent to: {@code twi(20, ra, si)} | |
9662 * <p> | |
9663 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9664 * | |
9665 * @see #twi(int, GPR, int) | |
9666 * | |
9667 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9668 */ | |
9669 // Template#: 533, Serial#: 533 | |
9670 public void twngi(final GPR ra, final int si) { | |
9671 int instruction = 0x0E800000; | |
9672 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9673 instruction |= ((ra.value() & 0x1f) << 16); | |
9674 instruction |= (si & 0xffff); | |
9675 emitInt(instruction); | |
9676 } | |
9677 | |
9678 /** | |
9679 * Pseudo-external assembler syntax: {@code twllti }<i>ra</i>, <i>si</i> | |
9680 * Example disassembly syntax: {@code twllti r0, -32768} | |
9681 * <p> | |
9682 * This is a synthetic instruction equivalent to: {@code twi(2, ra, si)} | |
9683 * <p> | |
9684 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9685 * | |
9686 * @see #twi(int, GPR, int) | |
9687 * | |
9688 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9689 */ | |
9690 // Template#: 534, Serial#: 534 | |
9691 public void twllti(final GPR ra, final int si) { | |
9692 int instruction = 0x0C400000; | |
9693 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9694 instruction |= ((ra.value() & 0x1f) << 16); | |
9695 instruction |= (si & 0xffff); | |
9696 emitInt(instruction); | |
9697 } | |
9698 | |
9699 /** | |
9700 * Pseudo-external assembler syntax: {@code twllei }<i>ra</i>, <i>si</i> | |
9701 * Example disassembly syntax: {@code twllei r0, -32768} | |
9702 * <p> | |
9703 * This is a synthetic instruction equivalent to: {@code twi(6, ra, si)} | |
9704 * <p> | |
9705 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9706 * | |
9707 * @see #twi(int, GPR, int) | |
9708 * | |
9709 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9710 */ | |
9711 // Template#: 535, Serial#: 535 | |
9712 public void twllei(final GPR ra, final int si) { | |
9713 int instruction = 0x0CC00000; | |
9714 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9715 instruction |= ((ra.value() & 0x1f) << 16); | |
9716 instruction |= (si & 0xffff); | |
9717 emitInt(instruction); | |
9718 } | |
9719 | |
9720 /** | |
9721 * Pseudo-external assembler syntax: {@code twlgei }<i>ra</i>, <i>si</i> | |
9722 * Example disassembly syntax: {@code twlgei r0, -32768} | |
9723 * <p> | |
9724 * This is a synthetic instruction equivalent to: {@code twi(5, ra, si)} | |
9725 * <p> | |
9726 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9727 * | |
9728 * @see #twi(int, GPR, int) | |
9729 * | |
9730 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9731 */ | |
9732 // Template#: 536, Serial#: 536 | |
9733 public void twlgei(final GPR ra, final int si) { | |
9734 int instruction = 0x0CA00000; | |
9735 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9736 instruction |= ((ra.value() & 0x1f) << 16); | |
9737 instruction |= (si & 0xffff); | |
9738 emitInt(instruction); | |
9739 } | |
9740 | |
9741 /** | |
9742 * Pseudo-external assembler syntax: {@code twlgti }<i>ra</i>, <i>si</i> | |
9743 * Example disassembly syntax: {@code twlgti r0, -32768} | |
9744 * <p> | |
9745 * This is a synthetic instruction equivalent to: {@code twi(1, ra, si)} | |
9746 * <p> | |
9747 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9748 * | |
9749 * @see #twi(int, GPR, int) | |
9750 * | |
9751 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9752 */ | |
9753 // Template#: 537, Serial#: 537 | |
9754 public void twlgti(final GPR ra, final int si) { | |
9755 int instruction = 0x0C200000; | |
9756 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9757 instruction |= ((ra.value() & 0x1f) << 16); | |
9758 instruction |= (si & 0xffff); | |
9759 emitInt(instruction); | |
9760 } | |
9761 | |
9762 /** | |
9763 * Pseudo-external assembler syntax: {@code twlnli }<i>ra</i>, <i>si</i> | |
9764 * Example disassembly syntax: {@code twlnli r0, -32768} | |
9765 * <p> | |
9766 * This is a synthetic instruction equivalent to: {@code twi(5, ra, si)} | |
9767 * <p> | |
9768 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9769 * | |
9770 * @see #twi(int, GPR, int) | |
9771 * | |
9772 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9773 */ | |
9774 // Template#: 538, Serial#: 538 | |
9775 public void twlnli(final GPR ra, final int si) { | |
9776 int instruction = 0x0CA00000; | |
9777 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9778 instruction |= ((ra.value() & 0x1f) << 16); | |
9779 instruction |= (si & 0xffff); | |
9780 emitInt(instruction); | |
9781 } | |
9782 | |
9783 /** | |
9784 * Pseudo-external assembler syntax: {@code twlngi }<i>ra</i>, <i>si</i> | |
9785 * Example disassembly syntax: {@code twlngi r0, -32768} | |
9786 * <p> | |
9787 * This is a synthetic instruction equivalent to: {@code twi(6, ra, si)} | |
9788 * <p> | |
9789 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
9790 * | |
9791 * @see #twi(int, GPR, int) | |
9792 * | |
9793 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9794 */ | |
9795 // Template#: 539, Serial#: 539 | |
9796 public void twlngi(final GPR ra, final int si) { | |
9797 int instruction = 0x0CC00000; | |
9798 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
9799 instruction |= ((ra.value() & 0x1f) << 16); | |
9800 instruction |= (si & 0xffff); | |
9801 emitInt(instruction); | |
9802 } | |
9803 | |
9804 /** | |
9805 * Pseudo-external assembler syntax: {@code twlt }<i>ra</i>, <i>rb</i> | |
9806 * Example disassembly syntax: {@code twlt r0, r0} | |
9807 * <p> | |
9808 * This is a synthetic instruction equivalent to: {@code tw(16, ra, rb)} | |
9809 * | |
9810 * @see #tw(int, GPR, GPR) | |
9811 * | |
9812 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9813 */ | |
9814 // Template#: 540, Serial#: 540 | |
9815 public void twlt(final GPR ra, final GPR rb) { | |
9816 int instruction = 0x7E000008; | |
9817 instruction |= ((ra.value() & 0x1f) << 16); | |
9818 instruction |= ((rb.value() & 0x1f) << 11); | |
9819 emitInt(instruction); | |
9820 } | |
9821 | |
9822 /** | |
9823 * Pseudo-external assembler syntax: {@code twle }<i>ra</i>, <i>rb</i> | |
9824 * Example disassembly syntax: {@code twle r0, r0} | |
9825 * <p> | |
9826 * This is a synthetic instruction equivalent to: {@code tw(20, ra, rb)} | |
9827 * | |
9828 * @see #tw(int, GPR, GPR) | |
9829 * | |
9830 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9831 */ | |
9832 // Template#: 541, Serial#: 541 | |
9833 public void twle(final GPR ra, final GPR rb) { | |
9834 int instruction = 0x7E800008; | |
9835 instruction |= ((ra.value() & 0x1f) << 16); | |
9836 instruction |= ((rb.value() & 0x1f) << 11); | |
9837 emitInt(instruction); | |
9838 } | |
9839 | |
9840 /** | |
9841 * Pseudo-external assembler syntax: {@code tweq }<i>ra</i>, <i>rb</i> | |
9842 * Example disassembly syntax: {@code tweq r0, r0} | |
9843 * <p> | |
9844 * This is a synthetic instruction equivalent to: {@code tw(4, ra, rb)} | |
9845 * | |
9846 * @see #tw(int, GPR, GPR) | |
9847 * | |
9848 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9849 */ | |
9850 // Template#: 542, Serial#: 542 | |
9851 public void tweq(final GPR ra, final GPR rb) { | |
9852 int instruction = 0x7C800008; | |
9853 instruction |= ((ra.value() & 0x1f) << 16); | |
9854 instruction |= ((rb.value() & 0x1f) << 11); | |
9855 emitInt(instruction); | |
9856 } | |
9857 | |
9858 /** | |
9859 * Pseudo-external assembler syntax: {@code twge }<i>ra</i>, <i>rb</i> | |
9860 * Example disassembly syntax: {@code twge r0, r0} | |
9861 * <p> | |
9862 * This is a synthetic instruction equivalent to: {@code tw(12, ra, rb)} | |
9863 * | |
9864 * @see #tw(int, GPR, GPR) | |
9865 * | |
9866 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9867 */ | |
9868 // Template#: 543, Serial#: 543 | |
9869 public void twge(final GPR ra, final GPR rb) { | |
9870 int instruction = 0x7D800008; | |
9871 instruction |= ((ra.value() & 0x1f) << 16); | |
9872 instruction |= ((rb.value() & 0x1f) << 11); | |
9873 emitInt(instruction); | |
9874 } | |
9875 | |
9876 /** | |
9877 * Pseudo-external assembler syntax: {@code twgt }<i>ra</i>, <i>rb</i> | |
9878 * Example disassembly syntax: {@code twgt r0, r0} | |
9879 * <p> | |
9880 * This is a synthetic instruction equivalent to: {@code tw(8, ra, rb)} | |
9881 * | |
9882 * @see #tw(int, GPR, GPR) | |
9883 * | |
9884 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9885 */ | |
9886 // Template#: 544, Serial#: 544 | |
9887 public void twgt(final GPR ra, final GPR rb) { | |
9888 int instruction = 0x7D000008; | |
9889 instruction |= ((ra.value() & 0x1f) << 16); | |
9890 instruction |= ((rb.value() & 0x1f) << 11); | |
9891 emitInt(instruction); | |
9892 } | |
9893 | |
9894 /** | |
9895 * Pseudo-external assembler syntax: {@code twnl }<i>ra</i>, <i>rb</i> | |
9896 * Example disassembly syntax: {@code twnl r0, r0} | |
9897 * <p> | |
9898 * This is a synthetic instruction equivalent to: {@code tw(12, ra, rb)} | |
9899 * | |
9900 * @see #tw(int, GPR, GPR) | |
9901 * | |
9902 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9903 */ | |
9904 // Template#: 545, Serial#: 545 | |
9905 public void twnl(final GPR ra, final GPR rb) { | |
9906 int instruction = 0x7D800008; | |
9907 instruction |= ((ra.value() & 0x1f) << 16); | |
9908 instruction |= ((rb.value() & 0x1f) << 11); | |
9909 emitInt(instruction); | |
9910 } | |
9911 | |
9912 /** | |
9913 * Pseudo-external assembler syntax: {@code twne }<i>ra</i>, <i>rb</i> | |
9914 * Example disassembly syntax: {@code twne r0, r0} | |
9915 * <p> | |
9916 * This is a synthetic instruction equivalent to: {@code tw(24, ra, rb)} | |
9917 * | |
9918 * @see #tw(int, GPR, GPR) | |
9919 * | |
9920 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9921 */ | |
9922 // Template#: 546, Serial#: 546 | |
9923 public void twne(final GPR ra, final GPR rb) { | |
9924 int instruction = 0x7F000008; | |
9925 instruction |= ((ra.value() & 0x1f) << 16); | |
9926 instruction |= ((rb.value() & 0x1f) << 11); | |
9927 emitInt(instruction); | |
9928 } | |
9929 | |
9930 /** | |
9931 * Pseudo-external assembler syntax: {@code twng }<i>ra</i>, <i>rb</i> | |
9932 * Example disassembly syntax: {@code twng r0, r0} | |
9933 * <p> | |
9934 * This is a synthetic instruction equivalent to: {@code tw(20, ra, rb)} | |
9935 * | |
9936 * @see #tw(int, GPR, GPR) | |
9937 * | |
9938 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9939 */ | |
9940 // Template#: 547, Serial#: 547 | |
9941 public void twng(final GPR ra, final GPR rb) { | |
9942 int instruction = 0x7E800008; | |
9943 instruction |= ((ra.value() & 0x1f) << 16); | |
9944 instruction |= ((rb.value() & 0x1f) << 11); | |
9945 emitInt(instruction); | |
9946 } | |
9947 | |
9948 /** | |
9949 * Pseudo-external assembler syntax: {@code twllt }<i>ra</i>, <i>rb</i> | |
9950 * Example disassembly syntax: {@code twllt r0, r0} | |
9951 * <p> | |
9952 * This is a synthetic instruction equivalent to: {@code tw(2, ra, rb)} | |
9953 * | |
9954 * @see #tw(int, GPR, GPR) | |
9955 * | |
9956 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9957 */ | |
9958 // Template#: 548, Serial#: 548 | |
9959 public void twllt(final GPR ra, final GPR rb) { | |
9960 int instruction = 0x7C400008; | |
9961 instruction |= ((ra.value() & 0x1f) << 16); | |
9962 instruction |= ((rb.value() & 0x1f) << 11); | |
9963 emitInt(instruction); | |
9964 } | |
9965 | |
9966 /** | |
9967 * Pseudo-external assembler syntax: {@code twlle }<i>ra</i>, <i>rb</i> | |
9968 * Example disassembly syntax: {@code twlle r0, r0} | |
9969 * <p> | |
9970 * This is a synthetic instruction equivalent to: {@code tw(6, ra, rb)} | |
9971 * | |
9972 * @see #tw(int, GPR, GPR) | |
9973 * | |
9974 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9975 */ | |
9976 // Template#: 549, Serial#: 549 | |
9977 public void twlle(final GPR ra, final GPR rb) { | |
9978 int instruction = 0x7CC00008; | |
9979 instruction |= ((ra.value() & 0x1f) << 16); | |
9980 instruction |= ((rb.value() & 0x1f) << 11); | |
9981 emitInt(instruction); | |
9982 } | |
9983 | |
9984 /** | |
9985 * Pseudo-external assembler syntax: {@code twlge }<i>ra</i>, <i>rb</i> | |
9986 * Example disassembly syntax: {@code twlge r0, r0} | |
9987 * <p> | |
9988 * This is a synthetic instruction equivalent to: {@code tw(5, ra, rb)} | |
9989 * | |
9990 * @see #tw(int, GPR, GPR) | |
9991 * | |
9992 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
9993 */ | |
9994 // Template#: 550, Serial#: 550 | |
9995 public void twlge(final GPR ra, final GPR rb) { | |
9996 int instruction = 0x7CA00008; | |
9997 instruction |= ((ra.value() & 0x1f) << 16); | |
9998 instruction |= ((rb.value() & 0x1f) << 11); | |
9999 emitInt(instruction); | |
10000 } | |
10001 | |
10002 /** | |
10003 * Pseudo-external assembler syntax: {@code twlgt }<i>ra</i>, <i>rb</i> | |
10004 * Example disassembly syntax: {@code twlgt r0, r0} | |
10005 * <p> | |
10006 * This is a synthetic instruction equivalent to: {@code tw(1, ra, rb)} | |
10007 * | |
10008 * @see #tw(int, GPR, GPR) | |
10009 * | |
10010 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10011 */ | |
10012 // Template#: 551, Serial#: 551 | |
10013 public void twlgt(final GPR ra, final GPR rb) { | |
10014 int instruction = 0x7C200008; | |
10015 instruction |= ((ra.value() & 0x1f) << 16); | |
10016 instruction |= ((rb.value() & 0x1f) << 11); | |
10017 emitInt(instruction); | |
10018 } | |
10019 | |
10020 /** | |
10021 * Pseudo-external assembler syntax: {@code twlnl }<i>ra</i>, <i>rb</i> | |
10022 * Example disassembly syntax: {@code twlnl r0, r0} | |
10023 * <p> | |
10024 * This is a synthetic instruction equivalent to: {@code tw(5, ra, rb)} | |
10025 * | |
10026 * @see #tw(int, GPR, GPR) | |
10027 * | |
10028 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10029 */ | |
10030 // Template#: 552, Serial#: 552 | |
10031 public void twlnl(final GPR ra, final GPR rb) { | |
10032 int instruction = 0x7CA00008; | |
10033 instruction |= ((ra.value() & 0x1f) << 16); | |
10034 instruction |= ((rb.value() & 0x1f) << 11); | |
10035 emitInt(instruction); | |
10036 } | |
10037 | |
10038 /** | |
10039 * Pseudo-external assembler syntax: {@code twlng }<i>ra</i>, <i>rb</i> | |
10040 * Example disassembly syntax: {@code twlng r0, r0} | |
10041 * <p> | |
10042 * This is a synthetic instruction equivalent to: {@code tw(6, ra, rb)} | |
10043 * | |
10044 * @see #tw(int, GPR, GPR) | |
10045 * | |
10046 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10047 */ | |
10048 // Template#: 553, Serial#: 553 | |
10049 public void twlng(final GPR ra, final GPR rb) { | |
10050 int instruction = 0x7CC00008; | |
10051 instruction |= ((ra.value() & 0x1f) << 16); | |
10052 instruction |= ((rb.value() & 0x1f) << 11); | |
10053 emitInt(instruction); | |
10054 } | |
10055 | |
10056 /** | |
10057 * Pseudo-external assembler syntax: {@code trap } | |
10058 * Example disassembly syntax: {@code trap } | |
10059 * <p> | |
10060 * This is a synthetic instruction equivalent to: {@code tw(31, R0, R0)} | |
10061 * | |
10062 * @see #tw(int, GPR, GPR) | |
10063 * | |
10064 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10065 */ | |
10066 // Template#: 554, Serial#: 554 | |
10067 public void trap() { | |
10068 int instruction = 0x7FE00008; | |
10069 emitInt(instruction); | |
10070 } | |
10071 | |
10072 /** | |
10073 * Pseudo-external assembler syntax: {@code tdlti }<i>ra</i>, <i>si</i> | |
10074 * Example disassembly syntax: {@code tdlti r0, -32768} | |
10075 * <p> | |
10076 * This is a synthetic instruction equivalent to: {@code tdi(16, ra, si)} | |
10077 * <p> | |
10078 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
10079 * | |
10080 * @see #tdi(int, GPR, int) | |
10081 * | |
10082 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10083 */ | |
10084 // Template#: 555, Serial#: 555 | |
10085 public void tdlti(final GPR ra, final int si) { | |
10086 int instruction = 0x0A000000; | |
10087 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
10088 instruction |= ((ra.value() & 0x1f) << 16); | |
10089 instruction |= (si & 0xffff); | |
10090 emitInt(instruction); | |
10091 } | |
10092 | |
10093 /** | |
10094 * Pseudo-external assembler syntax: {@code tdlei }<i>ra</i>, <i>si</i> | |
10095 * Example disassembly syntax: {@code tdlei r0, -32768} | |
10096 * <p> | |
10097 * This is a synthetic instruction equivalent to: {@code tdi(20, ra, si)} | |
10098 * <p> | |
10099 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
10100 * | |
10101 * @see #tdi(int, GPR, int) | |
10102 * | |
10103 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10104 */ | |
10105 // Template#: 556, Serial#: 556 | |
10106 public void tdlei(final GPR ra, final int si) { | |
10107 int instruction = 0x0A800000; | |
10108 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
10109 instruction |= ((ra.value() & 0x1f) << 16); | |
10110 instruction |= (si & 0xffff); | |
10111 emitInt(instruction); | |
10112 } | |
10113 | |
10114 /** | |
10115 * Pseudo-external assembler syntax: {@code tdeqi }<i>ra</i>, <i>si</i> | |
10116 * Example disassembly syntax: {@code tdeqi r0, -32768} | |
10117 * <p> | |
10118 * This is a synthetic instruction equivalent to: {@code tdi(4, ra, si)} | |
10119 * <p> | |
10120 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
10121 * | |
10122 * @see #tdi(int, GPR, int) | |
10123 * | |
10124 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10125 */ | |
10126 // Template#: 557, Serial#: 557 | |
10127 public void tdeqi(final GPR ra, final int si) { | |
10128 int instruction = 0x08800000; | |
10129 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
10130 instruction |= ((ra.value() & 0x1f) << 16); | |
10131 instruction |= (si & 0xffff); | |
10132 emitInt(instruction); | |
10133 } | |
10134 | |
10135 /** | |
10136 * Pseudo-external assembler syntax: {@code tdgei }<i>ra</i>, <i>si</i> | |
10137 * Example disassembly syntax: {@code tdgei r0, -32768} | |
10138 * <p> | |
10139 * This is a synthetic instruction equivalent to: {@code tdi(12, ra, si)} | |
10140 * <p> | |
10141 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
10142 * | |
10143 * @see #tdi(int, GPR, int) | |
10144 * | |
10145 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10146 */ | |
10147 // Template#: 558, Serial#: 558 | |
10148 public void tdgei(final GPR ra, final int si) { | |
10149 int instruction = 0x09800000; | |
10150 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
10151 instruction |= ((ra.value() & 0x1f) << 16); | |
10152 instruction |= (si & 0xffff); | |
10153 emitInt(instruction); | |
10154 } | |
10155 | |
10156 /** | |
10157 * Pseudo-external assembler syntax: {@code tdgti }<i>ra</i>, <i>si</i> | |
10158 * Example disassembly syntax: {@code tdgti r0, -32768} | |
10159 * <p> | |
10160 * This is a synthetic instruction equivalent to: {@code tdi(8, ra, si)} | |
10161 * <p> | |
10162 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
10163 * | |
10164 * @see #tdi(int, GPR, int) | |
10165 * | |
10166 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10167 */ | |
10168 // Template#: 559, Serial#: 559 | |
10169 public void tdgti(final GPR ra, final int si) { | |
10170 int instruction = 0x09000000; | |
10171 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
10172 instruction |= ((ra.value() & 0x1f) << 16); | |
10173 instruction |= (si & 0xffff); | |
10174 emitInt(instruction); | |
10175 } | |
10176 | |
10177 /** | |
10178 * Pseudo-external assembler syntax: {@code tdnli }<i>ra</i>, <i>si</i> | |
10179 * Example disassembly syntax: {@code tdnli r0, -32768} | |
10180 * <p> | |
10181 * This is a synthetic instruction equivalent to: {@code tdi(12, ra, si)} | |
10182 * <p> | |
10183 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
10184 * | |
10185 * @see #tdi(int, GPR, int) | |
10186 * | |
10187 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10188 */ | |
10189 // Template#: 560, Serial#: 560 | |
10190 public void tdnli(final GPR ra, final int si) { | |
10191 int instruction = 0x09800000; | |
10192 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
10193 instruction |= ((ra.value() & 0x1f) << 16); | |
10194 instruction |= (si & 0xffff); | |
10195 emitInt(instruction); | |
10196 } | |
10197 | |
10198 /** | |
10199 * Pseudo-external assembler syntax: {@code tdnei }<i>ra</i>, <i>si</i> | |
10200 * Example disassembly syntax: {@code tdnei r0, -32768} | |
10201 * <p> | |
10202 * This is a synthetic instruction equivalent to: {@code tdi(24, ra, si)} | |
10203 * <p> | |
10204 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
10205 * | |
10206 * @see #tdi(int, GPR, int) | |
10207 * | |
10208 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10209 */ | |
10210 // Template#: 561, Serial#: 561 | |
10211 public void tdnei(final GPR ra, final int si) { | |
10212 int instruction = 0x0B000000; | |
10213 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
10214 instruction |= ((ra.value() & 0x1f) << 16); | |
10215 instruction |= (si & 0xffff); | |
10216 emitInt(instruction); | |
10217 } | |
10218 | |
10219 /** | |
10220 * Pseudo-external assembler syntax: {@code tdngi }<i>ra</i>, <i>si</i> | |
10221 * Example disassembly syntax: {@code tdngi r0, -32768} | |
10222 * <p> | |
10223 * This is a synthetic instruction equivalent to: {@code tdi(20, ra, si)} | |
10224 * <p> | |
10225 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
10226 * | |
10227 * @see #tdi(int, GPR, int) | |
10228 * | |
10229 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10230 */ | |
10231 // Template#: 562, Serial#: 562 | |
10232 public void tdngi(final GPR ra, final int si) { | |
10233 int instruction = 0x0A800000; | |
10234 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
10235 instruction |= ((ra.value() & 0x1f) << 16); | |
10236 instruction |= (si & 0xffff); | |
10237 emitInt(instruction); | |
10238 } | |
10239 | |
10240 /** | |
10241 * Pseudo-external assembler syntax: {@code tdllti }<i>ra</i>, <i>si</i> | |
10242 * Example disassembly syntax: {@code tdllti r0, -32768} | |
10243 * <p> | |
10244 * This is a synthetic instruction equivalent to: {@code tdi(2, ra, si)} | |
10245 * <p> | |
10246 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
10247 * | |
10248 * @see #tdi(int, GPR, int) | |
10249 * | |
10250 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10251 */ | |
10252 // Template#: 563, Serial#: 563 | |
10253 public void tdllti(final GPR ra, final int si) { | |
10254 int instruction = 0x08400000; | |
10255 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
10256 instruction |= ((ra.value() & 0x1f) << 16); | |
10257 instruction |= (si & 0xffff); | |
10258 emitInt(instruction); | |
10259 } | |
10260 | |
10261 /** | |
10262 * Pseudo-external assembler syntax: {@code tdllei }<i>ra</i>, <i>si</i> | |
10263 * Example disassembly syntax: {@code tdllei r0, -32768} | |
10264 * <p> | |
10265 * This is a synthetic instruction equivalent to: {@code tdi(6, ra, si)} | |
10266 * <p> | |
10267 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
10268 * | |
10269 * @see #tdi(int, GPR, int) | |
10270 * | |
10271 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10272 */ | |
10273 // Template#: 564, Serial#: 564 | |
10274 public void tdllei(final GPR ra, final int si) { | |
10275 int instruction = 0x08C00000; | |
10276 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
10277 instruction |= ((ra.value() & 0x1f) << 16); | |
10278 instruction |= (si & 0xffff); | |
10279 emitInt(instruction); | |
10280 } | |
10281 | |
10282 /** | |
10283 * Pseudo-external assembler syntax: {@code tdlgei }<i>ra</i>, <i>si</i> | |
10284 * Example disassembly syntax: {@code tdlgei r0, -32768} | |
10285 * <p> | |
10286 * This is a synthetic instruction equivalent to: {@code tdi(5, ra, si)} | |
10287 * <p> | |
10288 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
10289 * | |
10290 * @see #tdi(int, GPR, int) | |
10291 * | |
10292 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10293 */ | |
10294 // Template#: 565, Serial#: 565 | |
10295 public void tdlgei(final GPR ra, final int si) { | |
10296 int instruction = 0x08A00000; | |
10297 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
10298 instruction |= ((ra.value() & 0x1f) << 16); | |
10299 instruction |= (si & 0xffff); | |
10300 emitInt(instruction); | |
10301 } | |
10302 | |
10303 /** | |
10304 * Pseudo-external assembler syntax: {@code tdlgti }<i>ra</i>, <i>si</i> | |
10305 * Example disassembly syntax: {@code tdlgti r0, -32768} | |
10306 * <p> | |
10307 * This is a synthetic instruction equivalent to: {@code tdi(1, ra, si)} | |
10308 * <p> | |
10309 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
10310 * | |
10311 * @see #tdi(int, GPR, int) | |
10312 * | |
10313 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10314 */ | |
10315 // Template#: 566, Serial#: 566 | |
10316 public void tdlgti(final GPR ra, final int si) { | |
10317 int instruction = 0x08200000; | |
10318 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
10319 instruction |= ((ra.value() & 0x1f) << 16); | |
10320 instruction |= (si & 0xffff); | |
10321 emitInt(instruction); | |
10322 } | |
10323 | |
10324 /** | |
10325 * Pseudo-external assembler syntax: {@code tdlnli }<i>ra</i>, <i>si</i> | |
10326 * Example disassembly syntax: {@code tdlnli r0, -32768} | |
10327 * <p> | |
10328 * This is a synthetic instruction equivalent to: {@code tdi(5, ra, si)} | |
10329 * <p> | |
10330 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
10331 * | |
10332 * @see #tdi(int, GPR, int) | |
10333 * | |
10334 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10335 */ | |
10336 // Template#: 567, Serial#: 567 | |
10337 public void tdlnli(final GPR ra, final int si) { | |
10338 int instruction = 0x08A00000; | |
10339 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
10340 instruction |= ((ra.value() & 0x1f) << 16); | |
10341 instruction |= (si & 0xffff); | |
10342 emitInt(instruction); | |
10343 } | |
10344 | |
10345 /** | |
10346 * Pseudo-external assembler syntax: {@code tdlngi }<i>ra</i>, <i>si</i> | |
10347 * Example disassembly syntax: {@code tdlngi r0, -32768} | |
10348 * <p> | |
10349 * This is a synthetic instruction equivalent to: {@code tdi(6, ra, si)} | |
10350 * <p> | |
10351 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
10352 * | |
10353 * @see #tdi(int, GPR, int) | |
10354 * | |
10355 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10356 */ | |
10357 // Template#: 568, Serial#: 568 | |
10358 public void tdlngi(final GPR ra, final int si) { | |
10359 int instruction = 0x08C00000; | |
10360 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
10361 instruction |= ((ra.value() & 0x1f) << 16); | |
10362 instruction |= (si & 0xffff); | |
10363 emitInt(instruction); | |
10364 } | |
10365 | |
10366 /** | |
10367 * Pseudo-external assembler syntax: {@code tdlt }<i>ra</i>, <i>rb</i> | |
10368 * Example disassembly syntax: {@code tdlt r0, r0} | |
10369 * <p> | |
10370 * This is a synthetic instruction equivalent to: {@code td(16, ra, rb)} | |
10371 * | |
10372 * @see #td(int, GPR, GPR) | |
10373 * | |
10374 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10375 */ | |
10376 // Template#: 569, Serial#: 569 | |
10377 public void tdlt(final GPR ra, final GPR rb) { | |
10378 int instruction = 0x7E000088; | |
10379 instruction |= ((ra.value() & 0x1f) << 16); | |
10380 instruction |= ((rb.value() & 0x1f) << 11); | |
10381 emitInt(instruction); | |
10382 } | |
10383 | |
10384 /** | |
10385 * Pseudo-external assembler syntax: {@code tdle }<i>ra</i>, <i>rb</i> | |
10386 * Example disassembly syntax: {@code tdle r0, r0} | |
10387 * <p> | |
10388 * This is a synthetic instruction equivalent to: {@code td(20, ra, rb)} | |
10389 * | |
10390 * @see #td(int, GPR, GPR) | |
10391 * | |
10392 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10393 */ | |
10394 // Template#: 570, Serial#: 570 | |
10395 public void tdle(final GPR ra, final GPR rb) { | |
10396 int instruction = 0x7E800088; | |
10397 instruction |= ((ra.value() & 0x1f) << 16); | |
10398 instruction |= ((rb.value() & 0x1f) << 11); | |
10399 emitInt(instruction); | |
10400 } | |
10401 | |
10402 /** | |
10403 * Pseudo-external assembler syntax: {@code tdeq }<i>ra</i>, <i>rb</i> | |
10404 * Example disassembly syntax: {@code tdeq r0, r0} | |
10405 * <p> | |
10406 * This is a synthetic instruction equivalent to: {@code td(4, ra, rb)} | |
10407 * | |
10408 * @see #td(int, GPR, GPR) | |
10409 * | |
10410 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10411 */ | |
10412 // Template#: 571, Serial#: 571 | |
10413 public void tdeq(final GPR ra, final GPR rb) { | |
10414 int instruction = 0x7C800088; | |
10415 instruction |= ((ra.value() & 0x1f) << 16); | |
10416 instruction |= ((rb.value() & 0x1f) << 11); | |
10417 emitInt(instruction); | |
10418 } | |
10419 | |
10420 /** | |
10421 * Pseudo-external assembler syntax: {@code tdge }<i>ra</i>, <i>rb</i> | |
10422 * Example disassembly syntax: {@code tdge r0, r0} | |
10423 * <p> | |
10424 * This is a synthetic instruction equivalent to: {@code td(12, ra, rb)} | |
10425 * | |
10426 * @see #td(int, GPR, GPR) | |
10427 * | |
10428 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10429 */ | |
10430 // Template#: 572, Serial#: 572 | |
10431 public void tdge(final GPR ra, final GPR rb) { | |
10432 int instruction = 0x7D800088; | |
10433 instruction |= ((ra.value() & 0x1f) << 16); | |
10434 instruction |= ((rb.value() & 0x1f) << 11); | |
10435 emitInt(instruction); | |
10436 } | |
10437 | |
10438 /** | |
10439 * Pseudo-external assembler syntax: {@code tdgt }<i>ra</i>, <i>rb</i> | |
10440 * Example disassembly syntax: {@code tdgt r0, r0} | |
10441 * <p> | |
10442 * This is a synthetic instruction equivalent to: {@code td(8, ra, rb)} | |
10443 * | |
10444 * @see #td(int, GPR, GPR) | |
10445 * | |
10446 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10447 */ | |
10448 // Template#: 573, Serial#: 573 | |
10449 public void tdgt(final GPR ra, final GPR rb) { | |
10450 int instruction = 0x7D000088; | |
10451 instruction |= ((ra.value() & 0x1f) << 16); | |
10452 instruction |= ((rb.value() & 0x1f) << 11); | |
10453 emitInt(instruction); | |
10454 } | |
10455 | |
10456 /** | |
10457 * Pseudo-external assembler syntax: {@code tdnl }<i>ra</i>, <i>rb</i> | |
10458 * Example disassembly syntax: {@code tdnl r0, r0} | |
10459 * <p> | |
10460 * This is a synthetic instruction equivalent to: {@code td(12, ra, rb)} | |
10461 * | |
10462 * @see #td(int, GPR, GPR) | |
10463 * | |
10464 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10465 */ | |
10466 // Template#: 574, Serial#: 574 | |
10467 public void tdnl(final GPR ra, final GPR rb) { | |
10468 int instruction = 0x7D800088; | |
10469 instruction |= ((ra.value() & 0x1f) << 16); | |
10470 instruction |= ((rb.value() & 0x1f) << 11); | |
10471 emitInt(instruction); | |
10472 } | |
10473 | |
10474 /** | |
10475 * Pseudo-external assembler syntax: {@code tdne }<i>ra</i>, <i>rb</i> | |
10476 * Example disassembly syntax: {@code tdne r0, r0} | |
10477 * <p> | |
10478 * This is a synthetic instruction equivalent to: {@code td(24, ra, rb)} | |
10479 * | |
10480 * @see #td(int, GPR, GPR) | |
10481 * | |
10482 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10483 */ | |
10484 // Template#: 575, Serial#: 575 | |
10485 public void tdne(final GPR ra, final GPR rb) { | |
10486 int instruction = 0x7F000088; | |
10487 instruction |= ((ra.value() & 0x1f) << 16); | |
10488 instruction |= ((rb.value() & 0x1f) << 11); | |
10489 emitInt(instruction); | |
10490 } | |
10491 | |
10492 /** | |
10493 * Pseudo-external assembler syntax: {@code tdng }<i>ra</i>, <i>rb</i> | |
10494 * Example disassembly syntax: {@code tdng r0, r0} | |
10495 * <p> | |
10496 * This is a synthetic instruction equivalent to: {@code td(20, ra, rb)} | |
10497 * | |
10498 * @see #td(int, GPR, GPR) | |
10499 * | |
10500 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10501 */ | |
10502 // Template#: 576, Serial#: 576 | |
10503 public void tdng(final GPR ra, final GPR rb) { | |
10504 int instruction = 0x7E800088; | |
10505 instruction |= ((ra.value() & 0x1f) << 16); | |
10506 instruction |= ((rb.value() & 0x1f) << 11); | |
10507 emitInt(instruction); | |
10508 } | |
10509 | |
10510 /** | |
10511 * Pseudo-external assembler syntax: {@code tdllt }<i>ra</i>, <i>rb</i> | |
10512 * Example disassembly syntax: {@code tdllt r0, r0} | |
10513 * <p> | |
10514 * This is a synthetic instruction equivalent to: {@code td(2, ra, rb)} | |
10515 * | |
10516 * @see #td(int, GPR, GPR) | |
10517 * | |
10518 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10519 */ | |
10520 // Template#: 577, Serial#: 577 | |
10521 public void tdllt(final GPR ra, final GPR rb) { | |
10522 int instruction = 0x7C400088; | |
10523 instruction |= ((ra.value() & 0x1f) << 16); | |
10524 instruction |= ((rb.value() & 0x1f) << 11); | |
10525 emitInt(instruction); | |
10526 } | |
10527 | |
10528 /** | |
10529 * Pseudo-external assembler syntax: {@code tdlle }<i>ra</i>, <i>rb</i> | |
10530 * Example disassembly syntax: {@code tdlle r0, r0} | |
10531 * <p> | |
10532 * This is a synthetic instruction equivalent to: {@code td(6, ra, rb)} | |
10533 * | |
10534 * @see #td(int, GPR, GPR) | |
10535 * | |
10536 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10537 */ | |
10538 // Template#: 578, Serial#: 578 | |
10539 public void tdlle(final GPR ra, final GPR rb) { | |
10540 int instruction = 0x7CC00088; | |
10541 instruction |= ((ra.value() & 0x1f) << 16); | |
10542 instruction |= ((rb.value() & 0x1f) << 11); | |
10543 emitInt(instruction); | |
10544 } | |
10545 | |
10546 /** | |
10547 * Pseudo-external assembler syntax: {@code tdlge }<i>ra</i>, <i>rb</i> | |
10548 * Example disassembly syntax: {@code tdlge r0, r0} | |
10549 * <p> | |
10550 * This is a synthetic instruction equivalent to: {@code td(5, ra, rb)} | |
10551 * | |
10552 * @see #td(int, GPR, GPR) | |
10553 * | |
10554 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10555 */ | |
10556 // Template#: 579, Serial#: 579 | |
10557 public void tdlge(final GPR ra, final GPR rb) { | |
10558 int instruction = 0x7CA00088; | |
10559 instruction |= ((ra.value() & 0x1f) << 16); | |
10560 instruction |= ((rb.value() & 0x1f) << 11); | |
10561 emitInt(instruction); | |
10562 } | |
10563 | |
10564 /** | |
10565 * Pseudo-external assembler syntax: {@code tdlgt }<i>ra</i>, <i>rb</i> | |
10566 * Example disassembly syntax: {@code tdlgt r0, r0} | |
10567 * <p> | |
10568 * This is a synthetic instruction equivalent to: {@code td(1, ra, rb)} | |
10569 * | |
10570 * @see #td(int, GPR, GPR) | |
10571 * | |
10572 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10573 */ | |
10574 // Template#: 580, Serial#: 580 | |
10575 public void tdlgt(final GPR ra, final GPR rb) { | |
10576 int instruction = 0x7C200088; | |
10577 instruction |= ((ra.value() & 0x1f) << 16); | |
10578 instruction |= ((rb.value() & 0x1f) << 11); | |
10579 emitInt(instruction); | |
10580 } | |
10581 | |
10582 /** | |
10583 * Pseudo-external assembler syntax: {@code tdlnl }<i>ra</i>, <i>rb</i> | |
10584 * Example disassembly syntax: {@code tdlnl r0, r0} | |
10585 * <p> | |
10586 * This is a synthetic instruction equivalent to: {@code td(5, ra, rb)} | |
10587 * | |
10588 * @see #td(int, GPR, GPR) | |
10589 * | |
10590 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10591 */ | |
10592 // Template#: 581, Serial#: 581 | |
10593 public void tdlnl(final GPR ra, final GPR rb) { | |
10594 int instruction = 0x7CA00088; | |
10595 instruction |= ((ra.value() & 0x1f) << 16); | |
10596 instruction |= ((rb.value() & 0x1f) << 11); | |
10597 emitInt(instruction); | |
10598 } | |
10599 | |
10600 /** | |
10601 * Pseudo-external assembler syntax: {@code tdlng }<i>ra</i>, <i>rb</i> | |
10602 * Example disassembly syntax: {@code tdlng r0, r0} | |
10603 * <p> | |
10604 * This is a synthetic instruction equivalent to: {@code td(6, ra, rb)} | |
10605 * | |
10606 * @see #td(int, GPR, GPR) | |
10607 * | |
10608 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.6 [Book 1]" | |
10609 */ | |
10610 // Template#: 582, Serial#: 582 | |
10611 public void tdlng(final GPR ra, final GPR rb) { | |
10612 int instruction = 0x7CC00088; | |
10613 instruction |= ((ra.value() & 0x1f) << 16); | |
10614 instruction |= ((rb.value() & 0x1f) << 11); | |
10615 emitInt(instruction); | |
10616 } | |
10617 | |
10618 /** | |
10619 * Pseudo-external assembler syntax: {@code extldi }<i>ra</i>, <i>rs</i>, <i>n</i>, <i>b</i> | |
10620 * Example disassembly syntax: {@code extldi r0, r0, 0x0, 0x0} | |
10621 * <p> | |
10622 * This is a synthetic instruction equivalent to: {@code rldicr(ra, rs, b, n - 1)} | |
10623 * <p> | |
10624 * Constraint: {@code 0 <= b && b <= 63}<br /> | |
10625 * Constraint: {@code 0 <= n - 1 && n - 1 <= 63}<br /> | |
10626 * | |
10627 * @see #rldicr(GPR, GPR, int, int) | |
10628 * | |
10629 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10630 */ | |
10631 // Template#: 583, Serial#: 583 | |
10632 public void extldi(final GPR ra, final GPR rs, final int n, final int b) { | |
10633 int instruction = 0x78000004; | |
10634 checkConstraint(0 <= b && b <= 63, "0 <= b && b <= 63"); | |
10635 checkConstraint(0 <= n - 1 && n - 1 <= 63, "0 <= n - 1 && n - 1 <= 63"); | |
10636 instruction |= ((ra.value() & 0x1f) << 16); | |
10637 instruction |= ((rs.value() & 0x1f) << 21); | |
10638 instruction |= ((b & 0x1f) << 11) | (((b >>> 5) & 0x1) << 1); | |
10639 instruction |= ((n - 1 & 0x1f) << 6) | (((n - 1 >>> 5) & 0x1) << 5); | |
10640 emitInt(instruction); | |
10641 } | |
10642 | |
10643 /** | |
10644 * Pseudo-external assembler syntax: {@code extldi. }<i>ra</i>, <i>rs</i>, <i>n</i>, <i>b</i> | |
10645 * Example disassembly syntax: {@code extldi. r0, r0, 0x0, 0x0} | |
10646 * <p> | |
10647 * This is a synthetic instruction equivalent to: {@code rldicr_(ra, rs, b, n - 1)} | |
10648 * <p> | |
10649 * Constraint: {@code 0 <= b && b <= 63}<br /> | |
10650 * Constraint: {@code 0 <= n - 1 && n - 1 <= 63}<br /> | |
10651 * | |
10652 * @see #rldicr_(GPR, GPR, int, int) | |
10653 * | |
10654 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10655 */ | |
10656 // Template#: 584, Serial#: 584 | |
10657 public void extldi_(final GPR ra, final GPR rs, final int n, final int b) { | |
10658 int instruction = 0x78000005; | |
10659 checkConstraint(0 <= b && b <= 63, "0 <= b && b <= 63"); | |
10660 checkConstraint(0 <= n - 1 && n - 1 <= 63, "0 <= n - 1 && n - 1 <= 63"); | |
10661 instruction |= ((ra.value() & 0x1f) << 16); | |
10662 instruction |= ((rs.value() & 0x1f) << 21); | |
10663 instruction |= ((b & 0x1f) << 11) | (((b >>> 5) & 0x1) << 1); | |
10664 instruction |= ((n - 1 & 0x1f) << 6) | (((n - 1 >>> 5) & 0x1) << 5); | |
10665 emitInt(instruction); | |
10666 } | |
10667 | |
10668 /** | |
10669 * Pseudo-external assembler syntax: {@code extrdi }<i>ra</i>, <i>rs</i>, <i>n</i>, <i>b</i> | |
10670 * Example disassembly syntax: {@code extrdi r0, r0, 0x0, 0x0} | |
10671 * <p> | |
10672 * This is a synthetic instruction equivalent to: {@code rldicl(ra, rs, b + n, 64 - n)} | |
10673 * <p> | |
10674 * Constraint: {@code 0 <= b + n && b + n <= 63}<br /> | |
10675 * Constraint: {@code 0 <= 64 - n && 64 - n <= 63}<br /> | |
10676 * | |
10677 * @see #rldicl(GPR, GPR, int, int) | |
10678 * | |
10679 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10680 */ | |
10681 // Template#: 585, Serial#: 585 | |
10682 public void extrdi(final GPR ra, final GPR rs, final int n, final int b) { | |
10683 int instruction = 0x78000000; | |
10684 checkConstraint(0 <= b + n && b + n <= 63, "0 <= b + n && b + n <= 63"); | |
10685 checkConstraint(0 <= 64 - n && 64 - n <= 63, "0 <= 64 - n && 64 - n <= 63"); | |
10686 instruction |= ((ra.value() & 0x1f) << 16); | |
10687 instruction |= ((rs.value() & 0x1f) << 21); | |
10688 instruction |= ((b + n & 0x1f) << 11) | (((b + n >>> 5) & 0x1) << 1); | |
10689 instruction |= ((64 - n & 0x1f) << 6) | (((64 - n >>> 5) & 0x1) << 5); | |
10690 emitInt(instruction); | |
10691 } | |
10692 | |
10693 /** | |
10694 * Pseudo-external assembler syntax: {@code extrdi. }<i>ra</i>, <i>rs</i>, <i>n</i>, <i>b</i> | |
10695 * Example disassembly syntax: {@code extrdi. r0, r0, 0x0, 0x0} | |
10696 * <p> | |
10697 * This is a synthetic instruction equivalent to: {@code rldicl_(ra, rs, b + n, 64 - n)} | |
10698 * <p> | |
10699 * Constraint: {@code 0 <= b + n && b + n <= 63}<br /> | |
10700 * Constraint: {@code 0 <= 64 - n && 64 - n <= 63}<br /> | |
10701 * | |
10702 * @see #rldicl_(GPR, GPR, int, int) | |
10703 * | |
10704 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10705 */ | |
10706 // Template#: 586, Serial#: 586 | |
10707 public void extrdi_(final GPR ra, final GPR rs, final int n, final int b) { | |
10708 int instruction = 0x78000001; | |
10709 checkConstraint(0 <= b + n && b + n <= 63, "0 <= b + n && b + n <= 63"); | |
10710 checkConstraint(0 <= 64 - n && 64 - n <= 63, "0 <= 64 - n && 64 - n <= 63"); | |
10711 instruction |= ((ra.value() & 0x1f) << 16); | |
10712 instruction |= ((rs.value() & 0x1f) << 21); | |
10713 instruction |= ((b + n & 0x1f) << 11) | (((b + n >>> 5) & 0x1) << 1); | |
10714 instruction |= ((64 - n & 0x1f) << 6) | (((64 - n >>> 5) & 0x1) << 5); | |
10715 emitInt(instruction); | |
10716 } | |
10717 | |
10718 /** | |
10719 * Pseudo-external assembler syntax: {@code insrdi }<i>ra</i>, <i>rs</i>, <i>n</i>, <i>b</i> | |
10720 * Example disassembly syntax: {@code insrdi r0, r0, 0x0, 0x0} | |
10721 * <p> | |
10722 * This is a synthetic instruction equivalent to: {@code rldimi(ra, rs, 64 - (b + n), b)} | |
10723 * <p> | |
10724 * Constraint: {@code 0 <= 64 - (b + n) && 64 - (b + n) <= 63}<br /> | |
10725 * Constraint: {@code 0 <= b && b <= 63}<br /> | |
10726 * | |
10727 * @see #rldimi(GPR, GPR, int, int) | |
10728 * | |
10729 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10730 */ | |
10731 // Template#: 587, Serial#: 587 | |
10732 public void insrdi(final GPR ra, final GPR rs, final int n, final int b) { | |
10733 int instruction = 0x7800000C; | |
10734 checkConstraint(0 <= 64 - (b + n) && 64 - (b + n) <= 63, "0 <= 64 - (b + n) && 64 - (b + n) <= 63"); | |
10735 checkConstraint(0 <= b && b <= 63, "0 <= b && b <= 63"); | |
10736 instruction |= ((ra.value() & 0x1f) << 16); | |
10737 instruction |= ((rs.value() & 0x1f) << 21); | |
10738 instruction |= ((64 - (b + n) & 0x1f) << 11) | (((64 - (b + n) >>> 5) & 0x1) << 1); | |
10739 instruction |= ((b & 0x1f) << 6) | (((b >>> 5) & 0x1) << 5); | |
10740 emitInt(instruction); | |
10741 } | |
10742 | |
10743 /** | |
10744 * Pseudo-external assembler syntax: {@code insrdi. }<i>ra</i>, <i>rs</i>, <i>n</i>, <i>b</i> | |
10745 * Example disassembly syntax: {@code insrdi. r0, r0, 0x0, 0x0} | |
10746 * <p> | |
10747 * This is a synthetic instruction equivalent to: {@code rldimi_(ra, rs, 64 - (b + n), b)} | |
10748 * <p> | |
10749 * Constraint: {@code 0 <= 64 - (b + n) && 64 - (b + n) <= 63}<br /> | |
10750 * Constraint: {@code 0 <= b && b <= 63}<br /> | |
10751 * | |
10752 * @see #rldimi_(GPR, GPR, int, int) | |
10753 * | |
10754 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10755 */ | |
10756 // Template#: 588, Serial#: 588 | |
10757 public void insrdi_(final GPR ra, final GPR rs, final int n, final int b) { | |
10758 int instruction = 0x7800000D; | |
10759 checkConstraint(0 <= 64 - (b + n) && 64 - (b + n) <= 63, "0 <= 64 - (b + n) && 64 - (b + n) <= 63"); | |
10760 checkConstraint(0 <= b && b <= 63, "0 <= b && b <= 63"); | |
10761 instruction |= ((ra.value() & 0x1f) << 16); | |
10762 instruction |= ((rs.value() & 0x1f) << 21); | |
10763 instruction |= ((64 - (b + n) & 0x1f) << 11) | (((64 - (b + n) >>> 5) & 0x1) << 1); | |
10764 instruction |= ((b & 0x1f) << 6) | (((b >>> 5) & 0x1) << 5); | |
10765 emitInt(instruction); | |
10766 } | |
10767 | |
10768 /** | |
10769 * Pseudo-external assembler syntax: {@code rotldi }<i>ra</i>, <i>rs</i>, <i>n</i> | |
10770 * Example disassembly syntax: {@code rotldi r0, r0, 0x0} | |
10771 * <p> | |
10772 * This is a synthetic instruction equivalent to: {@code rldicl(ra, rs, n, 0)} | |
10773 * <p> | |
10774 * Constraint: {@code 0 <= n && n <= 63}<br /> | |
10775 * | |
10776 * @see #rldicl(GPR, GPR, int, int) | |
10777 * | |
10778 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10779 */ | |
10780 // Template#: 589, Serial#: 589 | |
10781 public void rotldi(final GPR ra, final GPR rs, final int n) { | |
10782 int instruction = 0x78000000; | |
10783 checkConstraint(0 <= n && n <= 63, "0 <= n && n <= 63"); | |
10784 instruction |= ((ra.value() & 0x1f) << 16); | |
10785 instruction |= ((rs.value() & 0x1f) << 21); | |
10786 instruction |= ((n & 0x1f) << 11) | (((n >>> 5) & 0x1) << 1); | |
10787 emitInt(instruction); | |
10788 } | |
10789 | |
10790 /** | |
10791 * Pseudo-external assembler syntax: {@code rotldi. }<i>ra</i>, <i>rs</i>, <i>n</i> | |
10792 * Example disassembly syntax: {@code rotldi. r0, r0, 0x0} | |
10793 * <p> | |
10794 * This is a synthetic instruction equivalent to: {@code rldicl_(ra, rs, n, 0)} | |
10795 * <p> | |
10796 * Constraint: {@code 0 <= n && n <= 63}<br /> | |
10797 * | |
10798 * @see #rldicl_(GPR, GPR, int, int) | |
10799 * | |
10800 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10801 */ | |
10802 // Template#: 590, Serial#: 590 | |
10803 public void rotldi_(final GPR ra, final GPR rs, final int n) { | |
10804 int instruction = 0x78000001; | |
10805 checkConstraint(0 <= n && n <= 63, "0 <= n && n <= 63"); | |
10806 instruction |= ((ra.value() & 0x1f) << 16); | |
10807 instruction |= ((rs.value() & 0x1f) << 21); | |
10808 instruction |= ((n & 0x1f) << 11) | (((n >>> 5) & 0x1) << 1); | |
10809 emitInt(instruction); | |
10810 } | |
10811 | |
10812 /** | |
10813 * Pseudo-external assembler syntax: {@code rotrdi }<i>ra</i>, <i>rs</i>, <i>n</i> | |
10814 * Example disassembly syntax: {@code rotrdi r0, r0, 0x0} | |
10815 * <p> | |
10816 * This is a synthetic instruction equivalent to: {@code rldicl(ra, rs, 64 - n, 0)} | |
10817 * <p> | |
10818 * Constraint: {@code 0 <= 64 - n && 64 - n <= 63}<br /> | |
10819 * | |
10820 * @see #rldicl(GPR, GPR, int, int) | |
10821 * | |
10822 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10823 */ | |
10824 // Template#: 591, Serial#: 591 | |
10825 public void rotrdi(final GPR ra, final GPR rs, final int n) { | |
10826 int instruction = 0x78000000; | |
10827 checkConstraint(0 <= 64 - n && 64 - n <= 63, "0 <= 64 - n && 64 - n <= 63"); | |
10828 instruction |= ((ra.value() & 0x1f) << 16); | |
10829 instruction |= ((rs.value() & 0x1f) << 21); | |
10830 instruction |= ((64 - n & 0x1f) << 11) | (((64 - n >>> 5) & 0x1) << 1); | |
10831 emitInt(instruction); | |
10832 } | |
10833 | |
10834 /** | |
10835 * Pseudo-external assembler syntax: {@code rotrdi. }<i>ra</i>, <i>rs</i>, <i>n</i> | |
10836 * Example disassembly syntax: {@code rotrdi. r0, r0, 0x0} | |
10837 * <p> | |
10838 * This is a synthetic instruction equivalent to: {@code rldicl_(ra, rs, 64 - n, 0)} | |
10839 * <p> | |
10840 * Constraint: {@code 0 <= 64 - n && 64 - n <= 63}<br /> | |
10841 * | |
10842 * @see #rldicl_(GPR, GPR, int, int) | |
10843 * | |
10844 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10845 */ | |
10846 // Template#: 592, Serial#: 592 | |
10847 public void rotrdi_(final GPR ra, final GPR rs, final int n) { | |
10848 int instruction = 0x78000001; | |
10849 checkConstraint(0 <= 64 - n && 64 - n <= 63, "0 <= 64 - n && 64 - n <= 63"); | |
10850 instruction |= ((ra.value() & 0x1f) << 16); | |
10851 instruction |= ((rs.value() & 0x1f) << 21); | |
10852 instruction |= ((64 - n & 0x1f) << 11) | (((64 - n >>> 5) & 0x1) << 1); | |
10853 emitInt(instruction); | |
10854 } | |
10855 | |
10856 /** | |
10857 * Pseudo-external assembler syntax: {@code rotld }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
10858 * Example disassembly syntax: {@code rotld r0, r0, r0} | |
10859 * <p> | |
10860 * This is a synthetic instruction equivalent to: {@code rldcl(ra, rs, rb, 0)} | |
10861 * | |
10862 * @see #rldcl(GPR, GPR, GPR, int) | |
10863 * | |
10864 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10865 */ | |
10866 // Template#: 593, Serial#: 593 | |
10867 public void rotld(final GPR ra, final GPR rs, final GPR rb) { | |
10868 int instruction = 0x78000010; | |
10869 instruction |= ((ra.value() & 0x1f) << 16); | |
10870 instruction |= ((rs.value() & 0x1f) << 21); | |
10871 instruction |= ((rb.value() & 0x1f) << 11); | |
10872 emitInt(instruction); | |
10873 } | |
10874 | |
10875 /** | |
10876 * Pseudo-external assembler syntax: {@code rotld. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
10877 * Example disassembly syntax: {@code rotld. r0, r0, r0} | |
10878 * <p> | |
10879 * This is a synthetic instruction equivalent to: {@code rldcl_(ra, rs, rb, 0)} | |
10880 * | |
10881 * @see #rldcl_(GPR, GPR, GPR, int) | |
10882 * | |
10883 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10884 */ | |
10885 // Template#: 594, Serial#: 594 | |
10886 public void rotld_(final GPR ra, final GPR rs, final GPR rb) { | |
10887 int instruction = 0x78000011; | |
10888 instruction |= ((ra.value() & 0x1f) << 16); | |
10889 instruction |= ((rs.value() & 0x1f) << 21); | |
10890 instruction |= ((rb.value() & 0x1f) << 11); | |
10891 emitInt(instruction); | |
10892 } | |
10893 | |
10894 /** | |
10895 * Pseudo-external assembler syntax: {@code sldi }<i>ra</i>, <i>rs</i>, <i>n</i> | |
10896 * Example disassembly syntax: {@code sldi r0, r0, 0x0} | |
10897 * <p> | |
10898 * This is a synthetic instruction equivalent to: {@code rldicr(ra, rs, n, 63 - n)} | |
10899 * <p> | |
10900 * Constraint: {@code 0 <= n && n <= 63}<br /> | |
10901 * Constraint: {@code 0 <= 63 - n && 63 - n <= 63}<br /> | |
10902 * | |
10903 * @see #rldicr(GPR, GPR, int, int) | |
10904 * | |
10905 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10906 */ | |
10907 // Template#: 595, Serial#: 595 | |
10908 public void sldi(final GPR ra, final GPR rs, final int n) { | |
10909 int instruction = 0x78000004; | |
10910 checkConstraint(0 <= n && n <= 63, "0 <= n && n <= 63"); | |
10911 checkConstraint(0 <= 63 - n && 63 - n <= 63, "0 <= 63 - n && 63 - n <= 63"); | |
10912 instruction |= ((ra.value() & 0x1f) << 16); | |
10913 instruction |= ((rs.value() & 0x1f) << 21); | |
10914 instruction |= ((n & 0x1f) << 11) | (((n >>> 5) & 0x1) << 1); | |
10915 instruction |= ((63 - n & 0x1f) << 6) | (((63 - n >>> 5) & 0x1) << 5); | |
10916 emitInt(instruction); | |
10917 } | |
10918 | |
10919 /** | |
10920 * Pseudo-external assembler syntax: {@code sldi. }<i>ra</i>, <i>rs</i>, <i>n</i> | |
10921 * Example disassembly syntax: {@code sldi. r0, r0, 0x0} | |
10922 * <p> | |
10923 * This is a synthetic instruction equivalent to: {@code rldicr_(ra, rs, n, 63 - n)} | |
10924 * <p> | |
10925 * Constraint: {@code 0 <= n && n <= 63}<br /> | |
10926 * Constraint: {@code 0 <= 63 - n && 63 - n <= 63}<br /> | |
10927 * | |
10928 * @see #rldicr_(GPR, GPR, int, int) | |
10929 * | |
10930 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10931 */ | |
10932 // Template#: 596, Serial#: 596 | |
10933 public void sldi_(final GPR ra, final GPR rs, final int n) { | |
10934 int instruction = 0x78000005; | |
10935 checkConstraint(0 <= n && n <= 63, "0 <= n && n <= 63"); | |
10936 checkConstraint(0 <= 63 - n && 63 - n <= 63, "0 <= 63 - n && 63 - n <= 63"); | |
10937 instruction |= ((ra.value() & 0x1f) << 16); | |
10938 instruction |= ((rs.value() & 0x1f) << 21); | |
10939 instruction |= ((n & 0x1f) << 11) | (((n >>> 5) & 0x1) << 1); | |
10940 instruction |= ((63 - n & 0x1f) << 6) | (((63 - n >>> 5) & 0x1) << 5); | |
10941 emitInt(instruction); | |
10942 } | |
10943 | |
10944 /** | |
10945 * Pseudo-external assembler syntax: {@code srdi }<i>ra</i>, <i>rs</i>, <i>n</i> | |
10946 * Example disassembly syntax: {@code srdi r0, r0, 0x0} | |
10947 * <p> | |
10948 * This is a synthetic instruction equivalent to: {@code rldicl(ra, rs, 64 - n, n)} | |
10949 * <p> | |
10950 * Constraint: {@code 0 <= 64 - n && 64 - n <= 63}<br /> | |
10951 * Constraint: {@code 0 <= n && n <= 63}<br /> | |
10952 * | |
10953 * @see #rldicl(GPR, GPR, int, int) | |
10954 * | |
10955 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10956 */ | |
10957 // Template#: 597, Serial#: 597 | |
10958 public void srdi(final GPR ra, final GPR rs, final int n) { | |
10959 int instruction = 0x78000000; | |
10960 checkConstraint(0 <= 64 - n && 64 - n <= 63, "0 <= 64 - n && 64 - n <= 63"); | |
10961 checkConstraint(0 <= n && n <= 63, "0 <= n && n <= 63"); | |
10962 instruction |= ((ra.value() & 0x1f) << 16); | |
10963 instruction |= ((rs.value() & 0x1f) << 21); | |
10964 instruction |= ((64 - n & 0x1f) << 11) | (((64 - n >>> 5) & 0x1) << 1); | |
10965 instruction |= ((n & 0x1f) << 6) | (((n >>> 5) & 0x1) << 5); | |
10966 emitInt(instruction); | |
10967 } | |
10968 | |
10969 /** | |
10970 * Pseudo-external assembler syntax: {@code srdi. }<i>ra</i>, <i>rs</i>, <i>n</i> | |
10971 * Example disassembly syntax: {@code srdi. r0, r0, 0x0} | |
10972 * <p> | |
10973 * This is a synthetic instruction equivalent to: {@code rldicl_(ra, rs, 64 - n, n)} | |
10974 * <p> | |
10975 * Constraint: {@code 0 <= 64 - n && 64 - n <= 63}<br /> | |
10976 * Constraint: {@code 0 <= n && n <= 63}<br /> | |
10977 * | |
10978 * @see #rldicl_(GPR, GPR, int, int) | |
10979 * | |
10980 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
10981 */ | |
10982 // Template#: 598, Serial#: 598 | |
10983 public void srdi_(final GPR ra, final GPR rs, final int n) { | |
10984 int instruction = 0x78000001; | |
10985 checkConstraint(0 <= 64 - n && 64 - n <= 63, "0 <= 64 - n && 64 - n <= 63"); | |
10986 checkConstraint(0 <= n && n <= 63, "0 <= n && n <= 63"); | |
10987 instruction |= ((ra.value() & 0x1f) << 16); | |
10988 instruction |= ((rs.value() & 0x1f) << 21); | |
10989 instruction |= ((64 - n & 0x1f) << 11) | (((64 - n >>> 5) & 0x1) << 1); | |
10990 instruction |= ((n & 0x1f) << 6) | (((n >>> 5) & 0x1) << 5); | |
10991 emitInt(instruction); | |
10992 } | |
10993 | |
10994 /** | |
10995 * Pseudo-external assembler syntax: {@code clrldi }<i>ra</i>, <i>rs</i>, <i>n</i> | |
10996 * Example disassembly syntax: {@code clrldi r0, r0, 0x0} | |
10997 * <p> | |
10998 * This is a synthetic instruction equivalent to: {@code rldicl(ra, rs, 0, n)} | |
10999 * <p> | |
11000 * Constraint: {@code 0 <= n && n <= 63}<br /> | |
11001 * | |
11002 * @see #rldicl(GPR, GPR, int, int) | |
11003 * | |
11004 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
11005 */ | |
11006 // Template#: 599, Serial#: 599 | |
11007 public void clrldi(final GPR ra, final GPR rs, final int n) { | |
11008 int instruction = 0x78000000; | |
11009 checkConstraint(0 <= n && n <= 63, "0 <= n && n <= 63"); | |
11010 instruction |= ((ra.value() & 0x1f) << 16); | |
11011 instruction |= ((rs.value() & 0x1f) << 21); | |
11012 instruction |= ((n & 0x1f) << 6) | (((n >>> 5) & 0x1) << 5); | |
11013 emitInt(instruction); | |
11014 } | |
11015 | |
11016 /** | |
11017 * Pseudo-external assembler syntax: {@code clrldi. }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11018 * Example disassembly syntax: {@code clrldi. r0, r0, 0x0} | |
11019 * <p> | |
11020 * This is a synthetic instruction equivalent to: {@code rldicl_(ra, rs, 0, n)} | |
11021 * <p> | |
11022 * Constraint: {@code 0 <= n && n <= 63}<br /> | |
11023 * | |
11024 * @see #rldicl_(GPR, GPR, int, int) | |
11025 * | |
11026 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
11027 */ | |
11028 // Template#: 600, Serial#: 600 | |
11029 public void clrldi_(final GPR ra, final GPR rs, final int n) { | |
11030 int instruction = 0x78000001; | |
11031 checkConstraint(0 <= n && n <= 63, "0 <= n && n <= 63"); | |
11032 instruction |= ((ra.value() & 0x1f) << 16); | |
11033 instruction |= ((rs.value() & 0x1f) << 21); | |
11034 instruction |= ((n & 0x1f) << 6) | (((n >>> 5) & 0x1) << 5); | |
11035 emitInt(instruction); | |
11036 } | |
11037 | |
11038 /** | |
11039 * Pseudo-external assembler syntax: {@code clrrdi }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11040 * Example disassembly syntax: {@code clrrdi r0, r0, 0x0} | |
11041 * <p> | |
11042 * This is a synthetic instruction equivalent to: {@code rldicr(ra, rs, 0, 63 - n)} | |
11043 * <p> | |
11044 * Constraint: {@code 0 <= 63 - n && 63 - n <= 63}<br /> | |
11045 * | |
11046 * @see #rldicr(GPR, GPR, int, int) | |
11047 * | |
11048 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
11049 */ | |
11050 // Template#: 601, Serial#: 601 | |
11051 public void clrrdi(final GPR ra, final GPR rs, final int n) { | |
11052 int instruction = 0x78000004; | |
11053 checkConstraint(0 <= 63 - n && 63 - n <= 63, "0 <= 63 - n && 63 - n <= 63"); | |
11054 instruction |= ((ra.value() & 0x1f) << 16); | |
11055 instruction |= ((rs.value() & 0x1f) << 21); | |
11056 instruction |= ((63 - n & 0x1f) << 6) | (((63 - n >>> 5) & 0x1) << 5); | |
11057 emitInt(instruction); | |
11058 } | |
11059 | |
11060 /** | |
11061 * Pseudo-external assembler syntax: {@code clrrdi. }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11062 * Example disassembly syntax: {@code clrrdi. r0, r0, 0x0} | |
11063 * <p> | |
11064 * This is a synthetic instruction equivalent to: {@code rldicr_(ra, rs, 0, 63 - n)} | |
11065 * <p> | |
11066 * Constraint: {@code 0 <= 63 - n && 63 - n <= 63}<br /> | |
11067 * | |
11068 * @see #rldicr_(GPR, GPR, int, int) | |
11069 * | |
11070 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
11071 */ | |
11072 // Template#: 602, Serial#: 602 | |
11073 public void clrrdi_(final GPR ra, final GPR rs, final int n) { | |
11074 int instruction = 0x78000005; | |
11075 checkConstraint(0 <= 63 - n && 63 - n <= 63, "0 <= 63 - n && 63 - n <= 63"); | |
11076 instruction |= ((ra.value() & 0x1f) << 16); | |
11077 instruction |= ((rs.value() & 0x1f) << 21); | |
11078 instruction |= ((63 - n & 0x1f) << 6) | (((63 - n >>> 5) & 0x1) << 5); | |
11079 emitInt(instruction); | |
11080 } | |
11081 | |
11082 /** | |
11083 * Pseudo-external assembler syntax: {@code clrlsldi }<i>ra</i>, <i>rs</i>, <i>b</i>, <i>n</i> | |
11084 * Example disassembly syntax: {@code clrlsldi r0, r0, 0x0, 0x0} | |
11085 * <p> | |
11086 * This is a synthetic instruction equivalent to: {@code rldic(ra, rs, n, b - n)} | |
11087 * <p> | |
11088 * Constraint: {@code 0 <= n && n <= 63}<br /> | |
11089 * Constraint: {@code 0 <= b - n && b - n <= 63}<br /> | |
11090 * | |
11091 * @see #rldic(GPR, GPR, int, int) | |
11092 * | |
11093 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
11094 */ | |
11095 // Template#: 603, Serial#: 603 | |
11096 public void clrlsldi(final GPR ra, final GPR rs, final int b, final int n) { | |
11097 int instruction = 0x78000008; | |
11098 checkConstraint(0 <= n && n <= 63, "0 <= n && n <= 63"); | |
11099 checkConstraint(0 <= b - n && b - n <= 63, "0 <= b - n && b - n <= 63"); | |
11100 instruction |= ((ra.value() & 0x1f) << 16); | |
11101 instruction |= ((rs.value() & 0x1f) << 21); | |
11102 instruction |= ((n & 0x1f) << 11) | (((n >>> 5) & 0x1) << 1); | |
11103 instruction |= ((b - n & 0x1f) << 6) | (((b - n >>> 5) & 0x1) << 5); | |
11104 emitInt(instruction); | |
11105 } | |
11106 | |
11107 /** | |
11108 * Pseudo-external assembler syntax: {@code clrlsldi. }<i>ra</i>, <i>rs</i>, <i>b</i>, <i>n</i> | |
11109 * Example disassembly syntax: {@code clrlsldi. r0, r0, 0x0, 0x0} | |
11110 * <p> | |
11111 * This is a synthetic instruction equivalent to: {@code rldic_(ra, rs, n, b - n)} | |
11112 * <p> | |
11113 * Constraint: {@code 0 <= n && n <= 63}<br /> | |
11114 * Constraint: {@code 0 <= b - n && b - n <= 63}<br /> | |
11115 * | |
11116 * @see #rldic_(GPR, GPR, int, int) | |
11117 * | |
11118 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.1 [Book 1]" | |
11119 */ | |
11120 // Template#: 604, Serial#: 604 | |
11121 public void clrlsldi_(final GPR ra, final GPR rs, final int b, final int n) { | |
11122 int instruction = 0x78000009; | |
11123 checkConstraint(0 <= n && n <= 63, "0 <= n && n <= 63"); | |
11124 checkConstraint(0 <= b - n && b - n <= 63, "0 <= b - n && b - n <= 63"); | |
11125 instruction |= ((ra.value() & 0x1f) << 16); | |
11126 instruction |= ((rs.value() & 0x1f) << 21); | |
11127 instruction |= ((n & 0x1f) << 11) | (((n >>> 5) & 0x1) << 1); | |
11128 instruction |= ((b - n & 0x1f) << 6) | (((b - n >>> 5) & 0x1) << 5); | |
11129 emitInt(instruction); | |
11130 } | |
11131 | |
11132 /** | |
11133 * Pseudo-external assembler syntax: {@code extlwi }<i>ra</i>, <i>rs</i>, <i>n</i>, <i>b</i> | |
11134 * Example disassembly syntax: {@code extlwi r0, r0, 0x0, 0x0} | |
11135 * <p> | |
11136 * This is a synthetic instruction equivalent to: {@code rlwinm(ra, rs, b, 0, n - 1)} | |
11137 * <p> | |
11138 * Constraint: {@code 0 <= b && b <= 31}<br /> | |
11139 * Constraint: {@code 0 <= n - 1 && n - 1 <= 31}<br /> | |
11140 * Constraint: {@code n > 0}<br /> | |
11141 * | |
11142 * @see #rlwinm(GPR, GPR, int, int, int) | |
11143 * | |
11144 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11145 */ | |
11146 // Template#: 605, Serial#: 605 | |
11147 public void extlwi(final GPR ra, final GPR rs, final int n, final int b) { | |
11148 int instruction = 0x54000000; | |
11149 checkConstraint(0 <= b && b <= 31, "0 <= b && b <= 31"); | |
11150 checkConstraint(0 <= n - 1 && n - 1 <= 31, "0 <= n - 1 && n - 1 <= 31"); | |
11151 checkConstraint(n > 0, "n > 0"); | |
11152 instruction |= ((ra.value() & 0x1f) << 16); | |
11153 instruction |= ((rs.value() & 0x1f) << 21); | |
11154 instruction |= ((b & 0x1f) << 11); | |
11155 instruction |= ((n - 1 & 0x1f) << 1); | |
11156 emitInt(instruction); | |
11157 } | |
11158 | |
11159 /** | |
11160 * Pseudo-external assembler syntax: {@code extlwi. }<i>ra</i>, <i>rs</i>, <i>n</i>, <i>b</i> | |
11161 * Example disassembly syntax: {@code extlwi. r0, r0, 0x0, 0x0} | |
11162 * <p> | |
11163 * This is a synthetic instruction equivalent to: {@code rlwinm_(ra, rs, b, 0, n - 1)} | |
11164 * <p> | |
11165 * Constraint: {@code 0 <= b && b <= 31}<br /> | |
11166 * Constraint: {@code 0 <= n - 1 && n - 1 <= 31}<br /> | |
11167 * Constraint: {@code n > 0}<br /> | |
11168 * | |
11169 * @see #rlwinm_(GPR, GPR, int, int, int) | |
11170 * | |
11171 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11172 */ | |
11173 // Template#: 606, Serial#: 606 | |
11174 public void extlwi_(final GPR ra, final GPR rs, final int n, final int b) { | |
11175 int instruction = 0x54000001; | |
11176 checkConstraint(0 <= b && b <= 31, "0 <= b && b <= 31"); | |
11177 checkConstraint(0 <= n - 1 && n - 1 <= 31, "0 <= n - 1 && n - 1 <= 31"); | |
11178 checkConstraint(n > 0, "n > 0"); | |
11179 instruction |= ((ra.value() & 0x1f) << 16); | |
11180 instruction |= ((rs.value() & 0x1f) << 21); | |
11181 instruction |= ((b & 0x1f) << 11); | |
11182 instruction |= ((n - 1 & 0x1f) << 1); | |
11183 emitInt(instruction); | |
11184 } | |
11185 | |
11186 /** | |
11187 * Pseudo-external assembler syntax: {@code extrwi }<i>ra</i>, <i>rs</i>, <i>n</i>, <i>b</i> | |
11188 * Example disassembly syntax: {@code extrwi r0, r0, 0x0, 0x0} | |
11189 * <p> | |
11190 * This is a synthetic instruction equivalent to: {@code rlwinm(ra, rs, b + n, 32 - n, 31)} | |
11191 * <p> | |
11192 * Constraint: {@code 0 <= b + n && b + n <= 31}<br /> | |
11193 * Constraint: {@code 0 <= 32 - n && 32 - n <= 31}<br /> | |
11194 * Constraint: {@code n > 0}<br /> | |
11195 * | |
11196 * @see #rlwinm(GPR, GPR, int, int, int) | |
11197 * | |
11198 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11199 */ | |
11200 // Template#: 607, Serial#: 607 | |
11201 public void extrwi(final GPR ra, final GPR rs, final int n, final int b) { | |
11202 int instruction = 0x5400003E; | |
11203 checkConstraint(0 <= b + n && b + n <= 31, "0 <= b + n && b + n <= 31"); | |
11204 checkConstraint(0 <= 32 - n && 32 - n <= 31, "0 <= 32 - n && 32 - n <= 31"); | |
11205 checkConstraint(n > 0, "n > 0"); | |
11206 instruction |= ((ra.value() & 0x1f) << 16); | |
11207 instruction |= ((rs.value() & 0x1f) << 21); | |
11208 instruction |= ((b + n & 0x1f) << 11); | |
11209 instruction |= ((32 - n & 0x1f) << 6); | |
11210 emitInt(instruction); | |
11211 } | |
11212 | |
11213 /** | |
11214 * Pseudo-external assembler syntax: {@code extrwi. }<i>ra</i>, <i>rs</i>, <i>n</i>, <i>b</i> | |
11215 * Example disassembly syntax: {@code extrwi. r0, r0, 0x0, 0x0} | |
11216 * <p> | |
11217 * This is a synthetic instruction equivalent to: {@code rlwinm_(ra, rs, b + n, 32 - n, 31)} | |
11218 * <p> | |
11219 * Constraint: {@code 0 <= b + n && b + n <= 31}<br /> | |
11220 * Constraint: {@code 0 <= 32 - n && 32 - n <= 31}<br /> | |
11221 * Constraint: {@code n > 0}<br /> | |
11222 * | |
11223 * @see #rlwinm_(GPR, GPR, int, int, int) | |
11224 * | |
11225 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11226 */ | |
11227 // Template#: 608, Serial#: 608 | |
11228 public void extrwi_(final GPR ra, final GPR rs, final int n, final int b) { | |
11229 int instruction = 0x5400003F; | |
11230 checkConstraint(0 <= b + n && b + n <= 31, "0 <= b + n && b + n <= 31"); | |
11231 checkConstraint(0 <= 32 - n && 32 - n <= 31, "0 <= 32 - n && 32 - n <= 31"); | |
11232 checkConstraint(n > 0, "n > 0"); | |
11233 instruction |= ((ra.value() & 0x1f) << 16); | |
11234 instruction |= ((rs.value() & 0x1f) << 21); | |
11235 instruction |= ((b + n & 0x1f) << 11); | |
11236 instruction |= ((32 - n & 0x1f) << 6); | |
11237 emitInt(instruction); | |
11238 } | |
11239 | |
11240 /** | |
11241 * Pseudo-external assembler syntax: {@code inslwi }<i>ra</i>, <i>rs</i>, <i>n</i>, <i>b</i> | |
11242 * Example disassembly syntax: {@code inslwi r0, r0, 0x0, 0x0} | |
11243 * <p> | |
11244 * This is a synthetic instruction equivalent to: {@code rlwimi(ra, rs, 32 - b, b, (b + n) - 1)} | |
11245 * <p> | |
11246 * Constraint: {@code 0 <= 32 - b && 32 - b <= 31}<br /> | |
11247 * Constraint: {@code 0 <= b && b <= 31}<br /> | |
11248 * Constraint: {@code 0 <= (b + n) - 1 && (b + n) - 1 <= 31}<br /> | |
11249 * Constraint: {@code n > 0}<br /> | |
11250 * | |
11251 * @see #rlwimi(GPR, GPR, int, int, int) | |
11252 * | |
11253 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11254 */ | |
11255 // Template#: 609, Serial#: 609 | |
11256 public void inslwi(final GPR ra, final GPR rs, final int n, final int b) { | |
11257 int instruction = 0x50000000; | |
11258 checkConstraint(0 <= 32 - b && 32 - b <= 31, "0 <= 32 - b && 32 - b <= 31"); | |
11259 checkConstraint(0 <= b && b <= 31, "0 <= b && b <= 31"); | |
11260 checkConstraint(0 <= (b + n) - 1 && (b + n) - 1 <= 31, "0 <= (b + n) - 1 && (b + n) - 1 <= 31"); | |
11261 checkConstraint(n > 0, "n > 0"); | |
11262 instruction |= ((ra.value() & 0x1f) << 16); | |
11263 instruction |= ((rs.value() & 0x1f) << 21); | |
11264 instruction |= ((32 - b & 0x1f) << 11); | |
11265 instruction |= ((b & 0x1f) << 6); | |
11266 instruction |= (((b + n) - 1 & 0x1f) << 1); | |
11267 emitInt(instruction); | |
11268 } | |
11269 | |
11270 /** | |
11271 * Pseudo-external assembler syntax: {@code inslwi. }<i>ra</i>, <i>rs</i>, <i>n</i>, <i>b</i> | |
11272 * Example disassembly syntax: {@code inslwi. r0, r0, 0x0, 0x0} | |
11273 * <p> | |
11274 * This is a synthetic instruction equivalent to: {@code rlwimi_(ra, rs, 32 - b, b, (b + n) - 1)} | |
11275 * <p> | |
11276 * Constraint: {@code 0 <= 32 - b && 32 - b <= 31}<br /> | |
11277 * Constraint: {@code 0 <= b && b <= 31}<br /> | |
11278 * Constraint: {@code 0 <= (b + n) - 1 && (b + n) - 1 <= 31}<br /> | |
11279 * Constraint: {@code n > 0}<br /> | |
11280 * | |
11281 * @see #rlwimi_(GPR, GPR, int, int, int) | |
11282 * | |
11283 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11284 */ | |
11285 // Template#: 610, Serial#: 610 | |
11286 public void inslwi_(final GPR ra, final GPR rs, final int n, final int b) { | |
11287 int instruction = 0x50000001; | |
11288 checkConstraint(0 <= 32 - b && 32 - b <= 31, "0 <= 32 - b && 32 - b <= 31"); | |
11289 checkConstraint(0 <= b && b <= 31, "0 <= b && b <= 31"); | |
11290 checkConstraint(0 <= (b + n) - 1 && (b + n) - 1 <= 31, "0 <= (b + n) - 1 && (b + n) - 1 <= 31"); | |
11291 checkConstraint(n > 0, "n > 0"); | |
11292 instruction |= ((ra.value() & 0x1f) << 16); | |
11293 instruction |= ((rs.value() & 0x1f) << 21); | |
11294 instruction |= ((32 - b & 0x1f) << 11); | |
11295 instruction |= ((b & 0x1f) << 6); | |
11296 instruction |= (((b + n) - 1 & 0x1f) << 1); | |
11297 emitInt(instruction); | |
11298 } | |
11299 | |
11300 /** | |
11301 * Pseudo-external assembler syntax: {@code insrwi }<i>ra</i>, <i>rs</i>, <i>n</i>, <i>b</i> | |
11302 * Example disassembly syntax: {@code insrwi r0, r0, 0x0, 0x0} | |
11303 * <p> | |
11304 * This is a synthetic instruction equivalent to: {@code rlwimi(ra, rs, 32 - (b + n), b, (b + n) - 1)} | |
11305 * <p> | |
11306 * Constraint: {@code 0 <= 32 - (b + n) && 32 - (b + n) <= 31}<br /> | |
11307 * Constraint: {@code 0 <= b && b <= 31}<br /> | |
11308 * Constraint: {@code 0 <= (b + n) - 1 && (b + n) - 1 <= 31}<br /> | |
11309 * Constraint: {@code n > 0}<br /> | |
11310 * | |
11311 * @see #rlwimi(GPR, GPR, int, int, int) | |
11312 * | |
11313 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11314 */ | |
11315 // Template#: 611, Serial#: 611 | |
11316 public void insrwi(final GPR ra, final GPR rs, final int n, final int b) { | |
11317 int instruction = 0x50000000; | |
11318 checkConstraint(0 <= 32 - (b + n) && 32 - (b + n) <= 31, "0 <= 32 - (b + n) && 32 - (b + n) <= 31"); | |
11319 checkConstraint(0 <= b && b <= 31, "0 <= b && b <= 31"); | |
11320 checkConstraint(0 <= (b + n) - 1 && (b + n) - 1 <= 31, "0 <= (b + n) - 1 && (b + n) - 1 <= 31"); | |
11321 checkConstraint(n > 0, "n > 0"); | |
11322 instruction |= ((ra.value() & 0x1f) << 16); | |
11323 instruction |= ((rs.value() & 0x1f) << 21); | |
11324 instruction |= ((32 - (b + n) & 0x1f) << 11); | |
11325 instruction |= ((b & 0x1f) << 6); | |
11326 instruction |= (((b + n) - 1 & 0x1f) << 1); | |
11327 emitInt(instruction); | |
11328 } | |
11329 | |
11330 /** | |
11331 * Pseudo-external assembler syntax: {@code insrwi. }<i>ra</i>, <i>rs</i>, <i>n</i>, <i>b</i> | |
11332 * Example disassembly syntax: {@code insrwi. r0, r0, 0x0, 0x0} | |
11333 * <p> | |
11334 * This is a synthetic instruction equivalent to: {@code rlwimi_(ra, rs, 32 - (b + n), b, (b + n) - 1)} | |
11335 * <p> | |
11336 * Constraint: {@code 0 <= 32 - (b + n) && 32 - (b + n) <= 31}<br /> | |
11337 * Constraint: {@code 0 <= b && b <= 31}<br /> | |
11338 * Constraint: {@code 0 <= (b + n) - 1 && (b + n) - 1 <= 31}<br /> | |
11339 * Constraint: {@code n > 0}<br /> | |
11340 * | |
11341 * @see #rlwimi_(GPR, GPR, int, int, int) | |
11342 * | |
11343 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11344 */ | |
11345 // Template#: 612, Serial#: 612 | |
11346 public void insrwi_(final GPR ra, final GPR rs, final int n, final int b) { | |
11347 int instruction = 0x50000001; | |
11348 checkConstraint(0 <= 32 - (b + n) && 32 - (b + n) <= 31, "0 <= 32 - (b + n) && 32 - (b + n) <= 31"); | |
11349 checkConstraint(0 <= b && b <= 31, "0 <= b && b <= 31"); | |
11350 checkConstraint(0 <= (b + n) - 1 && (b + n) - 1 <= 31, "0 <= (b + n) - 1 && (b + n) - 1 <= 31"); | |
11351 checkConstraint(n > 0, "n > 0"); | |
11352 instruction |= ((ra.value() & 0x1f) << 16); | |
11353 instruction |= ((rs.value() & 0x1f) << 21); | |
11354 instruction |= ((32 - (b + n) & 0x1f) << 11); | |
11355 instruction |= ((b & 0x1f) << 6); | |
11356 instruction |= (((b + n) - 1 & 0x1f) << 1); | |
11357 emitInt(instruction); | |
11358 } | |
11359 | |
11360 /** | |
11361 * Pseudo-external assembler syntax: {@code rotlwi }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11362 * Example disassembly syntax: {@code rotlwi r0, r0, 0x0} | |
11363 * <p> | |
11364 * This is a synthetic instruction equivalent to: {@code rlwinm(ra, rs, n, 0, 31)} | |
11365 * <p> | |
11366 * Constraint: {@code 0 <= n && n <= 31}<br /> | |
11367 * | |
11368 * @see #rlwinm(GPR, GPR, int, int, int) | |
11369 * | |
11370 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11371 */ | |
11372 // Template#: 613, Serial#: 613 | |
11373 public void rotlwi(final GPR ra, final GPR rs, final int n) { | |
11374 int instruction = 0x5400003E; | |
11375 checkConstraint(0 <= n && n <= 31, "0 <= n && n <= 31"); | |
11376 instruction |= ((ra.value() & 0x1f) << 16); | |
11377 instruction |= ((rs.value() & 0x1f) << 21); | |
11378 instruction |= ((n & 0x1f) << 11); | |
11379 emitInt(instruction); | |
11380 } | |
11381 | |
11382 /** | |
11383 * Pseudo-external assembler syntax: {@code rotlwi. }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11384 * Example disassembly syntax: {@code rotlwi. r0, r0, 0x0} | |
11385 * <p> | |
11386 * This is a synthetic instruction equivalent to: {@code rlwinm_(ra, rs, n, 0, 31)} | |
11387 * <p> | |
11388 * Constraint: {@code 0 <= n && n <= 31}<br /> | |
11389 * | |
11390 * @see #rlwinm_(GPR, GPR, int, int, int) | |
11391 * | |
11392 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11393 */ | |
11394 // Template#: 614, Serial#: 614 | |
11395 public void rotlwi_(final GPR ra, final GPR rs, final int n) { | |
11396 int instruction = 0x5400003F; | |
11397 checkConstraint(0 <= n && n <= 31, "0 <= n && n <= 31"); | |
11398 instruction |= ((ra.value() & 0x1f) << 16); | |
11399 instruction |= ((rs.value() & 0x1f) << 21); | |
11400 instruction |= ((n & 0x1f) << 11); | |
11401 emitInt(instruction); | |
11402 } | |
11403 | |
11404 /** | |
11405 * Pseudo-external assembler syntax: {@code rotrwi }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11406 * Example disassembly syntax: {@code rotrwi r0, r0, 0x0} | |
11407 * <p> | |
11408 * This is a synthetic instruction equivalent to: {@code rlwinm(ra, rs, 32 - n, 0, 31)} | |
11409 * <p> | |
11410 * Constraint: {@code 0 <= 32 - n && 32 - n <= 31}<br /> | |
11411 * | |
11412 * @see #rlwinm(GPR, GPR, int, int, int) | |
11413 * | |
11414 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11415 */ | |
11416 // Template#: 615, Serial#: 615 | |
11417 public void rotrwi(final GPR ra, final GPR rs, final int n) { | |
11418 int instruction = 0x5400003E; | |
11419 checkConstraint(0 <= 32 - n && 32 - n <= 31, "0 <= 32 - n && 32 - n <= 31"); | |
11420 instruction |= ((ra.value() & 0x1f) << 16); | |
11421 instruction |= ((rs.value() & 0x1f) << 21); | |
11422 instruction |= ((32 - n & 0x1f) << 11); | |
11423 emitInt(instruction); | |
11424 } | |
11425 | |
11426 /** | |
11427 * Pseudo-external assembler syntax: {@code rotrwi. }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11428 * Example disassembly syntax: {@code rotrwi. r0, r0, 0x0} | |
11429 * <p> | |
11430 * This is a synthetic instruction equivalent to: {@code rlwinm_(ra, rs, 32 - n, 0, 31)} | |
11431 * <p> | |
11432 * Constraint: {@code 0 <= 32 - n && 32 - n <= 31}<br /> | |
11433 * | |
11434 * @see #rlwinm_(GPR, GPR, int, int, int) | |
11435 * | |
11436 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11437 */ | |
11438 // Template#: 616, Serial#: 616 | |
11439 public void rotrwi_(final GPR ra, final GPR rs, final int n) { | |
11440 int instruction = 0x5400003F; | |
11441 checkConstraint(0 <= 32 - n && 32 - n <= 31, "0 <= 32 - n && 32 - n <= 31"); | |
11442 instruction |= ((ra.value() & 0x1f) << 16); | |
11443 instruction |= ((rs.value() & 0x1f) << 21); | |
11444 instruction |= ((32 - n & 0x1f) << 11); | |
11445 emitInt(instruction); | |
11446 } | |
11447 | |
11448 /** | |
11449 * Pseudo-external assembler syntax: {@code rotlw }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
11450 * Example disassembly syntax: {@code rotlw r0, r0, r0} | |
11451 * <p> | |
11452 * This is a synthetic instruction equivalent to: {@code rlwnm(ra, rs, rb, 0, 31)} | |
11453 * | |
11454 * @see #rlwnm(GPR, GPR, GPR, int, int) | |
11455 * | |
11456 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11457 */ | |
11458 // Template#: 617, Serial#: 617 | |
11459 public void rotlw(final GPR ra, final GPR rs, final GPR rb) { | |
11460 int instruction = 0x5C00003E; | |
11461 instruction |= ((ra.value() & 0x1f) << 16); | |
11462 instruction |= ((rs.value() & 0x1f) << 21); | |
11463 instruction |= ((rb.value() & 0x1f) << 11); | |
11464 emitInt(instruction); | |
11465 } | |
11466 | |
11467 /** | |
11468 * Pseudo-external assembler syntax: {@code rotlw. }<i>ra</i>, <i>rs</i>, <i>rb</i> | |
11469 * Example disassembly syntax: {@code rotlw. r0, r0, r0} | |
11470 * <p> | |
11471 * This is a synthetic instruction equivalent to: {@code rlwnm_(ra, rs, rb, 0, 31)} | |
11472 * | |
11473 * @see #rlwnm_(GPR, GPR, GPR, int, int) | |
11474 * | |
11475 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11476 */ | |
11477 // Template#: 618, Serial#: 618 | |
11478 public void rotlw_(final GPR ra, final GPR rs, final GPR rb) { | |
11479 int instruction = 0x5C00003F; | |
11480 instruction |= ((ra.value() & 0x1f) << 16); | |
11481 instruction |= ((rs.value() & 0x1f) << 21); | |
11482 instruction |= ((rb.value() & 0x1f) << 11); | |
11483 emitInt(instruction); | |
11484 } | |
11485 | |
11486 /** | |
11487 * Pseudo-external assembler syntax: {@code slwi }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11488 * Example disassembly syntax: {@code slwi r0, r0, 0x0} | |
11489 * <p> | |
11490 * This is a synthetic instruction equivalent to: {@code rlwinm(ra, rs, n, 0, 31 - n)} | |
11491 * <p> | |
11492 * Constraint: {@code 0 <= n && n <= 31}<br /> | |
11493 * Constraint: {@code 0 <= 31 - n && 31 - n <= 31}<br /> | |
11494 * Constraint: {@code n < 32}<br /> | |
11495 * | |
11496 * @see #rlwinm(GPR, GPR, int, int, int) | |
11497 * | |
11498 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11499 */ | |
11500 // Template#: 619, Serial#: 619 | |
11501 public void slwi(final GPR ra, final GPR rs, final int n) { | |
11502 int instruction = 0x54000000; | |
11503 checkConstraint(0 <= n && n <= 31, "0 <= n && n <= 31"); | |
11504 checkConstraint(0 <= 31 - n && 31 - n <= 31, "0 <= 31 - n && 31 - n <= 31"); | |
11505 checkConstraint(n < 32, "n < 32"); | |
11506 instruction |= ((ra.value() & 0x1f) << 16); | |
11507 instruction |= ((rs.value() & 0x1f) << 21); | |
11508 instruction |= ((n & 0x1f) << 11); | |
11509 instruction |= ((31 - n & 0x1f) << 1); | |
11510 emitInt(instruction); | |
11511 } | |
11512 | |
11513 /** | |
11514 * Pseudo-external assembler syntax: {@code slwi. }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11515 * Example disassembly syntax: {@code slwi. r0, r0, 0x0} | |
11516 * <p> | |
11517 * This is a synthetic instruction equivalent to: {@code rlwinm_(ra, rs, n, 0, 31 - n)} | |
11518 * <p> | |
11519 * Constraint: {@code 0 <= n && n <= 31}<br /> | |
11520 * Constraint: {@code 0 <= 31 - n && 31 - n <= 31}<br /> | |
11521 * Constraint: {@code n < 32}<br /> | |
11522 * | |
11523 * @see #rlwinm_(GPR, GPR, int, int, int) | |
11524 * | |
11525 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11526 */ | |
11527 // Template#: 620, Serial#: 620 | |
11528 public void slwi_(final GPR ra, final GPR rs, final int n) { | |
11529 int instruction = 0x54000001; | |
11530 checkConstraint(0 <= n && n <= 31, "0 <= n && n <= 31"); | |
11531 checkConstraint(0 <= 31 - n && 31 - n <= 31, "0 <= 31 - n && 31 - n <= 31"); | |
11532 checkConstraint(n < 32, "n < 32"); | |
11533 instruction |= ((ra.value() & 0x1f) << 16); | |
11534 instruction |= ((rs.value() & 0x1f) << 21); | |
11535 instruction |= ((n & 0x1f) << 11); | |
11536 instruction |= ((31 - n & 0x1f) << 1); | |
11537 emitInt(instruction); | |
11538 } | |
11539 | |
11540 /** | |
11541 * Pseudo-external assembler syntax: {@code srwi }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11542 * Example disassembly syntax: {@code srwi r0, r0, 0x0} | |
11543 * <p> | |
11544 * This is a synthetic instruction equivalent to: {@code rlwinm(ra, rs, 32 - n, n, 31)} | |
11545 * <p> | |
11546 * Constraint: {@code 0 <= 32 - n && 32 - n <= 31}<br /> | |
11547 * Constraint: {@code 0 <= n && n <= 31}<br /> | |
11548 * Constraint: {@code n < 32}<br /> | |
11549 * | |
11550 * @see #rlwinm(GPR, GPR, int, int, int) | |
11551 * | |
11552 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11553 */ | |
11554 // Template#: 621, Serial#: 621 | |
11555 public void srwi(final GPR ra, final GPR rs, final int n) { | |
11556 int instruction = 0x5400003E; | |
11557 checkConstraint(0 <= 32 - n && 32 - n <= 31, "0 <= 32 - n && 32 - n <= 31"); | |
11558 checkConstraint(0 <= n && n <= 31, "0 <= n && n <= 31"); | |
11559 checkConstraint(n < 32, "n < 32"); | |
11560 instruction |= ((ra.value() & 0x1f) << 16); | |
11561 instruction |= ((rs.value() & 0x1f) << 21); | |
11562 instruction |= ((32 - n & 0x1f) << 11); | |
11563 instruction |= ((n & 0x1f) << 6); | |
11564 emitInt(instruction); | |
11565 } | |
11566 | |
11567 /** | |
11568 * Pseudo-external assembler syntax: {@code srwi. }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11569 * Example disassembly syntax: {@code srwi. r0, r0, 0x0} | |
11570 * <p> | |
11571 * This is a synthetic instruction equivalent to: {@code rlwinm_(ra, rs, 32 - n, n, 31)} | |
11572 * <p> | |
11573 * Constraint: {@code 0 <= 32 - n && 32 - n <= 31}<br /> | |
11574 * Constraint: {@code 0 <= n && n <= 31}<br /> | |
11575 * Constraint: {@code n < 32}<br /> | |
11576 * | |
11577 * @see #rlwinm_(GPR, GPR, int, int, int) | |
11578 * | |
11579 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11580 */ | |
11581 // Template#: 622, Serial#: 622 | |
11582 public void srwi_(final GPR ra, final GPR rs, final int n) { | |
11583 int instruction = 0x5400003F; | |
11584 checkConstraint(0 <= 32 - n && 32 - n <= 31, "0 <= 32 - n && 32 - n <= 31"); | |
11585 checkConstraint(0 <= n && n <= 31, "0 <= n && n <= 31"); | |
11586 checkConstraint(n < 32, "n < 32"); | |
11587 instruction |= ((ra.value() & 0x1f) << 16); | |
11588 instruction |= ((rs.value() & 0x1f) << 21); | |
11589 instruction |= ((32 - n & 0x1f) << 11); | |
11590 instruction |= ((n & 0x1f) << 6); | |
11591 emitInt(instruction); | |
11592 } | |
11593 | |
11594 /** | |
11595 * Pseudo-external assembler syntax: {@code clrlwi }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11596 * Example disassembly syntax: {@code clrlwi r0, r0, 0x0} | |
11597 * <p> | |
11598 * This is a synthetic instruction equivalent to: {@code rlwinm(ra, rs, 0, n, 31)} | |
11599 * <p> | |
11600 * Constraint: {@code 0 <= n && n <= 31}<br /> | |
11601 * Constraint: {@code n < 32}<br /> | |
11602 * | |
11603 * @see #rlwinm(GPR, GPR, int, int, int) | |
11604 * | |
11605 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11606 */ | |
11607 // Template#: 623, Serial#: 623 | |
11608 public void clrlwi(final GPR ra, final GPR rs, final int n) { | |
11609 int instruction = 0x5400003E; | |
11610 checkConstraint(0 <= n && n <= 31, "0 <= n && n <= 31"); | |
11611 checkConstraint(n < 32, "n < 32"); | |
11612 instruction |= ((ra.value() & 0x1f) << 16); | |
11613 instruction |= ((rs.value() & 0x1f) << 21); | |
11614 instruction |= ((n & 0x1f) << 6); | |
11615 emitInt(instruction); | |
11616 } | |
11617 | |
11618 /** | |
11619 * Pseudo-external assembler syntax: {@code clrlwi. }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11620 * Example disassembly syntax: {@code clrlwi. r0, r0, 0x0} | |
11621 * <p> | |
11622 * This is a synthetic instruction equivalent to: {@code rlwinm_(ra, rs, 0, n, 31)} | |
11623 * <p> | |
11624 * Constraint: {@code 0 <= n && n <= 31}<br /> | |
11625 * Constraint: {@code n < 32}<br /> | |
11626 * | |
11627 * @see #rlwinm_(GPR, GPR, int, int, int) | |
11628 * | |
11629 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11630 */ | |
11631 // Template#: 624, Serial#: 624 | |
11632 public void clrlwi_(final GPR ra, final GPR rs, final int n) { | |
11633 int instruction = 0x5400003F; | |
11634 checkConstraint(0 <= n && n <= 31, "0 <= n && n <= 31"); | |
11635 checkConstraint(n < 32, "n < 32"); | |
11636 instruction |= ((ra.value() & 0x1f) << 16); | |
11637 instruction |= ((rs.value() & 0x1f) << 21); | |
11638 instruction |= ((n & 0x1f) << 6); | |
11639 emitInt(instruction); | |
11640 } | |
11641 | |
11642 /** | |
11643 * Pseudo-external assembler syntax: {@code clrrwi }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11644 * Example disassembly syntax: {@code clrrwi r0, r0, 0x0} | |
11645 * <p> | |
11646 * This is a synthetic instruction equivalent to: {@code rlwinm(ra, rs, 0, 0, 31 - n)} | |
11647 * <p> | |
11648 * Constraint: {@code 0 <= 31 - n && 31 - n <= 31}<br /> | |
11649 * Constraint: {@code n < 32}<br /> | |
11650 * | |
11651 * @see #rlwinm(GPR, GPR, int, int, int) | |
11652 * | |
11653 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11654 */ | |
11655 // Template#: 625, Serial#: 625 | |
11656 public void clrrwi(final GPR ra, final GPR rs, final int n) { | |
11657 int instruction = 0x54000000; | |
11658 checkConstraint(0 <= 31 - n && 31 - n <= 31, "0 <= 31 - n && 31 - n <= 31"); | |
11659 checkConstraint(n < 32, "n < 32"); | |
11660 instruction |= ((ra.value() & 0x1f) << 16); | |
11661 instruction |= ((rs.value() & 0x1f) << 21); | |
11662 instruction |= ((31 - n & 0x1f) << 1); | |
11663 emitInt(instruction); | |
11664 } | |
11665 | |
11666 /** | |
11667 * Pseudo-external assembler syntax: {@code clrrwi. }<i>ra</i>, <i>rs</i>, <i>n</i> | |
11668 * Example disassembly syntax: {@code clrrwi. r0, r0, 0x0} | |
11669 * <p> | |
11670 * This is a synthetic instruction equivalent to: {@code rlwinm_(ra, rs, 0, 0, 31 - n)} | |
11671 * <p> | |
11672 * Constraint: {@code 0 <= 31 - n && 31 - n <= 31}<br /> | |
11673 * Constraint: {@code n < 32}<br /> | |
11674 * | |
11675 * @see #rlwinm_(GPR, GPR, int, int, int) | |
11676 * | |
11677 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11678 */ | |
11679 // Template#: 626, Serial#: 626 | |
11680 public void clrrwi_(final GPR ra, final GPR rs, final int n) { | |
11681 int instruction = 0x54000001; | |
11682 checkConstraint(0 <= 31 - n && 31 - n <= 31, "0 <= 31 - n && 31 - n <= 31"); | |
11683 checkConstraint(n < 32, "n < 32"); | |
11684 instruction |= ((ra.value() & 0x1f) << 16); | |
11685 instruction |= ((rs.value() & 0x1f) << 21); | |
11686 instruction |= ((31 - n & 0x1f) << 1); | |
11687 emitInt(instruction); | |
11688 } | |
11689 | |
11690 /** | |
11691 * Pseudo-external assembler syntax: {@code clrlslwi }<i>ra</i>, <i>rs</i>, <i>b</i>, <i>n</i> | |
11692 * Example disassembly syntax: {@code clrlslwi r0, r0, 0x0, 0x0} | |
11693 * <p> | |
11694 * This is a synthetic instruction equivalent to: {@code rlwinm(ra, rs, n, b - n, 31 - n)} | |
11695 * <p> | |
11696 * Constraint: {@code 0 <= n && n <= 31}<br /> | |
11697 * Constraint: {@code 0 <= b - n && b - n <= 31}<br /> | |
11698 * Constraint: {@code 0 <= 31 - n && 31 - n <= 31}<br /> | |
11699 * Constraint: {@code n <= b}<br /> | |
11700 * Constraint: {@code b < 32}<br /> | |
11701 * | |
11702 * @see #rlwinm(GPR, GPR, int, int, int) | |
11703 * | |
11704 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11705 */ | |
11706 // Template#: 627, Serial#: 627 | |
11707 public void clrlslwi(final GPR ra, final GPR rs, final int b, final int n) { | |
11708 int instruction = 0x54000000; | |
11709 checkConstraint(0 <= n && n <= 31, "0 <= n && n <= 31"); | |
11710 checkConstraint(0 <= b - n && b - n <= 31, "0 <= b - n && b - n <= 31"); | |
11711 checkConstraint(0 <= 31 - n && 31 - n <= 31, "0 <= 31 - n && 31 - n <= 31"); | |
11712 checkConstraint(n <= b, "n <= b"); | |
11713 checkConstraint(b < 32, "b < 32"); | |
11714 instruction |= ((ra.value() & 0x1f) << 16); | |
11715 instruction |= ((rs.value() & 0x1f) << 21); | |
11716 instruction |= ((n & 0x1f) << 11); | |
11717 instruction |= ((b - n & 0x1f) << 6); | |
11718 instruction |= ((31 - n & 0x1f) << 1); | |
11719 emitInt(instruction); | |
11720 } | |
11721 | |
11722 /** | |
11723 * Pseudo-external assembler syntax: {@code clrlslwi. }<i>ra</i>, <i>rs</i>, <i>b</i>, <i>n</i> | |
11724 * Example disassembly syntax: {@code clrlslwi. r0, r0, 0x0, 0x0} | |
11725 * <p> | |
11726 * This is a synthetic instruction equivalent to: {@code rlwinm_(ra, rs, n, b - n, 31 - n)} | |
11727 * <p> | |
11728 * Constraint: {@code 0 <= n && n <= 31}<br /> | |
11729 * Constraint: {@code 0 <= b - n && b - n <= 31}<br /> | |
11730 * Constraint: {@code 0 <= 31 - n && 31 - n <= 31}<br /> | |
11731 * Constraint: {@code n <= b}<br /> | |
11732 * Constraint: {@code b < 32}<br /> | |
11733 * | |
11734 * @see #rlwinm_(GPR, GPR, int, int, int) | |
11735 * | |
11736 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.7.2 [Book 1]" | |
11737 */ | |
11738 // Template#: 628, Serial#: 628 | |
11739 public void clrlslwi_(final GPR ra, final GPR rs, final int b, final int n) { | |
11740 int instruction = 0x54000001; | |
11741 checkConstraint(0 <= n && n <= 31, "0 <= n && n <= 31"); | |
11742 checkConstraint(0 <= b - n && b - n <= 31, "0 <= b - n && b - n <= 31"); | |
11743 checkConstraint(0 <= 31 - n && 31 - n <= 31, "0 <= 31 - n && 31 - n <= 31"); | |
11744 checkConstraint(n <= b, "n <= b"); | |
11745 checkConstraint(b < 32, "b < 32"); | |
11746 instruction |= ((ra.value() & 0x1f) << 16); | |
11747 instruction |= ((rs.value() & 0x1f) << 21); | |
11748 instruction |= ((n & 0x1f) << 11); | |
11749 instruction |= ((b - n & 0x1f) << 6); | |
11750 instruction |= ((31 - n & 0x1f) << 1); | |
11751 emitInt(instruction); | |
11752 } | |
11753 | |
11754 /** | |
11755 * Pseudo-external assembler syntax: {@code mtxer }<i>rs</i> | |
11756 * Example disassembly syntax: {@code mtxer r0} | |
11757 * <p> | |
11758 * This is a synthetic instruction equivalent to: {@code mtspr(1, rs)} | |
11759 * | |
11760 * @see #mtspr(int, GPR) | |
11761 * | |
11762 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.8 [Book 1]" | |
11763 */ | |
11764 // Template#: 629, Serial#: 629 | |
11765 public void mtxer(final GPR rs) { | |
11766 int instruction = 0x7C0103A6; | |
11767 instruction |= ((rs.value() & 0x1f) << 21); | |
11768 emitInt(instruction); | |
11769 } | |
11770 | |
11771 /** | |
11772 * Pseudo-external assembler syntax: {@code mtlr }<i>rs</i> | |
11773 * Example disassembly syntax: {@code mtlr r0} | |
11774 * <p> | |
11775 * This is a synthetic instruction equivalent to: {@code mtspr(8, rs)} | |
11776 * | |
11777 * @see #mtspr(int, GPR) | |
11778 * | |
11779 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.8 [Book 1]" | |
11780 */ | |
11781 // Template#: 630, Serial#: 630 | |
11782 public void mtlr(final GPR rs) { | |
11783 int instruction = 0x7C0803A6; | |
11784 instruction |= ((rs.value() & 0x1f) << 21); | |
11785 emitInt(instruction); | |
11786 } | |
11787 | |
11788 /** | |
11789 * Pseudo-external assembler syntax: {@code mtctr }<i>rs</i> | |
11790 * Example disassembly syntax: {@code mtctr r0} | |
11791 * <p> | |
11792 * This is a synthetic instruction equivalent to: {@code mtspr(9, rs)} | |
11793 * | |
11794 * @see #mtspr(int, GPR) | |
11795 * | |
11796 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.8 [Book 1]" | |
11797 */ | |
11798 // Template#: 631, Serial#: 631 | |
11799 public void mtctr(final GPR rs) { | |
11800 int instruction = 0x7C0903A6; | |
11801 instruction |= ((rs.value() & 0x1f) << 21); | |
11802 emitInt(instruction); | |
11803 } | |
11804 | |
11805 /** | |
11806 * Pseudo-external assembler syntax: {@code mfxer }<i>rt</i> | |
11807 * Example disassembly syntax: {@code mfxer r0} | |
11808 * <p> | |
11809 * This is a synthetic instruction equivalent to: {@code mfspr(rt, 1)} | |
11810 * | |
11811 * @see #mfspr(GPR, int) | |
11812 * | |
11813 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.8 [Book 1]" | |
11814 */ | |
11815 // Template#: 632, Serial#: 632 | |
11816 public void mfxer(final GPR rt) { | |
11817 int instruction = 0x7C0102A6; | |
11818 instruction |= ((rt.value() & 0x1f) << 21); | |
11819 emitInt(instruction); | |
11820 } | |
11821 | |
11822 /** | |
11823 * Pseudo-external assembler syntax: {@code mflr }<i>rt</i> | |
11824 * Example disassembly syntax: {@code mflr r0} | |
11825 * <p> | |
11826 * This is a synthetic instruction equivalent to: {@code mfspr(rt, 8)} | |
11827 * | |
11828 * @see #mfspr(GPR, int) | |
11829 * | |
11830 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.8 [Book 1]" | |
11831 */ | |
11832 // Template#: 633, Serial#: 633 | |
11833 public void mflr(final GPR rt) { | |
11834 int instruction = 0x7C0802A6; | |
11835 instruction |= ((rt.value() & 0x1f) << 21); | |
11836 emitInt(instruction); | |
11837 } | |
11838 | |
11839 /** | |
11840 * Pseudo-external assembler syntax: {@code mfctr }<i>rt</i> | |
11841 * Example disassembly syntax: {@code mfctr r0} | |
11842 * <p> | |
11843 * This is a synthetic instruction equivalent to: {@code mfspr(rt, 9)} | |
11844 * | |
11845 * @see #mfspr(GPR, int) | |
11846 * | |
11847 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.8 [Book 1]" | |
11848 */ | |
11849 // Template#: 634, Serial#: 634 | |
11850 public void mfctr(final GPR rt) { | |
11851 int instruction = 0x7C0902A6; | |
11852 instruction |= ((rt.value() & 0x1f) << 21); | |
11853 emitInt(instruction); | |
11854 } | |
11855 | |
11856 /** | |
11857 * Pseudo-external assembler syntax: {@code nop } | |
11858 * Example disassembly syntax: {@code nop } | |
11859 * <p> | |
11860 * This is a synthetic instruction equivalent to: {@code ori(R0, R0, 0)} | |
11861 * | |
11862 * @see #ori(GPR, GPR, int) | |
11863 * | |
11864 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.9 [Book 1]" | |
11865 */ | |
11866 // Template#: 635, Serial#: 635 | |
11867 public void nop() { | |
11868 int instruction = 0x60000000; | |
11869 emitInt(instruction); | |
11870 } | |
11871 | |
11872 /** | |
11873 * Pseudo-external assembler syntax: {@code li }<i>rt</i>, <i>si</i> | |
11874 * Example disassembly syntax: {@code li r0, -32768} | |
11875 * <p> | |
11876 * This is a synthetic instruction equivalent to: {@code addi(rt, 0, si)} | |
11877 * <p> | |
11878 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
11879 * | |
11880 * @see #addi(GPR, ZeroOrRegister, int) | |
11881 * | |
11882 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.9 [Book 1]" | |
11883 */ | |
11884 // Template#: 636, Serial#: 636 | |
11885 public void li(final GPR rt, final int si) { | |
11886 int instruction = 0x38000000; | |
11887 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
11888 instruction |= ((rt.value() & 0x1f) << 21); | |
11889 instruction |= (si & 0xffff); | |
11890 emitInt(instruction); | |
11891 } | |
11892 | |
11893 /** | |
11894 * Pseudo-external assembler syntax: {@code lis }<i>rt</i>, <i>sis</i> | |
11895 * Example disassembly syntax: {@code lis r0, 0x0} | |
11896 * <p> | |
11897 * This is a synthetic instruction equivalent to: {@code addis(rt, 0, sis)} | |
11898 * <p> | |
11899 * Constraint: {@code -32768 <= sis && sis <= 65535}<br /> | |
11900 * | |
11901 * @see #addis(GPR, ZeroOrRegister, int) | |
11902 * | |
11903 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.9 [Book 1]" | |
11904 */ | |
11905 // Template#: 637, Serial#: 637 | |
11906 public void lis(final GPR rt, final int sis) { | |
11907 int instruction = 0x3C000000; | |
11908 checkConstraint(-32768 <= sis && sis <= 65535, "-32768 <= sis && sis <= 65535"); | |
11909 instruction |= ((rt.value() & 0x1f) << 21); | |
11910 instruction |= (sis & 0xffff); | |
11911 emitInt(instruction); | |
11912 } | |
11913 | |
11914 /** | |
11915 * Pseudo-external assembler syntax: {@code la }<i>rt</i>, <i>si</i>, <i>ra</i> | |
11916 * Example disassembly syntax: {@code la r0, -32768(0)} | |
11917 * <p> | |
11918 * This is a synthetic instruction equivalent to: {@code addi(rt, ra, si)} | |
11919 * <p> | |
11920 * Constraint: {@code -32768 <= si && si <= 32767}<br /> | |
11921 * Constraint: {@code ra != R0}<br /> | |
11922 * | |
11923 * @see #addi(GPR, ZeroOrRegister, int) | |
11924 * | |
11925 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.9 [Book 1]" | |
11926 */ | |
11927 // Template#: 638, Serial#: 638 | |
11928 public void la(final GPR rt, final int si, final ZeroOrRegister ra) { | |
11929 int instruction = 0x38000000; | |
11930 checkConstraint(-32768 <= si && si <= 32767, "-32768 <= si && si <= 32767"); | |
11931 checkConstraint(ra != R0, "ra != R0"); | |
11932 instruction |= ((rt.value() & 0x1f) << 21); | |
11933 instruction |= (si & 0xffff); | |
11934 instruction |= ((ra.value() & 0x1f) << 16); | |
11935 emitInt(instruction); | |
11936 } | |
11937 | |
11938 /** | |
11939 * Pseudo-external assembler syntax: {@code mr }<i>ra</i>, <i>rb</i> | |
11940 * Example disassembly syntax: {@code mr r0, r0} | |
11941 * <p> | |
11942 * This is a synthetic instruction equivalent to: {@code or(ra, rb.value(), rb)} | |
11943 * | |
11944 * @see #or(GPR, GPR, GPR) | |
11945 * | |
11946 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.9 [Book 1]" | |
11947 */ | |
11948 // Template#: 639, Serial#: 639 | |
11949 public void mr(final GPR ra, final GPR rb) { | |
11950 int instruction = 0x7C000378; | |
11951 instruction |= ((ra.value() & 0x1f) << 16); | |
11952 instruction |= ((rb.value() & 0x1f) << 21); | |
11953 instruction |= ((rb.value() & 0x1f) << 11); | |
11954 emitInt(instruction); | |
11955 } | |
11956 | |
11957 /** | |
11958 * Pseudo-external assembler syntax: {@code mr. }<i>ra</i>, <i>rb</i> | |
11959 * Example disassembly syntax: {@code mr. r0, r0} | |
11960 * <p> | |
11961 * This is a synthetic instruction equivalent to: {@code or_(ra, rb.value(), rb)} | |
11962 * | |
11963 * @see #or_(GPR, GPR, GPR) | |
11964 * | |
11965 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.9 [Book 1]" | |
11966 */ | |
11967 // Template#: 640, Serial#: 640 | |
11968 public void mr_(final GPR ra, final GPR rb) { | |
11969 int instruction = 0x7C000379; | |
11970 instruction |= ((ra.value() & 0x1f) << 16); | |
11971 instruction |= ((rb.value() & 0x1f) << 21); | |
11972 instruction |= ((rb.value() & 0x1f) << 11); | |
11973 emitInt(instruction); | |
11974 } | |
11975 | |
11976 /** | |
11977 * Pseudo-external assembler syntax: {@code not }<i>ra</i>, <i>rb</i> | |
11978 * Example disassembly syntax: {@code not r0, r0} | |
11979 * <p> | |
11980 * This is a synthetic instruction equivalent to: {@code nor(ra, rb.value(), rb)} | |
11981 * | |
11982 * @see #nor(GPR, GPR, GPR) | |
11983 * | |
11984 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.9 [Book 1]" | |
11985 */ | |
11986 // Template#: 641, Serial#: 641 | |
11987 public void not(final GPR ra, final GPR rb) { | |
11988 int instruction = 0x7C0000F8; | |
11989 instruction |= ((ra.value() & 0x1f) << 16); | |
11990 instruction |= ((rb.value() & 0x1f) << 21); | |
11991 instruction |= ((rb.value() & 0x1f) << 11); | |
11992 emitInt(instruction); | |
11993 } | |
11994 | |
11995 /** | |
11996 * Pseudo-external assembler syntax: {@code not. }<i>ra</i>, <i>rb</i> | |
11997 * Example disassembly syntax: {@code not. r0, r0} | |
11998 * <p> | |
11999 * This is a synthetic instruction equivalent to: {@code nor_(ra, rb.value(), rb)} | |
12000 * | |
12001 * @see #nor_(GPR, GPR, GPR) | |
12002 * | |
12003 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.9 [Book 1]" | |
12004 */ | |
12005 // Template#: 642, Serial#: 642 | |
12006 public void not_(final GPR ra, final GPR rb) { | |
12007 int instruction = 0x7C0000F9; | |
12008 instruction |= ((ra.value() & 0x1f) << 16); | |
12009 instruction |= ((rb.value() & 0x1f) << 21); | |
12010 instruction |= ((rb.value() & 0x1f) << 11); | |
12011 emitInt(instruction); | |
12012 } | |
12013 | |
12014 /** | |
12015 * Pseudo-external assembler syntax: {@code mtcr }<i>rs</i> | |
12016 * Example disassembly syntax: {@code mtcr r0} | |
12017 * <p> | |
12018 * This is a synthetic instruction equivalent to: {@code mtcrf(255, rs)} | |
12019 * | |
12020 * @see #mtcrf(int, GPR) | |
12021 * | |
12022 * @see "<a href="http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html">PowerPC Architecture Book, Version 2.02</a> - Section B.9 [Book 1]" | |
12023 */ | |
12024 // Template#: 643, Serial#: 643 | |
12025 public void mtcr(final GPR rs) { | |
12026 int instruction = 0x7C0FF120; | |
12027 instruction |= ((rs.value() & 0x1f) << 21); | |
12028 emitInt(instruction); | |
12029 } | |
12030 | |
12031 // END GENERATED RAW ASSEMBLER METHODS | |
12032 | |
12033 } |