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comparison graal/com.oracle.max.asmdis/src/com/sun/max/asm/sparc/complete/SPARCRawAssembler.java @ 3733:e233f5660da4

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Added Java files from Maxine project.
author Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
date Sat, 17 Dec 2011 19:59:18 +0100
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3732:3e2e8b8abdaf 3733:e233f5660da4
1 /*
2 * Copyright (c) 2007, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 */
23
24 package com.sun.max.asm.sparc.complete;
25
26 import com.sun.max.asm.sparc.*;
27
28 public abstract class SPARCRawAssembler extends AbstractSPARCAssembler {
29
30 // START GENERATED RAW ASSEMBLER METHODS
31 /**
32 * Pseudo-external assembler syntax: {@code casa }<i>rs1</i>, <i>immAsi</i>, <i>rs2</i>, <i>rd</i>
33 * Example disassembly syntax: {@code casa [%g0] 0x0,%g0, %g0}
34 * <p>
35 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
36 *
37 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.9"
38 */
39 // Template#: 1, Serial#: 1
40 public void casa(final GPR rs1, final int immAsi, final GPR rs2, final GPR rd) {
41 int instruction = 0xC1E00000;
42 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
43 instruction |= ((rs1.value() & 0x1f) << 14);
44 instruction |= ((immAsi & 0xff) << 5);
45 instruction |= (rs2.value() & 0x1f);
46 instruction |= ((rd.value() & 0x1f) << 25);
47 emitInt(instruction);
48 }
49
50 /**
51 * Pseudo-external assembler syntax: {@code casa }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
52 * Example disassembly syntax: {@code casa [%g0] %asi, %g0, %g0}
53 *
54 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.9"
55 */
56 // Template#: 2, Serial#: 2
57 public void casa(final GPR rs1, final GPR rs2, final GPR rd) {
58 int instruction = 0xC1E02000;
59 instruction |= ((rs1.value() & 0x1f) << 14);
60 instruction |= (rs2.value() & 0x1f);
61 instruction |= ((rd.value() & 0x1f) << 25);
62 emitInt(instruction);
63 }
64
65 /**
66 * Pseudo-external assembler syntax: {@code casxa }<i>rs1</i>, <i>immAsi</i>, <i>rs2</i>, <i>rd</i>
67 * Example disassembly syntax: {@code casxa [%g0] 0x0,%g0, %g0}
68 * <p>
69 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
70 *
71 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.9"
72 */
73 // Template#: 3, Serial#: 3
74 public void casxa(final GPR rs1, final int immAsi, final GPR rs2, final GPR rd) {
75 int instruction = 0xC1F00000;
76 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
77 instruction |= ((rs1.value() & 0x1f) << 14);
78 instruction |= ((immAsi & 0xff) << 5);
79 instruction |= (rs2.value() & 0x1f);
80 instruction |= ((rd.value() & 0x1f) << 25);
81 emitInt(instruction);
82 }
83
84 /**
85 * Pseudo-external assembler syntax: {@code casxa }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
86 * Example disassembly syntax: {@code casxa [%g0] %asi, %g0, %g0}
87 *
88 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.9"
89 */
90 // Template#: 4, Serial#: 4
91 public void casxa(final GPR rs1, final GPR rs2, final GPR rd) {
92 int instruction = 0xC1F02000;
93 instruction |= ((rs1.value() & 0x1f) << 14);
94 instruction |= (rs2.value() & 0x1f);
95 instruction |= ((rd.value() & 0x1f) << 25);
96 emitInt(instruction);
97 }
98
99 /**
100 * Pseudo-external assembler syntax: {@code flush }<i>rs1</i>, <i>rs2</i>
101 * Example disassembly syntax: {@code flush %g0 + %g0}
102 *
103 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.20"
104 */
105 // Template#: 5, Serial#: 5
106 public void flush(final GPR rs1, final GPR rs2) {
107 int instruction = 0x81D80000;
108 instruction |= ((rs1.value() & 0x1f) << 14);
109 instruction |= (rs2.value() & 0x1f);
110 emitInt(instruction);
111 }
112
113 /**
114 * Pseudo-external assembler syntax: {@code flush }<i>rs1</i>, <i>simm13</i>
115 * Example disassembly syntax: {@code flush %g0 + -4096}
116 * <p>
117 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
118 *
119 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.20"
120 */
121 // Template#: 6, Serial#: 6
122 public void flush(final GPR rs1, final int simm13) {
123 int instruction = 0x81D82000;
124 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
125 instruction |= ((rs1.value() & 0x1f) << 14);
126 instruction |= (simm13 & 0x1fff);
127 emitInt(instruction);
128 }
129
130 /**
131 * Pseudo-external assembler syntax: {@code ld }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
132 * Example disassembly syntax: {@code ld [%g0 + %g0], %f0}
133 *
134 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.25"
135 */
136 // Template#: 7, Serial#: 7
137 public void ld(final GPR rs1, final GPR rs2, final SFPR rd) {
138 int instruction = 0xC1000000;
139 instruction |= ((rs1.value() & 0x1f) << 14);
140 instruction |= (rs2.value() & 0x1f);
141 instruction |= ((rd.value() & 0x1f) << 25);
142 emitInt(instruction);
143 }
144
145 /**
146 * Pseudo-external assembler syntax: {@code ld }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
147 * Example disassembly syntax: {@code ld [%g0 + -4096], %f0}
148 * <p>
149 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
150 *
151 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.25"
152 */
153 // Template#: 8, Serial#: 8
154 public void ld(final GPR rs1, final int simm13, final SFPR rd) {
155 int instruction = 0xC1002000;
156 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
157 instruction |= ((rs1.value() & 0x1f) << 14);
158 instruction |= (simm13 & 0x1fff);
159 instruction |= ((rd.value() & 0x1f) << 25);
160 emitInt(instruction);
161 }
162
163 /**
164 * Pseudo-external assembler syntax: {@code ldd }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
165 * Example disassembly syntax: {@code ldd [%g0 + %g0], %f0}
166 *
167 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.25"
168 */
169 // Template#: 9, Serial#: 9
170 public void ldd(final GPR rs1, final GPR rs2, final DFPR rd) {
171 int instruction = 0xC1180000;
172 instruction |= ((rs1.value() & 0x1f) << 14);
173 instruction |= (rs2.value() & 0x1f);
174 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
175 emitInt(instruction);
176 }
177
178 /**
179 * Pseudo-external assembler syntax: {@code ldd }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
180 * Example disassembly syntax: {@code ldd [%g0 + -4096], %f0}
181 * <p>
182 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
183 *
184 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.25"
185 */
186 // Template#: 10, Serial#: 10
187 public void ldd(final GPR rs1, final int simm13, final DFPR rd) {
188 int instruction = 0xC1182000;
189 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
190 instruction |= ((rs1.value() & 0x1f) << 14);
191 instruction |= (simm13 & 0x1fff);
192 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
193 emitInt(instruction);
194 }
195
196 /**
197 * Pseudo-external assembler syntax: {@code ldq }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
198 * Example disassembly syntax: {@code ldq [%g0 + %g0], %f0}
199 *
200 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.25"
201 */
202 // Template#: 11, Serial#: 11
203 public void ldq(final GPR rs1, final GPR rs2, final QFPR rd) {
204 int instruction = 0xC1100000;
205 instruction |= ((rs1.value() & 0x1f) << 14);
206 instruction |= (rs2.value() & 0x1f);
207 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
208 emitInt(instruction);
209 }
210
211 /**
212 * Pseudo-external assembler syntax: {@code ldq }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
213 * Example disassembly syntax: {@code ldq [%g0 + -4096], %f0}
214 * <p>
215 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
216 *
217 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.25"
218 */
219 // Template#: 12, Serial#: 12
220 public void ldq(final GPR rs1, final int simm13, final QFPR rd) {
221 int instruction = 0xC1102000;
222 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
223 instruction |= ((rs1.value() & 0x1f) << 14);
224 instruction |= (simm13 & 0x1fff);
225 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
226 emitInt(instruction);
227 }
228
229 /**
230 * Pseudo-external assembler syntax: {@code ldx }<i>rs1</i>, <i>rs2</i>
231 * Example disassembly syntax: {@code ldx [%g0 + %g0], %fsr}
232 *
233 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.25"
234 */
235 // Template#: 13, Serial#: 13
236 public void ldx_fsr(final GPR rs1, final GPR rs2) {
237 int instruction = 0xC3080000;
238 instruction |= ((rs1.value() & 0x1f) << 14);
239 instruction |= (rs2.value() & 0x1f);
240 emitInt(instruction);
241 }
242
243 /**
244 * Pseudo-external assembler syntax: {@code ldx }<i>rs1</i>, <i>simm13</i>
245 * Example disassembly syntax: {@code ldx [%g0 + -4096], %fsr}
246 * <p>
247 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
248 *
249 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.25"
250 */
251 // Template#: 14, Serial#: 14
252 public void ldx_fsr(final GPR rs1, final int simm13) {
253 int instruction = 0xC3082000;
254 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
255 instruction |= ((rs1.value() & 0x1f) << 14);
256 instruction |= (simm13 & 0x1fff);
257 emitInt(instruction);
258 }
259
260 /**
261 * Pseudo-external assembler syntax: {@code ld }<i>rs1</i>, <i>rs2</i>
262 * Example disassembly syntax: {@code ld [%g0 + %g0], %fsr}
263 *
264 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.25"
265 */
266 // Template#: 15, Serial#: 15
267 public void ld_fsr(final GPR rs1, final GPR rs2) {
268 int instruction = 0xC1080000;
269 instruction |= ((rs1.value() & 0x1f) << 14);
270 instruction |= (rs2.value() & 0x1f);
271 emitInt(instruction);
272 }
273
274 /**
275 * Pseudo-external assembler syntax: {@code ld }<i>rs1</i>, <i>simm13</i>
276 * Example disassembly syntax: {@code ld [%g0 + -4096], %fsr}
277 * <p>
278 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
279 *
280 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.25"
281 */
282 // Template#: 16, Serial#: 16
283 public void ld_fsr(final GPR rs1, final int simm13) {
284 int instruction = 0xC1082000;
285 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
286 instruction |= ((rs1.value() & 0x1f) << 14);
287 instruction |= (simm13 & 0x1fff);
288 emitInt(instruction);
289 }
290
291 /**
292 * Pseudo-external assembler syntax: {@code swap }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
293 * Example disassembly syntax: {@code swap [%g0 + %g0], %g0}
294 *
295 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.25"
296 */
297 // Template#: 17, Serial#: 17
298 public void swap(final GPR rs1, final GPR rs2, final GPR rd) {
299 int instruction = 0xC0780000;
300 instruction |= ((rs1.value() & 0x1f) << 14);
301 instruction |= (rs2.value() & 0x1f);
302 instruction |= ((rd.value() & 0x1f) << 25);
303 emitInt(instruction);
304 }
305
306 /**
307 * Pseudo-external assembler syntax: {@code swap }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
308 * Example disassembly syntax: {@code swap [%g0 + -4096], %g0}
309 * <p>
310 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
311 *
312 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.25"
313 */
314 // Template#: 18, Serial#: 18
315 public void swap(final GPR rs1, final int simm13, final GPR rd) {
316 int instruction = 0xC0782000;
317 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
318 instruction |= ((rs1.value() & 0x1f) << 14);
319 instruction |= (simm13 & 0x1fff);
320 instruction |= ((rd.value() & 0x1f) << 25);
321 emitInt(instruction);
322 }
323
324 /**
325 * Pseudo-external assembler syntax: {@code lda }<i>rs1</i>, <i>rs2</i>, <i>immAsi</i>, <i>rd</i>
326 * Example disassembly syntax: {@code lda [%g0 + %g0] 0x0, %f0}
327 * <p>
328 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
329 *
330 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.26"
331 */
332 // Template#: 19, Serial#: 19
333 public void lda(final GPR rs1, final GPR rs2, final int immAsi, final SFPR rd) {
334 int instruction = 0xC1800000;
335 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
336 instruction |= ((rs1.value() & 0x1f) << 14);
337 instruction |= (rs2.value() & 0x1f);
338 instruction |= ((immAsi & 0xff) << 5);
339 instruction |= ((rd.value() & 0x1f) << 25);
340 emitInt(instruction);
341 }
342
343 /**
344 * Pseudo-external assembler syntax: {@code lda }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
345 * Example disassembly syntax: {@code lda [%g0 + -4096] %asi, %f0}
346 * <p>
347 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
348 *
349 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.26"
350 */
351 // Template#: 20, Serial#: 20
352 public void lda(final GPR rs1, final int simm13, final SFPR rd) {
353 int instruction = 0xC1802000;
354 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
355 instruction |= ((rs1.value() & 0x1f) << 14);
356 instruction |= (simm13 & 0x1fff);
357 instruction |= ((rd.value() & 0x1f) << 25);
358 emitInt(instruction);
359 }
360
361 /**
362 * Pseudo-external assembler syntax: {@code ldda }<i>rs1</i>, <i>rs2</i>, <i>immAsi</i>, <i>rd</i>
363 * Example disassembly syntax: {@code ldda [%g0 + %g0] 0x0, %f0}
364 * <p>
365 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
366 *
367 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.26"
368 */
369 // Template#: 21, Serial#: 21
370 public void ldda(final GPR rs1, final GPR rs2, final int immAsi, final DFPR rd) {
371 int instruction = 0xC1980000;
372 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
373 instruction |= ((rs1.value() & 0x1f) << 14);
374 instruction |= (rs2.value() & 0x1f);
375 instruction |= ((immAsi & 0xff) << 5);
376 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
377 emitInt(instruction);
378 }
379
380 /**
381 * Pseudo-external assembler syntax: {@code ldda }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
382 * Example disassembly syntax: {@code ldda [%g0 + -4096] %asi, %f0}
383 * <p>
384 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
385 *
386 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.26"
387 */
388 // Template#: 22, Serial#: 22
389 public void ldda(final GPR rs1, final int simm13, final DFPR rd) {
390 int instruction = 0xC1982000;
391 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
392 instruction |= ((rs1.value() & 0x1f) << 14);
393 instruction |= (simm13 & 0x1fff);
394 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
395 emitInt(instruction);
396 }
397
398 /**
399 * Pseudo-external assembler syntax: {@code ldqa }<i>rs1</i>, <i>rs2</i>, <i>immAsi</i>, <i>rd</i>
400 * Example disassembly syntax: {@code ldqa [%g0 + %g0] 0x0, %f0}
401 * <p>
402 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
403 *
404 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.26"
405 */
406 // Template#: 23, Serial#: 23
407 public void ldqa(final GPR rs1, final GPR rs2, final int immAsi, final QFPR rd) {
408 int instruction = 0xC1900000;
409 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
410 instruction |= ((rs1.value() & 0x1f) << 14);
411 instruction |= (rs2.value() & 0x1f);
412 instruction |= ((immAsi & 0xff) << 5);
413 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
414 emitInt(instruction);
415 }
416
417 /**
418 * Pseudo-external assembler syntax: {@code ldqa }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
419 * Example disassembly syntax: {@code ldqa [%g0 + -4096] %asi, %f0}
420 * <p>
421 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
422 *
423 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.26"
424 */
425 // Template#: 24, Serial#: 24
426 public void ldqa(final GPR rs1, final int simm13, final QFPR rd) {
427 int instruction = 0xC1902000;
428 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
429 instruction |= ((rs1.value() & 0x1f) << 14);
430 instruction |= (simm13 & 0x1fff);
431 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
432 emitInt(instruction);
433 }
434
435 /**
436 * Pseudo-external assembler syntax: {@code ldsb }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
437 * Example disassembly syntax: {@code ldsb [%g0 + %g0], %g0}
438 *
439 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
440 */
441 // Template#: 25, Serial#: 25
442 public void ldsb(final GPR rs1, final GPR rs2, final GPR rd) {
443 int instruction = 0xC0480000;
444 instruction |= ((rs1.value() & 0x1f) << 14);
445 instruction |= (rs2.value() & 0x1f);
446 instruction |= ((rd.value() & 0x1f) << 25);
447 emitInt(instruction);
448 }
449
450 /**
451 * Pseudo-external assembler syntax: {@code ldsb }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
452 * Example disassembly syntax: {@code ldsb [%g0 + -4096], %g0}
453 * <p>
454 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
455 *
456 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
457 */
458 // Template#: 26, Serial#: 26
459 public void ldsb(final GPR rs1, final int simm13, final GPR rd) {
460 int instruction = 0xC0482000;
461 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
462 instruction |= ((rs1.value() & 0x1f) << 14);
463 instruction |= (simm13 & 0x1fff);
464 instruction |= ((rd.value() & 0x1f) << 25);
465 emitInt(instruction);
466 }
467
468 /**
469 * Pseudo-external assembler syntax: {@code ldsh }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
470 * Example disassembly syntax: {@code ldsh [%g0 + %g0], %g0}
471 *
472 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
473 */
474 // Template#: 27, Serial#: 27
475 public void ldsh(final GPR rs1, final GPR rs2, final GPR rd) {
476 int instruction = 0xC0500000;
477 instruction |= ((rs1.value() & 0x1f) << 14);
478 instruction |= (rs2.value() & 0x1f);
479 instruction |= ((rd.value() & 0x1f) << 25);
480 emitInt(instruction);
481 }
482
483 /**
484 * Pseudo-external assembler syntax: {@code ldsh }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
485 * Example disassembly syntax: {@code ldsh [%g0 + -4096], %g0}
486 * <p>
487 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
488 *
489 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
490 */
491 // Template#: 28, Serial#: 28
492 public void ldsh(final GPR rs1, final int simm13, final GPR rd) {
493 int instruction = 0xC0502000;
494 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
495 instruction |= ((rs1.value() & 0x1f) << 14);
496 instruction |= (simm13 & 0x1fff);
497 instruction |= ((rd.value() & 0x1f) << 25);
498 emitInt(instruction);
499 }
500
501 /**
502 * Pseudo-external assembler syntax: {@code ldsw }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
503 * Example disassembly syntax: {@code ldsw [%g0 + %g0], %g0}
504 *
505 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
506 */
507 // Template#: 29, Serial#: 29
508 public void ldsw(final GPR rs1, final GPR rs2, final GPR rd) {
509 int instruction = 0xC0400000;
510 instruction |= ((rs1.value() & 0x1f) << 14);
511 instruction |= (rs2.value() & 0x1f);
512 instruction |= ((rd.value() & 0x1f) << 25);
513 emitInt(instruction);
514 }
515
516 /**
517 * Pseudo-external assembler syntax: {@code ldsw }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
518 * Example disassembly syntax: {@code ldsw [%g0 + -4096], %g0}
519 * <p>
520 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
521 *
522 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
523 */
524 // Template#: 30, Serial#: 30
525 public void ldsw(final GPR rs1, final int simm13, final GPR rd) {
526 int instruction = 0xC0402000;
527 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
528 instruction |= ((rs1.value() & 0x1f) << 14);
529 instruction |= (simm13 & 0x1fff);
530 instruction |= ((rd.value() & 0x1f) << 25);
531 emitInt(instruction);
532 }
533
534 /**
535 * Pseudo-external assembler syntax: {@code ldub }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
536 * Example disassembly syntax: {@code ldub [%g0 + %g0], %g0}
537 *
538 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
539 */
540 // Template#: 31, Serial#: 31
541 public void ldub(final GPR rs1, final GPR rs2, final GPR rd) {
542 int instruction = 0xC0080000;
543 instruction |= ((rs1.value() & 0x1f) << 14);
544 instruction |= (rs2.value() & 0x1f);
545 instruction |= ((rd.value() & 0x1f) << 25);
546 emitInt(instruction);
547 }
548
549 /**
550 * Pseudo-external assembler syntax: {@code ldub }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
551 * Example disassembly syntax: {@code ldub [%g0 + -4096], %g0}
552 * <p>
553 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
554 *
555 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
556 */
557 // Template#: 32, Serial#: 32
558 public void ldub(final GPR rs1, final int simm13, final GPR rd) {
559 int instruction = 0xC0082000;
560 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
561 instruction |= ((rs1.value() & 0x1f) << 14);
562 instruction |= (simm13 & 0x1fff);
563 instruction |= ((rd.value() & 0x1f) << 25);
564 emitInt(instruction);
565 }
566
567 /**
568 * Pseudo-external assembler syntax: {@code lduh }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
569 * Example disassembly syntax: {@code lduh [%g0 + %g0], %g0}
570 *
571 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
572 */
573 // Template#: 33, Serial#: 33
574 public void lduh(final GPR rs1, final GPR rs2, final GPR rd) {
575 int instruction = 0xC0100000;
576 instruction |= ((rs1.value() & 0x1f) << 14);
577 instruction |= (rs2.value() & 0x1f);
578 instruction |= ((rd.value() & 0x1f) << 25);
579 emitInt(instruction);
580 }
581
582 /**
583 * Pseudo-external assembler syntax: {@code lduh }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
584 * Example disassembly syntax: {@code lduh [%g0 + -4096], %g0}
585 * <p>
586 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
587 *
588 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
589 */
590 // Template#: 34, Serial#: 34
591 public void lduh(final GPR rs1, final int simm13, final GPR rd) {
592 int instruction = 0xC0102000;
593 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
594 instruction |= ((rs1.value() & 0x1f) << 14);
595 instruction |= (simm13 & 0x1fff);
596 instruction |= ((rd.value() & 0x1f) << 25);
597 emitInt(instruction);
598 }
599
600 /**
601 * Pseudo-external assembler syntax: {@code lduw }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
602 * Example disassembly syntax: {@code lduw [%g0 + %g0], %g0}
603 *
604 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
605 */
606 // Template#: 35, Serial#: 35
607 public void lduw(final GPR rs1, final GPR rs2, final GPR rd) {
608 int instruction = 0xC0000000;
609 instruction |= ((rs1.value() & 0x1f) << 14);
610 instruction |= (rs2.value() & 0x1f);
611 instruction |= ((rd.value() & 0x1f) << 25);
612 emitInt(instruction);
613 }
614
615 /**
616 * Pseudo-external assembler syntax: {@code lduw }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
617 * Example disassembly syntax: {@code lduw [%g0 + -4096], %g0}
618 * <p>
619 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
620 *
621 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
622 */
623 // Template#: 36, Serial#: 36
624 public void lduw(final GPR rs1, final int simm13, final GPR rd) {
625 int instruction = 0xC0002000;
626 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
627 instruction |= ((rs1.value() & 0x1f) << 14);
628 instruction |= (simm13 & 0x1fff);
629 instruction |= ((rd.value() & 0x1f) << 25);
630 emitInt(instruction);
631 }
632
633 /**
634 * Pseudo-external assembler syntax: {@code ldx }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
635 * Example disassembly syntax: {@code ldx [%g0 + %g0], %g0}
636 *
637 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
638 */
639 // Template#: 37, Serial#: 37
640 public void ldx(final GPR rs1, final GPR rs2, final GPR rd) {
641 int instruction = 0xC0580000;
642 instruction |= ((rs1.value() & 0x1f) << 14);
643 instruction |= (rs2.value() & 0x1f);
644 instruction |= ((rd.value() & 0x1f) << 25);
645 emitInt(instruction);
646 }
647
648 /**
649 * Pseudo-external assembler syntax: {@code ldx }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
650 * Example disassembly syntax: {@code ldx [%g0 + -4096], %g0}
651 * <p>
652 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
653 *
654 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
655 */
656 // Template#: 38, Serial#: 38
657 public void ldx(final GPR rs1, final int simm13, final GPR rd) {
658 int instruction = 0xC0582000;
659 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
660 instruction |= ((rs1.value() & 0x1f) << 14);
661 instruction |= (simm13 & 0x1fff);
662 instruction |= ((rd.value() & 0x1f) << 25);
663 emitInt(instruction);
664 }
665
666 /**
667 * Pseudo-external assembler syntax: {@code ldd }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
668 * Example disassembly syntax: {@code ldd [%g0 + %g0], %g0}
669 *
670 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
671 */
672 // Template#: 39, Serial#: 39
673 public void ldd(final GPR rs1, final GPR rs2, final GPR.Even rd) {
674 int instruction = 0xC0180000;
675 instruction |= ((rs1.value() & 0x1f) << 14);
676 instruction |= (rs2.value() & 0x1f);
677 instruction |= ((rd.value() & 0x1f) << 25);
678 emitInt(instruction);
679 }
680
681 /**
682 * Pseudo-external assembler syntax: {@code ldd }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
683 * Example disassembly syntax: {@code ldd [%g0 + -4096], %g0}
684 * <p>
685 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
686 *
687 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.27"
688 */
689 // Template#: 40, Serial#: 40
690 public void ldd(final GPR rs1, final int simm13, final GPR.Even rd) {
691 int instruction = 0xC0182000;
692 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
693 instruction |= ((rs1.value() & 0x1f) << 14);
694 instruction |= (simm13 & 0x1fff);
695 instruction |= ((rd.value() & 0x1f) << 25);
696 emitInt(instruction);
697 }
698
699 /**
700 * Pseudo-external assembler syntax: {@code ldsba }<i>rs1</i>, <i>rs2</i>, <i>immAsi</i>, <i>rd</i>
701 * Example disassembly syntax: {@code ldsba [%g0 + %g0] 0x0, %g0}
702 * <p>
703 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
704 *
705 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
706 */
707 // Template#: 41, Serial#: 41
708 public void ldsba(final GPR rs1, final GPR rs2, final int immAsi, final GPR rd) {
709 int instruction = 0xC0C80000;
710 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
711 instruction |= ((rs1.value() & 0x1f) << 14);
712 instruction |= (rs2.value() & 0x1f);
713 instruction |= ((immAsi & 0xff) << 5);
714 instruction |= ((rd.value() & 0x1f) << 25);
715 emitInt(instruction);
716 }
717
718 /**
719 * Pseudo-external assembler syntax: {@code ldsba }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
720 * Example disassembly syntax: {@code ldsba [%g0 + -4096] %asi, %g0}
721 * <p>
722 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
723 *
724 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
725 */
726 // Template#: 42, Serial#: 42
727 public void ldsba(final GPR rs1, final int simm13, final GPR rd) {
728 int instruction = 0xC0C82000;
729 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
730 instruction |= ((rs1.value() & 0x1f) << 14);
731 instruction |= (simm13 & 0x1fff);
732 instruction |= ((rd.value() & 0x1f) << 25);
733 emitInt(instruction);
734 }
735
736 /**
737 * Pseudo-external assembler syntax: {@code ldsha }<i>rs1</i>, <i>rs2</i>, <i>immAsi</i>, <i>rd</i>
738 * Example disassembly syntax: {@code ldsha [%g0 + %g0] 0x0, %g0}
739 * <p>
740 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
741 *
742 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
743 */
744 // Template#: 43, Serial#: 43
745 public void ldsha(final GPR rs1, final GPR rs2, final int immAsi, final GPR rd) {
746 int instruction = 0xC0D00000;
747 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
748 instruction |= ((rs1.value() & 0x1f) << 14);
749 instruction |= (rs2.value() & 0x1f);
750 instruction |= ((immAsi & 0xff) << 5);
751 instruction |= ((rd.value() & 0x1f) << 25);
752 emitInt(instruction);
753 }
754
755 /**
756 * Pseudo-external assembler syntax: {@code ldsha }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
757 * Example disassembly syntax: {@code ldsha [%g0 + -4096] %asi, %g0}
758 * <p>
759 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
760 *
761 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
762 */
763 // Template#: 44, Serial#: 44
764 public void ldsha(final GPR rs1, final int simm13, final GPR rd) {
765 int instruction = 0xC0D02000;
766 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
767 instruction |= ((rs1.value() & 0x1f) << 14);
768 instruction |= (simm13 & 0x1fff);
769 instruction |= ((rd.value() & 0x1f) << 25);
770 emitInt(instruction);
771 }
772
773 /**
774 * Pseudo-external assembler syntax: {@code ldswa }<i>rs1</i>, <i>rs2</i>, <i>immAsi</i>, <i>rd</i>
775 * Example disassembly syntax: {@code ldswa [%g0 + %g0] 0x0, %g0}
776 * <p>
777 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
778 *
779 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
780 */
781 // Template#: 45, Serial#: 45
782 public void ldswa(final GPR rs1, final GPR rs2, final int immAsi, final GPR rd) {
783 int instruction = 0xC0C00000;
784 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
785 instruction |= ((rs1.value() & 0x1f) << 14);
786 instruction |= (rs2.value() & 0x1f);
787 instruction |= ((immAsi & 0xff) << 5);
788 instruction |= ((rd.value() & 0x1f) << 25);
789 emitInt(instruction);
790 }
791
792 /**
793 * Pseudo-external assembler syntax: {@code ldswa }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
794 * Example disassembly syntax: {@code ldswa [%g0 + -4096] %asi, %g0}
795 * <p>
796 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
797 *
798 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
799 */
800 // Template#: 46, Serial#: 46
801 public void ldswa(final GPR rs1, final int simm13, final GPR rd) {
802 int instruction = 0xC0C02000;
803 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
804 instruction |= ((rs1.value() & 0x1f) << 14);
805 instruction |= (simm13 & 0x1fff);
806 instruction |= ((rd.value() & 0x1f) << 25);
807 emitInt(instruction);
808 }
809
810 /**
811 * Pseudo-external assembler syntax: {@code lduba }<i>rs1</i>, <i>rs2</i>, <i>immAsi</i>, <i>rd</i>
812 * Example disassembly syntax: {@code lduba [%g0 + %g0] 0x0, %g0}
813 * <p>
814 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
815 *
816 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
817 */
818 // Template#: 47, Serial#: 47
819 public void lduba(final GPR rs1, final GPR rs2, final int immAsi, final GPR rd) {
820 int instruction = 0xC0880000;
821 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
822 instruction |= ((rs1.value() & 0x1f) << 14);
823 instruction |= (rs2.value() & 0x1f);
824 instruction |= ((immAsi & 0xff) << 5);
825 instruction |= ((rd.value() & 0x1f) << 25);
826 emitInt(instruction);
827 }
828
829 /**
830 * Pseudo-external assembler syntax: {@code lduba }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
831 * Example disassembly syntax: {@code lduba [%g0 + -4096] %asi, %g0}
832 * <p>
833 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
834 *
835 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
836 */
837 // Template#: 48, Serial#: 48
838 public void lduba(final GPR rs1, final int simm13, final GPR rd) {
839 int instruction = 0xC0882000;
840 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
841 instruction |= ((rs1.value() & 0x1f) << 14);
842 instruction |= (simm13 & 0x1fff);
843 instruction |= ((rd.value() & 0x1f) << 25);
844 emitInt(instruction);
845 }
846
847 /**
848 * Pseudo-external assembler syntax: {@code lduha }<i>rs1</i>, <i>rs2</i>, <i>immAsi</i>, <i>rd</i>
849 * Example disassembly syntax: {@code lduha [%g0 + %g0] 0x0, %g0}
850 * <p>
851 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
852 *
853 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
854 */
855 // Template#: 49, Serial#: 49
856 public void lduha(final GPR rs1, final GPR rs2, final int immAsi, final GPR rd) {
857 int instruction = 0xC0900000;
858 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
859 instruction |= ((rs1.value() & 0x1f) << 14);
860 instruction |= (rs2.value() & 0x1f);
861 instruction |= ((immAsi & 0xff) << 5);
862 instruction |= ((rd.value() & 0x1f) << 25);
863 emitInt(instruction);
864 }
865
866 /**
867 * Pseudo-external assembler syntax: {@code lduha }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
868 * Example disassembly syntax: {@code lduha [%g0 + -4096] %asi, %g0}
869 * <p>
870 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
871 *
872 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
873 */
874 // Template#: 50, Serial#: 50
875 public void lduha(final GPR rs1, final int simm13, final GPR rd) {
876 int instruction = 0xC0902000;
877 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
878 instruction |= ((rs1.value() & 0x1f) << 14);
879 instruction |= (simm13 & 0x1fff);
880 instruction |= ((rd.value() & 0x1f) << 25);
881 emitInt(instruction);
882 }
883
884 /**
885 * Pseudo-external assembler syntax: {@code lduwa }<i>rs1</i>, <i>rs2</i>, <i>immAsi</i>, <i>rd</i>
886 * Example disassembly syntax: {@code lduwa [%g0 + %g0] 0x0, %g0}
887 * <p>
888 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
889 *
890 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
891 */
892 // Template#: 51, Serial#: 51
893 public void lduwa(final GPR rs1, final GPR rs2, final int immAsi, final GPR rd) {
894 int instruction = 0xC0800000;
895 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
896 instruction |= ((rs1.value() & 0x1f) << 14);
897 instruction |= (rs2.value() & 0x1f);
898 instruction |= ((immAsi & 0xff) << 5);
899 instruction |= ((rd.value() & 0x1f) << 25);
900 emitInt(instruction);
901 }
902
903 /**
904 * Pseudo-external assembler syntax: {@code lduwa }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
905 * Example disassembly syntax: {@code lduwa [%g0 + -4096] %asi, %g0}
906 * <p>
907 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
908 *
909 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
910 */
911 // Template#: 52, Serial#: 52
912 public void lduwa(final GPR rs1, final int simm13, final GPR rd) {
913 int instruction = 0xC0802000;
914 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
915 instruction |= ((rs1.value() & 0x1f) << 14);
916 instruction |= (simm13 & 0x1fff);
917 instruction |= ((rd.value() & 0x1f) << 25);
918 emitInt(instruction);
919 }
920
921 /**
922 * Pseudo-external assembler syntax: {@code ldxa }<i>rs1</i>, <i>rs2</i>, <i>immAsi</i>, <i>rd</i>
923 * Example disassembly syntax: {@code ldxa [%g0 + %g0] 0x0, %g0}
924 * <p>
925 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
926 *
927 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
928 */
929 // Template#: 53, Serial#: 53
930 public void ldxa(final GPR rs1, final GPR rs2, final int immAsi, final GPR rd) {
931 int instruction = 0xC0D80000;
932 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
933 instruction |= ((rs1.value() & 0x1f) << 14);
934 instruction |= (rs2.value() & 0x1f);
935 instruction |= ((immAsi & 0xff) << 5);
936 instruction |= ((rd.value() & 0x1f) << 25);
937 emitInt(instruction);
938 }
939
940 /**
941 * Pseudo-external assembler syntax: {@code ldxa }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
942 * Example disassembly syntax: {@code ldxa [%g0 + -4096] %asi, %g0}
943 * <p>
944 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
945 *
946 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
947 */
948 // Template#: 54, Serial#: 54
949 public void ldxa(final GPR rs1, final int simm13, final GPR rd) {
950 int instruction = 0xC0D82000;
951 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
952 instruction |= ((rs1.value() & 0x1f) << 14);
953 instruction |= (simm13 & 0x1fff);
954 instruction |= ((rd.value() & 0x1f) << 25);
955 emitInt(instruction);
956 }
957
958 /**
959 * Pseudo-external assembler syntax: {@code ldda }<i>rs1</i>, <i>rs2</i>, <i>immAsi</i>, <i>rd</i>
960 * Example disassembly syntax: {@code ldda [%g0 + %g0] 0x0, %g0}
961 * <p>
962 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
963 *
964 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
965 */
966 // Template#: 55, Serial#: 55
967 public void ldda(final GPR rs1, final GPR rs2, final int immAsi, final GPR.Even rd) {
968 int instruction = 0xC0980000;
969 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
970 instruction |= ((rs1.value() & 0x1f) << 14);
971 instruction |= (rs2.value() & 0x1f);
972 instruction |= ((immAsi & 0xff) << 5);
973 instruction |= ((rd.value() & 0x1f) << 25);
974 emitInt(instruction);
975 }
976
977 /**
978 * Pseudo-external assembler syntax: {@code ldda }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
979 * Example disassembly syntax: {@code ldda [%g0 + -4096] %asi, %g0}
980 * <p>
981 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
982 *
983 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.28"
984 */
985 // Template#: 56, Serial#: 56
986 public void ldda(final GPR rs1, final int simm13, final GPR.Even rd) {
987 int instruction = 0xC0982000;
988 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
989 instruction |= ((rs1.value() & 0x1f) << 14);
990 instruction |= (simm13 & 0x1fff);
991 instruction |= ((rd.value() & 0x1f) << 25);
992 emitInt(instruction);
993 }
994
995 /**
996 * Pseudo-external assembler syntax: {@code ldstub }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
997 * Example disassembly syntax: {@code ldstub [%g0 + %g0], %g0}
998 *
999 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.29"
1000 */
1001 // Template#: 57, Serial#: 57
1002 public void ldstub(final GPR rs1, final GPR rs2, final GPR rd) {
1003 int instruction = 0xC0680000;
1004 instruction |= ((rs1.value() & 0x1f) << 14);
1005 instruction |= (rs2.value() & 0x1f);
1006 instruction |= ((rd.value() & 0x1f) << 25);
1007 emitInt(instruction);
1008 }
1009
1010 /**
1011 * Pseudo-external assembler syntax: {@code ldstub }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
1012 * Example disassembly syntax: {@code ldstub [%g0 + -4096], %g0}
1013 * <p>
1014 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1015 *
1016 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.29"
1017 */
1018 // Template#: 58, Serial#: 58
1019 public void ldstub(final GPR rs1, final int simm13, final GPR rd) {
1020 int instruction = 0xC0682000;
1021 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1022 instruction |= ((rs1.value() & 0x1f) << 14);
1023 instruction |= (simm13 & 0x1fff);
1024 instruction |= ((rd.value() & 0x1f) << 25);
1025 emitInt(instruction);
1026 }
1027
1028 /**
1029 * Pseudo-external assembler syntax: {@code ldstuba }<i>rs1</i>, <i>rs2</i>, <i>immAsi</i>, <i>rd</i>
1030 * Example disassembly syntax: {@code ldstuba [%g0 + %g0] 0x0, %g0}
1031 * <p>
1032 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
1033 *
1034 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.30"
1035 */
1036 // Template#: 59, Serial#: 59
1037 public void ldstuba(final GPR rs1, final GPR rs2, final int immAsi, final GPR rd) {
1038 int instruction = 0xC0E80000;
1039 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
1040 instruction |= ((rs1.value() & 0x1f) << 14);
1041 instruction |= (rs2.value() & 0x1f);
1042 instruction |= ((immAsi & 0xff) << 5);
1043 instruction |= ((rd.value() & 0x1f) << 25);
1044 emitInt(instruction);
1045 }
1046
1047 /**
1048 * Pseudo-external assembler syntax: {@code ldstuba }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
1049 * Example disassembly syntax: {@code ldstuba [%g0 + -4096] %asi, %g0}
1050 * <p>
1051 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1052 *
1053 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.30"
1054 */
1055 // Template#: 60, Serial#: 60
1056 public void ldstuba(final GPR rs1, final int simm13, final GPR rd) {
1057 int instruction = 0xC0E82000;
1058 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1059 instruction |= ((rs1.value() & 0x1f) << 14);
1060 instruction |= (simm13 & 0x1fff);
1061 instruction |= ((rd.value() & 0x1f) << 25);
1062 emitInt(instruction);
1063 }
1064
1065 /**
1066 * Pseudo-external assembler syntax: {@code prefetch }<i>rs1</i>, <i>rs2</i>, <i>fcn</i>
1067 * Example disassembly syntax: {@code prefetch [%g0 + %g0], 0x0}
1068 * <p>
1069 * Constraint: {@code 0 <= fcn && fcn <= 31}<br />
1070 *
1071 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.41"
1072 */
1073 // Template#: 61, Serial#: 61
1074 public void prefetch(final GPR rs1, final GPR rs2, final int fcn) {
1075 int instruction = 0xC1680000;
1076 checkConstraint(0 <= fcn && fcn <= 31, "0 <= fcn && fcn <= 31");
1077 instruction |= ((rs1.value() & 0x1f) << 14);
1078 instruction |= (rs2.value() & 0x1f);
1079 instruction |= ((fcn & 0x1f) << 25);
1080 emitInt(instruction);
1081 }
1082
1083 /**
1084 * Pseudo-external assembler syntax: {@code prefetch }<i>rs1</i>, <i>simm13</i>, <i>fcn</i>
1085 * Example disassembly syntax: {@code prefetch [%g0 + -4096], 0x0}
1086 * <p>
1087 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1088 * Constraint: {@code 0 <= fcn && fcn <= 31}<br />
1089 *
1090 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.41"
1091 */
1092 // Template#: 62, Serial#: 62
1093 public void prefetch(final GPR rs1, final int simm13, final int fcn) {
1094 int instruction = 0xC1682000;
1095 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1096 checkConstraint(0 <= fcn && fcn <= 31, "0 <= fcn && fcn <= 31");
1097 instruction |= ((rs1.value() & 0x1f) << 14);
1098 instruction |= (simm13 & 0x1fff);
1099 instruction |= ((fcn & 0x1f) << 25);
1100 emitInt(instruction);
1101 }
1102
1103 /**
1104 * Pseudo-external assembler syntax: {@code prefetcha }<i>rs1</i>, <i>rs2</i>, <i>immAsi</i>, <i>fcn</i>
1105 * Example disassembly syntax: {@code prefetcha [%g0 + %g0] 0x0, 0x0}
1106 * <p>
1107 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
1108 * Constraint: {@code 0 <= fcn && fcn <= 31}<br />
1109 *
1110 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.41"
1111 */
1112 // Template#: 63, Serial#: 63
1113 public void prefetcha(final GPR rs1, final GPR rs2, final int immAsi, final int fcn) {
1114 int instruction = 0xC1E80000;
1115 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
1116 checkConstraint(0 <= fcn && fcn <= 31, "0 <= fcn && fcn <= 31");
1117 instruction |= ((rs1.value() & 0x1f) << 14);
1118 instruction |= (rs2.value() & 0x1f);
1119 instruction |= ((immAsi & 0xff) << 5);
1120 instruction |= ((fcn & 0x1f) << 25);
1121 emitInt(instruction);
1122 }
1123
1124 /**
1125 * Pseudo-external assembler syntax: {@code prefetcha }<i>rs1</i>, <i>simm13</i>, <i>fcn</i>
1126 * Example disassembly syntax: {@code prefetcha [%g0 + -4096] %asi, 0x0}
1127 * <p>
1128 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1129 * Constraint: {@code 0 <= fcn && fcn <= 31}<br />
1130 *
1131 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.41"
1132 */
1133 // Template#: 64, Serial#: 64
1134 public void prefetcha(final GPR rs1, final int simm13, final int fcn) {
1135 int instruction = 0xC1E82000;
1136 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1137 checkConstraint(0 <= fcn && fcn <= 31, "0 <= fcn && fcn <= 31");
1138 instruction |= ((rs1.value() & 0x1f) << 14);
1139 instruction |= (simm13 & 0x1fff);
1140 instruction |= ((fcn & 0x1f) << 25);
1141 emitInt(instruction);
1142 }
1143
1144 /**
1145 * Pseudo-external assembler syntax: {@code st }<i>rd</i>, <i>rs1</i>, <i>rs2</i>
1146 * Example disassembly syntax: {@code st %f0, [%g0 + %g0]}
1147 *
1148 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.51"
1149 */
1150 // Template#: 65, Serial#: 65
1151 public void st(final SFPR rd, final GPR rs1, final GPR rs2) {
1152 int instruction = 0xC1200000;
1153 instruction |= ((rd.value() & 0x1f) << 25);
1154 instruction |= ((rs1.value() & 0x1f) << 14);
1155 instruction |= (rs2.value() & 0x1f);
1156 emitInt(instruction);
1157 }
1158
1159 /**
1160 * Pseudo-external assembler syntax: {@code st }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1161 * Example disassembly syntax: {@code st %f0, [%g0 + -4096]}
1162 * <p>
1163 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1164 *
1165 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.51"
1166 */
1167 // Template#: 66, Serial#: 66
1168 public void st(final SFPR rd, final GPR rs1, final int simm13) {
1169 int instruction = 0xC1202000;
1170 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1171 instruction |= ((rd.value() & 0x1f) << 25);
1172 instruction |= ((rs1.value() & 0x1f) << 14);
1173 instruction |= (simm13 & 0x1fff);
1174 emitInt(instruction);
1175 }
1176
1177 /**
1178 * Pseudo-external assembler syntax: {@code std }<i>rd</i>, <i>rs1</i>, <i>rs2</i>
1179 * Example disassembly syntax: {@code std %f0, [%g0 + %g0]}
1180 *
1181 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.51"
1182 */
1183 // Template#: 67, Serial#: 67
1184 public void std(final DFPR rd, final GPR rs1, final GPR rs2) {
1185 int instruction = 0xC1380000;
1186 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
1187 instruction |= ((rs1.value() & 0x1f) << 14);
1188 instruction |= (rs2.value() & 0x1f);
1189 emitInt(instruction);
1190 }
1191
1192 /**
1193 * Pseudo-external assembler syntax: {@code std }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1194 * Example disassembly syntax: {@code std %f0, [%g0 + -4096]}
1195 * <p>
1196 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1197 *
1198 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.51"
1199 */
1200 // Template#: 68, Serial#: 68
1201 public void std(final DFPR rd, final GPR rs1, final int simm13) {
1202 int instruction = 0xC1382000;
1203 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1204 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
1205 instruction |= ((rs1.value() & 0x1f) << 14);
1206 instruction |= (simm13 & 0x1fff);
1207 emitInt(instruction);
1208 }
1209
1210 /**
1211 * Pseudo-external assembler syntax: {@code stq }<i>rd</i>, <i>rs1</i>, <i>rs2</i>
1212 * Example disassembly syntax: {@code stq %f0, [%g0 + %g0]}
1213 *
1214 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.51"
1215 */
1216 // Template#: 69, Serial#: 69
1217 public void stq(final QFPR rd, final GPR rs1, final GPR rs2) {
1218 int instruction = 0xC1300000;
1219 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
1220 instruction |= ((rs1.value() & 0x1f) << 14);
1221 instruction |= (rs2.value() & 0x1f);
1222 emitInt(instruction);
1223 }
1224
1225 /**
1226 * Pseudo-external assembler syntax: {@code stq }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1227 * Example disassembly syntax: {@code stq %f0, [%g0 + -4096]}
1228 * <p>
1229 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1230 *
1231 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.51"
1232 */
1233 // Template#: 70, Serial#: 70
1234 public void stq(final QFPR rd, final GPR rs1, final int simm13) {
1235 int instruction = 0xC1302000;
1236 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1237 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
1238 instruction |= ((rs1.value() & 0x1f) << 14);
1239 instruction |= (simm13 & 0x1fff);
1240 emitInt(instruction);
1241 }
1242
1243 /**
1244 * Pseudo-external assembler syntax: {@code stx }<i>rs1</i>, <i>rs2</i>
1245 * Example disassembly syntax: {@code stx %fsr, [%g0 + %g0]}
1246 *
1247 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.51"
1248 */
1249 // Template#: 71, Serial#: 71
1250 public void stx_fsr(final GPR rs1, final GPR rs2) {
1251 int instruction = 0xC3280000;
1252 instruction |= ((rs1.value() & 0x1f) << 14);
1253 instruction |= (rs2.value() & 0x1f);
1254 emitInt(instruction);
1255 }
1256
1257 /**
1258 * Pseudo-external assembler syntax: {@code stx }<i>rs1</i>, <i>simm13</i>
1259 * Example disassembly syntax: {@code stx %fsr, [%g0 + -4096]}
1260 * <p>
1261 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1262 *
1263 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.51"
1264 */
1265 // Template#: 72, Serial#: 72
1266 public void stx_fsr(final GPR rs1, final int simm13) {
1267 int instruction = 0xC3282000;
1268 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1269 instruction |= ((rs1.value() & 0x1f) << 14);
1270 instruction |= (simm13 & 0x1fff);
1271 emitInt(instruction);
1272 }
1273
1274 /**
1275 * Pseudo-external assembler syntax: {@code st }<i>rs1</i>, <i>rs2</i>
1276 * Example disassembly syntax: {@code st %fsr, [%g0 + %g0]}
1277 *
1278 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.51"
1279 */
1280 // Template#: 73, Serial#: 73
1281 public void st_fsr(final GPR rs1, final GPR rs2) {
1282 int instruction = 0xC1280000;
1283 instruction |= ((rs1.value() & 0x1f) << 14);
1284 instruction |= (rs2.value() & 0x1f);
1285 emitInt(instruction);
1286 }
1287
1288 /**
1289 * Pseudo-external assembler syntax: {@code st }<i>rs1</i>, <i>simm13</i>
1290 * Example disassembly syntax: {@code st %fsr, [%g0 + -4096]}
1291 * <p>
1292 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1293 *
1294 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.51"
1295 */
1296 // Template#: 74, Serial#: 74
1297 public void st_fsr(final GPR rs1, final int simm13) {
1298 int instruction = 0xC1282000;
1299 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1300 instruction |= ((rs1.value() & 0x1f) << 14);
1301 instruction |= (simm13 & 0x1fff);
1302 emitInt(instruction);
1303 }
1304
1305 /**
1306 * Pseudo-external assembler syntax: {@code sta }<i>rd</i>, <i>rs1</i>, <i>rs2</i>, <i>immAsi</i>
1307 * Example disassembly syntax: {@code sta %f0, [%g0 + %g0]0x0}
1308 * <p>
1309 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
1310 *
1311 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.52"
1312 */
1313 // Template#: 75, Serial#: 75
1314 public void sta(final SFPR rd, final GPR rs1, final GPR rs2, final int immAsi) {
1315 int instruction = 0xC1A00000;
1316 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
1317 instruction |= ((rd.value() & 0x1f) << 25);
1318 instruction |= ((rs1.value() & 0x1f) << 14);
1319 instruction |= (rs2.value() & 0x1f);
1320 instruction |= ((immAsi & 0xff) << 5);
1321 emitInt(instruction);
1322 }
1323
1324 /**
1325 * Pseudo-external assembler syntax: {@code sta }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1326 * Example disassembly syntax: {@code sta %f0, [%g0 + -4096] %asi}
1327 * <p>
1328 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1329 *
1330 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.52"
1331 */
1332 // Template#: 76, Serial#: 76
1333 public void sta(final SFPR rd, final GPR rs1, final int simm13) {
1334 int instruction = 0xC1A02000;
1335 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1336 instruction |= ((rd.value() & 0x1f) << 25);
1337 instruction |= ((rs1.value() & 0x1f) << 14);
1338 instruction |= (simm13 & 0x1fff);
1339 emitInt(instruction);
1340 }
1341
1342 /**
1343 * Pseudo-external assembler syntax: {@code stda }<i>rd</i>, <i>rs1</i>, <i>rs2</i>, <i>immAsi</i>
1344 * Example disassembly syntax: {@code stda %f0, [%g0 + %g0]0x0}
1345 * <p>
1346 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
1347 *
1348 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.52"
1349 */
1350 // Template#: 77, Serial#: 77
1351 public void stda(final DFPR rd, final GPR rs1, final GPR rs2, final int immAsi) {
1352 int instruction = 0xC1B80000;
1353 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
1354 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
1355 instruction |= ((rs1.value() & 0x1f) << 14);
1356 instruction |= (rs2.value() & 0x1f);
1357 instruction |= ((immAsi & 0xff) << 5);
1358 emitInt(instruction);
1359 }
1360
1361 /**
1362 * Pseudo-external assembler syntax: {@code stda }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1363 * Example disassembly syntax: {@code stda %f0, [%g0 + -4096] %asi}
1364 * <p>
1365 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1366 *
1367 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.52"
1368 */
1369 // Template#: 78, Serial#: 78
1370 public void stda(final DFPR rd, final GPR rs1, final int simm13) {
1371 int instruction = 0xC1B82000;
1372 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1373 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
1374 instruction |= ((rs1.value() & 0x1f) << 14);
1375 instruction |= (simm13 & 0x1fff);
1376 emitInt(instruction);
1377 }
1378
1379 /**
1380 * Pseudo-external assembler syntax: {@code stqa }<i>rd</i>, <i>rs1</i>, <i>rs2</i>, <i>immAsi</i>
1381 * Example disassembly syntax: {@code stqa %f0, [%g0 + %g0]0x0}
1382 * <p>
1383 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
1384 *
1385 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.52"
1386 */
1387 // Template#: 79, Serial#: 79
1388 public void stqa(final QFPR rd, final GPR rs1, final GPR rs2, final int immAsi) {
1389 int instruction = 0xC1B00000;
1390 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
1391 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
1392 instruction |= ((rs1.value() & 0x1f) << 14);
1393 instruction |= (rs2.value() & 0x1f);
1394 instruction |= ((immAsi & 0xff) << 5);
1395 emitInt(instruction);
1396 }
1397
1398 /**
1399 * Pseudo-external assembler syntax: {@code stqa }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1400 * Example disassembly syntax: {@code stqa %f0, [%g0 + -4096] %asi}
1401 * <p>
1402 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1403 *
1404 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.52"
1405 */
1406 // Template#: 80, Serial#: 80
1407 public void stqa(final QFPR rd, final GPR rs1, final int simm13) {
1408 int instruction = 0xC1B02000;
1409 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1410 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
1411 instruction |= ((rs1.value() & 0x1f) << 14);
1412 instruction |= (simm13 & 0x1fff);
1413 emitInt(instruction);
1414 }
1415
1416 /**
1417 * Pseudo-external assembler syntax: {@code stb }<i>rd</i>, <i>rs1</i>, <i>rs2</i>
1418 * Example disassembly syntax: {@code stb %g0, [%g0 + %g0]}
1419 *
1420 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.53"
1421 */
1422 // Template#: 81, Serial#: 81
1423 public void stb(final GPR rd, final GPR rs1, final GPR rs2) {
1424 int instruction = 0xC0280000;
1425 instruction |= ((rd.value() & 0x1f) << 25);
1426 instruction |= ((rs1.value() & 0x1f) << 14);
1427 instruction |= (rs2.value() & 0x1f);
1428 emitInt(instruction);
1429 }
1430
1431 /**
1432 * Pseudo-external assembler syntax: {@code stb }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1433 * Example disassembly syntax: {@code stb %g0, [%g0 + -4096]}
1434 * <p>
1435 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1436 *
1437 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.53"
1438 */
1439 // Template#: 82, Serial#: 82
1440 public void stb(final GPR rd, final GPR rs1, final int simm13) {
1441 int instruction = 0xC0282000;
1442 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1443 instruction |= ((rd.value() & 0x1f) << 25);
1444 instruction |= ((rs1.value() & 0x1f) << 14);
1445 instruction |= (simm13 & 0x1fff);
1446 emitInt(instruction);
1447 }
1448
1449 /**
1450 * Pseudo-external assembler syntax: {@code sth }<i>rd</i>, <i>rs1</i>, <i>rs2</i>
1451 * Example disassembly syntax: {@code sth %g0, [%g0 + %g0]}
1452 *
1453 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.53"
1454 */
1455 // Template#: 83, Serial#: 83
1456 public void sth(final GPR rd, final GPR rs1, final GPR rs2) {
1457 int instruction = 0xC0300000;
1458 instruction |= ((rd.value() & 0x1f) << 25);
1459 instruction |= ((rs1.value() & 0x1f) << 14);
1460 instruction |= (rs2.value() & 0x1f);
1461 emitInt(instruction);
1462 }
1463
1464 /**
1465 * Pseudo-external assembler syntax: {@code sth }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1466 * Example disassembly syntax: {@code sth %g0, [%g0 + -4096]}
1467 * <p>
1468 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1469 *
1470 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.53"
1471 */
1472 // Template#: 84, Serial#: 84
1473 public void sth(final GPR rd, final GPR rs1, final int simm13) {
1474 int instruction = 0xC0302000;
1475 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1476 instruction |= ((rd.value() & 0x1f) << 25);
1477 instruction |= ((rs1.value() & 0x1f) << 14);
1478 instruction |= (simm13 & 0x1fff);
1479 emitInt(instruction);
1480 }
1481
1482 /**
1483 * Pseudo-external assembler syntax: {@code stw }<i>rd</i>, <i>rs1</i>, <i>rs2</i>
1484 * Example disassembly syntax: {@code stw %g0, [%g0 + %g0]}
1485 *
1486 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.53"
1487 */
1488 // Template#: 85, Serial#: 85
1489 public void stw(final GPR rd, final GPR rs1, final GPR rs2) {
1490 int instruction = 0xC0200000;
1491 instruction |= ((rd.value() & 0x1f) << 25);
1492 instruction |= ((rs1.value() & 0x1f) << 14);
1493 instruction |= (rs2.value() & 0x1f);
1494 emitInt(instruction);
1495 }
1496
1497 /**
1498 * Pseudo-external assembler syntax: {@code stw }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1499 * Example disassembly syntax: {@code stw %g0, [%g0 + -4096]}
1500 * <p>
1501 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1502 *
1503 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.53"
1504 */
1505 // Template#: 86, Serial#: 86
1506 public void stw(final GPR rd, final GPR rs1, final int simm13) {
1507 int instruction = 0xC0202000;
1508 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1509 instruction |= ((rd.value() & 0x1f) << 25);
1510 instruction |= ((rs1.value() & 0x1f) << 14);
1511 instruction |= (simm13 & 0x1fff);
1512 emitInt(instruction);
1513 }
1514
1515 /**
1516 * Pseudo-external assembler syntax: {@code stx }<i>rd</i>, <i>rs1</i>, <i>rs2</i>
1517 * Example disassembly syntax: {@code stx %g0, [%g0 + %g0]}
1518 *
1519 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.53"
1520 */
1521 // Template#: 87, Serial#: 87
1522 public void stx(final GPR rd, final GPR rs1, final GPR rs2) {
1523 int instruction = 0xC0700000;
1524 instruction |= ((rd.value() & 0x1f) << 25);
1525 instruction |= ((rs1.value() & 0x1f) << 14);
1526 instruction |= (rs2.value() & 0x1f);
1527 emitInt(instruction);
1528 }
1529
1530 /**
1531 * Pseudo-external assembler syntax: {@code stx }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1532 * Example disassembly syntax: {@code stx %g0, [%g0 + -4096]}
1533 * <p>
1534 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1535 *
1536 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.53"
1537 */
1538 // Template#: 88, Serial#: 88
1539 public void stx(final GPR rd, final GPR rs1, final int simm13) {
1540 int instruction = 0xC0702000;
1541 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1542 instruction |= ((rd.value() & 0x1f) << 25);
1543 instruction |= ((rs1.value() & 0x1f) << 14);
1544 instruction |= (simm13 & 0x1fff);
1545 emitInt(instruction);
1546 }
1547
1548 /**
1549 * Pseudo-external assembler syntax: {@code std }<i>rd</i>, <i>rs1</i>, <i>rs2</i>
1550 * Example disassembly syntax: {@code std %g0, [%g0 + %g0]}
1551 *
1552 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.53"
1553 */
1554 // Template#: 89, Serial#: 89
1555 public void std(final GPR.Even rd, final GPR rs1, final GPR rs2) {
1556 int instruction = 0xC0380000;
1557 instruction |= ((rd.value() & 0x1f) << 25);
1558 instruction |= ((rs1.value() & 0x1f) << 14);
1559 instruction |= (rs2.value() & 0x1f);
1560 emitInt(instruction);
1561 }
1562
1563 /**
1564 * Pseudo-external assembler syntax: {@code std }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1565 * Example disassembly syntax: {@code std %g0, [%g0 + -4096]}
1566 * <p>
1567 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1568 *
1569 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.53"
1570 */
1571 // Template#: 90, Serial#: 90
1572 public void std(final GPR.Even rd, final GPR rs1, final int simm13) {
1573 int instruction = 0xC0382000;
1574 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1575 instruction |= ((rd.value() & 0x1f) << 25);
1576 instruction |= ((rs1.value() & 0x1f) << 14);
1577 instruction |= (simm13 & 0x1fff);
1578 emitInt(instruction);
1579 }
1580
1581 /**
1582 * Pseudo-external assembler syntax: {@code stba }<i>rd</i>, <i>rs1</i>, <i>rs2</i>, <i>immAsi</i>
1583 * Example disassembly syntax: {@code stba %g0, [%g0 + %g0]0x0}
1584 * <p>
1585 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
1586 *
1587 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.54"
1588 */
1589 // Template#: 91, Serial#: 91
1590 public void stba(final GPR rd, final GPR rs1, final GPR rs2, final int immAsi) {
1591 int instruction = 0xC0A80000;
1592 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
1593 instruction |= ((rd.value() & 0x1f) << 25);
1594 instruction |= ((rs1.value() & 0x1f) << 14);
1595 instruction |= (rs2.value() & 0x1f);
1596 instruction |= ((immAsi & 0xff) << 5);
1597 emitInt(instruction);
1598 }
1599
1600 /**
1601 * Pseudo-external assembler syntax: {@code stba }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1602 * Example disassembly syntax: {@code stba %g0, [%g0 + -4096] %asi}
1603 * <p>
1604 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1605 *
1606 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.54"
1607 */
1608 // Template#: 92, Serial#: 92
1609 public void stba(final GPR rd, final GPR rs1, final int simm13) {
1610 int instruction = 0xC0A82000;
1611 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1612 instruction |= ((rd.value() & 0x1f) << 25);
1613 instruction |= ((rs1.value() & 0x1f) << 14);
1614 instruction |= (simm13 & 0x1fff);
1615 emitInt(instruction);
1616 }
1617
1618 /**
1619 * Pseudo-external assembler syntax: {@code stha }<i>rd</i>, <i>rs1</i>, <i>rs2</i>, <i>immAsi</i>
1620 * Example disassembly syntax: {@code stha %g0, [%g0 + %g0]0x0}
1621 * <p>
1622 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
1623 *
1624 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.54"
1625 */
1626 // Template#: 93, Serial#: 93
1627 public void stha(final GPR rd, final GPR rs1, final GPR rs2, final int immAsi) {
1628 int instruction = 0xC0B00000;
1629 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
1630 instruction |= ((rd.value() & 0x1f) << 25);
1631 instruction |= ((rs1.value() & 0x1f) << 14);
1632 instruction |= (rs2.value() & 0x1f);
1633 instruction |= ((immAsi & 0xff) << 5);
1634 emitInt(instruction);
1635 }
1636
1637 /**
1638 * Pseudo-external assembler syntax: {@code stha }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1639 * Example disassembly syntax: {@code stha %g0, [%g0 + -4096] %asi}
1640 * <p>
1641 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1642 *
1643 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.54"
1644 */
1645 // Template#: 94, Serial#: 94
1646 public void stha(final GPR rd, final GPR rs1, final int simm13) {
1647 int instruction = 0xC0B02000;
1648 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1649 instruction |= ((rd.value() & 0x1f) << 25);
1650 instruction |= ((rs1.value() & 0x1f) << 14);
1651 instruction |= (simm13 & 0x1fff);
1652 emitInt(instruction);
1653 }
1654
1655 /**
1656 * Pseudo-external assembler syntax: {@code stwa }<i>rd</i>, <i>rs1</i>, <i>rs2</i>, <i>immAsi</i>
1657 * Example disassembly syntax: {@code stwa %g0, [%g0 + %g0]0x0}
1658 * <p>
1659 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
1660 *
1661 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.54"
1662 */
1663 // Template#: 95, Serial#: 95
1664 public void stwa(final GPR rd, final GPR rs1, final GPR rs2, final int immAsi) {
1665 int instruction = 0xC0A00000;
1666 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
1667 instruction |= ((rd.value() & 0x1f) << 25);
1668 instruction |= ((rs1.value() & 0x1f) << 14);
1669 instruction |= (rs2.value() & 0x1f);
1670 instruction |= ((immAsi & 0xff) << 5);
1671 emitInt(instruction);
1672 }
1673
1674 /**
1675 * Pseudo-external assembler syntax: {@code stwa }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1676 * Example disassembly syntax: {@code stwa %g0, [%g0 + -4096] %asi}
1677 * <p>
1678 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1679 *
1680 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.54"
1681 */
1682 // Template#: 96, Serial#: 96
1683 public void stwa(final GPR rd, final GPR rs1, final int simm13) {
1684 int instruction = 0xC0A02000;
1685 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1686 instruction |= ((rd.value() & 0x1f) << 25);
1687 instruction |= ((rs1.value() & 0x1f) << 14);
1688 instruction |= (simm13 & 0x1fff);
1689 emitInt(instruction);
1690 }
1691
1692 /**
1693 * Pseudo-external assembler syntax: {@code stxa }<i>rd</i>, <i>rs1</i>, <i>rs2</i>, <i>immAsi</i>
1694 * Example disassembly syntax: {@code stxa %g0, [%g0 + %g0]0x0}
1695 * <p>
1696 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
1697 *
1698 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.54"
1699 */
1700 // Template#: 97, Serial#: 97
1701 public void stxa(final GPR rd, final GPR rs1, final GPR rs2, final int immAsi) {
1702 int instruction = 0xC0F00000;
1703 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
1704 instruction |= ((rd.value() & 0x1f) << 25);
1705 instruction |= ((rs1.value() & 0x1f) << 14);
1706 instruction |= (rs2.value() & 0x1f);
1707 instruction |= ((immAsi & 0xff) << 5);
1708 emitInt(instruction);
1709 }
1710
1711 /**
1712 * Pseudo-external assembler syntax: {@code stxa }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1713 * Example disassembly syntax: {@code stxa %g0, [%g0 + -4096] %asi}
1714 * <p>
1715 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1716 *
1717 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.54"
1718 */
1719 // Template#: 98, Serial#: 98
1720 public void stxa(final GPR rd, final GPR rs1, final int simm13) {
1721 int instruction = 0xC0F02000;
1722 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1723 instruction |= ((rd.value() & 0x1f) << 25);
1724 instruction |= ((rs1.value() & 0x1f) << 14);
1725 instruction |= (simm13 & 0x1fff);
1726 emitInt(instruction);
1727 }
1728
1729 /**
1730 * Pseudo-external assembler syntax: {@code stda }<i>rd</i>, <i>rs1</i>, <i>rs2</i>, <i>immAsi</i>
1731 * Example disassembly syntax: {@code stda %g0, [%g0 + %g0]0x0}
1732 * <p>
1733 * Constraint: {@code 0 <= immAsi && immAsi <= 255}<br />
1734 *
1735 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.54"
1736 */
1737 // Template#: 99, Serial#: 99
1738 public void stda(final GPR.Even rd, final GPR rs1, final GPR rs2, final int immAsi) {
1739 int instruction = 0xC0B80000;
1740 checkConstraint(0 <= immAsi && immAsi <= 255, "0 <= immAsi && immAsi <= 255");
1741 instruction |= ((rd.value() & 0x1f) << 25);
1742 instruction |= ((rs1.value() & 0x1f) << 14);
1743 instruction |= (rs2.value() & 0x1f);
1744 instruction |= ((immAsi & 0xff) << 5);
1745 emitInt(instruction);
1746 }
1747
1748 /**
1749 * Pseudo-external assembler syntax: {@code stda }<i>rd</i>, <i>rs1</i>, <i>simm13</i>
1750 * Example disassembly syntax: {@code stda %g0, [%g0 + -4096] %asi}
1751 * <p>
1752 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1753 *
1754 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.54"
1755 */
1756 // Template#: 100, Serial#: 100
1757 public void stda(final GPR.Even rd, final GPR rs1, final int simm13) {
1758 int instruction = 0xC0B82000;
1759 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1760 instruction |= ((rd.value() & 0x1f) << 25);
1761 instruction |= ((rs1.value() & 0x1f) << 14);
1762 instruction |= (simm13 & 0x1fff);
1763 emitInt(instruction);
1764 }
1765
1766 /**
1767 * Pseudo-external assembler syntax: {@code membar }<i>membarMask</i>
1768 * Example disassembly syntax: {@code membar 0}
1769 *
1770 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.32"
1771 */
1772 // Template#: 101, Serial#: 101
1773 public void membar(final MembarOperand membarMask) {
1774 int instruction = 0x8143E000;
1775 instruction |= (membarMask.value() & 0x7f);
1776 emitInt(instruction);
1777 }
1778
1779 /**
1780 * Pseudo-external assembler syntax: {@code stbar }
1781 * Example disassembly syntax: {@code stbar }
1782 *
1783 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.51"
1784 */
1785 // Template#: 102, Serial#: 102
1786 public void stbar() {
1787 int instruction = 0x8143C000;
1788 emitInt(instruction);
1789 }
1790
1791 /**
1792 * Pseudo-external assembler syntax: {@code add }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
1793 * Example disassembly syntax: {@code add %g0, %g0, %g0}
1794 *
1795 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.2"
1796 */
1797 // Template#: 103, Serial#: 103
1798 public void add(final GPR rs1, final GPR rs2, final GPR rd) {
1799 int instruction = 0x80000000;
1800 instruction |= ((rs1.value() & 0x1f) << 14);
1801 instruction |= (rs2.value() & 0x1f);
1802 instruction |= ((rd.value() & 0x1f) << 25);
1803 emitInt(instruction);
1804 }
1805
1806 /**
1807 * Pseudo-external assembler syntax: {@code add }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
1808 * Example disassembly syntax: {@code add %g0, -4096, %g0}
1809 * <p>
1810 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1811 *
1812 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.2"
1813 */
1814 // Template#: 104, Serial#: 104
1815 public void add(final GPR rs1, final int simm13, final GPR rd) {
1816 int instruction = 0x80002000;
1817 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1818 instruction |= ((rs1.value() & 0x1f) << 14);
1819 instruction |= (simm13 & 0x1fff);
1820 instruction |= ((rd.value() & 0x1f) << 25);
1821 emitInt(instruction);
1822 }
1823
1824 /**
1825 * Pseudo-external assembler syntax: {@code addc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
1826 * Example disassembly syntax: {@code addc %g0, %g0, %g0}
1827 *
1828 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.2"
1829 */
1830 // Template#: 105, Serial#: 105
1831 public void addc(final GPR rs1, final GPR rs2, final GPR rd) {
1832 int instruction = 0x80400000;
1833 instruction |= ((rs1.value() & 0x1f) << 14);
1834 instruction |= (rs2.value() & 0x1f);
1835 instruction |= ((rd.value() & 0x1f) << 25);
1836 emitInt(instruction);
1837 }
1838
1839 /**
1840 * Pseudo-external assembler syntax: {@code addc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
1841 * Example disassembly syntax: {@code addc %g0, -4096, %g0}
1842 * <p>
1843 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1844 *
1845 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.2"
1846 */
1847 // Template#: 106, Serial#: 106
1848 public void addc(final GPR rs1, final int simm13, final GPR rd) {
1849 int instruction = 0x80402000;
1850 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1851 instruction |= ((rs1.value() & 0x1f) << 14);
1852 instruction |= (simm13 & 0x1fff);
1853 instruction |= ((rd.value() & 0x1f) << 25);
1854 emitInt(instruction);
1855 }
1856
1857 /**
1858 * Pseudo-external assembler syntax: {@code addcc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
1859 * Example disassembly syntax: {@code addcc %g0, %g0, %g0}
1860 *
1861 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.2"
1862 */
1863 // Template#: 107, Serial#: 107
1864 public void addcc(final GPR rs1, final GPR rs2, final GPR rd) {
1865 int instruction = 0x80800000;
1866 instruction |= ((rs1.value() & 0x1f) << 14);
1867 instruction |= (rs2.value() & 0x1f);
1868 instruction |= ((rd.value() & 0x1f) << 25);
1869 emitInt(instruction);
1870 }
1871
1872 /**
1873 * Pseudo-external assembler syntax: {@code addcc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
1874 * Example disassembly syntax: {@code addcc %g0, -4096, %g0}
1875 * <p>
1876 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1877 *
1878 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.2"
1879 */
1880 // Template#: 108, Serial#: 108
1881 public void addcc(final GPR rs1, final int simm13, final GPR rd) {
1882 int instruction = 0x80802000;
1883 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1884 instruction |= ((rs1.value() & 0x1f) << 14);
1885 instruction |= (simm13 & 0x1fff);
1886 instruction |= ((rd.value() & 0x1f) << 25);
1887 emitInt(instruction);
1888 }
1889
1890 /**
1891 * Pseudo-external assembler syntax: {@code addccc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
1892 * Example disassembly syntax: {@code addccc %g0, %g0, %g0}
1893 *
1894 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.2"
1895 */
1896 // Template#: 109, Serial#: 109
1897 public void addccc(final GPR rs1, final GPR rs2, final GPR rd) {
1898 int instruction = 0x80C00000;
1899 instruction |= ((rs1.value() & 0x1f) << 14);
1900 instruction |= (rs2.value() & 0x1f);
1901 instruction |= ((rd.value() & 0x1f) << 25);
1902 emitInt(instruction);
1903 }
1904
1905 /**
1906 * Pseudo-external assembler syntax: {@code addccc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
1907 * Example disassembly syntax: {@code addccc %g0, -4096, %g0}
1908 * <p>
1909 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1910 *
1911 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.2"
1912 */
1913 // Template#: 110, Serial#: 110
1914 public void addccc(final GPR rs1, final int simm13, final GPR rd) {
1915 int instruction = 0x80C02000;
1916 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1917 instruction |= ((rs1.value() & 0x1f) << 14);
1918 instruction |= (simm13 & 0x1fff);
1919 instruction |= ((rd.value() & 0x1f) << 25);
1920 emitInt(instruction);
1921 }
1922
1923 /**
1924 * Pseudo-external assembler syntax: {@code udiv }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
1925 * Example disassembly syntax: {@code udiv %g0, %g0, %g0}
1926 *
1927 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.10"
1928 */
1929 // Template#: 111, Serial#: 111
1930 public void udiv(final GPR rs1, final GPR rs2, final GPR rd) {
1931 int instruction = 0x80700000;
1932 instruction |= ((rs1.value() & 0x1f) << 14);
1933 instruction |= (rs2.value() & 0x1f);
1934 instruction |= ((rd.value() & 0x1f) << 25);
1935 emitInt(instruction);
1936 }
1937
1938 /**
1939 * Pseudo-external assembler syntax: {@code udiv }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
1940 * Example disassembly syntax: {@code udiv %g0, -4096, %g0}
1941 * <p>
1942 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1943 *
1944 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.10"
1945 */
1946 // Template#: 112, Serial#: 112
1947 public void udiv(final GPR rs1, final int simm13, final GPR rd) {
1948 int instruction = 0x80702000;
1949 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1950 instruction |= ((rs1.value() & 0x1f) << 14);
1951 instruction |= (simm13 & 0x1fff);
1952 instruction |= ((rd.value() & 0x1f) << 25);
1953 emitInt(instruction);
1954 }
1955
1956 /**
1957 * Pseudo-external assembler syntax: {@code sdiv }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
1958 * Example disassembly syntax: {@code sdiv %g0, %g0, %g0}
1959 *
1960 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.10"
1961 */
1962 // Template#: 113, Serial#: 113
1963 public void sdiv(final GPR rs1, final GPR rs2, final GPR rd) {
1964 int instruction = 0x80780000;
1965 instruction |= ((rs1.value() & 0x1f) << 14);
1966 instruction |= (rs2.value() & 0x1f);
1967 instruction |= ((rd.value() & 0x1f) << 25);
1968 emitInt(instruction);
1969 }
1970
1971 /**
1972 * Pseudo-external assembler syntax: {@code sdiv }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
1973 * Example disassembly syntax: {@code sdiv %g0, -4096, %g0}
1974 * <p>
1975 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
1976 *
1977 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.10"
1978 */
1979 // Template#: 114, Serial#: 114
1980 public void sdiv(final GPR rs1, final int simm13, final GPR rd) {
1981 int instruction = 0x80782000;
1982 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
1983 instruction |= ((rs1.value() & 0x1f) << 14);
1984 instruction |= (simm13 & 0x1fff);
1985 instruction |= ((rd.value() & 0x1f) << 25);
1986 emitInt(instruction);
1987 }
1988
1989 /**
1990 * Pseudo-external assembler syntax: {@code udivcc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
1991 * Example disassembly syntax: {@code udivcc %g0, %g0, %g0}
1992 *
1993 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.10"
1994 */
1995 // Template#: 115, Serial#: 115
1996 public void udivcc(final GPR rs1, final GPR rs2, final GPR rd) {
1997 int instruction = 0x80F00000;
1998 instruction |= ((rs1.value() & 0x1f) << 14);
1999 instruction |= (rs2.value() & 0x1f);
2000 instruction |= ((rd.value() & 0x1f) << 25);
2001 emitInt(instruction);
2002 }
2003
2004 /**
2005 * Pseudo-external assembler syntax: {@code udivcc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2006 * Example disassembly syntax: {@code udivcc %g0, -4096, %g0}
2007 * <p>
2008 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2009 *
2010 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.10"
2011 */
2012 // Template#: 116, Serial#: 116
2013 public void udivcc(final GPR rs1, final int simm13, final GPR rd) {
2014 int instruction = 0x80F02000;
2015 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2016 instruction |= ((rs1.value() & 0x1f) << 14);
2017 instruction |= (simm13 & 0x1fff);
2018 instruction |= ((rd.value() & 0x1f) << 25);
2019 emitInt(instruction);
2020 }
2021
2022 /**
2023 * Pseudo-external assembler syntax: {@code sdivcc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2024 * Example disassembly syntax: {@code sdivcc %g0, %g0, %g0}
2025 *
2026 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.10"
2027 */
2028 // Template#: 117, Serial#: 117
2029 public void sdivcc(final GPR rs1, final GPR rs2, final GPR rd) {
2030 int instruction = 0x80F80000;
2031 instruction |= ((rs1.value() & 0x1f) << 14);
2032 instruction |= (rs2.value() & 0x1f);
2033 instruction |= ((rd.value() & 0x1f) << 25);
2034 emitInt(instruction);
2035 }
2036
2037 /**
2038 * Pseudo-external assembler syntax: {@code sdivcc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2039 * Example disassembly syntax: {@code sdivcc %g0, -4096, %g0}
2040 * <p>
2041 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2042 *
2043 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.10"
2044 */
2045 // Template#: 118, Serial#: 118
2046 public void sdivcc(final GPR rs1, final int simm13, final GPR rd) {
2047 int instruction = 0x80F82000;
2048 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2049 instruction |= ((rs1.value() & 0x1f) << 14);
2050 instruction |= (simm13 & 0x1fff);
2051 instruction |= ((rd.value() & 0x1f) << 25);
2052 emitInt(instruction);
2053 }
2054
2055 /**
2056 * Pseudo-external assembler syntax: {@code and }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2057 * Example disassembly syntax: {@code and %g0, %g0, %g0}
2058 *
2059 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2060 */
2061 // Template#: 119, Serial#: 119
2062 public void and(final GPR rs1, final GPR rs2, final GPR rd) {
2063 int instruction = 0x80080000;
2064 instruction |= ((rs1.value() & 0x1f) << 14);
2065 instruction |= (rs2.value() & 0x1f);
2066 instruction |= ((rd.value() & 0x1f) << 25);
2067 emitInt(instruction);
2068 }
2069
2070 /**
2071 * Pseudo-external assembler syntax: {@code and }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2072 * Example disassembly syntax: {@code and %g0, -4096, %g0}
2073 * <p>
2074 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2075 *
2076 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2077 */
2078 // Template#: 120, Serial#: 120
2079 public void and(final GPR rs1, final int simm13, final GPR rd) {
2080 int instruction = 0x80082000;
2081 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2082 instruction |= ((rs1.value() & 0x1f) << 14);
2083 instruction |= (simm13 & 0x1fff);
2084 instruction |= ((rd.value() & 0x1f) << 25);
2085 emitInt(instruction);
2086 }
2087
2088 /**
2089 * Pseudo-external assembler syntax: {@code andcc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2090 * Example disassembly syntax: {@code andcc %g0, %g0, %g0}
2091 *
2092 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2093 */
2094 // Template#: 121, Serial#: 121
2095 public void andcc(final GPR rs1, final GPR rs2, final GPR rd) {
2096 int instruction = 0x80880000;
2097 instruction |= ((rs1.value() & 0x1f) << 14);
2098 instruction |= (rs2.value() & 0x1f);
2099 instruction |= ((rd.value() & 0x1f) << 25);
2100 emitInt(instruction);
2101 }
2102
2103 /**
2104 * Pseudo-external assembler syntax: {@code andcc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2105 * Example disassembly syntax: {@code andcc %g0, -4096, %g0}
2106 * <p>
2107 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2108 *
2109 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2110 */
2111 // Template#: 122, Serial#: 122
2112 public void andcc(final GPR rs1, final int simm13, final GPR rd) {
2113 int instruction = 0x80882000;
2114 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2115 instruction |= ((rs1.value() & 0x1f) << 14);
2116 instruction |= (simm13 & 0x1fff);
2117 instruction |= ((rd.value() & 0x1f) << 25);
2118 emitInt(instruction);
2119 }
2120
2121 /**
2122 * Pseudo-external assembler syntax: {@code andn }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2123 * Example disassembly syntax: {@code andn %g0, %g0, %g0}
2124 *
2125 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2126 */
2127 // Template#: 123, Serial#: 123
2128 public void andn(final GPR rs1, final GPR rs2, final GPR rd) {
2129 int instruction = 0x80280000;
2130 instruction |= ((rs1.value() & 0x1f) << 14);
2131 instruction |= (rs2.value() & 0x1f);
2132 instruction |= ((rd.value() & 0x1f) << 25);
2133 emitInt(instruction);
2134 }
2135
2136 /**
2137 * Pseudo-external assembler syntax: {@code andn }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2138 * Example disassembly syntax: {@code andn %g0, -4096, %g0}
2139 * <p>
2140 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2141 *
2142 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2143 */
2144 // Template#: 124, Serial#: 124
2145 public void andn(final GPR rs1, final int simm13, final GPR rd) {
2146 int instruction = 0x80282000;
2147 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2148 instruction |= ((rs1.value() & 0x1f) << 14);
2149 instruction |= (simm13 & 0x1fff);
2150 instruction |= ((rd.value() & 0x1f) << 25);
2151 emitInt(instruction);
2152 }
2153
2154 /**
2155 * Pseudo-external assembler syntax: {@code andncc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2156 * Example disassembly syntax: {@code andncc %g0, %g0, %g0}
2157 *
2158 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2159 */
2160 // Template#: 125, Serial#: 125
2161 public void andncc(final GPR rs1, final GPR rs2, final GPR rd) {
2162 int instruction = 0x80A80000;
2163 instruction |= ((rs1.value() & 0x1f) << 14);
2164 instruction |= (rs2.value() & 0x1f);
2165 instruction |= ((rd.value() & 0x1f) << 25);
2166 emitInt(instruction);
2167 }
2168
2169 /**
2170 * Pseudo-external assembler syntax: {@code andncc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2171 * Example disassembly syntax: {@code andncc %g0, -4096, %g0}
2172 * <p>
2173 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2174 *
2175 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2176 */
2177 // Template#: 126, Serial#: 126
2178 public void andncc(final GPR rs1, final int simm13, final GPR rd) {
2179 int instruction = 0x80A82000;
2180 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2181 instruction |= ((rs1.value() & 0x1f) << 14);
2182 instruction |= (simm13 & 0x1fff);
2183 instruction |= ((rd.value() & 0x1f) << 25);
2184 emitInt(instruction);
2185 }
2186
2187 /**
2188 * Pseudo-external assembler syntax: {@code or }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2189 * Example disassembly syntax: {@code or %g0, %g0, %g0}
2190 *
2191 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2192 */
2193 // Template#: 127, Serial#: 127
2194 public void or(final GPR rs1, final GPR rs2, final GPR rd) {
2195 int instruction = 0x80100000;
2196 instruction |= ((rs1.value() & 0x1f) << 14);
2197 instruction |= (rs2.value() & 0x1f);
2198 instruction |= ((rd.value() & 0x1f) << 25);
2199 emitInt(instruction);
2200 }
2201
2202 /**
2203 * Pseudo-external assembler syntax: {@code or }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2204 * Example disassembly syntax: {@code or %g0, -4096, %g0}
2205 * <p>
2206 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2207 *
2208 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2209 */
2210 // Template#: 128, Serial#: 128
2211 public void or(final GPR rs1, final int simm13, final GPR rd) {
2212 int instruction = 0x80102000;
2213 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2214 instruction |= ((rs1.value() & 0x1f) << 14);
2215 instruction |= (simm13 & 0x1fff);
2216 instruction |= ((rd.value() & 0x1f) << 25);
2217 emitInt(instruction);
2218 }
2219
2220 /**
2221 * Pseudo-external assembler syntax: {@code orcc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2222 * Example disassembly syntax: {@code orcc %g0, %g0, %g0}
2223 *
2224 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2225 */
2226 // Template#: 129, Serial#: 129
2227 public void orcc(final GPR rs1, final GPR rs2, final GPR rd) {
2228 int instruction = 0x80900000;
2229 instruction |= ((rs1.value() & 0x1f) << 14);
2230 instruction |= (rs2.value() & 0x1f);
2231 instruction |= ((rd.value() & 0x1f) << 25);
2232 emitInt(instruction);
2233 }
2234
2235 /**
2236 * Pseudo-external assembler syntax: {@code orcc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2237 * Example disassembly syntax: {@code orcc %g0, -4096, %g0}
2238 * <p>
2239 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2240 *
2241 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2242 */
2243 // Template#: 130, Serial#: 130
2244 public void orcc(final GPR rs1, final int simm13, final GPR rd) {
2245 int instruction = 0x80902000;
2246 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2247 instruction |= ((rs1.value() & 0x1f) << 14);
2248 instruction |= (simm13 & 0x1fff);
2249 instruction |= ((rd.value() & 0x1f) << 25);
2250 emitInt(instruction);
2251 }
2252
2253 /**
2254 * Pseudo-external assembler syntax: {@code orn }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2255 * Example disassembly syntax: {@code orn %g0, %g0, %g0}
2256 *
2257 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2258 */
2259 // Template#: 131, Serial#: 131
2260 public void orn(final GPR rs1, final GPR rs2, final GPR rd) {
2261 int instruction = 0x80300000;
2262 instruction |= ((rs1.value() & 0x1f) << 14);
2263 instruction |= (rs2.value() & 0x1f);
2264 instruction |= ((rd.value() & 0x1f) << 25);
2265 emitInt(instruction);
2266 }
2267
2268 /**
2269 * Pseudo-external assembler syntax: {@code orn }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2270 * Example disassembly syntax: {@code orn %g0, -4096, %g0}
2271 * <p>
2272 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2273 *
2274 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2275 */
2276 // Template#: 132, Serial#: 132
2277 public void orn(final GPR rs1, final int simm13, final GPR rd) {
2278 int instruction = 0x80302000;
2279 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2280 instruction |= ((rs1.value() & 0x1f) << 14);
2281 instruction |= (simm13 & 0x1fff);
2282 instruction |= ((rd.value() & 0x1f) << 25);
2283 emitInt(instruction);
2284 }
2285
2286 /**
2287 * Pseudo-external assembler syntax: {@code orncc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2288 * Example disassembly syntax: {@code orncc %g0, %g0, %g0}
2289 *
2290 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2291 */
2292 // Template#: 133, Serial#: 133
2293 public void orncc(final GPR rs1, final GPR rs2, final GPR rd) {
2294 int instruction = 0x80B00000;
2295 instruction |= ((rs1.value() & 0x1f) << 14);
2296 instruction |= (rs2.value() & 0x1f);
2297 instruction |= ((rd.value() & 0x1f) << 25);
2298 emitInt(instruction);
2299 }
2300
2301 /**
2302 * Pseudo-external assembler syntax: {@code orncc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2303 * Example disassembly syntax: {@code orncc %g0, -4096, %g0}
2304 * <p>
2305 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2306 *
2307 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2308 */
2309 // Template#: 134, Serial#: 134
2310 public void orncc(final GPR rs1, final int simm13, final GPR rd) {
2311 int instruction = 0x80B02000;
2312 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2313 instruction |= ((rs1.value() & 0x1f) << 14);
2314 instruction |= (simm13 & 0x1fff);
2315 instruction |= ((rd.value() & 0x1f) << 25);
2316 emitInt(instruction);
2317 }
2318
2319 /**
2320 * Pseudo-external assembler syntax: {@code xor }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2321 * Example disassembly syntax: {@code xor %g0, %g0, %g0}
2322 *
2323 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2324 */
2325 // Template#: 135, Serial#: 135
2326 public void xor(final GPR rs1, final GPR rs2, final GPR rd) {
2327 int instruction = 0x80180000;
2328 instruction |= ((rs1.value() & 0x1f) << 14);
2329 instruction |= (rs2.value() & 0x1f);
2330 instruction |= ((rd.value() & 0x1f) << 25);
2331 emitInt(instruction);
2332 }
2333
2334 /**
2335 * Pseudo-external assembler syntax: {@code xor }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2336 * Example disassembly syntax: {@code xor %g0, -4096, %g0}
2337 * <p>
2338 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2339 *
2340 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2341 */
2342 // Template#: 136, Serial#: 136
2343 public void xor(final GPR rs1, final int simm13, final GPR rd) {
2344 int instruction = 0x80182000;
2345 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2346 instruction |= ((rs1.value() & 0x1f) << 14);
2347 instruction |= (simm13 & 0x1fff);
2348 instruction |= ((rd.value() & 0x1f) << 25);
2349 emitInt(instruction);
2350 }
2351
2352 /**
2353 * Pseudo-external assembler syntax: {@code xorcc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2354 * Example disassembly syntax: {@code xorcc %g0, %g0, %g0}
2355 *
2356 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2357 */
2358 // Template#: 137, Serial#: 137
2359 public void xorcc(final GPR rs1, final GPR rs2, final GPR rd) {
2360 int instruction = 0x80980000;
2361 instruction |= ((rs1.value() & 0x1f) << 14);
2362 instruction |= (rs2.value() & 0x1f);
2363 instruction |= ((rd.value() & 0x1f) << 25);
2364 emitInt(instruction);
2365 }
2366
2367 /**
2368 * Pseudo-external assembler syntax: {@code xorcc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2369 * Example disassembly syntax: {@code xorcc %g0, -4096, %g0}
2370 * <p>
2371 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2372 *
2373 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2374 */
2375 // Template#: 138, Serial#: 138
2376 public void xorcc(final GPR rs1, final int simm13, final GPR rd) {
2377 int instruction = 0x80982000;
2378 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2379 instruction |= ((rs1.value() & 0x1f) << 14);
2380 instruction |= (simm13 & 0x1fff);
2381 instruction |= ((rd.value() & 0x1f) << 25);
2382 emitInt(instruction);
2383 }
2384
2385 /**
2386 * Pseudo-external assembler syntax: {@code xnor }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2387 * Example disassembly syntax: {@code xnor %g0, %g0, %g0}
2388 *
2389 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2390 */
2391 // Template#: 139, Serial#: 139
2392 public void xnor(final GPR rs1, final GPR rs2, final GPR rd) {
2393 int instruction = 0x80380000;
2394 instruction |= ((rs1.value() & 0x1f) << 14);
2395 instruction |= (rs2.value() & 0x1f);
2396 instruction |= ((rd.value() & 0x1f) << 25);
2397 emitInt(instruction);
2398 }
2399
2400 /**
2401 * Pseudo-external assembler syntax: {@code xnor }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2402 * Example disassembly syntax: {@code xnor %g0, -4096, %g0}
2403 * <p>
2404 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2405 *
2406 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2407 */
2408 // Template#: 140, Serial#: 140
2409 public void xnor(final GPR rs1, final int simm13, final GPR rd) {
2410 int instruction = 0x80382000;
2411 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2412 instruction |= ((rs1.value() & 0x1f) << 14);
2413 instruction |= (simm13 & 0x1fff);
2414 instruction |= ((rd.value() & 0x1f) << 25);
2415 emitInt(instruction);
2416 }
2417
2418 /**
2419 * Pseudo-external assembler syntax: {@code xnorcc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2420 * Example disassembly syntax: {@code xnorcc %g0, %g0, %g0}
2421 *
2422 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2423 */
2424 // Template#: 141, Serial#: 141
2425 public void xnorcc(final GPR rs1, final GPR rs2, final GPR rd) {
2426 int instruction = 0x80B80000;
2427 instruction |= ((rs1.value() & 0x1f) << 14);
2428 instruction |= (rs2.value() & 0x1f);
2429 instruction |= ((rd.value() & 0x1f) << 25);
2430 emitInt(instruction);
2431 }
2432
2433 /**
2434 * Pseudo-external assembler syntax: {@code xnorcc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2435 * Example disassembly syntax: {@code xnorcc %g0, -4096, %g0}
2436 * <p>
2437 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2438 *
2439 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.31"
2440 */
2441 // Template#: 142, Serial#: 142
2442 public void xnorcc(final GPR rs1, final int simm13, final GPR rd) {
2443 int instruction = 0x80B82000;
2444 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2445 instruction |= ((rs1.value() & 0x1f) << 14);
2446 instruction |= (simm13 & 0x1fff);
2447 instruction |= ((rd.value() & 0x1f) << 25);
2448 emitInt(instruction);
2449 }
2450
2451 /**
2452 * Pseudo-external assembler syntax: {@code mulx }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2453 * Example disassembly syntax: {@code mulx %g0, %g0, %g0}
2454 *
2455 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
2456 */
2457 // Template#: 143, Serial#: 143
2458 public void mulx(final GPR rs1, final GPR rs2, final GPR rd) {
2459 int instruction = 0x80480000;
2460 instruction |= ((rs1.value() & 0x1f) << 14);
2461 instruction |= (rs2.value() & 0x1f);
2462 instruction |= ((rd.value() & 0x1f) << 25);
2463 emitInt(instruction);
2464 }
2465
2466 /**
2467 * Pseudo-external assembler syntax: {@code mulx }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2468 * Example disassembly syntax: {@code mulx %g0, -4096, %g0}
2469 * <p>
2470 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2471 *
2472 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
2473 */
2474 // Template#: 144, Serial#: 144
2475 public void mulx(final GPR rs1, final int simm13, final GPR rd) {
2476 int instruction = 0x80482000;
2477 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2478 instruction |= ((rs1.value() & 0x1f) << 14);
2479 instruction |= (simm13 & 0x1fff);
2480 instruction |= ((rd.value() & 0x1f) << 25);
2481 emitInt(instruction);
2482 }
2483
2484 /**
2485 * Pseudo-external assembler syntax: {@code sdivx }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2486 * Example disassembly syntax: {@code sdivx %g0, %g0, %g0}
2487 *
2488 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
2489 */
2490 // Template#: 145, Serial#: 145
2491 public void sdivx(final GPR rs1, final GPR rs2, final GPR rd) {
2492 int instruction = 0x81680000;
2493 instruction |= ((rs1.value() & 0x1f) << 14);
2494 instruction |= (rs2.value() & 0x1f);
2495 instruction |= ((rd.value() & 0x1f) << 25);
2496 emitInt(instruction);
2497 }
2498
2499 /**
2500 * Pseudo-external assembler syntax: {@code sdivx }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2501 * Example disassembly syntax: {@code sdivx %g0, -4096, %g0}
2502 * <p>
2503 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2504 *
2505 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
2506 */
2507 // Template#: 146, Serial#: 146
2508 public void sdivx(final GPR rs1, final int simm13, final GPR rd) {
2509 int instruction = 0x81682000;
2510 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2511 instruction |= ((rs1.value() & 0x1f) << 14);
2512 instruction |= (simm13 & 0x1fff);
2513 instruction |= ((rd.value() & 0x1f) << 25);
2514 emitInt(instruction);
2515 }
2516
2517 /**
2518 * Pseudo-external assembler syntax: {@code udivx }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2519 * Example disassembly syntax: {@code udivx %g0, %g0, %g0}
2520 *
2521 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
2522 */
2523 // Template#: 147, Serial#: 147
2524 public void udivx(final GPR rs1, final GPR rs2, final GPR rd) {
2525 int instruction = 0x80680000;
2526 instruction |= ((rs1.value() & 0x1f) << 14);
2527 instruction |= (rs2.value() & 0x1f);
2528 instruction |= ((rd.value() & 0x1f) << 25);
2529 emitInt(instruction);
2530 }
2531
2532 /**
2533 * Pseudo-external assembler syntax: {@code udivx }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2534 * Example disassembly syntax: {@code udivx %g0, -4096, %g0}
2535 * <p>
2536 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2537 *
2538 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
2539 */
2540 // Template#: 148, Serial#: 148
2541 public void udivx(final GPR rs1, final int simm13, final GPR rd) {
2542 int instruction = 0x80682000;
2543 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2544 instruction |= ((rs1.value() & 0x1f) << 14);
2545 instruction |= (simm13 & 0x1fff);
2546 instruction |= ((rd.value() & 0x1f) << 25);
2547 emitInt(instruction);
2548 }
2549
2550 /**
2551 * Pseudo-external assembler syntax: {@code umul }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2552 * Example disassembly syntax: {@code umul %g0, %g0, %g0}
2553 *
2554 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.38"
2555 */
2556 // Template#: 149, Serial#: 149
2557 public void umul(final GPR rs1, final GPR rs2, final GPR rd) {
2558 int instruction = 0x80500000;
2559 instruction |= ((rs1.value() & 0x1f) << 14);
2560 instruction |= (rs2.value() & 0x1f);
2561 instruction |= ((rd.value() & 0x1f) << 25);
2562 emitInt(instruction);
2563 }
2564
2565 /**
2566 * Pseudo-external assembler syntax: {@code umul }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2567 * Example disassembly syntax: {@code umul %g0, -4096, %g0}
2568 * <p>
2569 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2570 *
2571 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.38"
2572 */
2573 // Template#: 150, Serial#: 150
2574 public void umul(final GPR rs1, final int simm13, final GPR rd) {
2575 int instruction = 0x80502000;
2576 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2577 instruction |= ((rs1.value() & 0x1f) << 14);
2578 instruction |= (simm13 & 0x1fff);
2579 instruction |= ((rd.value() & 0x1f) << 25);
2580 emitInt(instruction);
2581 }
2582
2583 /**
2584 * Pseudo-external assembler syntax: {@code smul }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2585 * Example disassembly syntax: {@code smul %g0, %g0, %g0}
2586 *
2587 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.38"
2588 */
2589 // Template#: 151, Serial#: 151
2590 public void smul(final GPR rs1, final GPR rs2, final GPR rd) {
2591 int instruction = 0x80580000;
2592 instruction |= ((rs1.value() & 0x1f) << 14);
2593 instruction |= (rs2.value() & 0x1f);
2594 instruction |= ((rd.value() & 0x1f) << 25);
2595 emitInt(instruction);
2596 }
2597
2598 /**
2599 * Pseudo-external assembler syntax: {@code smul }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2600 * Example disassembly syntax: {@code smul %g0, -4096, %g0}
2601 * <p>
2602 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2603 *
2604 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.38"
2605 */
2606 // Template#: 152, Serial#: 152
2607 public void smul(final GPR rs1, final int simm13, final GPR rd) {
2608 int instruction = 0x80582000;
2609 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2610 instruction |= ((rs1.value() & 0x1f) << 14);
2611 instruction |= (simm13 & 0x1fff);
2612 instruction |= ((rd.value() & 0x1f) << 25);
2613 emitInt(instruction);
2614 }
2615
2616 /**
2617 * Pseudo-external assembler syntax: {@code umulcc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2618 * Example disassembly syntax: {@code umulcc %g0, %g0, %g0}
2619 *
2620 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.38"
2621 */
2622 // Template#: 153, Serial#: 153
2623 public void umulcc(final GPR rs1, final GPR rs2, final GPR rd) {
2624 int instruction = 0x80D00000;
2625 instruction |= ((rs1.value() & 0x1f) << 14);
2626 instruction |= (rs2.value() & 0x1f);
2627 instruction |= ((rd.value() & 0x1f) << 25);
2628 emitInt(instruction);
2629 }
2630
2631 /**
2632 * Pseudo-external assembler syntax: {@code umulcc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2633 * Example disassembly syntax: {@code umulcc %g0, -4096, %g0}
2634 * <p>
2635 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2636 *
2637 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.38"
2638 */
2639 // Template#: 154, Serial#: 154
2640 public void umulcc(final GPR rs1, final int simm13, final GPR rd) {
2641 int instruction = 0x80D02000;
2642 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2643 instruction |= ((rs1.value() & 0x1f) << 14);
2644 instruction |= (simm13 & 0x1fff);
2645 instruction |= ((rd.value() & 0x1f) << 25);
2646 emitInt(instruction);
2647 }
2648
2649 /**
2650 * Pseudo-external assembler syntax: {@code smulcc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2651 * Example disassembly syntax: {@code smulcc %g0, %g0, %g0}
2652 *
2653 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.38"
2654 */
2655 // Template#: 155, Serial#: 155
2656 public void smulcc(final GPR rs1, final GPR rs2, final GPR rd) {
2657 int instruction = 0x80D80000;
2658 instruction |= ((rs1.value() & 0x1f) << 14);
2659 instruction |= (rs2.value() & 0x1f);
2660 instruction |= ((rd.value() & 0x1f) << 25);
2661 emitInt(instruction);
2662 }
2663
2664 /**
2665 * Pseudo-external assembler syntax: {@code smulcc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2666 * Example disassembly syntax: {@code smulcc %g0, -4096, %g0}
2667 * <p>
2668 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2669 *
2670 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.38"
2671 */
2672 // Template#: 156, Serial#: 156
2673 public void smulcc(final GPR rs1, final int simm13, final GPR rd) {
2674 int instruction = 0x80D82000;
2675 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2676 instruction |= ((rs1.value() & 0x1f) << 14);
2677 instruction |= (simm13 & 0x1fff);
2678 instruction |= ((rd.value() & 0x1f) << 25);
2679 emitInt(instruction);
2680 }
2681
2682 /**
2683 * Pseudo-external assembler syntax: {@code mulscc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2684 * Example disassembly syntax: {@code mulscc %g0, %g0, %g0}
2685 *
2686 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.39"
2687 */
2688 // Template#: 157, Serial#: 157
2689 public void mulscc(final GPR rs1, final GPR rs2, final GPR rd) {
2690 int instruction = 0x81200000;
2691 instruction |= ((rs1.value() & 0x1f) << 14);
2692 instruction |= (rs2.value() & 0x1f);
2693 instruction |= ((rd.value() & 0x1f) << 25);
2694 emitInt(instruction);
2695 }
2696
2697 /**
2698 * Pseudo-external assembler syntax: {@code mulscc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2699 * Example disassembly syntax: {@code mulscc %g0, -4096, %g0}
2700 * <p>
2701 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2702 *
2703 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.39"
2704 */
2705 // Template#: 158, Serial#: 158
2706 public void mulscc(final GPR rs1, final int simm13, final GPR rd) {
2707 int instruction = 0x81202000;
2708 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2709 instruction |= ((rs1.value() & 0x1f) << 14);
2710 instruction |= (simm13 & 0x1fff);
2711 instruction |= ((rd.value() & 0x1f) << 25);
2712 emitInt(instruction);
2713 }
2714
2715 /**
2716 * Pseudo-external assembler syntax: {@code popc }<i>rs2</i>, <i>rd</i>
2717 * Example disassembly syntax: {@code popc %g0, %g0}
2718 *
2719 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.41"
2720 */
2721 // Template#: 159, Serial#: 159
2722 public void popc(final GPR rs2, final GPR rd) {
2723 int instruction = 0x81700000;
2724 instruction |= (rs2.value() & 0x1f);
2725 instruction |= ((rd.value() & 0x1f) << 25);
2726 emitInt(instruction);
2727 }
2728
2729 /**
2730 * Pseudo-external assembler syntax: {@code popc }<i>simm13</i>, <i>rd</i>
2731 * Example disassembly syntax: {@code popc -4096, %g0}
2732 * <p>
2733 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2734 *
2735 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.41"
2736 */
2737 // Template#: 160, Serial#: 160
2738 public void popc(final int simm13, final GPR rd) {
2739 int instruction = 0x81702000;
2740 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2741 instruction |= (simm13 & 0x1fff);
2742 instruction |= ((rd.value() & 0x1f) << 25);
2743 emitInt(instruction);
2744 }
2745
2746 /**
2747 * Pseudo-external assembler syntax: {@code sethi }<i>imm22</i>, <i>rd</i>
2748 * Example disassembly syntax: {@code sethi 0x0, %g0}
2749 * <p>
2750 * Constraint: {@code -2097152 <= imm22 && imm22 <= 4194303}<br />
2751 *
2752 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.48"
2753 */
2754 // Template#: 161, Serial#: 161
2755 public void sethi(final int imm22, final GPR rd) {
2756 int instruction = 0x01000000;
2757 checkConstraint(-2097152 <= imm22 && imm22 <= 4194303, "-2097152 <= imm22 && imm22 <= 4194303");
2758 instruction |= (imm22 & 0x3fffff);
2759 instruction |= ((rd.value() & 0x1f) << 25);
2760 emitInt(instruction);
2761 }
2762
2763 /**
2764 * Pseudo-external assembler syntax: {@code sll }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2765 * Example disassembly syntax: {@code sll %g0, %g0, %g0}
2766 *
2767 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.49"
2768 */
2769 // Template#: 162, Serial#: 162
2770 public void sll(final GPR rs1, final GPR rs2, final GPR rd) {
2771 int instruction = 0x81280000;
2772 instruction |= ((rs1.value() & 0x1f) << 14);
2773 instruction |= (rs2.value() & 0x1f);
2774 instruction |= ((rd.value() & 0x1f) << 25);
2775 emitInt(instruction);
2776 }
2777
2778 /**
2779 * Pseudo-external assembler syntax: {@code sllx }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2780 * Example disassembly syntax: {@code sllx %g0, %g0, %g0}
2781 *
2782 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.49"
2783 */
2784 // Template#: 163, Serial#: 163
2785 public void sllx(final GPR rs1, final GPR rs2, final GPR rd) {
2786 int instruction = 0x81281000;
2787 instruction |= ((rs1.value() & 0x1f) << 14);
2788 instruction |= (rs2.value() & 0x1f);
2789 instruction |= ((rd.value() & 0x1f) << 25);
2790 emitInt(instruction);
2791 }
2792
2793 /**
2794 * Pseudo-external assembler syntax: {@code sll }<i>rs1</i>, <i>shcnt32</i>, <i>rd</i>
2795 * Example disassembly syntax: {@code sll %g0, 0x0, %g0}
2796 * <p>
2797 * Constraint: {@code 0 <= shcnt32 && shcnt32 <= 31}<br />
2798 *
2799 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.49"
2800 */
2801 // Template#: 164, Serial#: 164
2802 public void sll(final GPR rs1, final int shcnt32, final GPR rd) {
2803 int instruction = 0x81282000;
2804 checkConstraint(0 <= shcnt32 && shcnt32 <= 31, "0 <= shcnt32 && shcnt32 <= 31");
2805 instruction |= ((rs1.value() & 0x1f) << 14);
2806 instruction |= (shcnt32 & 0x1f);
2807 instruction |= ((rd.value() & 0x1f) << 25);
2808 emitInt(instruction);
2809 }
2810
2811 /**
2812 * Pseudo-external assembler syntax: {@code sllx }<i>rs1</i>, <i>shcnt64</i>, <i>rd</i>
2813 * Example disassembly syntax: {@code sllx %g0, 0x0, %g0}
2814 * <p>
2815 * Constraint: {@code 0 <= shcnt64 && shcnt64 <= 63}<br />
2816 *
2817 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.49"
2818 */
2819 // Template#: 165, Serial#: 165
2820 public void sllx(final GPR rs1, final int shcnt64, final GPR rd) {
2821 int instruction = 0x81283000;
2822 checkConstraint(0 <= shcnt64 && shcnt64 <= 63, "0 <= shcnt64 && shcnt64 <= 63");
2823 instruction |= ((rs1.value() & 0x1f) << 14);
2824 instruction |= (shcnt64 & 0x3f);
2825 instruction |= ((rd.value() & 0x1f) << 25);
2826 emitInt(instruction);
2827 }
2828
2829 /**
2830 * Pseudo-external assembler syntax: {@code srl }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2831 * Example disassembly syntax: {@code srl %g0, %g0, %g0}
2832 *
2833 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.49"
2834 */
2835 // Template#: 166, Serial#: 166
2836 public void srl(final GPR rs1, final GPR rs2, final GPR rd) {
2837 int instruction = 0x81300000;
2838 instruction |= ((rs1.value() & 0x1f) << 14);
2839 instruction |= (rs2.value() & 0x1f);
2840 instruction |= ((rd.value() & 0x1f) << 25);
2841 emitInt(instruction);
2842 }
2843
2844 /**
2845 * Pseudo-external assembler syntax: {@code srlx }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2846 * Example disassembly syntax: {@code srlx %g0, %g0, %g0}
2847 *
2848 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.49"
2849 */
2850 // Template#: 167, Serial#: 167
2851 public void srlx(final GPR rs1, final GPR rs2, final GPR rd) {
2852 int instruction = 0x81301000;
2853 instruction |= ((rs1.value() & 0x1f) << 14);
2854 instruction |= (rs2.value() & 0x1f);
2855 instruction |= ((rd.value() & 0x1f) << 25);
2856 emitInt(instruction);
2857 }
2858
2859 /**
2860 * Pseudo-external assembler syntax: {@code srl }<i>rs1</i>, <i>shcnt32</i>, <i>rd</i>
2861 * Example disassembly syntax: {@code srl %g0, 0x0, %g0}
2862 * <p>
2863 * Constraint: {@code 0 <= shcnt32 && shcnt32 <= 31}<br />
2864 *
2865 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.49"
2866 */
2867 // Template#: 168, Serial#: 168
2868 public void srl(final GPR rs1, final int shcnt32, final GPR rd) {
2869 int instruction = 0x81302000;
2870 checkConstraint(0 <= shcnt32 && shcnt32 <= 31, "0 <= shcnt32 && shcnt32 <= 31");
2871 instruction |= ((rs1.value() & 0x1f) << 14);
2872 instruction |= (shcnt32 & 0x1f);
2873 instruction |= ((rd.value() & 0x1f) << 25);
2874 emitInt(instruction);
2875 }
2876
2877 /**
2878 * Pseudo-external assembler syntax: {@code srlx }<i>rs1</i>, <i>shcnt64</i>, <i>rd</i>
2879 * Example disassembly syntax: {@code srlx %g0, 0x0, %g0}
2880 * <p>
2881 * Constraint: {@code 0 <= shcnt64 && shcnt64 <= 63}<br />
2882 *
2883 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.49"
2884 */
2885 // Template#: 169, Serial#: 169
2886 public void srlx(final GPR rs1, final int shcnt64, final GPR rd) {
2887 int instruction = 0x81303000;
2888 checkConstraint(0 <= shcnt64 && shcnt64 <= 63, "0 <= shcnt64 && shcnt64 <= 63");
2889 instruction |= ((rs1.value() & 0x1f) << 14);
2890 instruction |= (shcnt64 & 0x3f);
2891 instruction |= ((rd.value() & 0x1f) << 25);
2892 emitInt(instruction);
2893 }
2894
2895 /**
2896 * Pseudo-external assembler syntax: {@code sra }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2897 * Example disassembly syntax: {@code sra %g0, %g0, %g0}
2898 *
2899 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.49"
2900 */
2901 // Template#: 170, Serial#: 170
2902 public void sra(final GPR rs1, final GPR rs2, final GPR rd) {
2903 int instruction = 0x81380000;
2904 instruction |= ((rs1.value() & 0x1f) << 14);
2905 instruction |= (rs2.value() & 0x1f);
2906 instruction |= ((rd.value() & 0x1f) << 25);
2907 emitInt(instruction);
2908 }
2909
2910 /**
2911 * Pseudo-external assembler syntax: {@code srax }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2912 * Example disassembly syntax: {@code srax %g0, %g0, %g0}
2913 *
2914 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.49"
2915 */
2916 // Template#: 171, Serial#: 171
2917 public void srax(final GPR rs1, final GPR rs2, final GPR rd) {
2918 int instruction = 0x81381000;
2919 instruction |= ((rs1.value() & 0x1f) << 14);
2920 instruction |= (rs2.value() & 0x1f);
2921 instruction |= ((rd.value() & 0x1f) << 25);
2922 emitInt(instruction);
2923 }
2924
2925 /**
2926 * Pseudo-external assembler syntax: {@code sra }<i>rs1</i>, <i>shcnt32</i>, <i>rd</i>
2927 * Example disassembly syntax: {@code sra %g0, 0x0, %g0}
2928 * <p>
2929 * Constraint: {@code 0 <= shcnt32 && shcnt32 <= 31}<br />
2930 *
2931 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.49"
2932 */
2933 // Template#: 172, Serial#: 172
2934 public void sra(final GPR rs1, final int shcnt32, final GPR rd) {
2935 int instruction = 0x81382000;
2936 checkConstraint(0 <= shcnt32 && shcnt32 <= 31, "0 <= shcnt32 && shcnt32 <= 31");
2937 instruction |= ((rs1.value() & 0x1f) << 14);
2938 instruction |= (shcnt32 & 0x1f);
2939 instruction |= ((rd.value() & 0x1f) << 25);
2940 emitInt(instruction);
2941 }
2942
2943 /**
2944 * Pseudo-external assembler syntax: {@code srax }<i>rs1</i>, <i>shcnt64</i>, <i>rd</i>
2945 * Example disassembly syntax: {@code srax %g0, 0x0, %g0}
2946 * <p>
2947 * Constraint: {@code 0 <= shcnt64 && shcnt64 <= 63}<br />
2948 *
2949 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.49"
2950 */
2951 // Template#: 173, Serial#: 173
2952 public void srax(final GPR rs1, final int shcnt64, final GPR rd) {
2953 int instruction = 0x81383000;
2954 checkConstraint(0 <= shcnt64 && shcnt64 <= 63, "0 <= shcnt64 && shcnt64 <= 63");
2955 instruction |= ((rs1.value() & 0x1f) << 14);
2956 instruction |= (shcnt64 & 0x3f);
2957 instruction |= ((rd.value() & 0x1f) << 25);
2958 emitInt(instruction);
2959 }
2960
2961 /**
2962 * Pseudo-external assembler syntax: {@code sub }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2963 * Example disassembly syntax: {@code sub %g0, %g0, %g0}
2964 *
2965 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.56"
2966 */
2967 // Template#: 174, Serial#: 174
2968 public void sub(final GPR rs1, final GPR rs2, final GPR rd) {
2969 int instruction = 0x80200000;
2970 instruction |= ((rs1.value() & 0x1f) << 14);
2971 instruction |= (rs2.value() & 0x1f);
2972 instruction |= ((rd.value() & 0x1f) << 25);
2973 emitInt(instruction);
2974 }
2975
2976 /**
2977 * Pseudo-external assembler syntax: {@code sub }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
2978 * Example disassembly syntax: {@code sub %g0, -4096, %g0}
2979 * <p>
2980 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
2981 *
2982 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.56"
2983 */
2984 // Template#: 175, Serial#: 175
2985 public void sub(final GPR rs1, final int simm13, final GPR rd) {
2986 int instruction = 0x80202000;
2987 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
2988 instruction |= ((rs1.value() & 0x1f) << 14);
2989 instruction |= (simm13 & 0x1fff);
2990 instruction |= ((rd.value() & 0x1f) << 25);
2991 emitInt(instruction);
2992 }
2993
2994 /**
2995 * Pseudo-external assembler syntax: {@code subcc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
2996 * Example disassembly syntax: {@code subcc %g0, %g0, %g0}
2997 *
2998 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.56"
2999 */
3000 // Template#: 176, Serial#: 176
3001 public void subcc(final GPR rs1, final GPR rs2, final GPR rd) {
3002 int instruction = 0x80A00000;
3003 instruction |= ((rs1.value() & 0x1f) << 14);
3004 instruction |= (rs2.value() & 0x1f);
3005 instruction |= ((rd.value() & 0x1f) << 25);
3006 emitInt(instruction);
3007 }
3008
3009 /**
3010 * Pseudo-external assembler syntax: {@code subcc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
3011 * Example disassembly syntax: {@code subcc %g0, -4096, %g0}
3012 * <p>
3013 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
3014 *
3015 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.56"
3016 */
3017 // Template#: 177, Serial#: 177
3018 public void subcc(final GPR rs1, final int simm13, final GPR rd) {
3019 int instruction = 0x80A02000;
3020 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
3021 instruction |= ((rs1.value() & 0x1f) << 14);
3022 instruction |= (simm13 & 0x1fff);
3023 instruction |= ((rd.value() & 0x1f) << 25);
3024 emitInt(instruction);
3025 }
3026
3027 /**
3028 * Pseudo-external assembler syntax: {@code subc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
3029 * Example disassembly syntax: {@code subc %g0, %g0, %g0}
3030 *
3031 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.56"
3032 */
3033 // Template#: 178, Serial#: 178
3034 public void subc(final GPR rs1, final GPR rs2, final GPR rd) {
3035 int instruction = 0x80600000;
3036 instruction |= ((rs1.value() & 0x1f) << 14);
3037 instruction |= (rs2.value() & 0x1f);
3038 instruction |= ((rd.value() & 0x1f) << 25);
3039 emitInt(instruction);
3040 }
3041
3042 /**
3043 * Pseudo-external assembler syntax: {@code subc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
3044 * Example disassembly syntax: {@code subc %g0, -4096, %g0}
3045 * <p>
3046 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
3047 *
3048 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.56"
3049 */
3050 // Template#: 179, Serial#: 179
3051 public void subc(final GPR rs1, final int simm13, final GPR rd) {
3052 int instruction = 0x80602000;
3053 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
3054 instruction |= ((rs1.value() & 0x1f) << 14);
3055 instruction |= (simm13 & 0x1fff);
3056 instruction |= ((rd.value() & 0x1f) << 25);
3057 emitInt(instruction);
3058 }
3059
3060 /**
3061 * Pseudo-external assembler syntax: {@code subccc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
3062 * Example disassembly syntax: {@code subccc %g0, %g0, %g0}
3063 *
3064 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.56"
3065 */
3066 // Template#: 180, Serial#: 180
3067 public void subccc(final GPR rs1, final GPR rs2, final GPR rd) {
3068 int instruction = 0x80E00000;
3069 instruction |= ((rs1.value() & 0x1f) << 14);
3070 instruction |= (rs2.value() & 0x1f);
3071 instruction |= ((rd.value() & 0x1f) << 25);
3072 emitInt(instruction);
3073 }
3074
3075 /**
3076 * Pseudo-external assembler syntax: {@code subccc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
3077 * Example disassembly syntax: {@code subccc %g0, -4096, %g0}
3078 * <p>
3079 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
3080 *
3081 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.56"
3082 */
3083 // Template#: 181, Serial#: 181
3084 public void subccc(final GPR rs1, final int simm13, final GPR rd) {
3085 int instruction = 0x80E02000;
3086 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
3087 instruction |= ((rs1.value() & 0x1f) << 14);
3088 instruction |= (simm13 & 0x1fff);
3089 instruction |= ((rd.value() & 0x1f) << 25);
3090 emitInt(instruction);
3091 }
3092
3093 /**
3094 * Pseudo-external assembler syntax: {@code taddcc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
3095 * Example disassembly syntax: {@code taddcc %g0, %g0, %g0}
3096 *
3097 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.59"
3098 */
3099 // Template#: 182, Serial#: 182
3100 public void taddcc(final GPR rs1, final GPR rs2, final GPR rd) {
3101 int instruction = 0x81000000;
3102 instruction |= ((rs1.value() & 0x1f) << 14);
3103 instruction |= (rs2.value() & 0x1f);
3104 instruction |= ((rd.value() & 0x1f) << 25);
3105 emitInt(instruction);
3106 }
3107
3108 /**
3109 * Pseudo-external assembler syntax: {@code taddcc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
3110 * Example disassembly syntax: {@code taddcc %g0, -4096, %g0}
3111 * <p>
3112 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
3113 *
3114 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.59"
3115 */
3116 // Template#: 183, Serial#: 183
3117 public void taddcc(final GPR rs1, final int simm13, final GPR rd) {
3118 int instruction = 0x81002000;
3119 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
3120 instruction |= ((rs1.value() & 0x1f) << 14);
3121 instruction |= (simm13 & 0x1fff);
3122 instruction |= ((rd.value() & 0x1f) << 25);
3123 emitInt(instruction);
3124 }
3125
3126 /**
3127 * Pseudo-external assembler syntax: {@code taddcctv }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
3128 * Example disassembly syntax: {@code taddcctv %g0, %g0, %g0}
3129 *
3130 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.59"
3131 */
3132 // Template#: 184, Serial#: 184
3133 public void taddcctv(final GPR rs1, final GPR rs2, final GPR rd) {
3134 int instruction = 0x81100000;
3135 instruction |= ((rs1.value() & 0x1f) << 14);
3136 instruction |= (rs2.value() & 0x1f);
3137 instruction |= ((rd.value() & 0x1f) << 25);
3138 emitInt(instruction);
3139 }
3140
3141 /**
3142 * Pseudo-external assembler syntax: {@code taddcctv }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
3143 * Example disassembly syntax: {@code taddcctv %g0, -4096, %g0}
3144 * <p>
3145 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
3146 *
3147 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.59"
3148 */
3149 // Template#: 185, Serial#: 185
3150 public void taddcctv(final GPR rs1, final int simm13, final GPR rd) {
3151 int instruction = 0x81102000;
3152 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
3153 instruction |= ((rs1.value() & 0x1f) << 14);
3154 instruction |= (simm13 & 0x1fff);
3155 instruction |= ((rd.value() & 0x1f) << 25);
3156 emitInt(instruction);
3157 }
3158
3159 /**
3160 * Pseudo-external assembler syntax: {@code tsubcc }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
3161 * Example disassembly syntax: {@code tsubcc %g0, %g0, %g0}
3162 *
3163 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.60"
3164 */
3165 // Template#: 186, Serial#: 186
3166 public void tsubcc(final GPR rs1, final GPR rs2, final GPR rd) {
3167 int instruction = 0x81080000;
3168 instruction |= ((rs1.value() & 0x1f) << 14);
3169 instruction |= (rs2.value() & 0x1f);
3170 instruction |= ((rd.value() & 0x1f) << 25);
3171 emitInt(instruction);
3172 }
3173
3174 /**
3175 * Pseudo-external assembler syntax: {@code tsubcc }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
3176 * Example disassembly syntax: {@code tsubcc %g0, -4096, %g0}
3177 * <p>
3178 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
3179 *
3180 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.60"
3181 */
3182 // Template#: 187, Serial#: 187
3183 public void tsubcc(final GPR rs1, final int simm13, final GPR rd) {
3184 int instruction = 0x81082000;
3185 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
3186 instruction |= ((rs1.value() & 0x1f) << 14);
3187 instruction |= (simm13 & 0x1fff);
3188 instruction |= ((rd.value() & 0x1f) << 25);
3189 emitInt(instruction);
3190 }
3191
3192 /**
3193 * Pseudo-external assembler syntax: {@code tsubcctv }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
3194 * Example disassembly syntax: {@code tsubcctv %g0, %g0, %g0}
3195 *
3196 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.60"
3197 */
3198 // Template#: 188, Serial#: 188
3199 public void tsubcctv(final GPR rs1, final GPR rs2, final GPR rd) {
3200 int instruction = 0x81180000;
3201 instruction |= ((rs1.value() & 0x1f) << 14);
3202 instruction |= (rs2.value() & 0x1f);
3203 instruction |= ((rd.value() & 0x1f) << 25);
3204 emitInt(instruction);
3205 }
3206
3207 /**
3208 * Pseudo-external assembler syntax: {@code tsubcctv }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
3209 * Example disassembly syntax: {@code tsubcctv %g0, -4096, %g0}
3210 * <p>
3211 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
3212 *
3213 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.60"
3214 */
3215 // Template#: 189, Serial#: 189
3216 public void tsubcctv(final GPR rs1, final int simm13, final GPR rd) {
3217 int instruction = 0x81182000;
3218 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
3219 instruction |= ((rs1.value() & 0x1f) << 14);
3220 instruction |= (simm13 & 0x1fff);
3221 instruction |= ((rd.value() & 0x1f) << 25);
3222 emitInt(instruction);
3223 }
3224
3225 /**
3226 * Pseudo-external assembler syntax: {@code brz{,a}{,pn|,pt} }<i>rs1</i>, <i>label</i>
3227 * Example disassembly syntax: {@code brz,pn %g0, L1: -131072}
3228 * <p>
3229 * Constraint: {@code (-131072 <= label && label <= 131068) && ((label % 4) == 0)}<br />
3230 *
3231 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.3"
3232 */
3233 // Template#: 190, Serial#: 190
3234 public void brz(final AnnulBit a, final BranchPredictionBit p, final GPR rs1, final int label) {
3235 int instruction = 0x02C00000;
3236 checkConstraint((-131072 <= label && label <= 131068) && ((label % 4) == 0), "(-131072 <= label && label <= 131068) && ((label % 4) == 0)");
3237 instruction |= ((a.value() & 0x1) << 29);
3238 instruction |= ((p.value() & 0x1) << 19);
3239 instruction |= ((rs1.value() & 0x1f) << 14);
3240 instruction |= ((label >> 2) & 0x3fff) | ((((label >> 2) >> 14) & 0x3) << 20);
3241 emitInt(instruction);
3242 }
3243
3244 /**
3245 * Pseudo-external assembler syntax: {@code brlez{,a}{,pn|,pt} }<i>rs1</i>, <i>label</i>
3246 * Example disassembly syntax: {@code brlez,pn %g0, L1: -131072}
3247 * <p>
3248 * Constraint: {@code (-131072 <= label && label <= 131068) && ((label % 4) == 0)}<br />
3249 *
3250 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.3"
3251 */
3252 // Template#: 191, Serial#: 191
3253 public void brlez(final AnnulBit a, final BranchPredictionBit p, final GPR rs1, final int label) {
3254 int instruction = 0x04C00000;
3255 checkConstraint((-131072 <= label && label <= 131068) && ((label % 4) == 0), "(-131072 <= label && label <= 131068) && ((label % 4) == 0)");
3256 instruction |= ((a.value() & 0x1) << 29);
3257 instruction |= ((p.value() & 0x1) << 19);
3258 instruction |= ((rs1.value() & 0x1f) << 14);
3259 instruction |= ((label >> 2) & 0x3fff) | ((((label >> 2) >> 14) & 0x3) << 20);
3260 emitInt(instruction);
3261 }
3262
3263 /**
3264 * Pseudo-external assembler syntax: {@code brlz{,a}{,pn|,pt} }<i>rs1</i>, <i>label</i>
3265 * Example disassembly syntax: {@code brlz,pn %g0, L1: -131072}
3266 * <p>
3267 * Constraint: {@code (-131072 <= label && label <= 131068) && ((label % 4) == 0)}<br />
3268 *
3269 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.3"
3270 */
3271 // Template#: 192, Serial#: 192
3272 public void brlz(final AnnulBit a, final BranchPredictionBit p, final GPR rs1, final int label) {
3273 int instruction = 0x06C00000;
3274 checkConstraint((-131072 <= label && label <= 131068) && ((label % 4) == 0), "(-131072 <= label && label <= 131068) && ((label % 4) == 0)");
3275 instruction |= ((a.value() & 0x1) << 29);
3276 instruction |= ((p.value() & 0x1) << 19);
3277 instruction |= ((rs1.value() & 0x1f) << 14);
3278 instruction |= ((label >> 2) & 0x3fff) | ((((label >> 2) >> 14) & 0x3) << 20);
3279 emitInt(instruction);
3280 }
3281
3282 /**
3283 * Pseudo-external assembler syntax: {@code brnz{,a}{,pn|,pt} }<i>rs1</i>, <i>label</i>
3284 * Example disassembly syntax: {@code brnz,pn %g0, L1: -131072}
3285 * <p>
3286 * Constraint: {@code (-131072 <= label && label <= 131068) && ((label % 4) == 0)}<br />
3287 *
3288 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.3"
3289 */
3290 // Template#: 193, Serial#: 193
3291 public void brnz(final AnnulBit a, final BranchPredictionBit p, final GPR rs1, final int label) {
3292 int instruction = 0x0AC00000;
3293 checkConstraint((-131072 <= label && label <= 131068) && ((label % 4) == 0), "(-131072 <= label && label <= 131068) && ((label % 4) == 0)");
3294 instruction |= ((a.value() & 0x1) << 29);
3295 instruction |= ((p.value() & 0x1) << 19);
3296 instruction |= ((rs1.value() & 0x1f) << 14);
3297 instruction |= ((label >> 2) & 0x3fff) | ((((label >> 2) >> 14) & 0x3) << 20);
3298 emitInt(instruction);
3299 }
3300
3301 /**
3302 * Pseudo-external assembler syntax: {@code brgz{,a}{,pn|,pt} }<i>rs1</i>, <i>label</i>
3303 * Example disassembly syntax: {@code brgz,pn %g0, L1: -131072}
3304 * <p>
3305 * Constraint: {@code (-131072 <= label && label <= 131068) && ((label % 4) == 0)}<br />
3306 *
3307 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.3"
3308 */
3309 // Template#: 194, Serial#: 194
3310 public void brgz(final AnnulBit a, final BranchPredictionBit p, final GPR rs1, final int label) {
3311 int instruction = 0x0CC00000;
3312 checkConstraint((-131072 <= label && label <= 131068) && ((label % 4) == 0), "(-131072 <= label && label <= 131068) && ((label % 4) == 0)");
3313 instruction |= ((a.value() & 0x1) << 29);
3314 instruction |= ((p.value() & 0x1) << 19);
3315 instruction |= ((rs1.value() & 0x1f) << 14);
3316 instruction |= ((label >> 2) & 0x3fff) | ((((label >> 2) >> 14) & 0x3) << 20);
3317 emitInt(instruction);
3318 }
3319
3320 /**
3321 * Pseudo-external assembler syntax: {@code brgez{,a}{,pn|,pt} }<i>rs1</i>, <i>label</i>
3322 * Example disassembly syntax: {@code brgez,pn %g0, L1: -131072}
3323 * <p>
3324 * Constraint: {@code (-131072 <= label && label <= 131068) && ((label % 4) == 0)}<br />
3325 *
3326 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.3"
3327 */
3328 // Template#: 195, Serial#: 195
3329 public void brgez(final AnnulBit a, final BranchPredictionBit p, final GPR rs1, final int label) {
3330 int instruction = 0x0EC00000;
3331 checkConstraint((-131072 <= label && label <= 131068) && ((label % 4) == 0), "(-131072 <= label && label <= 131068) && ((label % 4) == 0)");
3332 instruction |= ((a.value() & 0x1) << 29);
3333 instruction |= ((p.value() & 0x1) << 19);
3334 instruction |= ((rs1.value() & 0x1f) << 14);
3335 instruction |= ((label >> 2) & 0x3fff) | ((((label >> 2) >> 14) & 0x3) << 20);
3336 emitInt(instruction);
3337 }
3338
3339 /**
3340 * Pseudo-external assembler syntax: {@code brz }<i>rs1</i>, <i>label</i>
3341 * Example disassembly syntax: {@code brz %g0, L1: -131072}
3342 * <p>
3343 * Constraint: {@code (-131072 <= label && label <= 131068) && ((label % 4) == 0)}<br />
3344 *
3345 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.3"
3346 */
3347 // Template#: 196, Serial#: 196
3348 public void brz(final GPR rs1, final int label) {
3349 int instruction = 0x02C80000;
3350 checkConstraint((-131072 <= label && label <= 131068) && ((label % 4) == 0), "(-131072 <= label && label <= 131068) && ((label % 4) == 0)");
3351 instruction |= ((rs1.value() & 0x1f) << 14);
3352 instruction |= ((label >> 2) & 0x3fff) | ((((label >> 2) >> 14) & 0x3) << 20);
3353 emitInt(instruction);
3354 }
3355
3356 /**
3357 * Pseudo-external assembler syntax: {@code brlez }<i>rs1</i>, <i>label</i>
3358 * Example disassembly syntax: {@code brlez %g0, L1: -131072}
3359 * <p>
3360 * Constraint: {@code (-131072 <= label && label <= 131068) && ((label % 4) == 0)}<br />
3361 *
3362 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.3"
3363 */
3364 // Template#: 197, Serial#: 197
3365 public void brlez(final GPR rs1, final int label) {
3366 int instruction = 0x04C80000;
3367 checkConstraint((-131072 <= label && label <= 131068) && ((label % 4) == 0), "(-131072 <= label && label <= 131068) && ((label % 4) == 0)");
3368 instruction |= ((rs1.value() & 0x1f) << 14);
3369 instruction |= ((label >> 2) & 0x3fff) | ((((label >> 2) >> 14) & 0x3) << 20);
3370 emitInt(instruction);
3371 }
3372
3373 /**
3374 * Pseudo-external assembler syntax: {@code brlz }<i>rs1</i>, <i>label</i>
3375 * Example disassembly syntax: {@code brlz %g0, L1: -131072}
3376 * <p>
3377 * Constraint: {@code (-131072 <= label && label <= 131068) && ((label % 4) == 0)}<br />
3378 *
3379 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.3"
3380 */
3381 // Template#: 198, Serial#: 198
3382 public void brlz(final GPR rs1, final int label) {
3383 int instruction = 0x06C80000;
3384 checkConstraint((-131072 <= label && label <= 131068) && ((label % 4) == 0), "(-131072 <= label && label <= 131068) && ((label % 4) == 0)");
3385 instruction |= ((rs1.value() & 0x1f) << 14);
3386 instruction |= ((label >> 2) & 0x3fff) | ((((label >> 2) >> 14) & 0x3) << 20);
3387 emitInt(instruction);
3388 }
3389
3390 /**
3391 * Pseudo-external assembler syntax: {@code brnz }<i>rs1</i>, <i>label</i>
3392 * Example disassembly syntax: {@code brnz %g0, L1: -131072}
3393 * <p>
3394 * Constraint: {@code (-131072 <= label && label <= 131068) && ((label % 4) == 0)}<br />
3395 *
3396 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.3"
3397 */
3398 // Template#: 199, Serial#: 199
3399 public void brnz(final GPR rs1, final int label) {
3400 int instruction = 0x0AC80000;
3401 checkConstraint((-131072 <= label && label <= 131068) && ((label % 4) == 0), "(-131072 <= label && label <= 131068) && ((label % 4) == 0)");
3402 instruction |= ((rs1.value() & 0x1f) << 14);
3403 instruction |= ((label >> 2) & 0x3fff) | ((((label >> 2) >> 14) & 0x3) << 20);
3404 emitInt(instruction);
3405 }
3406
3407 /**
3408 * Pseudo-external assembler syntax: {@code brgz }<i>rs1</i>, <i>label</i>
3409 * Example disassembly syntax: {@code brgz %g0, L1: -131072}
3410 * <p>
3411 * Constraint: {@code (-131072 <= label && label <= 131068) && ((label % 4) == 0)}<br />
3412 *
3413 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.3"
3414 */
3415 // Template#: 200, Serial#: 200
3416 public void brgz(final GPR rs1, final int label) {
3417 int instruction = 0x0CC80000;
3418 checkConstraint((-131072 <= label && label <= 131068) && ((label % 4) == 0), "(-131072 <= label && label <= 131068) && ((label % 4) == 0)");
3419 instruction |= ((rs1.value() & 0x1f) << 14);
3420 instruction |= ((label >> 2) & 0x3fff) | ((((label >> 2) >> 14) & 0x3) << 20);
3421 emitInt(instruction);
3422 }
3423
3424 /**
3425 * Pseudo-external assembler syntax: {@code brgez }<i>rs1</i>, <i>label</i>
3426 * Example disassembly syntax: {@code brgez %g0, L1: -131072}
3427 * <p>
3428 * Constraint: {@code (-131072 <= label && label <= 131068) && ((label % 4) == 0)}<br />
3429 *
3430 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.3"
3431 */
3432 // Template#: 201, Serial#: 201
3433 public void brgez(final GPR rs1, final int label) {
3434 int instruction = 0x0EC80000;
3435 checkConstraint((-131072 <= label && label <= 131068) && ((label % 4) == 0), "(-131072 <= label && label <= 131068) && ((label % 4) == 0)");
3436 instruction |= ((rs1.value() & 0x1f) << 14);
3437 instruction |= ((label >> 2) & 0x3fff) | ((((label >> 2) >> 14) & 0x3) << 20);
3438 emitInt(instruction);
3439 }
3440
3441 /**
3442 * Pseudo-external assembler syntax: {@code br[z|lez|lz|nz|gz|gez]{,a}{,pn|,pt} }<i>rs1</i>, <i>label</i>
3443 * Example disassembly syntax: {@code brz,pn %g0, L1: -131072}
3444 * <p>
3445 * Constraint: {@code (-131072 <= label && label <= 131068) && ((label % 4) == 0)}<br />
3446 *
3447 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.3"
3448 */
3449 // Template#: 202, Serial#: 202
3450 public void br(final BPr cond, final AnnulBit a, final BranchPredictionBit p, final GPR rs1, final int label) {
3451 int instruction = 0x00C00000;
3452 checkConstraint((-131072 <= label && label <= 131068) && ((label % 4) == 0), "(-131072 <= label && label <= 131068) && ((label % 4) == 0)");
3453 instruction |= ((cond.value() & 0x7) << 25);
3454 instruction |= ((a.value() & 0x1) << 29);
3455 instruction |= ((p.value() & 0x1) << 19);
3456 instruction |= ((rs1.value() & 0x1f) << 14);
3457 instruction |= ((label >> 2) & 0x3fff) | ((((label >> 2) >> 14) & 0x3) << 20);
3458 emitInt(instruction);
3459 }
3460
3461 /**
3462 * Pseudo-external assembler syntax: {@code fba{,a} }<i>label</i>
3463 * Example disassembly syntax: {@code fba L1: -8388608}
3464 * <p>
3465 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3466 *
3467 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3468 */
3469 // Template#: 203, Serial#: 203
3470 public void fba(final AnnulBit a, final int label) {
3471 int instruction = 0x11800000;
3472 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3473 instruction |= ((a.value() & 0x1) << 29);
3474 instruction |= ((label >> 2) & 0x3fffff);
3475 emitInt(instruction);
3476 }
3477
3478 /**
3479 * Pseudo-external assembler syntax: {@code fbn{,a} }<i>label</i>
3480 * Example disassembly syntax: {@code fbn L1: -8388608}
3481 * <p>
3482 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3483 *
3484 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3485 */
3486 // Template#: 204, Serial#: 204
3487 public void fbn(final AnnulBit a, final int label) {
3488 int instruction = 0x01800000;
3489 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3490 instruction |= ((a.value() & 0x1) << 29);
3491 instruction |= ((label >> 2) & 0x3fffff);
3492 emitInt(instruction);
3493 }
3494
3495 /**
3496 * Pseudo-external assembler syntax: {@code fbu{,a} }<i>label</i>
3497 * Example disassembly syntax: {@code fbu L1: -8388608}
3498 * <p>
3499 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3500 *
3501 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3502 */
3503 // Template#: 205, Serial#: 205
3504 public void fbu(final AnnulBit a, final int label) {
3505 int instruction = 0x0F800000;
3506 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3507 instruction |= ((a.value() & 0x1) << 29);
3508 instruction |= ((label >> 2) & 0x3fffff);
3509 emitInt(instruction);
3510 }
3511
3512 /**
3513 * Pseudo-external assembler syntax: {@code fbg{,a} }<i>label</i>
3514 * Example disassembly syntax: {@code fbg L1: -8388608}
3515 * <p>
3516 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3517 *
3518 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3519 */
3520 // Template#: 206, Serial#: 206
3521 public void fbg(final AnnulBit a, final int label) {
3522 int instruction = 0x0D800000;
3523 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3524 instruction |= ((a.value() & 0x1) << 29);
3525 instruction |= ((label >> 2) & 0x3fffff);
3526 emitInt(instruction);
3527 }
3528
3529 /**
3530 * Pseudo-external assembler syntax: {@code fbug{,a} }<i>label</i>
3531 * Example disassembly syntax: {@code fbug L1: -8388608}
3532 * <p>
3533 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3534 *
3535 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3536 */
3537 // Template#: 207, Serial#: 207
3538 public void fbug(final AnnulBit a, final int label) {
3539 int instruction = 0x0B800000;
3540 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3541 instruction |= ((a.value() & 0x1) << 29);
3542 instruction |= ((label >> 2) & 0x3fffff);
3543 emitInt(instruction);
3544 }
3545
3546 /**
3547 * Pseudo-external assembler syntax: {@code fbl{,a} }<i>label</i>
3548 * Example disassembly syntax: {@code fbl L1: -8388608}
3549 * <p>
3550 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3551 *
3552 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3553 */
3554 // Template#: 208, Serial#: 208
3555 public void fbl(final AnnulBit a, final int label) {
3556 int instruction = 0x09800000;
3557 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3558 instruction |= ((a.value() & 0x1) << 29);
3559 instruction |= ((label >> 2) & 0x3fffff);
3560 emitInt(instruction);
3561 }
3562
3563 /**
3564 * Pseudo-external assembler syntax: {@code fbul{,a} }<i>label</i>
3565 * Example disassembly syntax: {@code fbul L1: -8388608}
3566 * <p>
3567 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3568 *
3569 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3570 */
3571 // Template#: 209, Serial#: 209
3572 public void fbul(final AnnulBit a, final int label) {
3573 int instruction = 0x07800000;
3574 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3575 instruction |= ((a.value() & 0x1) << 29);
3576 instruction |= ((label >> 2) & 0x3fffff);
3577 emitInt(instruction);
3578 }
3579
3580 /**
3581 * Pseudo-external assembler syntax: {@code fblg{,a} }<i>label</i>
3582 * Example disassembly syntax: {@code fblg L1: -8388608}
3583 * <p>
3584 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3585 *
3586 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3587 */
3588 // Template#: 210, Serial#: 210
3589 public void fblg(final AnnulBit a, final int label) {
3590 int instruction = 0x05800000;
3591 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3592 instruction |= ((a.value() & 0x1) << 29);
3593 instruction |= ((label >> 2) & 0x3fffff);
3594 emitInt(instruction);
3595 }
3596
3597 /**
3598 * Pseudo-external assembler syntax: {@code fbne{,a} }<i>label</i>
3599 * Example disassembly syntax: {@code fbne L1: -8388608}
3600 * <p>
3601 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3602 *
3603 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3604 */
3605 // Template#: 211, Serial#: 211
3606 public void fbne(final AnnulBit a, final int label) {
3607 int instruction = 0x03800000;
3608 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3609 instruction |= ((a.value() & 0x1) << 29);
3610 instruction |= ((label >> 2) & 0x3fffff);
3611 emitInt(instruction);
3612 }
3613
3614 /**
3615 * Pseudo-external assembler syntax: {@code fbe{,a} }<i>label</i>
3616 * Example disassembly syntax: {@code fbe L1: -8388608}
3617 * <p>
3618 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3619 *
3620 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3621 */
3622 // Template#: 212, Serial#: 212
3623 public void fbe(final AnnulBit a, final int label) {
3624 int instruction = 0x13800000;
3625 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3626 instruction |= ((a.value() & 0x1) << 29);
3627 instruction |= ((label >> 2) & 0x3fffff);
3628 emitInt(instruction);
3629 }
3630
3631 /**
3632 * Pseudo-external assembler syntax: {@code fbue{,a} }<i>label</i>
3633 * Example disassembly syntax: {@code fbue L1: -8388608}
3634 * <p>
3635 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3636 *
3637 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3638 */
3639 // Template#: 213, Serial#: 213
3640 public void fbue(final AnnulBit a, final int label) {
3641 int instruction = 0x15800000;
3642 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3643 instruction |= ((a.value() & 0x1) << 29);
3644 instruction |= ((label >> 2) & 0x3fffff);
3645 emitInt(instruction);
3646 }
3647
3648 /**
3649 * Pseudo-external assembler syntax: {@code fbge{,a} }<i>label</i>
3650 * Example disassembly syntax: {@code fbge L1: -8388608}
3651 * <p>
3652 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3653 *
3654 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3655 */
3656 // Template#: 214, Serial#: 214
3657 public void fbge(final AnnulBit a, final int label) {
3658 int instruction = 0x17800000;
3659 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3660 instruction |= ((a.value() & 0x1) << 29);
3661 instruction |= ((label >> 2) & 0x3fffff);
3662 emitInt(instruction);
3663 }
3664
3665 /**
3666 * Pseudo-external assembler syntax: {@code fbuge{,a} }<i>label</i>
3667 * Example disassembly syntax: {@code fbuge L1: -8388608}
3668 * <p>
3669 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3670 *
3671 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3672 */
3673 // Template#: 215, Serial#: 215
3674 public void fbuge(final AnnulBit a, final int label) {
3675 int instruction = 0x19800000;
3676 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3677 instruction |= ((a.value() & 0x1) << 29);
3678 instruction |= ((label >> 2) & 0x3fffff);
3679 emitInt(instruction);
3680 }
3681
3682 /**
3683 * Pseudo-external assembler syntax: {@code fble{,a} }<i>label</i>
3684 * Example disassembly syntax: {@code fble L1: -8388608}
3685 * <p>
3686 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3687 *
3688 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3689 */
3690 // Template#: 216, Serial#: 216
3691 public void fble(final AnnulBit a, final int label) {
3692 int instruction = 0x1B800000;
3693 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3694 instruction |= ((a.value() & 0x1) << 29);
3695 instruction |= ((label >> 2) & 0x3fffff);
3696 emitInt(instruction);
3697 }
3698
3699 /**
3700 * Pseudo-external assembler syntax: {@code fbule{,a} }<i>label</i>
3701 * Example disassembly syntax: {@code fbule L1: -8388608}
3702 * <p>
3703 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3704 *
3705 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3706 */
3707 // Template#: 217, Serial#: 217
3708 public void fbule(final AnnulBit a, final int label) {
3709 int instruction = 0x1D800000;
3710 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3711 instruction |= ((a.value() & 0x1) << 29);
3712 instruction |= ((label >> 2) & 0x3fffff);
3713 emitInt(instruction);
3714 }
3715
3716 /**
3717 * Pseudo-external assembler syntax: {@code fbo{,a} }<i>label</i>
3718 * Example disassembly syntax: {@code fbo L1: -8388608}
3719 * <p>
3720 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3721 *
3722 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3723 */
3724 // Template#: 218, Serial#: 218
3725 public void fbo(final AnnulBit a, final int label) {
3726 int instruction = 0x1F800000;
3727 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3728 instruction |= ((a.value() & 0x1) << 29);
3729 instruction |= ((label >> 2) & 0x3fffff);
3730 emitInt(instruction);
3731 }
3732
3733 /**
3734 * Pseudo-external assembler syntax: {@code fba }<i>label</i>
3735 * Example disassembly syntax: {@code fba L1: -8388608}
3736 * <p>
3737 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3738 *
3739 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3740 */
3741 // Template#: 219, Serial#: 219
3742 public void fba(final int label) {
3743 int instruction = 0x11800000;
3744 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3745 instruction |= ((label >> 2) & 0x3fffff);
3746 emitInt(instruction);
3747 }
3748
3749 /**
3750 * Pseudo-external assembler syntax: {@code fbn }<i>label</i>
3751 * Example disassembly syntax: {@code fbn L1: -8388608}
3752 * <p>
3753 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3754 *
3755 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3756 */
3757 // Template#: 220, Serial#: 220
3758 public void fbn(final int label) {
3759 int instruction = 0x01800000;
3760 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3761 instruction |= ((label >> 2) & 0x3fffff);
3762 emitInt(instruction);
3763 }
3764
3765 /**
3766 * Pseudo-external assembler syntax: {@code fbu }<i>label</i>
3767 * Example disassembly syntax: {@code fbu L1: -8388608}
3768 * <p>
3769 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3770 *
3771 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3772 */
3773 // Template#: 221, Serial#: 221
3774 public void fbu(final int label) {
3775 int instruction = 0x0F800000;
3776 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3777 instruction |= ((label >> 2) & 0x3fffff);
3778 emitInt(instruction);
3779 }
3780
3781 /**
3782 * Pseudo-external assembler syntax: {@code fbg }<i>label</i>
3783 * Example disassembly syntax: {@code fbg L1: -8388608}
3784 * <p>
3785 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3786 *
3787 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3788 */
3789 // Template#: 222, Serial#: 222
3790 public void fbg(final int label) {
3791 int instruction = 0x0D800000;
3792 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3793 instruction |= ((label >> 2) & 0x3fffff);
3794 emitInt(instruction);
3795 }
3796
3797 /**
3798 * Pseudo-external assembler syntax: {@code fbug }<i>label</i>
3799 * Example disassembly syntax: {@code fbug L1: -8388608}
3800 * <p>
3801 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3802 *
3803 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3804 */
3805 // Template#: 223, Serial#: 223
3806 public void fbug(final int label) {
3807 int instruction = 0x0B800000;
3808 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3809 instruction |= ((label >> 2) & 0x3fffff);
3810 emitInt(instruction);
3811 }
3812
3813 /**
3814 * Pseudo-external assembler syntax: {@code fbl }<i>label</i>
3815 * Example disassembly syntax: {@code fbl L1: -8388608}
3816 * <p>
3817 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3818 *
3819 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3820 */
3821 // Template#: 224, Serial#: 224
3822 public void fbl(final int label) {
3823 int instruction = 0x09800000;
3824 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3825 instruction |= ((label >> 2) & 0x3fffff);
3826 emitInt(instruction);
3827 }
3828
3829 /**
3830 * Pseudo-external assembler syntax: {@code fbul }<i>label</i>
3831 * Example disassembly syntax: {@code fbul L1: -8388608}
3832 * <p>
3833 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3834 *
3835 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3836 */
3837 // Template#: 225, Serial#: 225
3838 public void fbul(final int label) {
3839 int instruction = 0x07800000;
3840 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3841 instruction |= ((label >> 2) & 0x3fffff);
3842 emitInt(instruction);
3843 }
3844
3845 /**
3846 * Pseudo-external assembler syntax: {@code fblg }<i>label</i>
3847 * Example disassembly syntax: {@code fblg L1: -8388608}
3848 * <p>
3849 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3850 *
3851 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3852 */
3853 // Template#: 226, Serial#: 226
3854 public void fblg(final int label) {
3855 int instruction = 0x05800000;
3856 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3857 instruction |= ((label >> 2) & 0x3fffff);
3858 emitInt(instruction);
3859 }
3860
3861 /**
3862 * Pseudo-external assembler syntax: {@code fbne }<i>label</i>
3863 * Example disassembly syntax: {@code fbne L1: -8388608}
3864 * <p>
3865 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3866 *
3867 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3868 */
3869 // Template#: 227, Serial#: 227
3870 public void fbne(final int label) {
3871 int instruction = 0x03800000;
3872 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3873 instruction |= ((label >> 2) & 0x3fffff);
3874 emitInt(instruction);
3875 }
3876
3877 /**
3878 * Pseudo-external assembler syntax: {@code fbe }<i>label</i>
3879 * Example disassembly syntax: {@code fbe L1: -8388608}
3880 * <p>
3881 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3882 *
3883 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3884 */
3885 // Template#: 228, Serial#: 228
3886 public void fbe(final int label) {
3887 int instruction = 0x13800000;
3888 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3889 instruction |= ((label >> 2) & 0x3fffff);
3890 emitInt(instruction);
3891 }
3892
3893 /**
3894 * Pseudo-external assembler syntax: {@code fbue }<i>label</i>
3895 * Example disassembly syntax: {@code fbue L1: -8388608}
3896 * <p>
3897 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3898 *
3899 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3900 */
3901 // Template#: 229, Serial#: 229
3902 public void fbue(final int label) {
3903 int instruction = 0x15800000;
3904 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3905 instruction |= ((label >> 2) & 0x3fffff);
3906 emitInt(instruction);
3907 }
3908
3909 /**
3910 * Pseudo-external assembler syntax: {@code fbge }<i>label</i>
3911 * Example disassembly syntax: {@code fbge L1: -8388608}
3912 * <p>
3913 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3914 *
3915 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3916 */
3917 // Template#: 230, Serial#: 230
3918 public void fbge(final int label) {
3919 int instruction = 0x17800000;
3920 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3921 instruction |= ((label >> 2) & 0x3fffff);
3922 emitInt(instruction);
3923 }
3924
3925 /**
3926 * Pseudo-external assembler syntax: {@code fbuge }<i>label</i>
3927 * Example disassembly syntax: {@code fbuge L1: -8388608}
3928 * <p>
3929 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3930 *
3931 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3932 */
3933 // Template#: 231, Serial#: 231
3934 public void fbuge(final int label) {
3935 int instruction = 0x19800000;
3936 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3937 instruction |= ((label >> 2) & 0x3fffff);
3938 emitInt(instruction);
3939 }
3940
3941 /**
3942 * Pseudo-external assembler syntax: {@code fble }<i>label</i>
3943 * Example disassembly syntax: {@code fble L1: -8388608}
3944 * <p>
3945 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3946 *
3947 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3948 */
3949 // Template#: 232, Serial#: 232
3950 public void fble(final int label) {
3951 int instruction = 0x1B800000;
3952 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3953 instruction |= ((label >> 2) & 0x3fffff);
3954 emitInt(instruction);
3955 }
3956
3957 /**
3958 * Pseudo-external assembler syntax: {@code fbule }<i>label</i>
3959 * Example disassembly syntax: {@code fbule L1: -8388608}
3960 * <p>
3961 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3962 *
3963 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3964 */
3965 // Template#: 233, Serial#: 233
3966 public void fbule(final int label) {
3967 int instruction = 0x1D800000;
3968 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3969 instruction |= ((label >> 2) & 0x3fffff);
3970 emitInt(instruction);
3971 }
3972
3973 /**
3974 * Pseudo-external assembler syntax: {@code fbo }<i>label</i>
3975 * Example disassembly syntax: {@code fbo L1: -8388608}
3976 * <p>
3977 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3978 *
3979 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3980 */
3981 // Template#: 234, Serial#: 234
3982 public void fbo(final int label) {
3983 int instruction = 0x1F800000;
3984 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
3985 instruction |= ((label >> 2) & 0x3fffff);
3986 emitInt(instruction);
3987 }
3988
3989 /**
3990 * Pseudo-external assembler syntax: {@code fb[a|n|u|g|ug|l|ul|lg|ne|e|ue|ge|uge|le|ule|o]{,a} }<i>label</i>
3991 * Example disassembly syntax: {@code fba L1: -8388608}
3992 * <p>
3993 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
3994 *
3995 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.4"
3996 */
3997 // Template#: 235, Serial#: 235
3998 public void fb(final FBfcc cond, final AnnulBit a, final int label) {
3999 int instruction = 0x01800000;
4000 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4001 instruction |= ((cond.value() & 0xf) << 25);
4002 instruction |= ((a.value() & 0x1) << 29);
4003 instruction |= ((label >> 2) & 0x3fffff);
4004 emitInt(instruction);
4005 }
4006
4007 /**
4008 * Pseudo-external assembler syntax: {@code fba{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4009 * Example disassembly syntax: {@code fba,pn %fcc0, L1: -1048576}
4010 * <p>
4011 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4012 *
4013 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4014 */
4015 // Template#: 236, Serial#: 236
4016 public void fba(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4017 int instruction = 0x11400000;
4018 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4019 instruction |= ((a.value() & 0x1) << 29);
4020 instruction |= ((p.value() & 0x1) << 19);
4021 instruction |= ((n.value() & 0x3) << 20);
4022 instruction |= ((label >> 2) & 0x7ffff);
4023 emitInt(instruction);
4024 }
4025
4026 /**
4027 * Pseudo-external assembler syntax: {@code fbn{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4028 * Example disassembly syntax: {@code fbn,pn %fcc0, L1: -1048576}
4029 * <p>
4030 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4031 *
4032 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4033 */
4034 // Template#: 237, Serial#: 237
4035 public void fbn(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4036 int instruction = 0x01400000;
4037 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4038 instruction |= ((a.value() & 0x1) << 29);
4039 instruction |= ((p.value() & 0x1) << 19);
4040 instruction |= ((n.value() & 0x3) << 20);
4041 instruction |= ((label >> 2) & 0x7ffff);
4042 emitInt(instruction);
4043 }
4044
4045 /**
4046 * Pseudo-external assembler syntax: {@code fbu{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4047 * Example disassembly syntax: {@code fbu,pn %fcc0, L1: -1048576}
4048 * <p>
4049 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4050 *
4051 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4052 */
4053 // Template#: 238, Serial#: 238
4054 public void fbu(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4055 int instruction = 0x0F400000;
4056 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4057 instruction |= ((a.value() & 0x1) << 29);
4058 instruction |= ((p.value() & 0x1) << 19);
4059 instruction |= ((n.value() & 0x3) << 20);
4060 instruction |= ((label >> 2) & 0x7ffff);
4061 emitInt(instruction);
4062 }
4063
4064 /**
4065 * Pseudo-external assembler syntax: {@code fbg{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4066 * Example disassembly syntax: {@code fbg,pn %fcc0, L1: -1048576}
4067 * <p>
4068 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4069 *
4070 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4071 */
4072 // Template#: 239, Serial#: 239
4073 public void fbg(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4074 int instruction = 0x0D400000;
4075 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4076 instruction |= ((a.value() & 0x1) << 29);
4077 instruction |= ((p.value() & 0x1) << 19);
4078 instruction |= ((n.value() & 0x3) << 20);
4079 instruction |= ((label >> 2) & 0x7ffff);
4080 emitInt(instruction);
4081 }
4082
4083 /**
4084 * Pseudo-external assembler syntax: {@code fbug{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4085 * Example disassembly syntax: {@code fbug,pn %fcc0, L1: -1048576}
4086 * <p>
4087 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4088 *
4089 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4090 */
4091 // Template#: 240, Serial#: 240
4092 public void fbug(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4093 int instruction = 0x0B400000;
4094 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4095 instruction |= ((a.value() & 0x1) << 29);
4096 instruction |= ((p.value() & 0x1) << 19);
4097 instruction |= ((n.value() & 0x3) << 20);
4098 instruction |= ((label >> 2) & 0x7ffff);
4099 emitInt(instruction);
4100 }
4101
4102 /**
4103 * Pseudo-external assembler syntax: {@code fbl{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4104 * Example disassembly syntax: {@code fbl,pn %fcc0, L1: -1048576}
4105 * <p>
4106 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4107 *
4108 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4109 */
4110 // Template#: 241, Serial#: 241
4111 public void fbl(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4112 int instruction = 0x09400000;
4113 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4114 instruction |= ((a.value() & 0x1) << 29);
4115 instruction |= ((p.value() & 0x1) << 19);
4116 instruction |= ((n.value() & 0x3) << 20);
4117 instruction |= ((label >> 2) & 0x7ffff);
4118 emitInt(instruction);
4119 }
4120
4121 /**
4122 * Pseudo-external assembler syntax: {@code fbul{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4123 * Example disassembly syntax: {@code fbul,pn %fcc0, L1: -1048576}
4124 * <p>
4125 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4126 *
4127 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4128 */
4129 // Template#: 242, Serial#: 242
4130 public void fbul(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4131 int instruction = 0x07400000;
4132 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4133 instruction |= ((a.value() & 0x1) << 29);
4134 instruction |= ((p.value() & 0x1) << 19);
4135 instruction |= ((n.value() & 0x3) << 20);
4136 instruction |= ((label >> 2) & 0x7ffff);
4137 emitInt(instruction);
4138 }
4139
4140 /**
4141 * Pseudo-external assembler syntax: {@code fblg{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4142 * Example disassembly syntax: {@code fblg,pn %fcc0, L1: -1048576}
4143 * <p>
4144 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4145 *
4146 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4147 */
4148 // Template#: 243, Serial#: 243
4149 public void fblg(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4150 int instruction = 0x05400000;
4151 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4152 instruction |= ((a.value() & 0x1) << 29);
4153 instruction |= ((p.value() & 0x1) << 19);
4154 instruction |= ((n.value() & 0x3) << 20);
4155 instruction |= ((label >> 2) & 0x7ffff);
4156 emitInt(instruction);
4157 }
4158
4159 /**
4160 * Pseudo-external assembler syntax: {@code fbne{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4161 * Example disassembly syntax: {@code fbne,pn %fcc0, L1: -1048576}
4162 * <p>
4163 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4164 *
4165 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4166 */
4167 // Template#: 244, Serial#: 244
4168 public void fbne(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4169 int instruction = 0x03400000;
4170 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4171 instruction |= ((a.value() & 0x1) << 29);
4172 instruction |= ((p.value() & 0x1) << 19);
4173 instruction |= ((n.value() & 0x3) << 20);
4174 instruction |= ((label >> 2) & 0x7ffff);
4175 emitInt(instruction);
4176 }
4177
4178 /**
4179 * Pseudo-external assembler syntax: {@code fbe{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4180 * Example disassembly syntax: {@code fbe,pn %fcc0, L1: -1048576}
4181 * <p>
4182 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4183 *
4184 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4185 */
4186 // Template#: 245, Serial#: 245
4187 public void fbe(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4188 int instruction = 0x13400000;
4189 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4190 instruction |= ((a.value() & 0x1) << 29);
4191 instruction |= ((p.value() & 0x1) << 19);
4192 instruction |= ((n.value() & 0x3) << 20);
4193 instruction |= ((label >> 2) & 0x7ffff);
4194 emitInt(instruction);
4195 }
4196
4197 /**
4198 * Pseudo-external assembler syntax: {@code fbue{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4199 * Example disassembly syntax: {@code fbue,pn %fcc0, L1: -1048576}
4200 * <p>
4201 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4202 *
4203 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4204 */
4205 // Template#: 246, Serial#: 246
4206 public void fbue(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4207 int instruction = 0x15400000;
4208 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4209 instruction |= ((a.value() & 0x1) << 29);
4210 instruction |= ((p.value() & 0x1) << 19);
4211 instruction |= ((n.value() & 0x3) << 20);
4212 instruction |= ((label >> 2) & 0x7ffff);
4213 emitInt(instruction);
4214 }
4215
4216 /**
4217 * Pseudo-external assembler syntax: {@code fbge{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4218 * Example disassembly syntax: {@code fbge,pn %fcc0, L1: -1048576}
4219 * <p>
4220 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4221 *
4222 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4223 */
4224 // Template#: 247, Serial#: 247
4225 public void fbge(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4226 int instruction = 0x17400000;
4227 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4228 instruction |= ((a.value() & 0x1) << 29);
4229 instruction |= ((p.value() & 0x1) << 19);
4230 instruction |= ((n.value() & 0x3) << 20);
4231 instruction |= ((label >> 2) & 0x7ffff);
4232 emitInt(instruction);
4233 }
4234
4235 /**
4236 * Pseudo-external assembler syntax: {@code fbuge{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4237 * Example disassembly syntax: {@code fbuge,pn %fcc0, L1: -1048576}
4238 * <p>
4239 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4240 *
4241 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4242 */
4243 // Template#: 248, Serial#: 248
4244 public void fbuge(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4245 int instruction = 0x19400000;
4246 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4247 instruction |= ((a.value() & 0x1) << 29);
4248 instruction |= ((p.value() & 0x1) << 19);
4249 instruction |= ((n.value() & 0x3) << 20);
4250 instruction |= ((label >> 2) & 0x7ffff);
4251 emitInt(instruction);
4252 }
4253
4254 /**
4255 * Pseudo-external assembler syntax: {@code fble{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4256 * Example disassembly syntax: {@code fble,pn %fcc0, L1: -1048576}
4257 * <p>
4258 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4259 *
4260 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4261 */
4262 // Template#: 249, Serial#: 249
4263 public void fble(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4264 int instruction = 0x1B400000;
4265 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4266 instruction |= ((a.value() & 0x1) << 29);
4267 instruction |= ((p.value() & 0x1) << 19);
4268 instruction |= ((n.value() & 0x3) << 20);
4269 instruction |= ((label >> 2) & 0x7ffff);
4270 emitInt(instruction);
4271 }
4272
4273 /**
4274 * Pseudo-external assembler syntax: {@code fbule{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4275 * Example disassembly syntax: {@code fbule,pn %fcc0, L1: -1048576}
4276 * <p>
4277 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4278 *
4279 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4280 */
4281 // Template#: 250, Serial#: 250
4282 public void fbule(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4283 int instruction = 0x1D400000;
4284 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4285 instruction |= ((a.value() & 0x1) << 29);
4286 instruction |= ((p.value() & 0x1) << 19);
4287 instruction |= ((n.value() & 0x3) << 20);
4288 instruction |= ((label >> 2) & 0x7ffff);
4289 emitInt(instruction);
4290 }
4291
4292 /**
4293 * Pseudo-external assembler syntax: {@code fbo{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4294 * Example disassembly syntax: {@code fbo,pn %fcc0, L1: -1048576}
4295 * <p>
4296 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4297 *
4298 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4299 */
4300 // Template#: 251, Serial#: 251
4301 public void fbo(final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4302 int instruction = 0x1F400000;
4303 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4304 instruction |= ((a.value() & 0x1) << 29);
4305 instruction |= ((p.value() & 0x1) << 19);
4306 instruction |= ((n.value() & 0x3) << 20);
4307 instruction |= ((label >> 2) & 0x7ffff);
4308 emitInt(instruction);
4309 }
4310
4311 /**
4312 * Pseudo-external assembler syntax: {@code fba }<i>n</i>, <i>label</i>
4313 * Example disassembly syntax: {@code fba %fcc0, L1: -1048576}
4314 * <p>
4315 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4316 *
4317 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4318 */
4319 // Template#: 252, Serial#: 252
4320 public void fba(final FCCOperand n, final int label) {
4321 int instruction = 0x11480000;
4322 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4323 instruction |= ((n.value() & 0x3) << 20);
4324 instruction |= ((label >> 2) & 0x7ffff);
4325 emitInt(instruction);
4326 }
4327
4328 /**
4329 * Pseudo-external assembler syntax: {@code fbn }<i>n</i>, <i>label</i>
4330 * Example disassembly syntax: {@code fbn %fcc0, L1: -1048576}
4331 * <p>
4332 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4333 *
4334 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4335 */
4336 // Template#: 253, Serial#: 253
4337 public void fbn(final FCCOperand n, final int label) {
4338 int instruction = 0x01480000;
4339 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4340 instruction |= ((n.value() & 0x3) << 20);
4341 instruction |= ((label >> 2) & 0x7ffff);
4342 emitInt(instruction);
4343 }
4344
4345 /**
4346 * Pseudo-external assembler syntax: {@code fbu }<i>n</i>, <i>label</i>
4347 * Example disassembly syntax: {@code fbu %fcc0, L1: -1048576}
4348 * <p>
4349 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4350 *
4351 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4352 */
4353 // Template#: 254, Serial#: 254
4354 public void fbu(final FCCOperand n, final int label) {
4355 int instruction = 0x0F480000;
4356 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4357 instruction |= ((n.value() & 0x3) << 20);
4358 instruction |= ((label >> 2) & 0x7ffff);
4359 emitInt(instruction);
4360 }
4361
4362 /**
4363 * Pseudo-external assembler syntax: {@code fbg }<i>n</i>, <i>label</i>
4364 * Example disassembly syntax: {@code fbg %fcc0, L1: -1048576}
4365 * <p>
4366 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4367 *
4368 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4369 */
4370 // Template#: 255, Serial#: 255
4371 public void fbg(final FCCOperand n, final int label) {
4372 int instruction = 0x0D480000;
4373 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4374 instruction |= ((n.value() & 0x3) << 20);
4375 instruction |= ((label >> 2) & 0x7ffff);
4376 emitInt(instruction);
4377 }
4378
4379 /**
4380 * Pseudo-external assembler syntax: {@code fbug }<i>n</i>, <i>label</i>
4381 * Example disassembly syntax: {@code fbug %fcc0, L1: -1048576}
4382 * <p>
4383 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4384 *
4385 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4386 */
4387 // Template#: 256, Serial#: 256
4388 public void fbug(final FCCOperand n, final int label) {
4389 int instruction = 0x0B480000;
4390 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4391 instruction |= ((n.value() & 0x3) << 20);
4392 instruction |= ((label >> 2) & 0x7ffff);
4393 emitInt(instruction);
4394 }
4395
4396 /**
4397 * Pseudo-external assembler syntax: {@code fbl }<i>n</i>, <i>label</i>
4398 * Example disassembly syntax: {@code fbl %fcc0, L1: -1048576}
4399 * <p>
4400 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4401 *
4402 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4403 */
4404 // Template#: 257, Serial#: 257
4405 public void fbl(final FCCOperand n, final int label) {
4406 int instruction = 0x09480000;
4407 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4408 instruction |= ((n.value() & 0x3) << 20);
4409 instruction |= ((label >> 2) & 0x7ffff);
4410 emitInt(instruction);
4411 }
4412
4413 /**
4414 * Pseudo-external assembler syntax: {@code fbul }<i>n</i>, <i>label</i>
4415 * Example disassembly syntax: {@code fbul %fcc0, L1: -1048576}
4416 * <p>
4417 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4418 *
4419 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4420 */
4421 // Template#: 258, Serial#: 258
4422 public void fbul(final FCCOperand n, final int label) {
4423 int instruction = 0x07480000;
4424 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4425 instruction |= ((n.value() & 0x3) << 20);
4426 instruction |= ((label >> 2) & 0x7ffff);
4427 emitInt(instruction);
4428 }
4429
4430 /**
4431 * Pseudo-external assembler syntax: {@code fblg }<i>n</i>, <i>label</i>
4432 * Example disassembly syntax: {@code fblg %fcc0, L1: -1048576}
4433 * <p>
4434 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4435 *
4436 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4437 */
4438 // Template#: 259, Serial#: 259
4439 public void fblg(final FCCOperand n, final int label) {
4440 int instruction = 0x05480000;
4441 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4442 instruction |= ((n.value() & 0x3) << 20);
4443 instruction |= ((label >> 2) & 0x7ffff);
4444 emitInt(instruction);
4445 }
4446
4447 /**
4448 * Pseudo-external assembler syntax: {@code fbne }<i>n</i>, <i>label</i>
4449 * Example disassembly syntax: {@code fbne %fcc0, L1: -1048576}
4450 * <p>
4451 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4452 *
4453 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4454 */
4455 // Template#: 260, Serial#: 260
4456 public void fbne(final FCCOperand n, final int label) {
4457 int instruction = 0x03480000;
4458 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4459 instruction |= ((n.value() & 0x3) << 20);
4460 instruction |= ((label >> 2) & 0x7ffff);
4461 emitInt(instruction);
4462 }
4463
4464 /**
4465 * Pseudo-external assembler syntax: {@code fbe }<i>n</i>, <i>label</i>
4466 * Example disassembly syntax: {@code fbe %fcc0, L1: -1048576}
4467 * <p>
4468 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4469 *
4470 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4471 */
4472 // Template#: 261, Serial#: 261
4473 public void fbe(final FCCOperand n, final int label) {
4474 int instruction = 0x13480000;
4475 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4476 instruction |= ((n.value() & 0x3) << 20);
4477 instruction |= ((label >> 2) & 0x7ffff);
4478 emitInt(instruction);
4479 }
4480
4481 /**
4482 * Pseudo-external assembler syntax: {@code fbue }<i>n</i>, <i>label</i>
4483 * Example disassembly syntax: {@code fbue %fcc0, L1: -1048576}
4484 * <p>
4485 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4486 *
4487 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4488 */
4489 // Template#: 262, Serial#: 262
4490 public void fbue(final FCCOperand n, final int label) {
4491 int instruction = 0x15480000;
4492 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4493 instruction |= ((n.value() & 0x3) << 20);
4494 instruction |= ((label >> 2) & 0x7ffff);
4495 emitInt(instruction);
4496 }
4497
4498 /**
4499 * Pseudo-external assembler syntax: {@code fbge }<i>n</i>, <i>label</i>
4500 * Example disassembly syntax: {@code fbge %fcc0, L1: -1048576}
4501 * <p>
4502 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4503 *
4504 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4505 */
4506 // Template#: 263, Serial#: 263
4507 public void fbge(final FCCOperand n, final int label) {
4508 int instruction = 0x17480000;
4509 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4510 instruction |= ((n.value() & 0x3) << 20);
4511 instruction |= ((label >> 2) & 0x7ffff);
4512 emitInt(instruction);
4513 }
4514
4515 /**
4516 * Pseudo-external assembler syntax: {@code fbuge }<i>n</i>, <i>label</i>
4517 * Example disassembly syntax: {@code fbuge %fcc0, L1: -1048576}
4518 * <p>
4519 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4520 *
4521 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4522 */
4523 // Template#: 264, Serial#: 264
4524 public void fbuge(final FCCOperand n, final int label) {
4525 int instruction = 0x19480000;
4526 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4527 instruction |= ((n.value() & 0x3) << 20);
4528 instruction |= ((label >> 2) & 0x7ffff);
4529 emitInt(instruction);
4530 }
4531
4532 /**
4533 * Pseudo-external assembler syntax: {@code fble }<i>n</i>, <i>label</i>
4534 * Example disassembly syntax: {@code fble %fcc0, L1: -1048576}
4535 * <p>
4536 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4537 *
4538 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4539 */
4540 // Template#: 265, Serial#: 265
4541 public void fble(final FCCOperand n, final int label) {
4542 int instruction = 0x1B480000;
4543 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4544 instruction |= ((n.value() & 0x3) << 20);
4545 instruction |= ((label >> 2) & 0x7ffff);
4546 emitInt(instruction);
4547 }
4548
4549 /**
4550 * Pseudo-external assembler syntax: {@code fbule }<i>n</i>, <i>label</i>
4551 * Example disassembly syntax: {@code fbule %fcc0, L1: -1048576}
4552 * <p>
4553 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4554 *
4555 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4556 */
4557 // Template#: 266, Serial#: 266
4558 public void fbule(final FCCOperand n, final int label) {
4559 int instruction = 0x1D480000;
4560 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4561 instruction |= ((n.value() & 0x3) << 20);
4562 instruction |= ((label >> 2) & 0x7ffff);
4563 emitInt(instruction);
4564 }
4565
4566 /**
4567 * Pseudo-external assembler syntax: {@code fbo }<i>n</i>, <i>label</i>
4568 * Example disassembly syntax: {@code fbo %fcc0, L1: -1048576}
4569 * <p>
4570 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4571 *
4572 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4573 */
4574 // Template#: 267, Serial#: 267
4575 public void fbo(final FCCOperand n, final int label) {
4576 int instruction = 0x1F480000;
4577 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4578 instruction |= ((n.value() & 0x3) << 20);
4579 instruction |= ((label >> 2) & 0x7ffff);
4580 emitInt(instruction);
4581 }
4582
4583 /**
4584 * Pseudo-external assembler syntax: {@code fb[a|n|u|g|ug|l|ul|lg|ne|e|ue|ge|uge|le|ule|o]{,a}{,pn|,pt} }<i>n</i>, <i>label</i>
4585 * Example disassembly syntax: {@code fba,pn %fcc0, L1: -1048576}
4586 * <p>
4587 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
4588 *
4589 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.5"
4590 */
4591 // Template#: 268, Serial#: 268
4592 public void fb(final FBfcc cond, final AnnulBit a, final BranchPredictionBit p, final FCCOperand n, final int label) {
4593 int instruction = 0x01400000;
4594 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
4595 instruction |= ((cond.value() & 0xf) << 25);
4596 instruction |= ((a.value() & 0x1) << 29);
4597 instruction |= ((p.value() & 0x1) << 19);
4598 instruction |= ((n.value() & 0x3) << 20);
4599 instruction |= ((label >> 2) & 0x7ffff);
4600 emitInt(instruction);
4601 }
4602
4603 /**
4604 * Pseudo-external assembler syntax: {@code ba{,a} }<i>label</i>
4605 * Example disassembly syntax: {@code ba L1: -8388608}
4606 * <p>
4607 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4608 *
4609 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4610 */
4611 // Template#: 269, Serial#: 269
4612 public void ba(final AnnulBit a, final int label) {
4613 int instruction = 0x10800000;
4614 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4615 instruction |= ((a.value() & 0x1) << 29);
4616 instruction |= ((label >> 2) & 0x3fffff);
4617 emitInt(instruction);
4618 }
4619
4620 /**
4621 * Pseudo-external assembler syntax: {@code bn{,a} }<i>label</i>
4622 * Example disassembly syntax: {@code bn L1: -8388608}
4623 * <p>
4624 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4625 *
4626 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4627 */
4628 // Template#: 270, Serial#: 270
4629 public void bn(final AnnulBit a, final int label) {
4630 int instruction = 0x00800000;
4631 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4632 instruction |= ((a.value() & 0x1) << 29);
4633 instruction |= ((label >> 2) & 0x3fffff);
4634 emitInt(instruction);
4635 }
4636
4637 /**
4638 * Pseudo-external assembler syntax: {@code bne{,a} }<i>label</i>
4639 * Example disassembly syntax: {@code bne L1: -8388608}
4640 * <p>
4641 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4642 *
4643 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4644 */
4645 // Template#: 271, Serial#: 271
4646 public void bne(final AnnulBit a, final int label) {
4647 int instruction = 0x12800000;
4648 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4649 instruction |= ((a.value() & 0x1) << 29);
4650 instruction |= ((label >> 2) & 0x3fffff);
4651 emitInt(instruction);
4652 }
4653
4654 /**
4655 * Pseudo-external assembler syntax: {@code be{,a} }<i>label</i>
4656 * Example disassembly syntax: {@code be L1: -8388608}
4657 * <p>
4658 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4659 *
4660 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4661 */
4662 // Template#: 272, Serial#: 272
4663 public void be(final AnnulBit a, final int label) {
4664 int instruction = 0x02800000;
4665 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4666 instruction |= ((a.value() & 0x1) << 29);
4667 instruction |= ((label >> 2) & 0x3fffff);
4668 emitInt(instruction);
4669 }
4670
4671 /**
4672 * Pseudo-external assembler syntax: {@code bg{,a} }<i>label</i>
4673 * Example disassembly syntax: {@code bg L1: -8388608}
4674 * <p>
4675 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4676 *
4677 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4678 */
4679 // Template#: 273, Serial#: 273
4680 public void bg(final AnnulBit a, final int label) {
4681 int instruction = 0x14800000;
4682 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4683 instruction |= ((a.value() & 0x1) << 29);
4684 instruction |= ((label >> 2) & 0x3fffff);
4685 emitInt(instruction);
4686 }
4687
4688 /**
4689 * Pseudo-external assembler syntax: {@code ble{,a} }<i>label</i>
4690 * Example disassembly syntax: {@code ble L1: -8388608}
4691 * <p>
4692 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4693 *
4694 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4695 */
4696 // Template#: 274, Serial#: 274
4697 public void ble(final AnnulBit a, final int label) {
4698 int instruction = 0x04800000;
4699 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4700 instruction |= ((a.value() & 0x1) << 29);
4701 instruction |= ((label >> 2) & 0x3fffff);
4702 emitInt(instruction);
4703 }
4704
4705 /**
4706 * Pseudo-external assembler syntax: {@code bge{,a} }<i>label</i>
4707 * Example disassembly syntax: {@code bge L1: -8388608}
4708 * <p>
4709 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4710 *
4711 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4712 */
4713 // Template#: 275, Serial#: 275
4714 public void bge(final AnnulBit a, final int label) {
4715 int instruction = 0x16800000;
4716 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4717 instruction |= ((a.value() & 0x1) << 29);
4718 instruction |= ((label >> 2) & 0x3fffff);
4719 emitInt(instruction);
4720 }
4721
4722 /**
4723 * Pseudo-external assembler syntax: {@code bl{,a} }<i>label</i>
4724 * Example disassembly syntax: {@code bl L1: -8388608}
4725 * <p>
4726 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4727 *
4728 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4729 */
4730 // Template#: 276, Serial#: 276
4731 public void bl(final AnnulBit a, final int label) {
4732 int instruction = 0x06800000;
4733 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4734 instruction |= ((a.value() & 0x1) << 29);
4735 instruction |= ((label >> 2) & 0x3fffff);
4736 emitInt(instruction);
4737 }
4738
4739 /**
4740 * Pseudo-external assembler syntax: {@code bgu{,a} }<i>label</i>
4741 * Example disassembly syntax: {@code bgu L1: -8388608}
4742 * <p>
4743 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4744 *
4745 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4746 */
4747 // Template#: 277, Serial#: 277
4748 public void bgu(final AnnulBit a, final int label) {
4749 int instruction = 0x18800000;
4750 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4751 instruction |= ((a.value() & 0x1) << 29);
4752 instruction |= ((label >> 2) & 0x3fffff);
4753 emitInt(instruction);
4754 }
4755
4756 /**
4757 * Pseudo-external assembler syntax: {@code bleu{,a} }<i>label</i>
4758 * Example disassembly syntax: {@code bleu L1: -8388608}
4759 * <p>
4760 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4761 *
4762 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4763 */
4764 // Template#: 278, Serial#: 278
4765 public void bleu(final AnnulBit a, final int label) {
4766 int instruction = 0x08800000;
4767 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4768 instruction |= ((a.value() & 0x1) << 29);
4769 instruction |= ((label >> 2) & 0x3fffff);
4770 emitInt(instruction);
4771 }
4772
4773 /**
4774 * Pseudo-external assembler syntax: {@code bcc{,a} }<i>label</i>
4775 * Example disassembly syntax: {@code bcc L1: -8388608}
4776 * <p>
4777 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4778 *
4779 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4780 */
4781 // Template#: 279, Serial#: 279
4782 public void bcc(final AnnulBit a, final int label) {
4783 int instruction = 0x1A800000;
4784 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4785 instruction |= ((a.value() & 0x1) << 29);
4786 instruction |= ((label >> 2) & 0x3fffff);
4787 emitInt(instruction);
4788 }
4789
4790 /**
4791 * Pseudo-external assembler syntax: {@code bcs{,a} }<i>label</i>
4792 * Example disassembly syntax: {@code bcs L1: -8388608}
4793 * <p>
4794 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4795 *
4796 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4797 */
4798 // Template#: 280, Serial#: 280
4799 public void bcs(final AnnulBit a, final int label) {
4800 int instruction = 0x0A800000;
4801 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4802 instruction |= ((a.value() & 0x1) << 29);
4803 instruction |= ((label >> 2) & 0x3fffff);
4804 emitInt(instruction);
4805 }
4806
4807 /**
4808 * Pseudo-external assembler syntax: {@code bpos{,a} }<i>label</i>
4809 * Example disassembly syntax: {@code bpos L1: -8388608}
4810 * <p>
4811 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4812 *
4813 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4814 */
4815 // Template#: 281, Serial#: 281
4816 public void bpos(final AnnulBit a, final int label) {
4817 int instruction = 0x1C800000;
4818 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4819 instruction |= ((a.value() & 0x1) << 29);
4820 instruction |= ((label >> 2) & 0x3fffff);
4821 emitInt(instruction);
4822 }
4823
4824 /**
4825 * Pseudo-external assembler syntax: {@code bneg{,a} }<i>label</i>
4826 * Example disassembly syntax: {@code bneg L1: -8388608}
4827 * <p>
4828 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4829 *
4830 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4831 */
4832 // Template#: 282, Serial#: 282
4833 public void bneg(final AnnulBit a, final int label) {
4834 int instruction = 0x0C800000;
4835 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4836 instruction |= ((a.value() & 0x1) << 29);
4837 instruction |= ((label >> 2) & 0x3fffff);
4838 emitInt(instruction);
4839 }
4840
4841 /**
4842 * Pseudo-external assembler syntax: {@code bvc{,a} }<i>label</i>
4843 * Example disassembly syntax: {@code bvc L1: -8388608}
4844 * <p>
4845 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4846 *
4847 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4848 */
4849 // Template#: 283, Serial#: 283
4850 public void bvc(final AnnulBit a, final int label) {
4851 int instruction = 0x1E800000;
4852 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4853 instruction |= ((a.value() & 0x1) << 29);
4854 instruction |= ((label >> 2) & 0x3fffff);
4855 emitInt(instruction);
4856 }
4857
4858 /**
4859 * Pseudo-external assembler syntax: {@code bvs{,a} }<i>label</i>
4860 * Example disassembly syntax: {@code bvs L1: -8388608}
4861 * <p>
4862 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4863 *
4864 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4865 */
4866 // Template#: 284, Serial#: 284
4867 public void bvs(final AnnulBit a, final int label) {
4868 int instruction = 0x0E800000;
4869 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4870 instruction |= ((a.value() & 0x1) << 29);
4871 instruction |= ((label >> 2) & 0x3fffff);
4872 emitInt(instruction);
4873 }
4874
4875 /**
4876 * Pseudo-external assembler syntax: {@code ba }<i>label</i>
4877 * Example disassembly syntax: {@code ba L1: -8388608}
4878 * <p>
4879 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4880 *
4881 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4882 */
4883 // Template#: 285, Serial#: 285
4884 public void ba(final int label) {
4885 int instruction = 0x10800000;
4886 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4887 instruction |= ((label >> 2) & 0x3fffff);
4888 emitInt(instruction);
4889 }
4890
4891 /**
4892 * Pseudo-external assembler syntax: {@code bn }<i>label</i>
4893 * Example disassembly syntax: {@code bn L1: -8388608}
4894 * <p>
4895 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4896 *
4897 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4898 */
4899 // Template#: 286, Serial#: 286
4900 public void bn(final int label) {
4901 int instruction = 0x00800000;
4902 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4903 instruction |= ((label >> 2) & 0x3fffff);
4904 emitInt(instruction);
4905 }
4906
4907 /**
4908 * Pseudo-external assembler syntax: {@code bne }<i>label</i>
4909 * Example disassembly syntax: {@code bne L1: -8388608}
4910 * <p>
4911 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4912 *
4913 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4914 */
4915 // Template#: 287, Serial#: 287
4916 public void bne(final int label) {
4917 int instruction = 0x12800000;
4918 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4919 instruction |= ((label >> 2) & 0x3fffff);
4920 emitInt(instruction);
4921 }
4922
4923 /**
4924 * Pseudo-external assembler syntax: {@code be }<i>label</i>
4925 * Example disassembly syntax: {@code be L1: -8388608}
4926 * <p>
4927 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4928 *
4929 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4930 */
4931 // Template#: 288, Serial#: 288
4932 public void be(final int label) {
4933 int instruction = 0x02800000;
4934 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4935 instruction |= ((label >> 2) & 0x3fffff);
4936 emitInt(instruction);
4937 }
4938
4939 /**
4940 * Pseudo-external assembler syntax: {@code bg }<i>label</i>
4941 * Example disassembly syntax: {@code bg L1: -8388608}
4942 * <p>
4943 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4944 *
4945 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4946 */
4947 // Template#: 289, Serial#: 289
4948 public void bg(final int label) {
4949 int instruction = 0x14800000;
4950 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4951 instruction |= ((label >> 2) & 0x3fffff);
4952 emitInt(instruction);
4953 }
4954
4955 /**
4956 * Pseudo-external assembler syntax: {@code ble }<i>label</i>
4957 * Example disassembly syntax: {@code ble L1: -8388608}
4958 * <p>
4959 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4960 *
4961 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4962 */
4963 // Template#: 290, Serial#: 290
4964 public void ble(final int label) {
4965 int instruction = 0x04800000;
4966 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4967 instruction |= ((label >> 2) & 0x3fffff);
4968 emitInt(instruction);
4969 }
4970
4971 /**
4972 * Pseudo-external assembler syntax: {@code bge }<i>label</i>
4973 * Example disassembly syntax: {@code bge L1: -8388608}
4974 * <p>
4975 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4976 *
4977 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4978 */
4979 // Template#: 291, Serial#: 291
4980 public void bge(final int label) {
4981 int instruction = 0x16800000;
4982 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4983 instruction |= ((label >> 2) & 0x3fffff);
4984 emitInt(instruction);
4985 }
4986
4987 /**
4988 * Pseudo-external assembler syntax: {@code bl }<i>label</i>
4989 * Example disassembly syntax: {@code bl L1: -8388608}
4990 * <p>
4991 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
4992 *
4993 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
4994 */
4995 // Template#: 292, Serial#: 292
4996 public void bl(final int label) {
4997 int instruction = 0x06800000;
4998 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
4999 instruction |= ((label >> 2) & 0x3fffff);
5000 emitInt(instruction);
5001 }
5002
5003 /**
5004 * Pseudo-external assembler syntax: {@code bgu }<i>label</i>
5005 * Example disassembly syntax: {@code bgu L1: -8388608}
5006 * <p>
5007 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
5008 *
5009 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
5010 */
5011 // Template#: 293, Serial#: 293
5012 public void bgu(final int label) {
5013 int instruction = 0x18800000;
5014 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
5015 instruction |= ((label >> 2) & 0x3fffff);
5016 emitInt(instruction);
5017 }
5018
5019 /**
5020 * Pseudo-external assembler syntax: {@code bleu }<i>label</i>
5021 * Example disassembly syntax: {@code bleu L1: -8388608}
5022 * <p>
5023 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
5024 *
5025 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
5026 */
5027 // Template#: 294, Serial#: 294
5028 public void bleu(final int label) {
5029 int instruction = 0x08800000;
5030 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
5031 instruction |= ((label >> 2) & 0x3fffff);
5032 emitInt(instruction);
5033 }
5034
5035 /**
5036 * Pseudo-external assembler syntax: {@code bcc }<i>label</i>
5037 * Example disassembly syntax: {@code bcc L1: -8388608}
5038 * <p>
5039 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
5040 *
5041 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
5042 */
5043 // Template#: 295, Serial#: 295
5044 public void bcc(final int label) {
5045 int instruction = 0x1A800000;
5046 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
5047 instruction |= ((label >> 2) & 0x3fffff);
5048 emitInt(instruction);
5049 }
5050
5051 /**
5052 * Pseudo-external assembler syntax: {@code bcs }<i>label</i>
5053 * Example disassembly syntax: {@code bcs L1: -8388608}
5054 * <p>
5055 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
5056 *
5057 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
5058 */
5059 // Template#: 296, Serial#: 296
5060 public void bcs(final int label) {
5061 int instruction = 0x0A800000;
5062 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
5063 instruction |= ((label >> 2) & 0x3fffff);
5064 emitInt(instruction);
5065 }
5066
5067 /**
5068 * Pseudo-external assembler syntax: {@code bpos }<i>label</i>
5069 * Example disassembly syntax: {@code bpos L1: -8388608}
5070 * <p>
5071 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
5072 *
5073 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
5074 */
5075 // Template#: 297, Serial#: 297
5076 public void bpos(final int label) {
5077 int instruction = 0x1C800000;
5078 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
5079 instruction |= ((label >> 2) & 0x3fffff);
5080 emitInt(instruction);
5081 }
5082
5083 /**
5084 * Pseudo-external assembler syntax: {@code bneg }<i>label</i>
5085 * Example disassembly syntax: {@code bneg L1: -8388608}
5086 * <p>
5087 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
5088 *
5089 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
5090 */
5091 // Template#: 298, Serial#: 298
5092 public void bneg(final int label) {
5093 int instruction = 0x0C800000;
5094 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
5095 instruction |= ((label >> 2) & 0x3fffff);
5096 emitInt(instruction);
5097 }
5098
5099 /**
5100 * Pseudo-external assembler syntax: {@code bvc }<i>label</i>
5101 * Example disassembly syntax: {@code bvc L1: -8388608}
5102 * <p>
5103 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
5104 *
5105 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
5106 */
5107 // Template#: 299, Serial#: 299
5108 public void bvc(final int label) {
5109 int instruction = 0x1E800000;
5110 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
5111 instruction |= ((label >> 2) & 0x3fffff);
5112 emitInt(instruction);
5113 }
5114
5115 /**
5116 * Pseudo-external assembler syntax: {@code bvs }<i>label</i>
5117 * Example disassembly syntax: {@code bvs L1: -8388608}
5118 * <p>
5119 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
5120 *
5121 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
5122 */
5123 // Template#: 300, Serial#: 300
5124 public void bvs(final int label) {
5125 int instruction = 0x0E800000;
5126 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
5127 instruction |= ((label >> 2) & 0x3fffff);
5128 emitInt(instruction);
5129 }
5130
5131 /**
5132 * Pseudo-external assembler syntax: {@code b[a|n|ne|e|g|le|ge|l|gu|leu|cc|cs|pos|neg|vc|vs]{,a} }<i>label</i>
5133 * Example disassembly syntax: {@code ba L1: -8388608}
5134 * <p>
5135 * Constraint: {@code (-8388608 <= label && label <= 8388604) && ((label % 4) == 0)}<br />
5136 *
5137 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.6"
5138 */
5139 // Template#: 301, Serial#: 301
5140 public void b(final Bicc cond, final AnnulBit a, final int label) {
5141 int instruction = 0x00800000;
5142 checkConstraint((-8388608 <= label && label <= 8388604) && ((label % 4) == 0), "(-8388608 <= label && label <= 8388604) && ((label % 4) == 0)");
5143 instruction |= ((cond.value() & 0xf) << 25);
5144 instruction |= ((a.value() & 0x1) << 29);
5145 instruction |= ((label >> 2) & 0x3fffff);
5146 emitInt(instruction);
5147 }
5148
5149 /**
5150 * Pseudo-external assembler syntax: {@code ba{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5151 * Example disassembly syntax: {@code ba,pn %icc, L1: -1048576}
5152 * <p>
5153 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5154 *
5155 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5156 */
5157 // Template#: 302, Serial#: 302
5158 public void ba(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5159 int instruction = 0x10400000;
5160 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5161 instruction |= ((a.value() & 0x1) << 29);
5162 instruction |= ((p.value() & 0x1) << 19);
5163 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5164 instruction |= ((label >> 2) & 0x7ffff);
5165 emitInt(instruction);
5166 }
5167
5168 /**
5169 * Pseudo-external assembler syntax: {@code bn{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5170 * Example disassembly syntax: {@code bn,pn %icc, L1: -1048576}
5171 * <p>
5172 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5173 *
5174 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5175 */
5176 // Template#: 303, Serial#: 303
5177 public void bn(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5178 int instruction = 0x00400000;
5179 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5180 instruction |= ((a.value() & 0x1) << 29);
5181 instruction |= ((p.value() & 0x1) << 19);
5182 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5183 instruction |= ((label >> 2) & 0x7ffff);
5184 emitInt(instruction);
5185 }
5186
5187 /**
5188 * Pseudo-external assembler syntax: {@code bne{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5189 * Example disassembly syntax: {@code bne,pn %icc, L1: -1048576}
5190 * <p>
5191 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5192 *
5193 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5194 */
5195 // Template#: 304, Serial#: 304
5196 public void bne(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5197 int instruction = 0x12400000;
5198 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5199 instruction |= ((a.value() & 0x1) << 29);
5200 instruction |= ((p.value() & 0x1) << 19);
5201 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5202 instruction |= ((label >> 2) & 0x7ffff);
5203 emitInt(instruction);
5204 }
5205
5206 /**
5207 * Pseudo-external assembler syntax: {@code be{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5208 * Example disassembly syntax: {@code be,pn %icc, L1: -1048576}
5209 * <p>
5210 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5211 *
5212 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5213 */
5214 // Template#: 305, Serial#: 305
5215 public void be(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5216 int instruction = 0x02400000;
5217 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5218 instruction |= ((a.value() & 0x1) << 29);
5219 instruction |= ((p.value() & 0x1) << 19);
5220 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5221 instruction |= ((label >> 2) & 0x7ffff);
5222 emitInt(instruction);
5223 }
5224
5225 /**
5226 * Pseudo-external assembler syntax: {@code bg{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5227 * Example disassembly syntax: {@code bg,pn %icc, L1: -1048576}
5228 * <p>
5229 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5230 *
5231 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5232 */
5233 // Template#: 306, Serial#: 306
5234 public void bg(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5235 int instruction = 0x14400000;
5236 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5237 instruction |= ((a.value() & 0x1) << 29);
5238 instruction |= ((p.value() & 0x1) << 19);
5239 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5240 instruction |= ((label >> 2) & 0x7ffff);
5241 emitInt(instruction);
5242 }
5243
5244 /**
5245 * Pseudo-external assembler syntax: {@code ble{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5246 * Example disassembly syntax: {@code ble,pn %icc, L1: -1048576}
5247 * <p>
5248 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5249 *
5250 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5251 */
5252 // Template#: 307, Serial#: 307
5253 public void ble(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5254 int instruction = 0x04400000;
5255 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5256 instruction |= ((a.value() & 0x1) << 29);
5257 instruction |= ((p.value() & 0x1) << 19);
5258 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5259 instruction |= ((label >> 2) & 0x7ffff);
5260 emitInt(instruction);
5261 }
5262
5263 /**
5264 * Pseudo-external assembler syntax: {@code bge{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5265 * Example disassembly syntax: {@code bge,pn %icc, L1: -1048576}
5266 * <p>
5267 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5268 *
5269 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5270 */
5271 // Template#: 308, Serial#: 308
5272 public void bge(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5273 int instruction = 0x16400000;
5274 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5275 instruction |= ((a.value() & 0x1) << 29);
5276 instruction |= ((p.value() & 0x1) << 19);
5277 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5278 instruction |= ((label >> 2) & 0x7ffff);
5279 emitInt(instruction);
5280 }
5281
5282 /**
5283 * Pseudo-external assembler syntax: {@code bl{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5284 * Example disassembly syntax: {@code bl,pn %icc, L1: -1048576}
5285 * <p>
5286 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5287 *
5288 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5289 */
5290 // Template#: 309, Serial#: 309
5291 public void bl(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5292 int instruction = 0x06400000;
5293 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5294 instruction |= ((a.value() & 0x1) << 29);
5295 instruction |= ((p.value() & 0x1) << 19);
5296 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5297 instruction |= ((label >> 2) & 0x7ffff);
5298 emitInt(instruction);
5299 }
5300
5301 /**
5302 * Pseudo-external assembler syntax: {@code bgu{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5303 * Example disassembly syntax: {@code bgu,pn %icc, L1: -1048576}
5304 * <p>
5305 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5306 *
5307 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5308 */
5309 // Template#: 310, Serial#: 310
5310 public void bgu(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5311 int instruction = 0x18400000;
5312 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5313 instruction |= ((a.value() & 0x1) << 29);
5314 instruction |= ((p.value() & 0x1) << 19);
5315 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5316 instruction |= ((label >> 2) & 0x7ffff);
5317 emitInt(instruction);
5318 }
5319
5320 /**
5321 * Pseudo-external assembler syntax: {@code bleu{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5322 * Example disassembly syntax: {@code bleu,pn %icc, L1: -1048576}
5323 * <p>
5324 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5325 *
5326 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5327 */
5328 // Template#: 311, Serial#: 311
5329 public void bleu(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5330 int instruction = 0x08400000;
5331 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5332 instruction |= ((a.value() & 0x1) << 29);
5333 instruction |= ((p.value() & 0x1) << 19);
5334 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5335 instruction |= ((label >> 2) & 0x7ffff);
5336 emitInt(instruction);
5337 }
5338
5339 /**
5340 * Pseudo-external assembler syntax: {@code bcc{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5341 * Example disassembly syntax: {@code bcc,pn %icc, L1: -1048576}
5342 * <p>
5343 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5344 *
5345 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5346 */
5347 // Template#: 312, Serial#: 312
5348 public void bcc(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5349 int instruction = 0x1A400000;
5350 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5351 instruction |= ((a.value() & 0x1) << 29);
5352 instruction |= ((p.value() & 0x1) << 19);
5353 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5354 instruction |= ((label >> 2) & 0x7ffff);
5355 emitInt(instruction);
5356 }
5357
5358 /**
5359 * Pseudo-external assembler syntax: {@code bcs{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5360 * Example disassembly syntax: {@code bcs,pn %icc, L1: -1048576}
5361 * <p>
5362 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5363 *
5364 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5365 */
5366 // Template#: 313, Serial#: 313
5367 public void bcs(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5368 int instruction = 0x0A400000;
5369 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5370 instruction |= ((a.value() & 0x1) << 29);
5371 instruction |= ((p.value() & 0x1) << 19);
5372 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5373 instruction |= ((label >> 2) & 0x7ffff);
5374 emitInt(instruction);
5375 }
5376
5377 /**
5378 * Pseudo-external assembler syntax: {@code bpos{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5379 * Example disassembly syntax: {@code bpos,pn %icc, L1: -1048576}
5380 * <p>
5381 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5382 *
5383 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5384 */
5385 // Template#: 314, Serial#: 314
5386 public void bpos(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5387 int instruction = 0x1C400000;
5388 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5389 instruction |= ((a.value() & 0x1) << 29);
5390 instruction |= ((p.value() & 0x1) << 19);
5391 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5392 instruction |= ((label >> 2) & 0x7ffff);
5393 emitInt(instruction);
5394 }
5395
5396 /**
5397 * Pseudo-external assembler syntax: {@code bneg{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5398 * Example disassembly syntax: {@code bneg,pn %icc, L1: -1048576}
5399 * <p>
5400 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5401 *
5402 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5403 */
5404 // Template#: 315, Serial#: 315
5405 public void bneg(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5406 int instruction = 0x0C400000;
5407 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5408 instruction |= ((a.value() & 0x1) << 29);
5409 instruction |= ((p.value() & 0x1) << 19);
5410 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5411 instruction |= ((label >> 2) & 0x7ffff);
5412 emitInt(instruction);
5413 }
5414
5415 /**
5416 * Pseudo-external assembler syntax: {@code bvc{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5417 * Example disassembly syntax: {@code bvc,pn %icc, L1: -1048576}
5418 * <p>
5419 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5420 *
5421 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5422 */
5423 // Template#: 316, Serial#: 316
5424 public void bvc(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5425 int instruction = 0x1E400000;
5426 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5427 instruction |= ((a.value() & 0x1) << 29);
5428 instruction |= ((p.value() & 0x1) << 19);
5429 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5430 instruction |= ((label >> 2) & 0x7ffff);
5431 emitInt(instruction);
5432 }
5433
5434 /**
5435 * Pseudo-external assembler syntax: {@code bvs{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5436 * Example disassembly syntax: {@code bvs,pn %icc, L1: -1048576}
5437 * <p>
5438 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5439 *
5440 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5441 */
5442 // Template#: 317, Serial#: 317
5443 public void bvs(final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5444 int instruction = 0x0E400000;
5445 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5446 instruction |= ((a.value() & 0x1) << 29);
5447 instruction |= ((p.value() & 0x1) << 19);
5448 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5449 instruction |= ((label >> 2) & 0x7ffff);
5450 emitInt(instruction);
5451 }
5452
5453 /**
5454 * Pseudo-external assembler syntax: {@code ba }<i>i_or_x_cc</i>, <i>label</i>
5455 * Example disassembly syntax: {@code ba %icc, L1: -1048576}
5456 * <p>
5457 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5458 *
5459 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5460 */
5461 // Template#: 318, Serial#: 318
5462 public void ba(final ICCOperand i_or_x_cc, final int label) {
5463 int instruction = 0x10480000;
5464 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5465 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5466 instruction |= ((label >> 2) & 0x7ffff);
5467 emitInt(instruction);
5468 }
5469
5470 /**
5471 * Pseudo-external assembler syntax: {@code bn }<i>i_or_x_cc</i>, <i>label</i>
5472 * Example disassembly syntax: {@code bn %icc, L1: -1048576}
5473 * <p>
5474 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5475 *
5476 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5477 */
5478 // Template#: 319, Serial#: 319
5479 public void bn(final ICCOperand i_or_x_cc, final int label) {
5480 int instruction = 0x00480000;
5481 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5482 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5483 instruction |= ((label >> 2) & 0x7ffff);
5484 emitInt(instruction);
5485 }
5486
5487 /**
5488 * Pseudo-external assembler syntax: {@code bne }<i>i_or_x_cc</i>, <i>label</i>
5489 * Example disassembly syntax: {@code bne %icc, L1: -1048576}
5490 * <p>
5491 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5492 *
5493 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5494 */
5495 // Template#: 320, Serial#: 320
5496 public void bne(final ICCOperand i_or_x_cc, final int label) {
5497 int instruction = 0x12480000;
5498 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5499 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5500 instruction |= ((label >> 2) & 0x7ffff);
5501 emitInt(instruction);
5502 }
5503
5504 /**
5505 * Pseudo-external assembler syntax: {@code be }<i>i_or_x_cc</i>, <i>label</i>
5506 * Example disassembly syntax: {@code be %icc, L1: -1048576}
5507 * <p>
5508 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5509 *
5510 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5511 */
5512 // Template#: 321, Serial#: 321
5513 public void be(final ICCOperand i_or_x_cc, final int label) {
5514 int instruction = 0x02480000;
5515 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5516 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5517 instruction |= ((label >> 2) & 0x7ffff);
5518 emitInt(instruction);
5519 }
5520
5521 /**
5522 * Pseudo-external assembler syntax: {@code bg }<i>i_or_x_cc</i>, <i>label</i>
5523 * Example disassembly syntax: {@code bg %icc, L1: -1048576}
5524 * <p>
5525 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5526 *
5527 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5528 */
5529 // Template#: 322, Serial#: 322
5530 public void bg(final ICCOperand i_or_x_cc, final int label) {
5531 int instruction = 0x14480000;
5532 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5533 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5534 instruction |= ((label >> 2) & 0x7ffff);
5535 emitInt(instruction);
5536 }
5537
5538 /**
5539 * Pseudo-external assembler syntax: {@code ble }<i>i_or_x_cc</i>, <i>label</i>
5540 * Example disassembly syntax: {@code ble %icc, L1: -1048576}
5541 * <p>
5542 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5543 *
5544 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5545 */
5546 // Template#: 323, Serial#: 323
5547 public void ble(final ICCOperand i_or_x_cc, final int label) {
5548 int instruction = 0x04480000;
5549 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5550 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5551 instruction |= ((label >> 2) & 0x7ffff);
5552 emitInt(instruction);
5553 }
5554
5555 /**
5556 * Pseudo-external assembler syntax: {@code bge }<i>i_or_x_cc</i>, <i>label</i>
5557 * Example disassembly syntax: {@code bge %icc, L1: -1048576}
5558 * <p>
5559 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5560 *
5561 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5562 */
5563 // Template#: 324, Serial#: 324
5564 public void bge(final ICCOperand i_or_x_cc, final int label) {
5565 int instruction = 0x16480000;
5566 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5567 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5568 instruction |= ((label >> 2) & 0x7ffff);
5569 emitInt(instruction);
5570 }
5571
5572 /**
5573 * Pseudo-external assembler syntax: {@code bl }<i>i_or_x_cc</i>, <i>label</i>
5574 * Example disassembly syntax: {@code bl %icc, L1: -1048576}
5575 * <p>
5576 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5577 *
5578 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5579 */
5580 // Template#: 325, Serial#: 325
5581 public void bl(final ICCOperand i_or_x_cc, final int label) {
5582 int instruction = 0x06480000;
5583 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5584 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5585 instruction |= ((label >> 2) & 0x7ffff);
5586 emitInt(instruction);
5587 }
5588
5589 /**
5590 * Pseudo-external assembler syntax: {@code bgu }<i>i_or_x_cc</i>, <i>label</i>
5591 * Example disassembly syntax: {@code bgu %icc, L1: -1048576}
5592 * <p>
5593 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5594 *
5595 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5596 */
5597 // Template#: 326, Serial#: 326
5598 public void bgu(final ICCOperand i_or_x_cc, final int label) {
5599 int instruction = 0x18480000;
5600 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5601 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5602 instruction |= ((label >> 2) & 0x7ffff);
5603 emitInt(instruction);
5604 }
5605
5606 /**
5607 * Pseudo-external assembler syntax: {@code bleu }<i>i_or_x_cc</i>, <i>label</i>
5608 * Example disassembly syntax: {@code bleu %icc, L1: -1048576}
5609 * <p>
5610 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5611 *
5612 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5613 */
5614 // Template#: 327, Serial#: 327
5615 public void bleu(final ICCOperand i_or_x_cc, final int label) {
5616 int instruction = 0x08480000;
5617 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5618 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5619 instruction |= ((label >> 2) & 0x7ffff);
5620 emitInt(instruction);
5621 }
5622
5623 /**
5624 * Pseudo-external assembler syntax: {@code bcc }<i>i_or_x_cc</i>, <i>label</i>
5625 * Example disassembly syntax: {@code bcc %icc, L1: -1048576}
5626 * <p>
5627 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5628 *
5629 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5630 */
5631 // Template#: 328, Serial#: 328
5632 public void bcc(final ICCOperand i_or_x_cc, final int label) {
5633 int instruction = 0x1A480000;
5634 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5635 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5636 instruction |= ((label >> 2) & 0x7ffff);
5637 emitInt(instruction);
5638 }
5639
5640 /**
5641 * Pseudo-external assembler syntax: {@code bcs }<i>i_or_x_cc</i>, <i>label</i>
5642 * Example disassembly syntax: {@code bcs %icc, L1: -1048576}
5643 * <p>
5644 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5645 *
5646 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5647 */
5648 // Template#: 329, Serial#: 329
5649 public void bcs(final ICCOperand i_or_x_cc, final int label) {
5650 int instruction = 0x0A480000;
5651 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5652 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5653 instruction |= ((label >> 2) & 0x7ffff);
5654 emitInt(instruction);
5655 }
5656
5657 /**
5658 * Pseudo-external assembler syntax: {@code bpos }<i>i_or_x_cc</i>, <i>label</i>
5659 * Example disassembly syntax: {@code bpos %icc, L1: -1048576}
5660 * <p>
5661 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5662 *
5663 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5664 */
5665 // Template#: 330, Serial#: 330
5666 public void bpos(final ICCOperand i_or_x_cc, final int label) {
5667 int instruction = 0x1C480000;
5668 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5669 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5670 instruction |= ((label >> 2) & 0x7ffff);
5671 emitInt(instruction);
5672 }
5673
5674 /**
5675 * Pseudo-external assembler syntax: {@code bneg }<i>i_or_x_cc</i>, <i>label</i>
5676 * Example disassembly syntax: {@code bneg %icc, L1: -1048576}
5677 * <p>
5678 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5679 *
5680 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5681 */
5682 // Template#: 331, Serial#: 331
5683 public void bneg(final ICCOperand i_or_x_cc, final int label) {
5684 int instruction = 0x0C480000;
5685 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5686 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5687 instruction |= ((label >> 2) & 0x7ffff);
5688 emitInt(instruction);
5689 }
5690
5691 /**
5692 * Pseudo-external assembler syntax: {@code bvc }<i>i_or_x_cc</i>, <i>label</i>
5693 * Example disassembly syntax: {@code bvc %icc, L1: -1048576}
5694 * <p>
5695 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5696 *
5697 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5698 */
5699 // Template#: 332, Serial#: 332
5700 public void bvc(final ICCOperand i_or_x_cc, final int label) {
5701 int instruction = 0x1E480000;
5702 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5703 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5704 instruction |= ((label >> 2) & 0x7ffff);
5705 emitInt(instruction);
5706 }
5707
5708 /**
5709 * Pseudo-external assembler syntax: {@code bvs }<i>i_or_x_cc</i>, <i>label</i>
5710 * Example disassembly syntax: {@code bvs %icc, L1: -1048576}
5711 * <p>
5712 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5713 *
5714 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5715 */
5716 // Template#: 333, Serial#: 333
5717 public void bvs(final ICCOperand i_or_x_cc, final int label) {
5718 int instruction = 0x0E480000;
5719 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5720 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5721 instruction |= ((label >> 2) & 0x7ffff);
5722 emitInt(instruction);
5723 }
5724
5725 /**
5726 * Pseudo-external assembler syntax: {@code b[a|n|ne|e|g|le|ge|l|gu|leu|cc|cs|pos|neg|vc|vs]{,a}{,pn|,pt} }<i>i_or_x_cc</i>, <i>label</i>
5727 * Example disassembly syntax: {@code ba,pn %icc, L1: -1048576}
5728 * <p>
5729 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
5730 *
5731 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.7"
5732 */
5733 // Template#: 334, Serial#: 334
5734 public void b(final Bicc cond, final AnnulBit a, final BranchPredictionBit p, final ICCOperand i_or_x_cc, final int label) {
5735 int instruction = 0x00400000;
5736 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
5737 instruction |= ((cond.value() & 0xf) << 25);
5738 instruction |= ((a.value() & 0x1) << 29);
5739 instruction |= ((p.value() & 0x1) << 19);
5740 instruction |= ((i_or_x_cc.value() & 0x3) << 20);
5741 instruction |= ((label >> 2) & 0x7ffff);
5742 emitInt(instruction);
5743 }
5744
5745 /**
5746 * Pseudo-external assembler syntax: {@code call }<i>label</i>
5747 * Example disassembly syntax: {@code call L1: -2147483648}
5748 * <p>
5749 * Constraint: {@code (-2147483648 <= label && label <= 2147483644) && ((label % 4) == 0)}<br />
5750 *
5751 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.8"
5752 */
5753 // Template#: 335, Serial#: 335
5754 public void call(final int label) {
5755 int instruction = 0x40000000;
5756 checkConstraint((-2147483648 <= label && label <= 2147483644) && ((label % 4) == 0), "(-2147483648 <= label && label <= 2147483644) && ((label % 4) == 0)");
5757 instruction |= ((label >> 2) & 0x3fffffff);
5758 emitInt(instruction);
5759 }
5760
5761 /**
5762 * Pseudo-external assembler syntax: {@code done }
5763 * Example disassembly syntax: {@code done }
5764 *
5765 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.11"
5766 */
5767 // Template#: 336, Serial#: 336
5768 public void done() {
5769 int instruction = 0x81F00000;
5770 emitInt(instruction);
5771 }
5772
5773 /**
5774 * Pseudo-external assembler syntax: {@code retry }
5775 * Example disassembly syntax: {@code retry }
5776 *
5777 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.11"
5778 */
5779 // Template#: 337, Serial#: 337
5780 public void retry() {
5781 int instruction = 0x83F00000;
5782 emitInt(instruction);
5783 }
5784
5785 /**
5786 * Pseudo-external assembler syntax: {@code illtrap }<i>const22</i>
5787 * Example disassembly syntax: {@code illtrap 0x0}
5788 * <p>
5789 * Constraint: {@code 0 <= const22 && const22 <= 4194303}<br />
5790 *
5791 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.22"
5792 */
5793 // Template#: 338, Serial#: 338
5794 public void illtrap(final int const22) {
5795 int instruction = 0x00000000;
5796 checkConstraint(0 <= const22 && const22 <= 4194303, "0 <= const22 && const22 <= 4194303");
5797 instruction |= (const22 & 0x3fffff);
5798 emitInt(instruction);
5799 }
5800
5801 /**
5802 * Pseudo-external assembler syntax: {@code jmpl }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
5803 * Example disassembly syntax: {@code jmpl %g0 + %g0, %g0}
5804 *
5805 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.24"
5806 */
5807 // Template#: 339, Serial#: 339
5808 public void jmpl(final GPR rs1, final GPR rs2, final GPR rd) {
5809 int instruction = 0x81C00000;
5810 instruction |= ((rs1.value() & 0x1f) << 14);
5811 instruction |= (rs2.value() & 0x1f);
5812 instruction |= ((rd.value() & 0x1f) << 25);
5813 emitInt(instruction);
5814 }
5815
5816 /**
5817 * Pseudo-external assembler syntax: {@code jmpl }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
5818 * Example disassembly syntax: {@code jmpl %g0 + -4096, %g0}
5819 * <p>
5820 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
5821 *
5822 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.24"
5823 */
5824 // Template#: 340, Serial#: 340
5825 public void jmpl(final GPR rs1, final int simm13, final GPR rd) {
5826 int instruction = 0x81C02000;
5827 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
5828 instruction |= ((rs1.value() & 0x1f) << 14);
5829 instruction |= (simm13 & 0x1fff);
5830 instruction |= ((rd.value() & 0x1f) << 25);
5831 emitInt(instruction);
5832 }
5833
5834 /**
5835 * Pseudo-external assembler syntax: {@code return }<i>rs1</i>, <i>rs2</i>
5836 * Example disassembly syntax: {@code return %g0 + %g0}
5837 *
5838 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.45"
5839 */
5840 // Template#: 341, Serial#: 341
5841 public void return_(final GPR rs1, final GPR rs2) {
5842 int instruction = 0x81C80000;
5843 instruction |= ((rs1.value() & 0x1f) << 14);
5844 instruction |= (rs2.value() & 0x1f);
5845 emitInt(instruction);
5846 }
5847
5848 /**
5849 * Pseudo-external assembler syntax: {@code return }<i>rs1</i>, <i>simm13</i>
5850 * Example disassembly syntax: {@code return %g0 + -4096}
5851 * <p>
5852 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
5853 *
5854 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.45"
5855 */
5856 // Template#: 342, Serial#: 342
5857 public void return_(final GPR rs1, final int simm13) {
5858 int instruction = 0x81C82000;
5859 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
5860 instruction |= ((rs1.value() & 0x1f) << 14);
5861 instruction |= (simm13 & 0x1fff);
5862 emitInt(instruction);
5863 }
5864
5865 /**
5866 * Pseudo-external assembler syntax: {@code sir }<i>simm13</i>
5867 * Example disassembly syntax: {@code sir -4096}
5868 * <p>
5869 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
5870 *
5871 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.50"
5872 */
5873 // Template#: 343, Serial#: 343
5874 public void sir(final int simm13) {
5875 int instruction = 0x9F802000;
5876 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
5877 instruction |= (simm13 & 0x1fff);
5878 emitInt(instruction);
5879 }
5880
5881 /**
5882 * Pseudo-external assembler syntax: {@code ta }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
5883 * Example disassembly syntax: {@code ta %icc, %g0 + %g0}
5884 *
5885 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
5886 */
5887 // Template#: 344, Serial#: 344
5888 public void ta(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
5889 int instruction = 0x91D00000;
5890 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
5891 instruction |= ((rs1.value() & 0x1f) << 14);
5892 instruction |= (rs2.value() & 0x1f);
5893 emitInt(instruction);
5894 }
5895
5896 /**
5897 * Pseudo-external assembler syntax: {@code tn }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
5898 * Example disassembly syntax: {@code tn %icc, %g0 + %g0}
5899 *
5900 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
5901 */
5902 // Template#: 345, Serial#: 345
5903 public void tn(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
5904 int instruction = 0x81D00000;
5905 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
5906 instruction |= ((rs1.value() & 0x1f) << 14);
5907 instruction |= (rs2.value() & 0x1f);
5908 emitInt(instruction);
5909 }
5910
5911 /**
5912 * Pseudo-external assembler syntax: {@code tne }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
5913 * Example disassembly syntax: {@code tne %icc, %g0 + %g0}
5914 *
5915 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
5916 */
5917 // Template#: 346, Serial#: 346
5918 public void tne(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
5919 int instruction = 0x93D00000;
5920 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
5921 instruction |= ((rs1.value() & 0x1f) << 14);
5922 instruction |= (rs2.value() & 0x1f);
5923 emitInt(instruction);
5924 }
5925
5926 /**
5927 * Pseudo-external assembler syntax: {@code te }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
5928 * Example disassembly syntax: {@code te %icc, %g0 + %g0}
5929 *
5930 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
5931 */
5932 // Template#: 347, Serial#: 347
5933 public void te(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
5934 int instruction = 0x83D00000;
5935 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
5936 instruction |= ((rs1.value() & 0x1f) << 14);
5937 instruction |= (rs2.value() & 0x1f);
5938 emitInt(instruction);
5939 }
5940
5941 /**
5942 * Pseudo-external assembler syntax: {@code tg }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
5943 * Example disassembly syntax: {@code tg %icc, %g0 + %g0}
5944 *
5945 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
5946 */
5947 // Template#: 348, Serial#: 348
5948 public void tg(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
5949 int instruction = 0x95D00000;
5950 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
5951 instruction |= ((rs1.value() & 0x1f) << 14);
5952 instruction |= (rs2.value() & 0x1f);
5953 emitInt(instruction);
5954 }
5955
5956 /**
5957 * Pseudo-external assembler syntax: {@code tle }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
5958 * Example disassembly syntax: {@code tle %icc, %g0 + %g0}
5959 *
5960 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
5961 */
5962 // Template#: 349, Serial#: 349
5963 public void tle(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
5964 int instruction = 0x85D00000;
5965 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
5966 instruction |= ((rs1.value() & 0x1f) << 14);
5967 instruction |= (rs2.value() & 0x1f);
5968 emitInt(instruction);
5969 }
5970
5971 /**
5972 * Pseudo-external assembler syntax: {@code tge }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
5973 * Example disassembly syntax: {@code tge %icc, %g0 + %g0}
5974 *
5975 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
5976 */
5977 // Template#: 350, Serial#: 350
5978 public void tge(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
5979 int instruction = 0x97D00000;
5980 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
5981 instruction |= ((rs1.value() & 0x1f) << 14);
5982 instruction |= (rs2.value() & 0x1f);
5983 emitInt(instruction);
5984 }
5985
5986 /**
5987 * Pseudo-external assembler syntax: {@code tl }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
5988 * Example disassembly syntax: {@code tl %icc, %g0 + %g0}
5989 *
5990 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
5991 */
5992 // Template#: 351, Serial#: 351
5993 public void tl(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
5994 int instruction = 0x87D00000;
5995 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
5996 instruction |= ((rs1.value() & 0x1f) << 14);
5997 instruction |= (rs2.value() & 0x1f);
5998 emitInt(instruction);
5999 }
6000
6001 /**
6002 * Pseudo-external assembler syntax: {@code tgu }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
6003 * Example disassembly syntax: {@code tgu %icc, %g0 + %g0}
6004 *
6005 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6006 */
6007 // Template#: 352, Serial#: 352
6008 public void tgu(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
6009 int instruction = 0x99D00000;
6010 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6011 instruction |= ((rs1.value() & 0x1f) << 14);
6012 instruction |= (rs2.value() & 0x1f);
6013 emitInt(instruction);
6014 }
6015
6016 /**
6017 * Pseudo-external assembler syntax: {@code tleu }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
6018 * Example disassembly syntax: {@code tleu %icc, %g0 + %g0}
6019 *
6020 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6021 */
6022 // Template#: 353, Serial#: 353
6023 public void tleu(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
6024 int instruction = 0x89D00000;
6025 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6026 instruction |= ((rs1.value() & 0x1f) << 14);
6027 instruction |= (rs2.value() & 0x1f);
6028 emitInt(instruction);
6029 }
6030
6031 /**
6032 * Pseudo-external assembler syntax: {@code tcc }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
6033 * Example disassembly syntax: {@code tcc %icc, %g0 + %g0}
6034 *
6035 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6036 */
6037 // Template#: 354, Serial#: 354
6038 public void tcc(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
6039 int instruction = 0x9BD00000;
6040 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6041 instruction |= ((rs1.value() & 0x1f) << 14);
6042 instruction |= (rs2.value() & 0x1f);
6043 emitInt(instruction);
6044 }
6045
6046 /**
6047 * Pseudo-external assembler syntax: {@code tcs }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
6048 * Example disassembly syntax: {@code tcs %icc, %g0 + %g0}
6049 *
6050 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6051 */
6052 // Template#: 355, Serial#: 355
6053 public void tcs(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
6054 int instruction = 0x8BD00000;
6055 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6056 instruction |= ((rs1.value() & 0x1f) << 14);
6057 instruction |= (rs2.value() & 0x1f);
6058 emitInt(instruction);
6059 }
6060
6061 /**
6062 * Pseudo-external assembler syntax: {@code tpos }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
6063 * Example disassembly syntax: {@code tpos %icc, %g0 + %g0}
6064 *
6065 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6066 */
6067 // Template#: 356, Serial#: 356
6068 public void tpos(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
6069 int instruction = 0x9DD00000;
6070 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6071 instruction |= ((rs1.value() & 0x1f) << 14);
6072 instruction |= (rs2.value() & 0x1f);
6073 emitInt(instruction);
6074 }
6075
6076 /**
6077 * Pseudo-external assembler syntax: {@code tneg }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
6078 * Example disassembly syntax: {@code tneg %icc, %g0 + %g0}
6079 *
6080 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6081 */
6082 // Template#: 357, Serial#: 357
6083 public void tneg(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
6084 int instruction = 0x8DD00000;
6085 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6086 instruction |= ((rs1.value() & 0x1f) << 14);
6087 instruction |= (rs2.value() & 0x1f);
6088 emitInt(instruction);
6089 }
6090
6091 /**
6092 * Pseudo-external assembler syntax: {@code tvc }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
6093 * Example disassembly syntax: {@code tvc %icc, %g0 + %g0}
6094 *
6095 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6096 */
6097 // Template#: 358, Serial#: 358
6098 public void tvc(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
6099 int instruction = 0x9FD00000;
6100 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6101 instruction |= ((rs1.value() & 0x1f) << 14);
6102 instruction |= (rs2.value() & 0x1f);
6103 emitInt(instruction);
6104 }
6105
6106 /**
6107 * Pseudo-external assembler syntax: {@code tvs }<i>i_or_x_cc</i>, <i>rs1</i>, <i>rs2</i>
6108 * Example disassembly syntax: {@code tvs %icc, %g0 + %g0}
6109 *
6110 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6111 */
6112 // Template#: 359, Serial#: 359
6113 public void tvs(final ICCOperand i_or_x_cc, final GPR rs1, final GPR rs2) {
6114 int instruction = 0x8FD00000;
6115 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6116 instruction |= ((rs1.value() & 0x1f) << 14);
6117 instruction |= (rs2.value() & 0x1f);
6118 emitInt(instruction);
6119 }
6120
6121 /**
6122 * Pseudo-external assembler syntax: {@code ta }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6123 * Example disassembly syntax: {@code ta %icc, %g0 + 0x0}
6124 * <p>
6125 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6126 *
6127 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6128 */
6129 // Template#: 360, Serial#: 360
6130 public void ta(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6131 int instruction = 0x91D02000;
6132 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6133 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6134 instruction |= ((rs1.value() & 0x1f) << 14);
6135 instruction |= (software_trap_number & 0x7f);
6136 emitInt(instruction);
6137 }
6138
6139 /**
6140 * Pseudo-external assembler syntax: {@code tn }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6141 * Example disassembly syntax: {@code tn %icc, %g0 + 0x0}
6142 * <p>
6143 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6144 *
6145 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6146 */
6147 // Template#: 361, Serial#: 361
6148 public void tn(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6149 int instruction = 0x81D02000;
6150 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6151 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6152 instruction |= ((rs1.value() & 0x1f) << 14);
6153 instruction |= (software_trap_number & 0x7f);
6154 emitInt(instruction);
6155 }
6156
6157 /**
6158 * Pseudo-external assembler syntax: {@code tne }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6159 * Example disassembly syntax: {@code tne %icc, %g0 + 0x0}
6160 * <p>
6161 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6162 *
6163 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6164 */
6165 // Template#: 362, Serial#: 362
6166 public void tne(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6167 int instruction = 0x93D02000;
6168 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6169 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6170 instruction |= ((rs1.value() & 0x1f) << 14);
6171 instruction |= (software_trap_number & 0x7f);
6172 emitInt(instruction);
6173 }
6174
6175 /**
6176 * Pseudo-external assembler syntax: {@code te }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6177 * Example disassembly syntax: {@code te %icc, %g0 + 0x0}
6178 * <p>
6179 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6180 *
6181 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6182 */
6183 // Template#: 363, Serial#: 363
6184 public void te(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6185 int instruction = 0x83D02000;
6186 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6187 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6188 instruction |= ((rs1.value() & 0x1f) << 14);
6189 instruction |= (software_trap_number & 0x7f);
6190 emitInt(instruction);
6191 }
6192
6193 /**
6194 * Pseudo-external assembler syntax: {@code tg }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6195 * Example disassembly syntax: {@code tg %icc, %g0 + 0x0}
6196 * <p>
6197 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6198 *
6199 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6200 */
6201 // Template#: 364, Serial#: 364
6202 public void tg(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6203 int instruction = 0x95D02000;
6204 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6205 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6206 instruction |= ((rs1.value() & 0x1f) << 14);
6207 instruction |= (software_trap_number & 0x7f);
6208 emitInt(instruction);
6209 }
6210
6211 /**
6212 * Pseudo-external assembler syntax: {@code tle }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6213 * Example disassembly syntax: {@code tle %icc, %g0 + 0x0}
6214 * <p>
6215 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6216 *
6217 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6218 */
6219 // Template#: 365, Serial#: 365
6220 public void tle(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6221 int instruction = 0x85D02000;
6222 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6223 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6224 instruction |= ((rs1.value() & 0x1f) << 14);
6225 instruction |= (software_trap_number & 0x7f);
6226 emitInt(instruction);
6227 }
6228
6229 /**
6230 * Pseudo-external assembler syntax: {@code tge }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6231 * Example disassembly syntax: {@code tge %icc, %g0 + 0x0}
6232 * <p>
6233 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6234 *
6235 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6236 */
6237 // Template#: 366, Serial#: 366
6238 public void tge(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6239 int instruction = 0x97D02000;
6240 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6241 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6242 instruction |= ((rs1.value() & 0x1f) << 14);
6243 instruction |= (software_trap_number & 0x7f);
6244 emitInt(instruction);
6245 }
6246
6247 /**
6248 * Pseudo-external assembler syntax: {@code tl }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6249 * Example disassembly syntax: {@code tl %icc, %g0 + 0x0}
6250 * <p>
6251 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6252 *
6253 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6254 */
6255 // Template#: 367, Serial#: 367
6256 public void tl(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6257 int instruction = 0x87D02000;
6258 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6259 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6260 instruction |= ((rs1.value() & 0x1f) << 14);
6261 instruction |= (software_trap_number & 0x7f);
6262 emitInt(instruction);
6263 }
6264
6265 /**
6266 * Pseudo-external assembler syntax: {@code tgu }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6267 * Example disassembly syntax: {@code tgu %icc, %g0 + 0x0}
6268 * <p>
6269 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6270 *
6271 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6272 */
6273 // Template#: 368, Serial#: 368
6274 public void tgu(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6275 int instruction = 0x99D02000;
6276 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6277 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6278 instruction |= ((rs1.value() & 0x1f) << 14);
6279 instruction |= (software_trap_number & 0x7f);
6280 emitInt(instruction);
6281 }
6282
6283 /**
6284 * Pseudo-external assembler syntax: {@code tleu }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6285 * Example disassembly syntax: {@code tleu %icc, %g0 + 0x0}
6286 * <p>
6287 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6288 *
6289 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6290 */
6291 // Template#: 369, Serial#: 369
6292 public void tleu(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6293 int instruction = 0x89D02000;
6294 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6295 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6296 instruction |= ((rs1.value() & 0x1f) << 14);
6297 instruction |= (software_trap_number & 0x7f);
6298 emitInt(instruction);
6299 }
6300
6301 /**
6302 * Pseudo-external assembler syntax: {@code tcc }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6303 * Example disassembly syntax: {@code tcc %icc, %g0 + 0x0}
6304 * <p>
6305 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6306 *
6307 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6308 */
6309 // Template#: 370, Serial#: 370
6310 public void tcc(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6311 int instruction = 0x9BD02000;
6312 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6313 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6314 instruction |= ((rs1.value() & 0x1f) << 14);
6315 instruction |= (software_trap_number & 0x7f);
6316 emitInt(instruction);
6317 }
6318
6319 /**
6320 * Pseudo-external assembler syntax: {@code tcs }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6321 * Example disassembly syntax: {@code tcs %icc, %g0 + 0x0}
6322 * <p>
6323 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6324 *
6325 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6326 */
6327 // Template#: 371, Serial#: 371
6328 public void tcs(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6329 int instruction = 0x8BD02000;
6330 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6331 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6332 instruction |= ((rs1.value() & 0x1f) << 14);
6333 instruction |= (software_trap_number & 0x7f);
6334 emitInt(instruction);
6335 }
6336
6337 /**
6338 * Pseudo-external assembler syntax: {@code tpos }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6339 * Example disassembly syntax: {@code tpos %icc, %g0 + 0x0}
6340 * <p>
6341 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6342 *
6343 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6344 */
6345 // Template#: 372, Serial#: 372
6346 public void tpos(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6347 int instruction = 0x9DD02000;
6348 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6349 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6350 instruction |= ((rs1.value() & 0x1f) << 14);
6351 instruction |= (software_trap_number & 0x7f);
6352 emitInt(instruction);
6353 }
6354
6355 /**
6356 * Pseudo-external assembler syntax: {@code tneg }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6357 * Example disassembly syntax: {@code tneg %icc, %g0 + 0x0}
6358 * <p>
6359 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6360 *
6361 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6362 */
6363 // Template#: 373, Serial#: 373
6364 public void tneg(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6365 int instruction = 0x8DD02000;
6366 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6367 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6368 instruction |= ((rs1.value() & 0x1f) << 14);
6369 instruction |= (software_trap_number & 0x7f);
6370 emitInt(instruction);
6371 }
6372
6373 /**
6374 * Pseudo-external assembler syntax: {@code tvc }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6375 * Example disassembly syntax: {@code tvc %icc, %g0 + 0x0}
6376 * <p>
6377 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6378 *
6379 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6380 */
6381 // Template#: 374, Serial#: 374
6382 public void tvc(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6383 int instruction = 0x9FD02000;
6384 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6385 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6386 instruction |= ((rs1.value() & 0x1f) << 14);
6387 instruction |= (software_trap_number & 0x7f);
6388 emitInt(instruction);
6389 }
6390
6391 /**
6392 * Pseudo-external assembler syntax: {@code tvs }<i>i_or_x_cc</i>, <i>rs1</i>, <i>software_trap_number</i>
6393 * Example disassembly syntax: {@code tvs %icc, %g0 + 0x0}
6394 * <p>
6395 * Constraint: {@code 0 <= software_trap_number && software_trap_number <= 127}<br />
6396 *
6397 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
6398 */
6399 // Template#: 375, Serial#: 375
6400 public void tvs(final ICCOperand i_or_x_cc, final GPR rs1, final int software_trap_number) {
6401 int instruction = 0x8FD02000;
6402 checkConstraint(0 <= software_trap_number && software_trap_number <= 127, "0 <= software_trap_number && software_trap_number <= 127");
6403 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6404 instruction |= ((rs1.value() & 0x1f) << 14);
6405 instruction |= (software_trap_number & 0x7f);
6406 emitInt(instruction);
6407 }
6408
6409 /**
6410 * Pseudo-external assembler syntax: {@code fmovrse }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6411 * Example disassembly syntax: {@code fmovrse %g0, %f0, %f0}
6412 *
6413 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6414 */
6415 // Template#: 376, Serial#: 376
6416 public void fmovrse(final GPR rs1, final SFPR rs2, final SFPR rd) {
6417 int instruction = 0x81A804A0;
6418 instruction |= ((rs1.value() & 0x1f) << 14);
6419 instruction |= (rs2.value() & 0x1f);
6420 instruction |= ((rd.value() & 0x1f) << 25);
6421 emitInt(instruction);
6422 }
6423
6424 /**
6425 * Pseudo-external assembler syntax: {@code fmovrde }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6426 * Example disassembly syntax: {@code fmovrde %g0, %f0, %f0}
6427 *
6428 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6429 */
6430 // Template#: 377, Serial#: 377
6431 public void fmovrde(final GPR rs1, final DFPR rs2, final DFPR rd) {
6432 int instruction = 0x81A804C0;
6433 instruction |= ((rs1.value() & 0x1f) << 14);
6434 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
6435 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
6436 emitInt(instruction);
6437 }
6438
6439 /**
6440 * Pseudo-external assembler syntax: {@code fmovrqe }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6441 * Example disassembly syntax: {@code fmovrqe %g0, %f0, %f0}
6442 *
6443 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6444 */
6445 // Template#: 378, Serial#: 378
6446 public void fmovrqe(final GPR rs1, final QFPR rs2, final QFPR rd) {
6447 int instruction = 0x81A804E0;
6448 instruction |= ((rs1.value() & 0x1f) << 14);
6449 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
6450 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
6451 emitInt(instruction);
6452 }
6453
6454 /**
6455 * Pseudo-external assembler syntax: {@code movre }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6456 * Example disassembly syntax: {@code movre %g0, %g0, %g0}
6457 *
6458 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
6459 */
6460 // Template#: 379, Serial#: 379
6461 public void movre(final GPR rs1, final GPR rs2, final GPR rd) {
6462 int instruction = 0x81780400;
6463 instruction |= ((rs1.value() & 0x1f) << 14);
6464 instruction |= (rs2.value() & 0x1f);
6465 instruction |= ((rd.value() & 0x1f) << 25);
6466 emitInt(instruction);
6467 }
6468
6469 /**
6470 * Pseudo-external assembler syntax: {@code movre }<i>rs1</i>, <i>simm10</i>, <i>rd</i>
6471 * Example disassembly syntax: {@code movre %g0, -512, %g0}
6472 * <p>
6473 * Constraint: {@code -512 <= simm10 && simm10 <= 511}<br />
6474 *
6475 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
6476 */
6477 // Template#: 380, Serial#: 380
6478 public void movre(final GPR rs1, final int simm10, final GPR rd) {
6479 int instruction = 0x81782400;
6480 checkConstraint(-512 <= simm10 && simm10 <= 511, "-512 <= simm10 && simm10 <= 511");
6481 instruction |= ((rs1.value() & 0x1f) << 14);
6482 instruction |= (simm10 & 0x3ff);
6483 instruction |= ((rd.value() & 0x1f) << 25);
6484 emitInt(instruction);
6485 }
6486
6487 /**
6488 * Pseudo-external assembler syntax: {@code fmovrslez }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6489 * Example disassembly syntax: {@code fmovrslez %g0, %f0, %f0}
6490 *
6491 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6492 */
6493 // Template#: 381, Serial#: 381
6494 public void fmovrslez(final GPR rs1, final SFPR rs2, final SFPR rd) {
6495 int instruction = 0x81A808A0;
6496 instruction |= ((rs1.value() & 0x1f) << 14);
6497 instruction |= (rs2.value() & 0x1f);
6498 instruction |= ((rd.value() & 0x1f) << 25);
6499 emitInt(instruction);
6500 }
6501
6502 /**
6503 * Pseudo-external assembler syntax: {@code fmovrdlez }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6504 * Example disassembly syntax: {@code fmovrdlez %g0, %f0, %f0}
6505 *
6506 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6507 */
6508 // Template#: 382, Serial#: 382
6509 public void fmovrdlez(final GPR rs1, final DFPR rs2, final DFPR rd) {
6510 int instruction = 0x81A808C0;
6511 instruction |= ((rs1.value() & 0x1f) << 14);
6512 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
6513 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
6514 emitInt(instruction);
6515 }
6516
6517 /**
6518 * Pseudo-external assembler syntax: {@code fmovrqlez }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6519 * Example disassembly syntax: {@code fmovrqlez %g0, %f0, %f0}
6520 *
6521 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6522 */
6523 // Template#: 383, Serial#: 383
6524 public void fmovrqlez(final GPR rs1, final QFPR rs2, final QFPR rd) {
6525 int instruction = 0x81A808E0;
6526 instruction |= ((rs1.value() & 0x1f) << 14);
6527 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
6528 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
6529 emitInt(instruction);
6530 }
6531
6532 /**
6533 * Pseudo-external assembler syntax: {@code movrlez }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6534 * Example disassembly syntax: {@code movrlez %g0, %g0, %g0}
6535 *
6536 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
6537 */
6538 // Template#: 384, Serial#: 384
6539 public void movrlez(final GPR rs1, final GPR rs2, final GPR rd) {
6540 int instruction = 0x81780800;
6541 instruction |= ((rs1.value() & 0x1f) << 14);
6542 instruction |= (rs2.value() & 0x1f);
6543 instruction |= ((rd.value() & 0x1f) << 25);
6544 emitInt(instruction);
6545 }
6546
6547 /**
6548 * Pseudo-external assembler syntax: {@code movrlez }<i>rs1</i>, <i>simm10</i>, <i>rd</i>
6549 * Example disassembly syntax: {@code movrlez %g0, -512, %g0}
6550 * <p>
6551 * Constraint: {@code -512 <= simm10 && simm10 <= 511}<br />
6552 *
6553 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
6554 */
6555 // Template#: 385, Serial#: 385
6556 public void movrlez(final GPR rs1, final int simm10, final GPR rd) {
6557 int instruction = 0x81782800;
6558 checkConstraint(-512 <= simm10 && simm10 <= 511, "-512 <= simm10 && simm10 <= 511");
6559 instruction |= ((rs1.value() & 0x1f) << 14);
6560 instruction |= (simm10 & 0x3ff);
6561 instruction |= ((rd.value() & 0x1f) << 25);
6562 emitInt(instruction);
6563 }
6564
6565 /**
6566 * Pseudo-external assembler syntax: {@code fmovrslz }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6567 * Example disassembly syntax: {@code fmovrslz %g0, %f0, %f0}
6568 *
6569 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6570 */
6571 // Template#: 386, Serial#: 386
6572 public void fmovrslz(final GPR rs1, final SFPR rs2, final SFPR rd) {
6573 int instruction = 0x81A80CA0;
6574 instruction |= ((rs1.value() & 0x1f) << 14);
6575 instruction |= (rs2.value() & 0x1f);
6576 instruction |= ((rd.value() & 0x1f) << 25);
6577 emitInt(instruction);
6578 }
6579
6580 /**
6581 * Pseudo-external assembler syntax: {@code fmovrdlz }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6582 * Example disassembly syntax: {@code fmovrdlz %g0, %f0, %f0}
6583 *
6584 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6585 */
6586 // Template#: 387, Serial#: 387
6587 public void fmovrdlz(final GPR rs1, final DFPR rs2, final DFPR rd) {
6588 int instruction = 0x81A80CC0;
6589 instruction |= ((rs1.value() & 0x1f) << 14);
6590 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
6591 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
6592 emitInt(instruction);
6593 }
6594
6595 /**
6596 * Pseudo-external assembler syntax: {@code fmovrqlz }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6597 * Example disassembly syntax: {@code fmovrqlz %g0, %f0, %f0}
6598 *
6599 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6600 */
6601 // Template#: 388, Serial#: 388
6602 public void fmovrqlz(final GPR rs1, final QFPR rs2, final QFPR rd) {
6603 int instruction = 0x81A80CE0;
6604 instruction |= ((rs1.value() & 0x1f) << 14);
6605 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
6606 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
6607 emitInt(instruction);
6608 }
6609
6610 /**
6611 * Pseudo-external assembler syntax: {@code movrlz }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6612 * Example disassembly syntax: {@code movrlz %g0, %g0, %g0}
6613 *
6614 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
6615 */
6616 // Template#: 389, Serial#: 389
6617 public void movrlz(final GPR rs1, final GPR rs2, final GPR rd) {
6618 int instruction = 0x81780C00;
6619 instruction |= ((rs1.value() & 0x1f) << 14);
6620 instruction |= (rs2.value() & 0x1f);
6621 instruction |= ((rd.value() & 0x1f) << 25);
6622 emitInt(instruction);
6623 }
6624
6625 /**
6626 * Pseudo-external assembler syntax: {@code movrlz }<i>rs1</i>, <i>simm10</i>, <i>rd</i>
6627 * Example disassembly syntax: {@code movrlz %g0, -512, %g0}
6628 * <p>
6629 * Constraint: {@code -512 <= simm10 && simm10 <= 511}<br />
6630 *
6631 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
6632 */
6633 // Template#: 390, Serial#: 390
6634 public void movrlz(final GPR rs1, final int simm10, final GPR rd) {
6635 int instruction = 0x81782C00;
6636 checkConstraint(-512 <= simm10 && simm10 <= 511, "-512 <= simm10 && simm10 <= 511");
6637 instruction |= ((rs1.value() & 0x1f) << 14);
6638 instruction |= (simm10 & 0x3ff);
6639 instruction |= ((rd.value() & 0x1f) << 25);
6640 emitInt(instruction);
6641 }
6642
6643 /**
6644 * Pseudo-external assembler syntax: {@code fmovrsne }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6645 * Example disassembly syntax: {@code fmovrsne %g0, %f0, %f0}
6646 *
6647 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6648 */
6649 // Template#: 391, Serial#: 391
6650 public void fmovrsne(final GPR rs1, final SFPR rs2, final SFPR rd) {
6651 int instruction = 0x81A814A0;
6652 instruction |= ((rs1.value() & 0x1f) << 14);
6653 instruction |= (rs2.value() & 0x1f);
6654 instruction |= ((rd.value() & 0x1f) << 25);
6655 emitInt(instruction);
6656 }
6657
6658 /**
6659 * Pseudo-external assembler syntax: {@code fmovrdne }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6660 * Example disassembly syntax: {@code fmovrdne %g0, %f0, %f0}
6661 *
6662 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6663 */
6664 // Template#: 392, Serial#: 392
6665 public void fmovrdne(final GPR rs1, final DFPR rs2, final DFPR rd) {
6666 int instruction = 0x81A814C0;
6667 instruction |= ((rs1.value() & 0x1f) << 14);
6668 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
6669 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
6670 emitInt(instruction);
6671 }
6672
6673 /**
6674 * Pseudo-external assembler syntax: {@code fmovrqne }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6675 * Example disassembly syntax: {@code fmovrqne %g0, %f0, %f0}
6676 *
6677 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6678 */
6679 // Template#: 393, Serial#: 393
6680 public void fmovrqne(final GPR rs1, final QFPR rs2, final QFPR rd) {
6681 int instruction = 0x81A814E0;
6682 instruction |= ((rs1.value() & 0x1f) << 14);
6683 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
6684 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
6685 emitInt(instruction);
6686 }
6687
6688 /**
6689 * Pseudo-external assembler syntax: {@code movrne }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6690 * Example disassembly syntax: {@code movrne %g0, %g0, %g0}
6691 *
6692 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
6693 */
6694 // Template#: 394, Serial#: 394
6695 public void movrne(final GPR rs1, final GPR rs2, final GPR rd) {
6696 int instruction = 0x81781400;
6697 instruction |= ((rs1.value() & 0x1f) << 14);
6698 instruction |= (rs2.value() & 0x1f);
6699 instruction |= ((rd.value() & 0x1f) << 25);
6700 emitInt(instruction);
6701 }
6702
6703 /**
6704 * Pseudo-external assembler syntax: {@code movrne }<i>rs1</i>, <i>simm10</i>, <i>rd</i>
6705 * Example disassembly syntax: {@code movrne %g0, -512, %g0}
6706 * <p>
6707 * Constraint: {@code -512 <= simm10 && simm10 <= 511}<br />
6708 *
6709 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
6710 */
6711 // Template#: 395, Serial#: 395
6712 public void movrne(final GPR rs1, final int simm10, final GPR rd) {
6713 int instruction = 0x81783400;
6714 checkConstraint(-512 <= simm10 && simm10 <= 511, "-512 <= simm10 && simm10 <= 511");
6715 instruction |= ((rs1.value() & 0x1f) << 14);
6716 instruction |= (simm10 & 0x3ff);
6717 instruction |= ((rd.value() & 0x1f) << 25);
6718 emitInt(instruction);
6719 }
6720
6721 /**
6722 * Pseudo-external assembler syntax: {@code fmovrsgz }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6723 * Example disassembly syntax: {@code fmovrsgz %g0, %f0, %f0}
6724 *
6725 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6726 */
6727 // Template#: 396, Serial#: 396
6728 public void fmovrsgz(final GPR rs1, final SFPR rs2, final SFPR rd) {
6729 int instruction = 0x81A818A0;
6730 instruction |= ((rs1.value() & 0x1f) << 14);
6731 instruction |= (rs2.value() & 0x1f);
6732 instruction |= ((rd.value() & 0x1f) << 25);
6733 emitInt(instruction);
6734 }
6735
6736 /**
6737 * Pseudo-external assembler syntax: {@code fmovrdgz }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6738 * Example disassembly syntax: {@code fmovrdgz %g0, %f0, %f0}
6739 *
6740 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6741 */
6742 // Template#: 397, Serial#: 397
6743 public void fmovrdgz(final GPR rs1, final DFPR rs2, final DFPR rd) {
6744 int instruction = 0x81A818C0;
6745 instruction |= ((rs1.value() & 0x1f) << 14);
6746 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
6747 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
6748 emitInt(instruction);
6749 }
6750
6751 /**
6752 * Pseudo-external assembler syntax: {@code fmovrqgz }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6753 * Example disassembly syntax: {@code fmovrqgz %g0, %f0, %f0}
6754 *
6755 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6756 */
6757 // Template#: 398, Serial#: 398
6758 public void fmovrqgz(final GPR rs1, final QFPR rs2, final QFPR rd) {
6759 int instruction = 0x81A818E0;
6760 instruction |= ((rs1.value() & 0x1f) << 14);
6761 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
6762 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
6763 emitInt(instruction);
6764 }
6765
6766 /**
6767 * Pseudo-external assembler syntax: {@code movrgz }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6768 * Example disassembly syntax: {@code movrgz %g0, %g0, %g0}
6769 *
6770 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
6771 */
6772 // Template#: 399, Serial#: 399
6773 public void movrgz(final GPR rs1, final GPR rs2, final GPR rd) {
6774 int instruction = 0x81781800;
6775 instruction |= ((rs1.value() & 0x1f) << 14);
6776 instruction |= (rs2.value() & 0x1f);
6777 instruction |= ((rd.value() & 0x1f) << 25);
6778 emitInt(instruction);
6779 }
6780
6781 /**
6782 * Pseudo-external assembler syntax: {@code movrgz }<i>rs1</i>, <i>simm10</i>, <i>rd</i>
6783 * Example disassembly syntax: {@code movrgz %g0, -512, %g0}
6784 * <p>
6785 * Constraint: {@code -512 <= simm10 && simm10 <= 511}<br />
6786 *
6787 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
6788 */
6789 // Template#: 400, Serial#: 400
6790 public void movrgz(final GPR rs1, final int simm10, final GPR rd) {
6791 int instruction = 0x81783800;
6792 checkConstraint(-512 <= simm10 && simm10 <= 511, "-512 <= simm10 && simm10 <= 511");
6793 instruction |= ((rs1.value() & 0x1f) << 14);
6794 instruction |= (simm10 & 0x3ff);
6795 instruction |= ((rd.value() & 0x1f) << 25);
6796 emitInt(instruction);
6797 }
6798
6799 /**
6800 * Pseudo-external assembler syntax: {@code fmovrsgez }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6801 * Example disassembly syntax: {@code fmovrsgez %g0, %f0, %f0}
6802 *
6803 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6804 */
6805 // Template#: 401, Serial#: 401
6806 public void fmovrsgez(final GPR rs1, final SFPR rs2, final SFPR rd) {
6807 int instruction = 0x81A81CA0;
6808 instruction |= ((rs1.value() & 0x1f) << 14);
6809 instruction |= (rs2.value() & 0x1f);
6810 instruction |= ((rd.value() & 0x1f) << 25);
6811 emitInt(instruction);
6812 }
6813
6814 /**
6815 * Pseudo-external assembler syntax: {@code fmovrdgez }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6816 * Example disassembly syntax: {@code fmovrdgez %g0, %f0, %f0}
6817 *
6818 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6819 */
6820 // Template#: 402, Serial#: 402
6821 public void fmovrdgez(final GPR rs1, final DFPR rs2, final DFPR rd) {
6822 int instruction = 0x81A81CC0;
6823 instruction |= ((rs1.value() & 0x1f) << 14);
6824 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
6825 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
6826 emitInt(instruction);
6827 }
6828
6829 /**
6830 * Pseudo-external assembler syntax: {@code fmovrqgez }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6831 * Example disassembly syntax: {@code fmovrqgez %g0, %f0, %f0}
6832 *
6833 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.34"
6834 */
6835 // Template#: 403, Serial#: 403
6836 public void fmovrqgez(final GPR rs1, final QFPR rs2, final QFPR rd) {
6837 int instruction = 0x81A81CE0;
6838 instruction |= ((rs1.value() & 0x1f) << 14);
6839 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
6840 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
6841 emitInt(instruction);
6842 }
6843
6844 /**
6845 * Pseudo-external assembler syntax: {@code movrgez }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
6846 * Example disassembly syntax: {@code movrgez %g0, %g0, %g0}
6847 *
6848 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
6849 */
6850 // Template#: 404, Serial#: 404
6851 public void movrgez(final GPR rs1, final GPR rs2, final GPR rd) {
6852 int instruction = 0x81781C00;
6853 instruction |= ((rs1.value() & 0x1f) << 14);
6854 instruction |= (rs2.value() & 0x1f);
6855 instruction |= ((rd.value() & 0x1f) << 25);
6856 emitInt(instruction);
6857 }
6858
6859 /**
6860 * Pseudo-external assembler syntax: {@code movrgez }<i>rs1</i>, <i>simm10</i>, <i>rd</i>
6861 * Example disassembly syntax: {@code movrgez %g0, -512, %g0}
6862 * <p>
6863 * Constraint: {@code -512 <= simm10 && simm10 <= 511}<br />
6864 *
6865 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.36"
6866 */
6867 // Template#: 405, Serial#: 405
6868 public void movrgez(final GPR rs1, final int simm10, final GPR rd) {
6869 int instruction = 0x81783C00;
6870 checkConstraint(-512 <= simm10 && simm10 <= 511, "-512 <= simm10 && simm10 <= 511");
6871 instruction |= ((rs1.value() & 0x1f) << 14);
6872 instruction |= (simm10 & 0x3ff);
6873 instruction |= ((rd.value() & 0x1f) << 25);
6874 emitInt(instruction);
6875 }
6876
6877 /**
6878 * Pseudo-external assembler syntax: {@code fmovsa }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
6879 * Example disassembly syntax: {@code fmovsa %icc, %f0, %f0}
6880 *
6881 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
6882 */
6883 // Template#: 406, Serial#: 406
6884 public void fmovsa(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
6885 int instruction = 0x81AA2020;
6886 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6887 instruction |= (rs2.value() & 0x1f);
6888 instruction |= ((rd.value() & 0x1f) << 25);
6889 emitInt(instruction);
6890 }
6891
6892 /**
6893 * Pseudo-external assembler syntax: {@code fmovda }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
6894 * Example disassembly syntax: {@code fmovda %icc, %f0, %f0}
6895 *
6896 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
6897 */
6898 // Template#: 407, Serial#: 407
6899 public void fmovda(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
6900 int instruction = 0x81AA2040;
6901 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6902 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
6903 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
6904 emitInt(instruction);
6905 }
6906
6907 /**
6908 * Pseudo-external assembler syntax: {@code fmovqa }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
6909 * Example disassembly syntax: {@code fmovqa %icc, %f0, %f0}
6910 *
6911 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
6912 */
6913 // Template#: 408, Serial#: 408
6914 public void fmovqa(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
6915 int instruction = 0x81AA2060;
6916 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6917 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
6918 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
6919 emitInt(instruction);
6920 }
6921
6922 /**
6923 * Pseudo-external assembler syntax: {@code mova }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
6924 * Example disassembly syntax: {@code mova %icc, -1024, %g0}
6925 * <p>
6926 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
6927 *
6928 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
6929 */
6930 // Template#: 409, Serial#: 409
6931 public void mova(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
6932 int instruction = 0x81662000;
6933 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
6934 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6935 instruction |= (simm11 & 0x7ff);
6936 instruction |= ((rd.value() & 0x1f) << 25);
6937 emitInt(instruction);
6938 }
6939
6940 /**
6941 * Pseudo-external assembler syntax: {@code mova }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
6942 * Example disassembly syntax: {@code mova %icc, %g0, %g0}
6943 *
6944 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
6945 */
6946 // Template#: 410, Serial#: 410
6947 public void mova(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
6948 int instruction = 0x81660000;
6949 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6950 instruction |= (rs2.value() & 0x1f);
6951 instruction |= ((rd.value() & 0x1f) << 25);
6952 emitInt(instruction);
6953 }
6954
6955 /**
6956 * Pseudo-external assembler syntax: {@code fmovsn }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
6957 * Example disassembly syntax: {@code fmovsn %icc, %f0, %f0}
6958 *
6959 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
6960 */
6961 // Template#: 411, Serial#: 411
6962 public void fmovsn(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
6963 int instruction = 0x81A82020;
6964 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6965 instruction |= (rs2.value() & 0x1f);
6966 instruction |= ((rd.value() & 0x1f) << 25);
6967 emitInt(instruction);
6968 }
6969
6970 /**
6971 * Pseudo-external assembler syntax: {@code fmovdn }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
6972 * Example disassembly syntax: {@code fmovdn %icc, %f0, %f0}
6973 *
6974 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
6975 */
6976 // Template#: 412, Serial#: 412
6977 public void fmovdn(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
6978 int instruction = 0x81A82040;
6979 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6980 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
6981 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
6982 emitInt(instruction);
6983 }
6984
6985 /**
6986 * Pseudo-external assembler syntax: {@code fmovqn }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
6987 * Example disassembly syntax: {@code fmovqn %icc, %f0, %f0}
6988 *
6989 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
6990 */
6991 // Template#: 413, Serial#: 413
6992 public void fmovqn(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
6993 int instruction = 0x81A82060;
6994 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
6995 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
6996 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
6997 emitInt(instruction);
6998 }
6999
7000 /**
7001 * Pseudo-external assembler syntax: {@code movn }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
7002 * Example disassembly syntax: {@code movn %icc, -1024, %g0}
7003 * <p>
7004 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
7005 *
7006 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7007 */
7008 // Template#: 414, Serial#: 414
7009 public void movn(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
7010 int instruction = 0x81642000;
7011 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
7012 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7013 instruction |= (simm11 & 0x7ff);
7014 instruction |= ((rd.value() & 0x1f) << 25);
7015 emitInt(instruction);
7016 }
7017
7018 /**
7019 * Pseudo-external assembler syntax: {@code movn }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7020 * Example disassembly syntax: {@code movn %icc, %g0, %g0}
7021 *
7022 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7023 */
7024 // Template#: 415, Serial#: 415
7025 public void movn(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
7026 int instruction = 0x81640000;
7027 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7028 instruction |= (rs2.value() & 0x1f);
7029 instruction |= ((rd.value() & 0x1f) << 25);
7030 emitInt(instruction);
7031 }
7032
7033 /**
7034 * Pseudo-external assembler syntax: {@code fmovsne }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7035 * Example disassembly syntax: {@code fmovsne %icc, %f0, %f0}
7036 *
7037 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7038 */
7039 // Template#: 416, Serial#: 416
7040 public void fmovsne(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
7041 int instruction = 0x81AA6020;
7042 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7043 instruction |= (rs2.value() & 0x1f);
7044 instruction |= ((rd.value() & 0x1f) << 25);
7045 emitInt(instruction);
7046 }
7047
7048 /**
7049 * Pseudo-external assembler syntax: {@code fmovdne }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7050 * Example disassembly syntax: {@code fmovdne %icc, %f0, %f0}
7051 *
7052 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7053 */
7054 // Template#: 417, Serial#: 417
7055 public void fmovdne(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
7056 int instruction = 0x81AA6040;
7057 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7058 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
7059 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
7060 emitInt(instruction);
7061 }
7062
7063 /**
7064 * Pseudo-external assembler syntax: {@code fmovqne }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7065 * Example disassembly syntax: {@code fmovqne %icc, %f0, %f0}
7066 *
7067 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7068 */
7069 // Template#: 418, Serial#: 418
7070 public void fmovqne(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
7071 int instruction = 0x81AA6060;
7072 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7073 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
7074 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
7075 emitInt(instruction);
7076 }
7077
7078 /**
7079 * Pseudo-external assembler syntax: {@code movne }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
7080 * Example disassembly syntax: {@code movne %icc, -1024, %g0}
7081 * <p>
7082 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
7083 *
7084 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7085 */
7086 // Template#: 419, Serial#: 419
7087 public void movne(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
7088 int instruction = 0x81666000;
7089 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
7090 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7091 instruction |= (simm11 & 0x7ff);
7092 instruction |= ((rd.value() & 0x1f) << 25);
7093 emitInt(instruction);
7094 }
7095
7096 /**
7097 * Pseudo-external assembler syntax: {@code movne }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7098 * Example disassembly syntax: {@code movne %icc, %g0, %g0}
7099 *
7100 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7101 */
7102 // Template#: 420, Serial#: 420
7103 public void movne(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
7104 int instruction = 0x81664000;
7105 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7106 instruction |= (rs2.value() & 0x1f);
7107 instruction |= ((rd.value() & 0x1f) << 25);
7108 emitInt(instruction);
7109 }
7110
7111 /**
7112 * Pseudo-external assembler syntax: {@code fmovse }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7113 * Example disassembly syntax: {@code fmovse %icc, %f0, %f0}
7114 *
7115 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7116 */
7117 // Template#: 421, Serial#: 421
7118 public void fmovse(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
7119 int instruction = 0x81A86020;
7120 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7121 instruction |= (rs2.value() & 0x1f);
7122 instruction |= ((rd.value() & 0x1f) << 25);
7123 emitInt(instruction);
7124 }
7125
7126 /**
7127 * Pseudo-external assembler syntax: {@code fmovde }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7128 * Example disassembly syntax: {@code fmovde %icc, %f0, %f0}
7129 *
7130 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7131 */
7132 // Template#: 422, Serial#: 422
7133 public void fmovde(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
7134 int instruction = 0x81A86040;
7135 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7136 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
7137 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
7138 emitInt(instruction);
7139 }
7140
7141 /**
7142 * Pseudo-external assembler syntax: {@code fmovqe }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7143 * Example disassembly syntax: {@code fmovqe %icc, %f0, %f0}
7144 *
7145 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7146 */
7147 // Template#: 423, Serial#: 423
7148 public void fmovqe(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
7149 int instruction = 0x81A86060;
7150 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7151 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
7152 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
7153 emitInt(instruction);
7154 }
7155
7156 /**
7157 * Pseudo-external assembler syntax: {@code move }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
7158 * Example disassembly syntax: {@code move %icc, -1024, %g0}
7159 * <p>
7160 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
7161 *
7162 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7163 */
7164 // Template#: 424, Serial#: 424
7165 public void move(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
7166 int instruction = 0x81646000;
7167 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
7168 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7169 instruction |= (simm11 & 0x7ff);
7170 instruction |= ((rd.value() & 0x1f) << 25);
7171 emitInt(instruction);
7172 }
7173
7174 /**
7175 * Pseudo-external assembler syntax: {@code move }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7176 * Example disassembly syntax: {@code move %icc, %g0, %g0}
7177 *
7178 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7179 */
7180 // Template#: 425, Serial#: 425
7181 public void move(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
7182 int instruction = 0x81644000;
7183 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7184 instruction |= (rs2.value() & 0x1f);
7185 instruction |= ((rd.value() & 0x1f) << 25);
7186 emitInt(instruction);
7187 }
7188
7189 /**
7190 * Pseudo-external assembler syntax: {@code fmovsg }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7191 * Example disassembly syntax: {@code fmovsg %icc, %f0, %f0}
7192 *
7193 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7194 */
7195 // Template#: 426, Serial#: 426
7196 public void fmovsg(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
7197 int instruction = 0x81AAA020;
7198 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7199 instruction |= (rs2.value() & 0x1f);
7200 instruction |= ((rd.value() & 0x1f) << 25);
7201 emitInt(instruction);
7202 }
7203
7204 /**
7205 * Pseudo-external assembler syntax: {@code fmovdg }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7206 * Example disassembly syntax: {@code fmovdg %icc, %f0, %f0}
7207 *
7208 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7209 */
7210 // Template#: 427, Serial#: 427
7211 public void fmovdg(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
7212 int instruction = 0x81AAA040;
7213 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7214 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
7215 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
7216 emitInt(instruction);
7217 }
7218
7219 /**
7220 * Pseudo-external assembler syntax: {@code fmovqg }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7221 * Example disassembly syntax: {@code fmovqg %icc, %f0, %f0}
7222 *
7223 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7224 */
7225 // Template#: 428, Serial#: 428
7226 public void fmovqg(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
7227 int instruction = 0x81AAA060;
7228 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7229 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
7230 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
7231 emitInt(instruction);
7232 }
7233
7234 /**
7235 * Pseudo-external assembler syntax: {@code movg }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
7236 * Example disassembly syntax: {@code movg %icc, -1024, %g0}
7237 * <p>
7238 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
7239 *
7240 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7241 */
7242 // Template#: 429, Serial#: 429
7243 public void movg(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
7244 int instruction = 0x8166A000;
7245 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
7246 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7247 instruction |= (simm11 & 0x7ff);
7248 instruction |= ((rd.value() & 0x1f) << 25);
7249 emitInt(instruction);
7250 }
7251
7252 /**
7253 * Pseudo-external assembler syntax: {@code movg }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7254 * Example disassembly syntax: {@code movg %icc, %g0, %g0}
7255 *
7256 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7257 */
7258 // Template#: 430, Serial#: 430
7259 public void movg(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
7260 int instruction = 0x81668000;
7261 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7262 instruction |= (rs2.value() & 0x1f);
7263 instruction |= ((rd.value() & 0x1f) << 25);
7264 emitInt(instruction);
7265 }
7266
7267 /**
7268 * Pseudo-external assembler syntax: {@code fmovsle }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7269 * Example disassembly syntax: {@code fmovsle %icc, %f0, %f0}
7270 *
7271 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7272 */
7273 // Template#: 431, Serial#: 431
7274 public void fmovsle(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
7275 int instruction = 0x81A8A020;
7276 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7277 instruction |= (rs2.value() & 0x1f);
7278 instruction |= ((rd.value() & 0x1f) << 25);
7279 emitInt(instruction);
7280 }
7281
7282 /**
7283 * Pseudo-external assembler syntax: {@code fmovdle }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7284 * Example disassembly syntax: {@code fmovdle %icc, %f0, %f0}
7285 *
7286 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7287 */
7288 // Template#: 432, Serial#: 432
7289 public void fmovdle(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
7290 int instruction = 0x81A8A040;
7291 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7292 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
7293 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
7294 emitInt(instruction);
7295 }
7296
7297 /**
7298 * Pseudo-external assembler syntax: {@code fmovqle }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7299 * Example disassembly syntax: {@code fmovqle %icc, %f0, %f0}
7300 *
7301 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7302 */
7303 // Template#: 433, Serial#: 433
7304 public void fmovqle(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
7305 int instruction = 0x81A8A060;
7306 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7307 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
7308 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
7309 emitInt(instruction);
7310 }
7311
7312 /**
7313 * Pseudo-external assembler syntax: {@code movle }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
7314 * Example disassembly syntax: {@code movle %icc, -1024, %g0}
7315 * <p>
7316 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
7317 *
7318 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7319 */
7320 // Template#: 434, Serial#: 434
7321 public void movle(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
7322 int instruction = 0x8164A000;
7323 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
7324 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7325 instruction |= (simm11 & 0x7ff);
7326 instruction |= ((rd.value() & 0x1f) << 25);
7327 emitInt(instruction);
7328 }
7329
7330 /**
7331 * Pseudo-external assembler syntax: {@code movle }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7332 * Example disassembly syntax: {@code movle %icc, %g0, %g0}
7333 *
7334 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7335 */
7336 // Template#: 435, Serial#: 435
7337 public void movle(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
7338 int instruction = 0x81648000;
7339 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7340 instruction |= (rs2.value() & 0x1f);
7341 instruction |= ((rd.value() & 0x1f) << 25);
7342 emitInt(instruction);
7343 }
7344
7345 /**
7346 * Pseudo-external assembler syntax: {@code fmovsge }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7347 * Example disassembly syntax: {@code fmovsge %icc, %f0, %f0}
7348 *
7349 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7350 */
7351 // Template#: 436, Serial#: 436
7352 public void fmovsge(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
7353 int instruction = 0x81AAE020;
7354 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7355 instruction |= (rs2.value() & 0x1f);
7356 instruction |= ((rd.value() & 0x1f) << 25);
7357 emitInt(instruction);
7358 }
7359
7360 /**
7361 * Pseudo-external assembler syntax: {@code fmovdge }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7362 * Example disassembly syntax: {@code fmovdge %icc, %f0, %f0}
7363 *
7364 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7365 */
7366 // Template#: 437, Serial#: 437
7367 public void fmovdge(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
7368 int instruction = 0x81AAE040;
7369 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7370 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
7371 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
7372 emitInt(instruction);
7373 }
7374
7375 /**
7376 * Pseudo-external assembler syntax: {@code fmovqge }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7377 * Example disassembly syntax: {@code fmovqge %icc, %f0, %f0}
7378 *
7379 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7380 */
7381 // Template#: 438, Serial#: 438
7382 public void fmovqge(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
7383 int instruction = 0x81AAE060;
7384 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7385 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
7386 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
7387 emitInt(instruction);
7388 }
7389
7390 /**
7391 * Pseudo-external assembler syntax: {@code movge }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
7392 * Example disassembly syntax: {@code movge %icc, -1024, %g0}
7393 * <p>
7394 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
7395 *
7396 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7397 */
7398 // Template#: 439, Serial#: 439
7399 public void movge(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
7400 int instruction = 0x8166E000;
7401 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
7402 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7403 instruction |= (simm11 & 0x7ff);
7404 instruction |= ((rd.value() & 0x1f) << 25);
7405 emitInt(instruction);
7406 }
7407
7408 /**
7409 * Pseudo-external assembler syntax: {@code movge }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7410 * Example disassembly syntax: {@code movge %icc, %g0, %g0}
7411 *
7412 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7413 */
7414 // Template#: 440, Serial#: 440
7415 public void movge(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
7416 int instruction = 0x8166C000;
7417 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7418 instruction |= (rs2.value() & 0x1f);
7419 instruction |= ((rd.value() & 0x1f) << 25);
7420 emitInt(instruction);
7421 }
7422
7423 /**
7424 * Pseudo-external assembler syntax: {@code fmovsl }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7425 * Example disassembly syntax: {@code fmovsl %icc, %f0, %f0}
7426 *
7427 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7428 */
7429 // Template#: 441, Serial#: 441
7430 public void fmovsl(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
7431 int instruction = 0x81A8E020;
7432 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7433 instruction |= (rs2.value() & 0x1f);
7434 instruction |= ((rd.value() & 0x1f) << 25);
7435 emitInt(instruction);
7436 }
7437
7438 /**
7439 * Pseudo-external assembler syntax: {@code fmovdl }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7440 * Example disassembly syntax: {@code fmovdl %icc, %f0, %f0}
7441 *
7442 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7443 */
7444 // Template#: 442, Serial#: 442
7445 public void fmovdl(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
7446 int instruction = 0x81A8E040;
7447 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7448 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
7449 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
7450 emitInt(instruction);
7451 }
7452
7453 /**
7454 * Pseudo-external assembler syntax: {@code fmovql }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7455 * Example disassembly syntax: {@code fmovql %icc, %f0, %f0}
7456 *
7457 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7458 */
7459 // Template#: 443, Serial#: 443
7460 public void fmovql(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
7461 int instruction = 0x81A8E060;
7462 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7463 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
7464 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
7465 emitInt(instruction);
7466 }
7467
7468 /**
7469 * Pseudo-external assembler syntax: {@code movl }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
7470 * Example disassembly syntax: {@code movl %icc, -1024, %g0}
7471 * <p>
7472 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
7473 *
7474 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7475 */
7476 // Template#: 444, Serial#: 444
7477 public void movl(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
7478 int instruction = 0x8164E000;
7479 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
7480 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7481 instruction |= (simm11 & 0x7ff);
7482 instruction |= ((rd.value() & 0x1f) << 25);
7483 emitInt(instruction);
7484 }
7485
7486 /**
7487 * Pseudo-external assembler syntax: {@code movl }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7488 * Example disassembly syntax: {@code movl %icc, %g0, %g0}
7489 *
7490 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7491 */
7492 // Template#: 445, Serial#: 445
7493 public void movl(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
7494 int instruction = 0x8164C000;
7495 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7496 instruction |= (rs2.value() & 0x1f);
7497 instruction |= ((rd.value() & 0x1f) << 25);
7498 emitInt(instruction);
7499 }
7500
7501 /**
7502 * Pseudo-external assembler syntax: {@code fmovsgu }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7503 * Example disassembly syntax: {@code fmovsgu %icc, %f0, %f0}
7504 *
7505 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7506 */
7507 // Template#: 446, Serial#: 446
7508 public void fmovsgu(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
7509 int instruction = 0x81AB2020;
7510 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7511 instruction |= (rs2.value() & 0x1f);
7512 instruction |= ((rd.value() & 0x1f) << 25);
7513 emitInt(instruction);
7514 }
7515
7516 /**
7517 * Pseudo-external assembler syntax: {@code fmovdgu }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7518 * Example disassembly syntax: {@code fmovdgu %icc, %f0, %f0}
7519 *
7520 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7521 */
7522 // Template#: 447, Serial#: 447
7523 public void fmovdgu(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
7524 int instruction = 0x81AB2040;
7525 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7526 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
7527 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
7528 emitInt(instruction);
7529 }
7530
7531 /**
7532 * Pseudo-external assembler syntax: {@code fmovqgu }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7533 * Example disassembly syntax: {@code fmovqgu %icc, %f0, %f0}
7534 *
7535 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7536 */
7537 // Template#: 448, Serial#: 448
7538 public void fmovqgu(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
7539 int instruction = 0x81AB2060;
7540 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7541 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
7542 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
7543 emitInt(instruction);
7544 }
7545
7546 /**
7547 * Pseudo-external assembler syntax: {@code movgu }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
7548 * Example disassembly syntax: {@code movgu %icc, -1024, %g0}
7549 * <p>
7550 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
7551 *
7552 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7553 */
7554 // Template#: 449, Serial#: 449
7555 public void movgu(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
7556 int instruction = 0x81672000;
7557 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
7558 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7559 instruction |= (simm11 & 0x7ff);
7560 instruction |= ((rd.value() & 0x1f) << 25);
7561 emitInt(instruction);
7562 }
7563
7564 /**
7565 * Pseudo-external assembler syntax: {@code movgu }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7566 * Example disassembly syntax: {@code movgu %icc, %g0, %g0}
7567 *
7568 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7569 */
7570 // Template#: 450, Serial#: 450
7571 public void movgu(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
7572 int instruction = 0x81670000;
7573 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7574 instruction |= (rs2.value() & 0x1f);
7575 instruction |= ((rd.value() & 0x1f) << 25);
7576 emitInt(instruction);
7577 }
7578
7579 /**
7580 * Pseudo-external assembler syntax: {@code fmovsleu }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7581 * Example disassembly syntax: {@code fmovsleu %icc, %f0, %f0}
7582 *
7583 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7584 */
7585 // Template#: 451, Serial#: 451
7586 public void fmovsleu(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
7587 int instruction = 0x81A92020;
7588 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7589 instruction |= (rs2.value() & 0x1f);
7590 instruction |= ((rd.value() & 0x1f) << 25);
7591 emitInt(instruction);
7592 }
7593
7594 /**
7595 * Pseudo-external assembler syntax: {@code fmovdleu }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7596 * Example disassembly syntax: {@code fmovdleu %icc, %f0, %f0}
7597 *
7598 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7599 */
7600 // Template#: 452, Serial#: 452
7601 public void fmovdleu(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
7602 int instruction = 0x81A92040;
7603 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7604 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
7605 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
7606 emitInt(instruction);
7607 }
7608
7609 /**
7610 * Pseudo-external assembler syntax: {@code fmovqleu }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7611 * Example disassembly syntax: {@code fmovqleu %icc, %f0, %f0}
7612 *
7613 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7614 */
7615 // Template#: 453, Serial#: 453
7616 public void fmovqleu(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
7617 int instruction = 0x81A92060;
7618 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7619 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
7620 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
7621 emitInt(instruction);
7622 }
7623
7624 /**
7625 * Pseudo-external assembler syntax: {@code movleu }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
7626 * Example disassembly syntax: {@code movleu %icc, -1024, %g0}
7627 * <p>
7628 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
7629 *
7630 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7631 */
7632 // Template#: 454, Serial#: 454
7633 public void movleu(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
7634 int instruction = 0x81652000;
7635 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
7636 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7637 instruction |= (simm11 & 0x7ff);
7638 instruction |= ((rd.value() & 0x1f) << 25);
7639 emitInt(instruction);
7640 }
7641
7642 /**
7643 * Pseudo-external assembler syntax: {@code movleu }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7644 * Example disassembly syntax: {@code movleu %icc, %g0, %g0}
7645 *
7646 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7647 */
7648 // Template#: 455, Serial#: 455
7649 public void movleu(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
7650 int instruction = 0x81650000;
7651 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7652 instruction |= (rs2.value() & 0x1f);
7653 instruction |= ((rd.value() & 0x1f) << 25);
7654 emitInt(instruction);
7655 }
7656
7657 /**
7658 * Pseudo-external assembler syntax: {@code fmovscc }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7659 * Example disassembly syntax: {@code fmovscc %icc, %f0, %f0}
7660 *
7661 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7662 */
7663 // Template#: 456, Serial#: 456
7664 public void fmovscc(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
7665 int instruction = 0x81AB6020;
7666 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7667 instruction |= (rs2.value() & 0x1f);
7668 instruction |= ((rd.value() & 0x1f) << 25);
7669 emitInt(instruction);
7670 }
7671
7672 /**
7673 * Pseudo-external assembler syntax: {@code fmovdcc }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7674 * Example disassembly syntax: {@code fmovdcc %icc, %f0, %f0}
7675 *
7676 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7677 */
7678 // Template#: 457, Serial#: 457
7679 public void fmovdcc(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
7680 int instruction = 0x81AB6040;
7681 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7682 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
7683 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
7684 emitInt(instruction);
7685 }
7686
7687 /**
7688 * Pseudo-external assembler syntax: {@code fmovqcc }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7689 * Example disassembly syntax: {@code fmovqcc %icc, %f0, %f0}
7690 *
7691 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7692 */
7693 // Template#: 458, Serial#: 458
7694 public void fmovqcc(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
7695 int instruction = 0x81AB6060;
7696 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7697 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
7698 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
7699 emitInt(instruction);
7700 }
7701
7702 /**
7703 * Pseudo-external assembler syntax: {@code movcc }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
7704 * Example disassembly syntax: {@code movcc %icc, -1024, %g0}
7705 * <p>
7706 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
7707 *
7708 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7709 */
7710 // Template#: 459, Serial#: 459
7711 public void movcc(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
7712 int instruction = 0x81676000;
7713 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
7714 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7715 instruction |= (simm11 & 0x7ff);
7716 instruction |= ((rd.value() & 0x1f) << 25);
7717 emitInt(instruction);
7718 }
7719
7720 /**
7721 * Pseudo-external assembler syntax: {@code movcc }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7722 * Example disassembly syntax: {@code movcc %icc, %g0, %g0}
7723 *
7724 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7725 */
7726 // Template#: 460, Serial#: 460
7727 public void movcc(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
7728 int instruction = 0x81674000;
7729 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7730 instruction |= (rs2.value() & 0x1f);
7731 instruction |= ((rd.value() & 0x1f) << 25);
7732 emitInt(instruction);
7733 }
7734
7735 /**
7736 * Pseudo-external assembler syntax: {@code fmovscs }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7737 * Example disassembly syntax: {@code fmovscs %icc, %f0, %f0}
7738 *
7739 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7740 */
7741 // Template#: 461, Serial#: 461
7742 public void fmovscs(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
7743 int instruction = 0x81A96020;
7744 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7745 instruction |= (rs2.value() & 0x1f);
7746 instruction |= ((rd.value() & 0x1f) << 25);
7747 emitInt(instruction);
7748 }
7749
7750 /**
7751 * Pseudo-external assembler syntax: {@code fmovdcs }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7752 * Example disassembly syntax: {@code fmovdcs %icc, %f0, %f0}
7753 *
7754 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7755 */
7756 // Template#: 462, Serial#: 462
7757 public void fmovdcs(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
7758 int instruction = 0x81A96040;
7759 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7760 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
7761 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
7762 emitInt(instruction);
7763 }
7764
7765 /**
7766 * Pseudo-external assembler syntax: {@code fmovqcs }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7767 * Example disassembly syntax: {@code fmovqcs %icc, %f0, %f0}
7768 *
7769 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7770 */
7771 // Template#: 463, Serial#: 463
7772 public void fmovqcs(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
7773 int instruction = 0x81A96060;
7774 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7775 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
7776 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
7777 emitInt(instruction);
7778 }
7779
7780 /**
7781 * Pseudo-external assembler syntax: {@code movcs }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
7782 * Example disassembly syntax: {@code movcs %icc, -1024, %g0}
7783 * <p>
7784 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
7785 *
7786 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7787 */
7788 // Template#: 464, Serial#: 464
7789 public void movcs(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
7790 int instruction = 0x81656000;
7791 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
7792 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7793 instruction |= (simm11 & 0x7ff);
7794 instruction |= ((rd.value() & 0x1f) << 25);
7795 emitInt(instruction);
7796 }
7797
7798 /**
7799 * Pseudo-external assembler syntax: {@code movcs }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7800 * Example disassembly syntax: {@code movcs %icc, %g0, %g0}
7801 *
7802 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7803 */
7804 // Template#: 465, Serial#: 465
7805 public void movcs(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
7806 int instruction = 0x81654000;
7807 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7808 instruction |= (rs2.value() & 0x1f);
7809 instruction |= ((rd.value() & 0x1f) << 25);
7810 emitInt(instruction);
7811 }
7812
7813 /**
7814 * Pseudo-external assembler syntax: {@code fmovspos }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7815 * Example disassembly syntax: {@code fmovspos %icc, %f0, %f0}
7816 *
7817 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7818 */
7819 // Template#: 466, Serial#: 466
7820 public void fmovspos(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
7821 int instruction = 0x81ABA020;
7822 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7823 instruction |= (rs2.value() & 0x1f);
7824 instruction |= ((rd.value() & 0x1f) << 25);
7825 emitInt(instruction);
7826 }
7827
7828 /**
7829 * Pseudo-external assembler syntax: {@code fmovdpos }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7830 * Example disassembly syntax: {@code fmovdpos %icc, %f0, %f0}
7831 *
7832 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7833 */
7834 // Template#: 467, Serial#: 467
7835 public void fmovdpos(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
7836 int instruction = 0x81ABA040;
7837 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7838 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
7839 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
7840 emitInt(instruction);
7841 }
7842
7843 /**
7844 * Pseudo-external assembler syntax: {@code fmovqpos }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7845 * Example disassembly syntax: {@code fmovqpos %icc, %f0, %f0}
7846 *
7847 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7848 */
7849 // Template#: 468, Serial#: 468
7850 public void fmovqpos(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
7851 int instruction = 0x81ABA060;
7852 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7853 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
7854 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
7855 emitInt(instruction);
7856 }
7857
7858 /**
7859 * Pseudo-external assembler syntax: {@code movpos }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
7860 * Example disassembly syntax: {@code movpos %icc, -1024, %g0}
7861 * <p>
7862 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
7863 *
7864 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7865 */
7866 // Template#: 469, Serial#: 469
7867 public void movpos(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
7868 int instruction = 0x8167A000;
7869 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
7870 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7871 instruction |= (simm11 & 0x7ff);
7872 instruction |= ((rd.value() & 0x1f) << 25);
7873 emitInt(instruction);
7874 }
7875
7876 /**
7877 * Pseudo-external assembler syntax: {@code movpos }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7878 * Example disassembly syntax: {@code movpos %icc, %g0, %g0}
7879 *
7880 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7881 */
7882 // Template#: 470, Serial#: 470
7883 public void movpos(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
7884 int instruction = 0x81678000;
7885 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7886 instruction |= (rs2.value() & 0x1f);
7887 instruction |= ((rd.value() & 0x1f) << 25);
7888 emitInt(instruction);
7889 }
7890
7891 /**
7892 * Pseudo-external assembler syntax: {@code fmovsneg }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7893 * Example disassembly syntax: {@code fmovsneg %icc, %f0, %f0}
7894 *
7895 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7896 */
7897 // Template#: 471, Serial#: 471
7898 public void fmovsneg(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
7899 int instruction = 0x81A9A020;
7900 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7901 instruction |= (rs2.value() & 0x1f);
7902 instruction |= ((rd.value() & 0x1f) << 25);
7903 emitInt(instruction);
7904 }
7905
7906 /**
7907 * Pseudo-external assembler syntax: {@code fmovdneg }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7908 * Example disassembly syntax: {@code fmovdneg %icc, %f0, %f0}
7909 *
7910 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7911 */
7912 // Template#: 472, Serial#: 472
7913 public void fmovdneg(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
7914 int instruction = 0x81A9A040;
7915 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7916 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
7917 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
7918 emitInt(instruction);
7919 }
7920
7921 /**
7922 * Pseudo-external assembler syntax: {@code fmovqneg }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7923 * Example disassembly syntax: {@code fmovqneg %icc, %f0, %f0}
7924 *
7925 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7926 */
7927 // Template#: 473, Serial#: 473
7928 public void fmovqneg(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
7929 int instruction = 0x81A9A060;
7930 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7931 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
7932 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
7933 emitInt(instruction);
7934 }
7935
7936 /**
7937 * Pseudo-external assembler syntax: {@code movneg }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
7938 * Example disassembly syntax: {@code movneg %icc, -1024, %g0}
7939 * <p>
7940 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
7941 *
7942 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7943 */
7944 // Template#: 474, Serial#: 474
7945 public void movneg(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
7946 int instruction = 0x8165A000;
7947 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
7948 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7949 instruction |= (simm11 & 0x7ff);
7950 instruction |= ((rd.value() & 0x1f) << 25);
7951 emitInt(instruction);
7952 }
7953
7954 /**
7955 * Pseudo-external assembler syntax: {@code movneg }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7956 * Example disassembly syntax: {@code movneg %icc, %g0, %g0}
7957 *
7958 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
7959 */
7960 // Template#: 475, Serial#: 475
7961 public void movneg(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
7962 int instruction = 0x81658000;
7963 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7964 instruction |= (rs2.value() & 0x1f);
7965 instruction |= ((rd.value() & 0x1f) << 25);
7966 emitInt(instruction);
7967 }
7968
7969 /**
7970 * Pseudo-external assembler syntax: {@code fmovsvc }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7971 * Example disassembly syntax: {@code fmovsvc %icc, %f0, %f0}
7972 *
7973 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7974 */
7975 // Template#: 476, Serial#: 476
7976 public void fmovsvc(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
7977 int instruction = 0x81ABE020;
7978 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7979 instruction |= (rs2.value() & 0x1f);
7980 instruction |= ((rd.value() & 0x1f) << 25);
7981 emitInt(instruction);
7982 }
7983
7984 /**
7985 * Pseudo-external assembler syntax: {@code fmovdvc }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
7986 * Example disassembly syntax: {@code fmovdvc %icc, %f0, %f0}
7987 *
7988 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
7989 */
7990 // Template#: 477, Serial#: 477
7991 public void fmovdvc(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
7992 int instruction = 0x81ABE040;
7993 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
7994 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
7995 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
7996 emitInt(instruction);
7997 }
7998
7999 /**
8000 * Pseudo-external assembler syntax: {@code fmovqvc }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
8001 * Example disassembly syntax: {@code fmovqvc %icc, %f0, %f0}
8002 *
8003 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8004 */
8005 // Template#: 478, Serial#: 478
8006 public void fmovqvc(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
8007 int instruction = 0x81ABE060;
8008 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
8009 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
8010 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
8011 emitInt(instruction);
8012 }
8013
8014 /**
8015 * Pseudo-external assembler syntax: {@code movvc }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
8016 * Example disassembly syntax: {@code movvc %icc, -1024, %g0}
8017 * <p>
8018 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
8019 *
8020 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8021 */
8022 // Template#: 479, Serial#: 479
8023 public void movvc(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
8024 int instruction = 0x8167E000;
8025 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
8026 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
8027 instruction |= (simm11 & 0x7ff);
8028 instruction |= ((rd.value() & 0x1f) << 25);
8029 emitInt(instruction);
8030 }
8031
8032 /**
8033 * Pseudo-external assembler syntax: {@code movvc }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
8034 * Example disassembly syntax: {@code movvc %icc, %g0, %g0}
8035 *
8036 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8037 */
8038 // Template#: 480, Serial#: 480
8039 public void movvc(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
8040 int instruction = 0x8167C000;
8041 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
8042 instruction |= (rs2.value() & 0x1f);
8043 instruction |= ((rd.value() & 0x1f) << 25);
8044 emitInt(instruction);
8045 }
8046
8047 /**
8048 * Pseudo-external assembler syntax: {@code fmovsvs }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
8049 * Example disassembly syntax: {@code fmovsvs %icc, %f0, %f0}
8050 *
8051 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8052 */
8053 // Template#: 481, Serial#: 481
8054 public void fmovsvs(final ICCOperand i_or_x_cc, final SFPR rs2, final SFPR rd) {
8055 int instruction = 0x81A9E020;
8056 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
8057 instruction |= (rs2.value() & 0x1f);
8058 instruction |= ((rd.value() & 0x1f) << 25);
8059 emitInt(instruction);
8060 }
8061
8062 /**
8063 * Pseudo-external assembler syntax: {@code fmovdvs }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
8064 * Example disassembly syntax: {@code fmovdvs %icc, %f0, %f0}
8065 *
8066 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8067 */
8068 // Template#: 482, Serial#: 482
8069 public void fmovdvs(final ICCOperand i_or_x_cc, final DFPR rs2, final DFPR rd) {
8070 int instruction = 0x81A9E040;
8071 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
8072 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
8073 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
8074 emitInt(instruction);
8075 }
8076
8077 /**
8078 * Pseudo-external assembler syntax: {@code fmovqvs }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
8079 * Example disassembly syntax: {@code fmovqvs %icc, %f0, %f0}
8080 *
8081 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8082 */
8083 // Template#: 483, Serial#: 483
8084 public void fmovqvs(final ICCOperand i_or_x_cc, final QFPR rs2, final QFPR rd) {
8085 int instruction = 0x81A9E060;
8086 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
8087 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
8088 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
8089 emitInt(instruction);
8090 }
8091
8092 /**
8093 * Pseudo-external assembler syntax: {@code movvs }<i>i_or_x_cc</i>, <i>simm11</i>, <i>rd</i>
8094 * Example disassembly syntax: {@code movvs %icc, -1024, %g0}
8095 * <p>
8096 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
8097 *
8098 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8099 */
8100 // Template#: 484, Serial#: 484
8101 public void movvs(final ICCOperand i_or_x_cc, final int simm11, final GPR rd) {
8102 int instruction = 0x8165E000;
8103 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
8104 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
8105 instruction |= (simm11 & 0x7ff);
8106 instruction |= ((rd.value() & 0x1f) << 25);
8107 emitInt(instruction);
8108 }
8109
8110 /**
8111 * Pseudo-external assembler syntax: {@code movvs }<i>i_or_x_cc</i>, <i>rs2</i>, <i>rd</i>
8112 * Example disassembly syntax: {@code movvs %icc, %g0, %g0}
8113 *
8114 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8115 */
8116 // Template#: 485, Serial#: 485
8117 public void movvs(final ICCOperand i_or_x_cc, final GPR rs2, final GPR rd) {
8118 int instruction = 0x8165C000;
8119 instruction |= ((i_or_x_cc.value() & 0x3) << 11);
8120 instruction |= (rs2.value() & 0x1f);
8121 instruction |= ((rd.value() & 0x1f) << 25);
8122 emitInt(instruction);
8123 }
8124
8125 /**
8126 * Pseudo-external assembler syntax: {@code fmovsa }<i>n</i>, <i>rs2</i>, <i>rd</i>
8127 * Example disassembly syntax: {@code fmovsa %fcc0, %f0, %f0}
8128 *
8129 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8130 */
8131 // Template#: 486, Serial#: 486
8132 public void fmovsa(final FCCOperand n, final SFPR rs2, final SFPR rd) {
8133 int instruction = 0x81AA0020;
8134 instruction |= ((n.value() & 0x3) << 11);
8135 instruction |= (rs2.value() & 0x1f);
8136 instruction |= ((rd.value() & 0x1f) << 25);
8137 emitInt(instruction);
8138 }
8139
8140 /**
8141 * Pseudo-external assembler syntax: {@code fmovda }<i>n</i>, <i>rs2</i>, <i>rd</i>
8142 * Example disassembly syntax: {@code fmovda %fcc0, %f0, %f0}
8143 *
8144 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8145 */
8146 // Template#: 487, Serial#: 487
8147 public void fmovda(final FCCOperand n, final DFPR rs2, final DFPR rd) {
8148 int instruction = 0x81AA0040;
8149 instruction |= ((n.value() & 0x3) << 11);
8150 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
8151 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
8152 emitInt(instruction);
8153 }
8154
8155 /**
8156 * Pseudo-external assembler syntax: {@code fmovqa }<i>n</i>, <i>rs2</i>, <i>rd</i>
8157 * Example disassembly syntax: {@code fmovqa %fcc0, %f0, %f0}
8158 *
8159 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8160 */
8161 // Template#: 488, Serial#: 488
8162 public void fmovqa(final FCCOperand n, final QFPR rs2, final QFPR rd) {
8163 int instruction = 0x81AA0060;
8164 instruction |= ((n.value() & 0x3) << 11);
8165 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
8166 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
8167 emitInt(instruction);
8168 }
8169
8170 /**
8171 * Pseudo-external assembler syntax: {@code mova }<i>n</i>, <i>simm11</i>, <i>rd</i>
8172 * Example disassembly syntax: {@code mova %fcc0, -1024, %g0}
8173 * <p>
8174 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
8175 *
8176 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8177 */
8178 // Template#: 489, Serial#: 489
8179 public void mova(final FCCOperand n, final int simm11, final GPR rd) {
8180 int instruction = 0x81622000;
8181 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
8182 instruction |= ((n.value() & 0x3) << 11);
8183 instruction |= (simm11 & 0x7ff);
8184 instruction |= ((rd.value() & 0x1f) << 25);
8185 emitInt(instruction);
8186 }
8187
8188 /**
8189 * Pseudo-external assembler syntax: {@code mova }<i>n</i>, <i>rs2</i>, <i>rd</i>
8190 * Example disassembly syntax: {@code mova %fcc0, %g0, %g0}
8191 *
8192 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8193 */
8194 // Template#: 490, Serial#: 490
8195 public void mova(final FCCOperand n, final GPR rs2, final GPR rd) {
8196 int instruction = 0x81620000;
8197 instruction |= ((n.value() & 0x3) << 11);
8198 instruction |= (rs2.value() & 0x1f);
8199 instruction |= ((rd.value() & 0x1f) << 25);
8200 emitInt(instruction);
8201 }
8202
8203 /**
8204 * Pseudo-external assembler syntax: {@code fmovsn }<i>n</i>, <i>rs2</i>, <i>rd</i>
8205 * Example disassembly syntax: {@code fmovsn %fcc0, %f0, %f0}
8206 *
8207 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8208 */
8209 // Template#: 491, Serial#: 491
8210 public void fmovsn(final FCCOperand n, final SFPR rs2, final SFPR rd) {
8211 int instruction = 0x81A80020;
8212 instruction |= ((n.value() & 0x3) << 11);
8213 instruction |= (rs2.value() & 0x1f);
8214 instruction |= ((rd.value() & 0x1f) << 25);
8215 emitInt(instruction);
8216 }
8217
8218 /**
8219 * Pseudo-external assembler syntax: {@code fmovdn }<i>n</i>, <i>rs2</i>, <i>rd</i>
8220 * Example disassembly syntax: {@code fmovdn %fcc0, %f0, %f0}
8221 *
8222 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8223 */
8224 // Template#: 492, Serial#: 492
8225 public void fmovdn(final FCCOperand n, final DFPR rs2, final DFPR rd) {
8226 int instruction = 0x81A80040;
8227 instruction |= ((n.value() & 0x3) << 11);
8228 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
8229 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
8230 emitInt(instruction);
8231 }
8232
8233 /**
8234 * Pseudo-external assembler syntax: {@code fmovqn }<i>n</i>, <i>rs2</i>, <i>rd</i>
8235 * Example disassembly syntax: {@code fmovqn %fcc0, %f0, %f0}
8236 *
8237 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8238 */
8239 // Template#: 493, Serial#: 493
8240 public void fmovqn(final FCCOperand n, final QFPR rs2, final QFPR rd) {
8241 int instruction = 0x81A80060;
8242 instruction |= ((n.value() & 0x3) << 11);
8243 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
8244 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
8245 emitInt(instruction);
8246 }
8247
8248 /**
8249 * Pseudo-external assembler syntax: {@code movn }<i>n</i>, <i>simm11</i>, <i>rd</i>
8250 * Example disassembly syntax: {@code movn %fcc0, -1024, %g0}
8251 * <p>
8252 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
8253 *
8254 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8255 */
8256 // Template#: 494, Serial#: 494
8257 public void movn(final FCCOperand n, final int simm11, final GPR rd) {
8258 int instruction = 0x81602000;
8259 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
8260 instruction |= ((n.value() & 0x3) << 11);
8261 instruction |= (simm11 & 0x7ff);
8262 instruction |= ((rd.value() & 0x1f) << 25);
8263 emitInt(instruction);
8264 }
8265
8266 /**
8267 * Pseudo-external assembler syntax: {@code movn }<i>n</i>, <i>rs2</i>, <i>rd</i>
8268 * Example disassembly syntax: {@code movn %fcc0, %g0, %g0}
8269 *
8270 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8271 */
8272 // Template#: 495, Serial#: 495
8273 public void movn(final FCCOperand n, final GPR rs2, final GPR rd) {
8274 int instruction = 0x81600000;
8275 instruction |= ((n.value() & 0x3) << 11);
8276 instruction |= (rs2.value() & 0x1f);
8277 instruction |= ((rd.value() & 0x1f) << 25);
8278 emitInt(instruction);
8279 }
8280
8281 /**
8282 * Pseudo-external assembler syntax: {@code fmovsu }<i>n</i>, <i>rs2</i>, <i>rd</i>
8283 * Example disassembly syntax: {@code fmovsu %fcc0, %f0, %f0}
8284 *
8285 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8286 */
8287 // Template#: 496, Serial#: 496
8288 public void fmovsu(final FCCOperand n, final SFPR rs2, final SFPR rd) {
8289 int instruction = 0x81A9C020;
8290 instruction |= ((n.value() & 0x3) << 11);
8291 instruction |= (rs2.value() & 0x1f);
8292 instruction |= ((rd.value() & 0x1f) << 25);
8293 emitInt(instruction);
8294 }
8295
8296 /**
8297 * Pseudo-external assembler syntax: {@code fmovdu }<i>n</i>, <i>rs2</i>, <i>rd</i>
8298 * Example disassembly syntax: {@code fmovdu %fcc0, %f0, %f0}
8299 *
8300 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8301 */
8302 // Template#: 497, Serial#: 497
8303 public void fmovdu(final FCCOperand n, final DFPR rs2, final DFPR rd) {
8304 int instruction = 0x81A9C040;
8305 instruction |= ((n.value() & 0x3) << 11);
8306 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
8307 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
8308 emitInt(instruction);
8309 }
8310
8311 /**
8312 * Pseudo-external assembler syntax: {@code fmovqu }<i>n</i>, <i>rs2</i>, <i>rd</i>
8313 * Example disassembly syntax: {@code fmovqu %fcc0, %f0, %f0}
8314 *
8315 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8316 */
8317 // Template#: 498, Serial#: 498
8318 public void fmovqu(final FCCOperand n, final QFPR rs2, final QFPR rd) {
8319 int instruction = 0x81A9C060;
8320 instruction |= ((n.value() & 0x3) << 11);
8321 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
8322 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
8323 emitInt(instruction);
8324 }
8325
8326 /**
8327 * Pseudo-external assembler syntax: {@code movu }<i>n</i>, <i>simm11</i>, <i>rd</i>
8328 * Example disassembly syntax: {@code movu %fcc0, -1024, %g0}
8329 * <p>
8330 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
8331 *
8332 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8333 */
8334 // Template#: 499, Serial#: 499
8335 public void movu(final FCCOperand n, final int simm11, final GPR rd) {
8336 int instruction = 0x8161E000;
8337 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
8338 instruction |= ((n.value() & 0x3) << 11);
8339 instruction |= (simm11 & 0x7ff);
8340 instruction |= ((rd.value() & 0x1f) << 25);
8341 emitInt(instruction);
8342 }
8343
8344 /**
8345 * Pseudo-external assembler syntax: {@code movu }<i>n</i>, <i>rs2</i>, <i>rd</i>
8346 * Example disassembly syntax: {@code movu %fcc0, %g0, %g0}
8347 *
8348 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8349 */
8350 // Template#: 500, Serial#: 500
8351 public void movu(final FCCOperand n, final GPR rs2, final GPR rd) {
8352 int instruction = 0x8161C000;
8353 instruction |= ((n.value() & 0x3) << 11);
8354 instruction |= (rs2.value() & 0x1f);
8355 instruction |= ((rd.value() & 0x1f) << 25);
8356 emitInt(instruction);
8357 }
8358
8359 /**
8360 * Pseudo-external assembler syntax: {@code fmovsg }<i>n</i>, <i>rs2</i>, <i>rd</i>
8361 * Example disassembly syntax: {@code fmovsg %fcc0, %f0, %f0}
8362 *
8363 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8364 */
8365 // Template#: 501, Serial#: 501
8366 public void fmovsg(final FCCOperand n, final SFPR rs2, final SFPR rd) {
8367 int instruction = 0x81A98020;
8368 instruction |= ((n.value() & 0x3) << 11);
8369 instruction |= (rs2.value() & 0x1f);
8370 instruction |= ((rd.value() & 0x1f) << 25);
8371 emitInt(instruction);
8372 }
8373
8374 /**
8375 * Pseudo-external assembler syntax: {@code fmovdg }<i>n</i>, <i>rs2</i>, <i>rd</i>
8376 * Example disassembly syntax: {@code fmovdg %fcc0, %f0, %f0}
8377 *
8378 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8379 */
8380 // Template#: 502, Serial#: 502
8381 public void fmovdg(final FCCOperand n, final DFPR rs2, final DFPR rd) {
8382 int instruction = 0x81A98040;
8383 instruction |= ((n.value() & 0x3) << 11);
8384 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
8385 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
8386 emitInt(instruction);
8387 }
8388
8389 /**
8390 * Pseudo-external assembler syntax: {@code fmovqg }<i>n</i>, <i>rs2</i>, <i>rd</i>
8391 * Example disassembly syntax: {@code fmovqg %fcc0, %f0, %f0}
8392 *
8393 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8394 */
8395 // Template#: 503, Serial#: 503
8396 public void fmovqg(final FCCOperand n, final QFPR rs2, final QFPR rd) {
8397 int instruction = 0x81A98060;
8398 instruction |= ((n.value() & 0x3) << 11);
8399 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
8400 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
8401 emitInt(instruction);
8402 }
8403
8404 /**
8405 * Pseudo-external assembler syntax: {@code movg }<i>n</i>, <i>simm11</i>, <i>rd</i>
8406 * Example disassembly syntax: {@code movg %fcc0, -1024, %g0}
8407 * <p>
8408 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
8409 *
8410 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8411 */
8412 // Template#: 504, Serial#: 504
8413 public void movg(final FCCOperand n, final int simm11, final GPR rd) {
8414 int instruction = 0x8161A000;
8415 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
8416 instruction |= ((n.value() & 0x3) << 11);
8417 instruction |= (simm11 & 0x7ff);
8418 instruction |= ((rd.value() & 0x1f) << 25);
8419 emitInt(instruction);
8420 }
8421
8422 /**
8423 * Pseudo-external assembler syntax: {@code movg }<i>n</i>, <i>rs2</i>, <i>rd</i>
8424 * Example disassembly syntax: {@code movg %fcc0, %g0, %g0}
8425 *
8426 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8427 */
8428 // Template#: 505, Serial#: 505
8429 public void movg(final FCCOperand n, final GPR rs2, final GPR rd) {
8430 int instruction = 0x81618000;
8431 instruction |= ((n.value() & 0x3) << 11);
8432 instruction |= (rs2.value() & 0x1f);
8433 instruction |= ((rd.value() & 0x1f) << 25);
8434 emitInt(instruction);
8435 }
8436
8437 /**
8438 * Pseudo-external assembler syntax: {@code fmovsug }<i>n</i>, <i>rs2</i>, <i>rd</i>
8439 * Example disassembly syntax: {@code fmovsug %fcc0, %f0, %f0}
8440 *
8441 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8442 */
8443 // Template#: 506, Serial#: 506
8444 public void fmovsug(final FCCOperand n, final SFPR rs2, final SFPR rd) {
8445 int instruction = 0x81A94020;
8446 instruction |= ((n.value() & 0x3) << 11);
8447 instruction |= (rs2.value() & 0x1f);
8448 instruction |= ((rd.value() & 0x1f) << 25);
8449 emitInt(instruction);
8450 }
8451
8452 /**
8453 * Pseudo-external assembler syntax: {@code fmovdug }<i>n</i>, <i>rs2</i>, <i>rd</i>
8454 * Example disassembly syntax: {@code fmovdug %fcc0, %f0, %f0}
8455 *
8456 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8457 */
8458 // Template#: 507, Serial#: 507
8459 public void fmovdug(final FCCOperand n, final DFPR rs2, final DFPR rd) {
8460 int instruction = 0x81A94040;
8461 instruction |= ((n.value() & 0x3) << 11);
8462 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
8463 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
8464 emitInt(instruction);
8465 }
8466
8467 /**
8468 * Pseudo-external assembler syntax: {@code fmovqug }<i>n</i>, <i>rs2</i>, <i>rd</i>
8469 * Example disassembly syntax: {@code fmovqug %fcc0, %f0, %f0}
8470 *
8471 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8472 */
8473 // Template#: 508, Serial#: 508
8474 public void fmovqug(final FCCOperand n, final QFPR rs2, final QFPR rd) {
8475 int instruction = 0x81A94060;
8476 instruction |= ((n.value() & 0x3) << 11);
8477 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
8478 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
8479 emitInt(instruction);
8480 }
8481
8482 /**
8483 * Pseudo-external assembler syntax: {@code movug }<i>n</i>, <i>simm11</i>, <i>rd</i>
8484 * Example disassembly syntax: {@code movug %fcc0, -1024, %g0}
8485 * <p>
8486 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
8487 *
8488 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8489 */
8490 // Template#: 509, Serial#: 509
8491 public void movug(final FCCOperand n, final int simm11, final GPR rd) {
8492 int instruction = 0x81616000;
8493 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
8494 instruction |= ((n.value() & 0x3) << 11);
8495 instruction |= (simm11 & 0x7ff);
8496 instruction |= ((rd.value() & 0x1f) << 25);
8497 emitInt(instruction);
8498 }
8499
8500 /**
8501 * Pseudo-external assembler syntax: {@code movug }<i>n</i>, <i>rs2</i>, <i>rd</i>
8502 * Example disassembly syntax: {@code movug %fcc0, %g0, %g0}
8503 *
8504 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8505 */
8506 // Template#: 510, Serial#: 510
8507 public void movug(final FCCOperand n, final GPR rs2, final GPR rd) {
8508 int instruction = 0x81614000;
8509 instruction |= ((n.value() & 0x3) << 11);
8510 instruction |= (rs2.value() & 0x1f);
8511 instruction |= ((rd.value() & 0x1f) << 25);
8512 emitInt(instruction);
8513 }
8514
8515 /**
8516 * Pseudo-external assembler syntax: {@code fmovsl }<i>n</i>, <i>rs2</i>, <i>rd</i>
8517 * Example disassembly syntax: {@code fmovsl %fcc0, %f0, %f0}
8518 *
8519 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8520 */
8521 // Template#: 511, Serial#: 511
8522 public void fmovsl(final FCCOperand n, final SFPR rs2, final SFPR rd) {
8523 int instruction = 0x81A90020;
8524 instruction |= ((n.value() & 0x3) << 11);
8525 instruction |= (rs2.value() & 0x1f);
8526 instruction |= ((rd.value() & 0x1f) << 25);
8527 emitInt(instruction);
8528 }
8529
8530 /**
8531 * Pseudo-external assembler syntax: {@code fmovdl }<i>n</i>, <i>rs2</i>, <i>rd</i>
8532 * Example disassembly syntax: {@code fmovdl %fcc0, %f0, %f0}
8533 *
8534 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8535 */
8536 // Template#: 512, Serial#: 512
8537 public void fmovdl(final FCCOperand n, final DFPR rs2, final DFPR rd) {
8538 int instruction = 0x81A90040;
8539 instruction |= ((n.value() & 0x3) << 11);
8540 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
8541 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
8542 emitInt(instruction);
8543 }
8544
8545 /**
8546 * Pseudo-external assembler syntax: {@code fmovql }<i>n</i>, <i>rs2</i>, <i>rd</i>
8547 * Example disassembly syntax: {@code fmovql %fcc0, %f0, %f0}
8548 *
8549 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8550 */
8551 // Template#: 513, Serial#: 513
8552 public void fmovql(final FCCOperand n, final QFPR rs2, final QFPR rd) {
8553 int instruction = 0x81A90060;
8554 instruction |= ((n.value() & 0x3) << 11);
8555 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
8556 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
8557 emitInt(instruction);
8558 }
8559
8560 /**
8561 * Pseudo-external assembler syntax: {@code movl }<i>n</i>, <i>simm11</i>, <i>rd</i>
8562 * Example disassembly syntax: {@code movl %fcc0, -1024, %g0}
8563 * <p>
8564 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
8565 *
8566 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8567 */
8568 // Template#: 514, Serial#: 514
8569 public void movl(final FCCOperand n, final int simm11, final GPR rd) {
8570 int instruction = 0x81612000;
8571 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
8572 instruction |= ((n.value() & 0x3) << 11);
8573 instruction |= (simm11 & 0x7ff);
8574 instruction |= ((rd.value() & 0x1f) << 25);
8575 emitInt(instruction);
8576 }
8577
8578 /**
8579 * Pseudo-external assembler syntax: {@code movl }<i>n</i>, <i>rs2</i>, <i>rd</i>
8580 * Example disassembly syntax: {@code movl %fcc0, %g0, %g0}
8581 *
8582 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8583 */
8584 // Template#: 515, Serial#: 515
8585 public void movl(final FCCOperand n, final GPR rs2, final GPR rd) {
8586 int instruction = 0x81610000;
8587 instruction |= ((n.value() & 0x3) << 11);
8588 instruction |= (rs2.value() & 0x1f);
8589 instruction |= ((rd.value() & 0x1f) << 25);
8590 emitInt(instruction);
8591 }
8592
8593 /**
8594 * Pseudo-external assembler syntax: {@code fmovsul }<i>n</i>, <i>rs2</i>, <i>rd</i>
8595 * Example disassembly syntax: {@code fmovsul %fcc0, %f0, %f0}
8596 *
8597 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8598 */
8599 // Template#: 516, Serial#: 516
8600 public void fmovsul(final FCCOperand n, final SFPR rs2, final SFPR rd) {
8601 int instruction = 0x81A8C020;
8602 instruction |= ((n.value() & 0x3) << 11);
8603 instruction |= (rs2.value() & 0x1f);
8604 instruction |= ((rd.value() & 0x1f) << 25);
8605 emitInt(instruction);
8606 }
8607
8608 /**
8609 * Pseudo-external assembler syntax: {@code fmovdul }<i>n</i>, <i>rs2</i>, <i>rd</i>
8610 * Example disassembly syntax: {@code fmovdul %fcc0, %f0, %f0}
8611 *
8612 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8613 */
8614 // Template#: 517, Serial#: 517
8615 public void fmovdul(final FCCOperand n, final DFPR rs2, final DFPR rd) {
8616 int instruction = 0x81A8C040;
8617 instruction |= ((n.value() & 0x3) << 11);
8618 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
8619 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
8620 emitInt(instruction);
8621 }
8622
8623 /**
8624 * Pseudo-external assembler syntax: {@code fmovqul }<i>n</i>, <i>rs2</i>, <i>rd</i>
8625 * Example disassembly syntax: {@code fmovqul %fcc0, %f0, %f0}
8626 *
8627 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8628 */
8629 // Template#: 518, Serial#: 518
8630 public void fmovqul(final FCCOperand n, final QFPR rs2, final QFPR rd) {
8631 int instruction = 0x81A8C060;
8632 instruction |= ((n.value() & 0x3) << 11);
8633 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
8634 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
8635 emitInt(instruction);
8636 }
8637
8638 /**
8639 * Pseudo-external assembler syntax: {@code movul }<i>n</i>, <i>simm11</i>, <i>rd</i>
8640 * Example disassembly syntax: {@code movul %fcc0, -1024, %g0}
8641 * <p>
8642 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
8643 *
8644 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8645 */
8646 // Template#: 519, Serial#: 519
8647 public void movul(final FCCOperand n, final int simm11, final GPR rd) {
8648 int instruction = 0x8160E000;
8649 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
8650 instruction |= ((n.value() & 0x3) << 11);
8651 instruction |= (simm11 & 0x7ff);
8652 instruction |= ((rd.value() & 0x1f) << 25);
8653 emitInt(instruction);
8654 }
8655
8656 /**
8657 * Pseudo-external assembler syntax: {@code movul }<i>n</i>, <i>rs2</i>, <i>rd</i>
8658 * Example disassembly syntax: {@code movul %fcc0, %g0, %g0}
8659 *
8660 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8661 */
8662 // Template#: 520, Serial#: 520
8663 public void movul(final FCCOperand n, final GPR rs2, final GPR rd) {
8664 int instruction = 0x8160C000;
8665 instruction |= ((n.value() & 0x3) << 11);
8666 instruction |= (rs2.value() & 0x1f);
8667 instruction |= ((rd.value() & 0x1f) << 25);
8668 emitInt(instruction);
8669 }
8670
8671 /**
8672 * Pseudo-external assembler syntax: {@code fmovslg }<i>n</i>, <i>rs2</i>, <i>rd</i>
8673 * Example disassembly syntax: {@code fmovslg %fcc0, %f0, %f0}
8674 *
8675 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8676 */
8677 // Template#: 521, Serial#: 521
8678 public void fmovslg(final FCCOperand n, final SFPR rs2, final SFPR rd) {
8679 int instruction = 0x81A88020;
8680 instruction |= ((n.value() & 0x3) << 11);
8681 instruction |= (rs2.value() & 0x1f);
8682 instruction |= ((rd.value() & 0x1f) << 25);
8683 emitInt(instruction);
8684 }
8685
8686 /**
8687 * Pseudo-external assembler syntax: {@code fmovdlg }<i>n</i>, <i>rs2</i>, <i>rd</i>
8688 * Example disassembly syntax: {@code fmovdlg %fcc0, %f0, %f0}
8689 *
8690 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8691 */
8692 // Template#: 522, Serial#: 522
8693 public void fmovdlg(final FCCOperand n, final DFPR rs2, final DFPR rd) {
8694 int instruction = 0x81A88040;
8695 instruction |= ((n.value() & 0x3) << 11);
8696 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
8697 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
8698 emitInt(instruction);
8699 }
8700
8701 /**
8702 * Pseudo-external assembler syntax: {@code fmovqlg }<i>n</i>, <i>rs2</i>, <i>rd</i>
8703 * Example disassembly syntax: {@code fmovqlg %fcc0, %f0, %f0}
8704 *
8705 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8706 */
8707 // Template#: 523, Serial#: 523
8708 public void fmovqlg(final FCCOperand n, final QFPR rs2, final QFPR rd) {
8709 int instruction = 0x81A88060;
8710 instruction |= ((n.value() & 0x3) << 11);
8711 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
8712 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
8713 emitInt(instruction);
8714 }
8715
8716 /**
8717 * Pseudo-external assembler syntax: {@code movlg }<i>n</i>, <i>simm11</i>, <i>rd</i>
8718 * Example disassembly syntax: {@code movlg %fcc0, -1024, %g0}
8719 * <p>
8720 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
8721 *
8722 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8723 */
8724 // Template#: 524, Serial#: 524
8725 public void movlg(final FCCOperand n, final int simm11, final GPR rd) {
8726 int instruction = 0x8160A000;
8727 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
8728 instruction |= ((n.value() & 0x3) << 11);
8729 instruction |= (simm11 & 0x7ff);
8730 instruction |= ((rd.value() & 0x1f) << 25);
8731 emitInt(instruction);
8732 }
8733
8734 /**
8735 * Pseudo-external assembler syntax: {@code movlg }<i>n</i>, <i>rs2</i>, <i>rd</i>
8736 * Example disassembly syntax: {@code movlg %fcc0, %g0, %g0}
8737 *
8738 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8739 */
8740 // Template#: 525, Serial#: 525
8741 public void movlg(final FCCOperand n, final GPR rs2, final GPR rd) {
8742 int instruction = 0x81608000;
8743 instruction |= ((n.value() & 0x3) << 11);
8744 instruction |= (rs2.value() & 0x1f);
8745 instruction |= ((rd.value() & 0x1f) << 25);
8746 emitInt(instruction);
8747 }
8748
8749 /**
8750 * Pseudo-external assembler syntax: {@code fmovsne }<i>n</i>, <i>rs2</i>, <i>rd</i>
8751 * Example disassembly syntax: {@code fmovsne %fcc0, %f0, %f0}
8752 *
8753 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8754 */
8755 // Template#: 526, Serial#: 526
8756 public void fmovsne(final FCCOperand n, final SFPR rs2, final SFPR rd) {
8757 int instruction = 0x81A84020;
8758 instruction |= ((n.value() & 0x3) << 11);
8759 instruction |= (rs2.value() & 0x1f);
8760 instruction |= ((rd.value() & 0x1f) << 25);
8761 emitInt(instruction);
8762 }
8763
8764 /**
8765 * Pseudo-external assembler syntax: {@code fmovdne }<i>n</i>, <i>rs2</i>, <i>rd</i>
8766 * Example disassembly syntax: {@code fmovdne %fcc0, %f0, %f0}
8767 *
8768 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8769 */
8770 // Template#: 527, Serial#: 527
8771 public void fmovdne(final FCCOperand n, final DFPR rs2, final DFPR rd) {
8772 int instruction = 0x81A84040;
8773 instruction |= ((n.value() & 0x3) << 11);
8774 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
8775 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
8776 emitInt(instruction);
8777 }
8778
8779 /**
8780 * Pseudo-external assembler syntax: {@code fmovqne }<i>n</i>, <i>rs2</i>, <i>rd</i>
8781 * Example disassembly syntax: {@code fmovqne %fcc0, %f0, %f0}
8782 *
8783 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8784 */
8785 // Template#: 528, Serial#: 528
8786 public void fmovqne(final FCCOperand n, final QFPR rs2, final QFPR rd) {
8787 int instruction = 0x81A84060;
8788 instruction |= ((n.value() & 0x3) << 11);
8789 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
8790 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
8791 emitInt(instruction);
8792 }
8793
8794 /**
8795 * Pseudo-external assembler syntax: {@code movne }<i>n</i>, <i>simm11</i>, <i>rd</i>
8796 * Example disassembly syntax: {@code movne %fcc0, -1024, %g0}
8797 * <p>
8798 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
8799 *
8800 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8801 */
8802 // Template#: 529, Serial#: 529
8803 public void movne(final FCCOperand n, final int simm11, final GPR rd) {
8804 int instruction = 0x81606000;
8805 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
8806 instruction |= ((n.value() & 0x3) << 11);
8807 instruction |= (simm11 & 0x7ff);
8808 instruction |= ((rd.value() & 0x1f) << 25);
8809 emitInt(instruction);
8810 }
8811
8812 /**
8813 * Pseudo-external assembler syntax: {@code movne }<i>n</i>, <i>rs2</i>, <i>rd</i>
8814 * Example disassembly syntax: {@code movne %fcc0, %g0, %g0}
8815 *
8816 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8817 */
8818 // Template#: 530, Serial#: 530
8819 public void movne(final FCCOperand n, final GPR rs2, final GPR rd) {
8820 int instruction = 0x81604000;
8821 instruction |= ((n.value() & 0x3) << 11);
8822 instruction |= (rs2.value() & 0x1f);
8823 instruction |= ((rd.value() & 0x1f) << 25);
8824 emitInt(instruction);
8825 }
8826
8827 /**
8828 * Pseudo-external assembler syntax: {@code fmovse }<i>n</i>, <i>rs2</i>, <i>rd</i>
8829 * Example disassembly syntax: {@code fmovse %fcc0, %f0, %f0}
8830 *
8831 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8832 */
8833 // Template#: 531, Serial#: 531
8834 public void fmovse(final FCCOperand n, final SFPR rs2, final SFPR rd) {
8835 int instruction = 0x81AA4020;
8836 instruction |= ((n.value() & 0x3) << 11);
8837 instruction |= (rs2.value() & 0x1f);
8838 instruction |= ((rd.value() & 0x1f) << 25);
8839 emitInt(instruction);
8840 }
8841
8842 /**
8843 * Pseudo-external assembler syntax: {@code fmovde }<i>n</i>, <i>rs2</i>, <i>rd</i>
8844 * Example disassembly syntax: {@code fmovde %fcc0, %f0, %f0}
8845 *
8846 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8847 */
8848 // Template#: 532, Serial#: 532
8849 public void fmovde(final FCCOperand n, final DFPR rs2, final DFPR rd) {
8850 int instruction = 0x81AA4040;
8851 instruction |= ((n.value() & 0x3) << 11);
8852 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
8853 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
8854 emitInt(instruction);
8855 }
8856
8857 /**
8858 * Pseudo-external assembler syntax: {@code fmovqe }<i>n</i>, <i>rs2</i>, <i>rd</i>
8859 * Example disassembly syntax: {@code fmovqe %fcc0, %f0, %f0}
8860 *
8861 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8862 */
8863 // Template#: 533, Serial#: 533
8864 public void fmovqe(final FCCOperand n, final QFPR rs2, final QFPR rd) {
8865 int instruction = 0x81AA4060;
8866 instruction |= ((n.value() & 0x3) << 11);
8867 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
8868 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
8869 emitInt(instruction);
8870 }
8871
8872 /**
8873 * Pseudo-external assembler syntax: {@code move }<i>n</i>, <i>simm11</i>, <i>rd</i>
8874 * Example disassembly syntax: {@code move %fcc0, -1024, %g0}
8875 * <p>
8876 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
8877 *
8878 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8879 */
8880 // Template#: 534, Serial#: 534
8881 public void move(final FCCOperand n, final int simm11, final GPR rd) {
8882 int instruction = 0x81626000;
8883 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
8884 instruction |= ((n.value() & 0x3) << 11);
8885 instruction |= (simm11 & 0x7ff);
8886 instruction |= ((rd.value() & 0x1f) << 25);
8887 emitInt(instruction);
8888 }
8889
8890 /**
8891 * Pseudo-external assembler syntax: {@code move }<i>n</i>, <i>rs2</i>, <i>rd</i>
8892 * Example disassembly syntax: {@code move %fcc0, %g0, %g0}
8893 *
8894 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8895 */
8896 // Template#: 535, Serial#: 535
8897 public void move(final FCCOperand n, final GPR rs2, final GPR rd) {
8898 int instruction = 0x81624000;
8899 instruction |= ((n.value() & 0x3) << 11);
8900 instruction |= (rs2.value() & 0x1f);
8901 instruction |= ((rd.value() & 0x1f) << 25);
8902 emitInt(instruction);
8903 }
8904
8905 /**
8906 * Pseudo-external assembler syntax: {@code fmovsue }<i>n</i>, <i>rs2</i>, <i>rd</i>
8907 * Example disassembly syntax: {@code fmovsue %fcc0, %f0, %f0}
8908 *
8909 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8910 */
8911 // Template#: 536, Serial#: 536
8912 public void fmovsue(final FCCOperand n, final SFPR rs2, final SFPR rd) {
8913 int instruction = 0x81AA8020;
8914 instruction |= ((n.value() & 0x3) << 11);
8915 instruction |= (rs2.value() & 0x1f);
8916 instruction |= ((rd.value() & 0x1f) << 25);
8917 emitInt(instruction);
8918 }
8919
8920 /**
8921 * Pseudo-external assembler syntax: {@code fmovdue }<i>n</i>, <i>rs2</i>, <i>rd</i>
8922 * Example disassembly syntax: {@code fmovdue %fcc0, %f0, %f0}
8923 *
8924 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8925 */
8926 // Template#: 537, Serial#: 537
8927 public void fmovdue(final FCCOperand n, final DFPR rs2, final DFPR rd) {
8928 int instruction = 0x81AA8040;
8929 instruction |= ((n.value() & 0x3) << 11);
8930 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
8931 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
8932 emitInt(instruction);
8933 }
8934
8935 /**
8936 * Pseudo-external assembler syntax: {@code fmovque }<i>n</i>, <i>rs2</i>, <i>rd</i>
8937 * Example disassembly syntax: {@code fmovque %fcc0, %f0, %f0}
8938 *
8939 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8940 */
8941 // Template#: 538, Serial#: 538
8942 public void fmovque(final FCCOperand n, final QFPR rs2, final QFPR rd) {
8943 int instruction = 0x81AA8060;
8944 instruction |= ((n.value() & 0x3) << 11);
8945 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
8946 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
8947 emitInt(instruction);
8948 }
8949
8950 /**
8951 * Pseudo-external assembler syntax: {@code movue }<i>n</i>, <i>simm11</i>, <i>rd</i>
8952 * Example disassembly syntax: {@code movue %fcc0, -1024, %g0}
8953 * <p>
8954 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
8955 *
8956 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8957 */
8958 // Template#: 539, Serial#: 539
8959 public void movue(final FCCOperand n, final int simm11, final GPR rd) {
8960 int instruction = 0x8162A000;
8961 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
8962 instruction |= ((n.value() & 0x3) << 11);
8963 instruction |= (simm11 & 0x7ff);
8964 instruction |= ((rd.value() & 0x1f) << 25);
8965 emitInt(instruction);
8966 }
8967
8968 /**
8969 * Pseudo-external assembler syntax: {@code movue }<i>n</i>, <i>rs2</i>, <i>rd</i>
8970 * Example disassembly syntax: {@code movue %fcc0, %g0, %g0}
8971 *
8972 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
8973 */
8974 // Template#: 540, Serial#: 540
8975 public void movue(final FCCOperand n, final GPR rs2, final GPR rd) {
8976 int instruction = 0x81628000;
8977 instruction |= ((n.value() & 0x3) << 11);
8978 instruction |= (rs2.value() & 0x1f);
8979 instruction |= ((rd.value() & 0x1f) << 25);
8980 emitInt(instruction);
8981 }
8982
8983 /**
8984 * Pseudo-external assembler syntax: {@code fmovsge }<i>n</i>, <i>rs2</i>, <i>rd</i>
8985 * Example disassembly syntax: {@code fmovsge %fcc0, %f0, %f0}
8986 *
8987 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
8988 */
8989 // Template#: 541, Serial#: 541
8990 public void fmovsge(final FCCOperand n, final SFPR rs2, final SFPR rd) {
8991 int instruction = 0x81AAC020;
8992 instruction |= ((n.value() & 0x3) << 11);
8993 instruction |= (rs2.value() & 0x1f);
8994 instruction |= ((rd.value() & 0x1f) << 25);
8995 emitInt(instruction);
8996 }
8997
8998 /**
8999 * Pseudo-external assembler syntax: {@code fmovdge }<i>n</i>, <i>rs2</i>, <i>rd</i>
9000 * Example disassembly syntax: {@code fmovdge %fcc0, %f0, %f0}
9001 *
9002 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
9003 */
9004 // Template#: 542, Serial#: 542
9005 public void fmovdge(final FCCOperand n, final DFPR rs2, final DFPR rd) {
9006 int instruction = 0x81AAC040;
9007 instruction |= ((n.value() & 0x3) << 11);
9008 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9009 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
9010 emitInt(instruction);
9011 }
9012
9013 /**
9014 * Pseudo-external assembler syntax: {@code fmovqge }<i>n</i>, <i>rs2</i>, <i>rd</i>
9015 * Example disassembly syntax: {@code fmovqge %fcc0, %f0, %f0}
9016 *
9017 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
9018 */
9019 // Template#: 543, Serial#: 543
9020 public void fmovqge(final FCCOperand n, final QFPR rs2, final QFPR rd) {
9021 int instruction = 0x81AAC060;
9022 instruction |= ((n.value() & 0x3) << 11);
9023 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
9024 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
9025 emitInt(instruction);
9026 }
9027
9028 /**
9029 * Pseudo-external assembler syntax: {@code movge }<i>n</i>, <i>simm11</i>, <i>rd</i>
9030 * Example disassembly syntax: {@code movge %fcc0, -1024, %g0}
9031 * <p>
9032 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
9033 *
9034 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
9035 */
9036 // Template#: 544, Serial#: 544
9037 public void movge(final FCCOperand n, final int simm11, final GPR rd) {
9038 int instruction = 0x8162E000;
9039 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
9040 instruction |= ((n.value() & 0x3) << 11);
9041 instruction |= (simm11 & 0x7ff);
9042 instruction |= ((rd.value() & 0x1f) << 25);
9043 emitInt(instruction);
9044 }
9045
9046 /**
9047 * Pseudo-external assembler syntax: {@code movge }<i>n</i>, <i>rs2</i>, <i>rd</i>
9048 * Example disassembly syntax: {@code movge %fcc0, %g0, %g0}
9049 *
9050 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
9051 */
9052 // Template#: 545, Serial#: 545
9053 public void movge(final FCCOperand n, final GPR rs2, final GPR rd) {
9054 int instruction = 0x8162C000;
9055 instruction |= ((n.value() & 0x3) << 11);
9056 instruction |= (rs2.value() & 0x1f);
9057 instruction |= ((rd.value() & 0x1f) << 25);
9058 emitInt(instruction);
9059 }
9060
9061 /**
9062 * Pseudo-external assembler syntax: {@code fmovsuge }<i>n</i>, <i>rs2</i>, <i>rd</i>
9063 * Example disassembly syntax: {@code fmovsuge %fcc0, %f0, %f0}
9064 *
9065 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
9066 */
9067 // Template#: 546, Serial#: 546
9068 public void fmovsuge(final FCCOperand n, final SFPR rs2, final SFPR rd) {
9069 int instruction = 0x81AB0020;
9070 instruction |= ((n.value() & 0x3) << 11);
9071 instruction |= (rs2.value() & 0x1f);
9072 instruction |= ((rd.value() & 0x1f) << 25);
9073 emitInt(instruction);
9074 }
9075
9076 /**
9077 * Pseudo-external assembler syntax: {@code fmovduge }<i>n</i>, <i>rs2</i>, <i>rd</i>
9078 * Example disassembly syntax: {@code fmovduge %fcc0, %f0, %f0}
9079 *
9080 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
9081 */
9082 // Template#: 547, Serial#: 547
9083 public void fmovduge(final FCCOperand n, final DFPR rs2, final DFPR rd) {
9084 int instruction = 0x81AB0040;
9085 instruction |= ((n.value() & 0x3) << 11);
9086 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9087 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
9088 emitInt(instruction);
9089 }
9090
9091 /**
9092 * Pseudo-external assembler syntax: {@code fmovquge }<i>n</i>, <i>rs2</i>, <i>rd</i>
9093 * Example disassembly syntax: {@code fmovquge %fcc0, %f0, %f0}
9094 *
9095 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
9096 */
9097 // Template#: 548, Serial#: 548
9098 public void fmovquge(final FCCOperand n, final QFPR rs2, final QFPR rd) {
9099 int instruction = 0x81AB0060;
9100 instruction |= ((n.value() & 0x3) << 11);
9101 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
9102 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
9103 emitInt(instruction);
9104 }
9105
9106 /**
9107 * Pseudo-external assembler syntax: {@code movuge }<i>n</i>, <i>simm11</i>, <i>rd</i>
9108 * Example disassembly syntax: {@code movuge %fcc0, -1024, %g0}
9109 * <p>
9110 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
9111 *
9112 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
9113 */
9114 // Template#: 549, Serial#: 549
9115 public void movuge(final FCCOperand n, final int simm11, final GPR rd) {
9116 int instruction = 0x81632000;
9117 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
9118 instruction |= ((n.value() & 0x3) << 11);
9119 instruction |= (simm11 & 0x7ff);
9120 instruction |= ((rd.value() & 0x1f) << 25);
9121 emitInt(instruction);
9122 }
9123
9124 /**
9125 * Pseudo-external assembler syntax: {@code movuge }<i>n</i>, <i>rs2</i>, <i>rd</i>
9126 * Example disassembly syntax: {@code movuge %fcc0, %g0, %g0}
9127 *
9128 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
9129 */
9130 // Template#: 550, Serial#: 550
9131 public void movuge(final FCCOperand n, final GPR rs2, final GPR rd) {
9132 int instruction = 0x81630000;
9133 instruction |= ((n.value() & 0x3) << 11);
9134 instruction |= (rs2.value() & 0x1f);
9135 instruction |= ((rd.value() & 0x1f) << 25);
9136 emitInt(instruction);
9137 }
9138
9139 /**
9140 * Pseudo-external assembler syntax: {@code fmovsle }<i>n</i>, <i>rs2</i>, <i>rd</i>
9141 * Example disassembly syntax: {@code fmovsle %fcc0, %f0, %f0}
9142 *
9143 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
9144 */
9145 // Template#: 551, Serial#: 551
9146 public void fmovsle(final FCCOperand n, final SFPR rs2, final SFPR rd) {
9147 int instruction = 0x81AB4020;
9148 instruction |= ((n.value() & 0x3) << 11);
9149 instruction |= (rs2.value() & 0x1f);
9150 instruction |= ((rd.value() & 0x1f) << 25);
9151 emitInt(instruction);
9152 }
9153
9154 /**
9155 * Pseudo-external assembler syntax: {@code fmovdle }<i>n</i>, <i>rs2</i>, <i>rd</i>
9156 * Example disassembly syntax: {@code fmovdle %fcc0, %f0, %f0}
9157 *
9158 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
9159 */
9160 // Template#: 552, Serial#: 552
9161 public void fmovdle(final FCCOperand n, final DFPR rs2, final DFPR rd) {
9162 int instruction = 0x81AB4040;
9163 instruction |= ((n.value() & 0x3) << 11);
9164 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9165 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
9166 emitInt(instruction);
9167 }
9168
9169 /**
9170 * Pseudo-external assembler syntax: {@code fmovqle }<i>n</i>, <i>rs2</i>, <i>rd</i>
9171 * Example disassembly syntax: {@code fmovqle %fcc0, %f0, %f0}
9172 *
9173 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
9174 */
9175 // Template#: 553, Serial#: 553
9176 public void fmovqle(final FCCOperand n, final QFPR rs2, final QFPR rd) {
9177 int instruction = 0x81AB4060;
9178 instruction |= ((n.value() & 0x3) << 11);
9179 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
9180 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
9181 emitInt(instruction);
9182 }
9183
9184 /**
9185 * Pseudo-external assembler syntax: {@code movle }<i>n</i>, <i>simm11</i>, <i>rd</i>
9186 * Example disassembly syntax: {@code movle %fcc0, -1024, %g0}
9187 * <p>
9188 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
9189 *
9190 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
9191 */
9192 // Template#: 554, Serial#: 554
9193 public void movle(final FCCOperand n, final int simm11, final GPR rd) {
9194 int instruction = 0x81636000;
9195 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
9196 instruction |= ((n.value() & 0x3) << 11);
9197 instruction |= (simm11 & 0x7ff);
9198 instruction |= ((rd.value() & 0x1f) << 25);
9199 emitInt(instruction);
9200 }
9201
9202 /**
9203 * Pseudo-external assembler syntax: {@code movle }<i>n</i>, <i>rs2</i>, <i>rd</i>
9204 * Example disassembly syntax: {@code movle %fcc0, %g0, %g0}
9205 *
9206 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
9207 */
9208 // Template#: 555, Serial#: 555
9209 public void movle(final FCCOperand n, final GPR rs2, final GPR rd) {
9210 int instruction = 0x81634000;
9211 instruction |= ((n.value() & 0x3) << 11);
9212 instruction |= (rs2.value() & 0x1f);
9213 instruction |= ((rd.value() & 0x1f) << 25);
9214 emitInt(instruction);
9215 }
9216
9217 /**
9218 * Pseudo-external assembler syntax: {@code fmovsule }<i>n</i>, <i>rs2</i>, <i>rd</i>
9219 * Example disassembly syntax: {@code fmovsule %fcc0, %f0, %f0}
9220 *
9221 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
9222 */
9223 // Template#: 556, Serial#: 556
9224 public void fmovsule(final FCCOperand n, final SFPR rs2, final SFPR rd) {
9225 int instruction = 0x81AB8020;
9226 instruction |= ((n.value() & 0x3) << 11);
9227 instruction |= (rs2.value() & 0x1f);
9228 instruction |= ((rd.value() & 0x1f) << 25);
9229 emitInt(instruction);
9230 }
9231
9232 /**
9233 * Pseudo-external assembler syntax: {@code fmovdule }<i>n</i>, <i>rs2</i>, <i>rd</i>
9234 * Example disassembly syntax: {@code fmovdule %fcc0, %f0, %f0}
9235 *
9236 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
9237 */
9238 // Template#: 557, Serial#: 557
9239 public void fmovdule(final FCCOperand n, final DFPR rs2, final DFPR rd) {
9240 int instruction = 0x81AB8040;
9241 instruction |= ((n.value() & 0x3) << 11);
9242 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9243 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
9244 emitInt(instruction);
9245 }
9246
9247 /**
9248 * Pseudo-external assembler syntax: {@code fmovqule }<i>n</i>, <i>rs2</i>, <i>rd</i>
9249 * Example disassembly syntax: {@code fmovqule %fcc0, %f0, %f0}
9250 *
9251 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
9252 */
9253 // Template#: 558, Serial#: 558
9254 public void fmovqule(final FCCOperand n, final QFPR rs2, final QFPR rd) {
9255 int instruction = 0x81AB8060;
9256 instruction |= ((n.value() & 0x3) << 11);
9257 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
9258 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
9259 emitInt(instruction);
9260 }
9261
9262 /**
9263 * Pseudo-external assembler syntax: {@code movule }<i>n</i>, <i>simm11</i>, <i>rd</i>
9264 * Example disassembly syntax: {@code movule %fcc0, -1024, %g0}
9265 * <p>
9266 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
9267 *
9268 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
9269 */
9270 // Template#: 559, Serial#: 559
9271 public void movule(final FCCOperand n, final int simm11, final GPR rd) {
9272 int instruction = 0x8163A000;
9273 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
9274 instruction |= ((n.value() & 0x3) << 11);
9275 instruction |= (simm11 & 0x7ff);
9276 instruction |= ((rd.value() & 0x1f) << 25);
9277 emitInt(instruction);
9278 }
9279
9280 /**
9281 * Pseudo-external assembler syntax: {@code movule }<i>n</i>, <i>rs2</i>, <i>rd</i>
9282 * Example disassembly syntax: {@code movule %fcc0, %g0, %g0}
9283 *
9284 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
9285 */
9286 // Template#: 560, Serial#: 560
9287 public void movule(final FCCOperand n, final GPR rs2, final GPR rd) {
9288 int instruction = 0x81638000;
9289 instruction |= ((n.value() & 0x3) << 11);
9290 instruction |= (rs2.value() & 0x1f);
9291 instruction |= ((rd.value() & 0x1f) << 25);
9292 emitInt(instruction);
9293 }
9294
9295 /**
9296 * Pseudo-external assembler syntax: {@code fmovso }<i>n</i>, <i>rs2</i>, <i>rd</i>
9297 * Example disassembly syntax: {@code fmovso %fcc0, %f0, %f0}
9298 *
9299 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
9300 */
9301 // Template#: 561, Serial#: 561
9302 public void fmovso(final FCCOperand n, final SFPR rs2, final SFPR rd) {
9303 int instruction = 0x81ABC020;
9304 instruction |= ((n.value() & 0x3) << 11);
9305 instruction |= (rs2.value() & 0x1f);
9306 instruction |= ((rd.value() & 0x1f) << 25);
9307 emitInt(instruction);
9308 }
9309
9310 /**
9311 * Pseudo-external assembler syntax: {@code fmovdo }<i>n</i>, <i>rs2</i>, <i>rd</i>
9312 * Example disassembly syntax: {@code fmovdo %fcc0, %f0, %f0}
9313 *
9314 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
9315 */
9316 // Template#: 562, Serial#: 562
9317 public void fmovdo(final FCCOperand n, final DFPR rs2, final DFPR rd) {
9318 int instruction = 0x81ABC040;
9319 instruction |= ((n.value() & 0x3) << 11);
9320 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9321 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
9322 emitInt(instruction);
9323 }
9324
9325 /**
9326 * Pseudo-external assembler syntax: {@code fmovqo }<i>n</i>, <i>rs2</i>, <i>rd</i>
9327 * Example disassembly syntax: {@code fmovqo %fcc0, %f0, %f0}
9328 *
9329 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.33"
9330 */
9331 // Template#: 563, Serial#: 563
9332 public void fmovqo(final FCCOperand n, final QFPR rs2, final QFPR rd) {
9333 int instruction = 0x81ABC060;
9334 instruction |= ((n.value() & 0x3) << 11);
9335 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
9336 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
9337 emitInt(instruction);
9338 }
9339
9340 /**
9341 * Pseudo-external assembler syntax: {@code movo }<i>n</i>, <i>simm11</i>, <i>rd</i>
9342 * Example disassembly syntax: {@code movo %fcc0, -1024, %g0}
9343 * <p>
9344 * Constraint: {@code -1024 <= simm11 && simm11 <= 1023}<br />
9345 *
9346 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
9347 */
9348 // Template#: 564, Serial#: 564
9349 public void movo(final FCCOperand n, final int simm11, final GPR rd) {
9350 int instruction = 0x8163E000;
9351 checkConstraint(-1024 <= simm11 && simm11 <= 1023, "-1024 <= simm11 && simm11 <= 1023");
9352 instruction |= ((n.value() & 0x3) << 11);
9353 instruction |= (simm11 & 0x7ff);
9354 instruction |= ((rd.value() & 0x1f) << 25);
9355 emitInt(instruction);
9356 }
9357
9358 /**
9359 * Pseudo-external assembler syntax: {@code movo }<i>n</i>, <i>rs2</i>, <i>rd</i>
9360 * Example disassembly syntax: {@code movo %fcc0, %g0, %g0}
9361 *
9362 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.35"
9363 */
9364 // Template#: 565, Serial#: 565
9365 public void movo(final FCCOperand n, final GPR rs2, final GPR rd) {
9366 int instruction = 0x8163C000;
9367 instruction |= ((n.value() & 0x3) << 11);
9368 instruction |= (rs2.value() & 0x1f);
9369 instruction |= ((rd.value() & 0x1f) << 25);
9370 emitInt(instruction);
9371 }
9372
9373 /**
9374 * Pseudo-external assembler syntax: {@code flushw }
9375 * Example disassembly syntax: {@code flushw }
9376 *
9377 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.21"
9378 */
9379 // Template#: 566, Serial#: 566
9380 public void flushw() {
9381 int instruction = 0x81580000;
9382 emitInt(instruction);
9383 }
9384
9385 /**
9386 * Pseudo-external assembler syntax: {@code save }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
9387 * Example disassembly syntax: {@code save %g0, %g0, %g0}
9388 *
9389 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.45"
9390 */
9391 // Template#: 567, Serial#: 567
9392 public void save(final GPR rs1, final GPR rs2, final GPR rd) {
9393 int instruction = 0x81E00000;
9394 instruction |= ((rs1.value() & 0x1f) << 14);
9395 instruction |= (rs2.value() & 0x1f);
9396 instruction |= ((rd.value() & 0x1f) << 25);
9397 emitInt(instruction);
9398 }
9399
9400 /**
9401 * Pseudo-external assembler syntax: {@code save }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
9402 * Example disassembly syntax: {@code save %g0, -4096, %g0}
9403 * <p>
9404 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
9405 *
9406 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.45"
9407 */
9408 // Template#: 568, Serial#: 568
9409 public void save(final GPR rs1, final int simm13, final GPR rd) {
9410 int instruction = 0x81E02000;
9411 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
9412 instruction |= ((rs1.value() & 0x1f) << 14);
9413 instruction |= (simm13 & 0x1fff);
9414 instruction |= ((rd.value() & 0x1f) << 25);
9415 emitInt(instruction);
9416 }
9417
9418 /**
9419 * Pseudo-external assembler syntax: {@code restore }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
9420 * Example disassembly syntax: {@code restore %g0, %g0, %g0}
9421 *
9422 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.45"
9423 */
9424 // Template#: 569, Serial#: 569
9425 public void restore(final GPR rs1, final GPR rs2, final GPR rd) {
9426 int instruction = 0x81E80000;
9427 instruction |= ((rs1.value() & 0x1f) << 14);
9428 instruction |= (rs2.value() & 0x1f);
9429 instruction |= ((rd.value() & 0x1f) << 25);
9430 emitInt(instruction);
9431 }
9432
9433 /**
9434 * Pseudo-external assembler syntax: {@code restore }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
9435 * Example disassembly syntax: {@code restore %g0, -4096, %g0}
9436 * <p>
9437 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
9438 *
9439 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.45"
9440 */
9441 // Template#: 570, Serial#: 570
9442 public void restore(final GPR rs1, final int simm13, final GPR rd) {
9443 int instruction = 0x81E82000;
9444 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
9445 instruction |= ((rs1.value() & 0x1f) << 14);
9446 instruction |= (simm13 & 0x1fff);
9447 instruction |= ((rd.value() & 0x1f) << 25);
9448 emitInt(instruction);
9449 }
9450
9451 /**
9452 * Pseudo-external assembler syntax: {@code saved }
9453 * Example disassembly syntax: {@code saved }
9454 *
9455 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.46"
9456 */
9457 // Template#: 571, Serial#: 571
9458 public void saved() {
9459 int instruction = 0x81880000;
9460 emitInt(instruction);
9461 }
9462
9463 /**
9464 * Pseudo-external assembler syntax: {@code restored }
9465 * Example disassembly syntax: {@code restored }
9466 *
9467 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.46"
9468 */
9469 // Template#: 572, Serial#: 572
9470 public void restored() {
9471 int instruction = 0x83880000;
9472 emitInt(instruction);
9473 }
9474
9475 /**
9476 * Pseudo-external assembler syntax: {@code rd }<i>rs1</i>, <i>rd</i>
9477 * Example disassembly syntax: {@code rd %y, %g0}
9478 *
9479 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.43"
9480 */
9481 // Template#: 573, Serial#: 573
9482 public void rd(final StateRegister rs1, final GPR rd) {
9483 int instruction = 0x81400000;
9484 instruction |= ((rs1.value() & 0x1f) << 14);
9485 instruction |= ((rd.value() & 0x1f) << 25);
9486 emitInt(instruction);
9487 }
9488
9489 /**
9490 * Pseudo-external assembler syntax: {@code wr }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
9491 * Example disassembly syntax: {@code wr %g0, %g0, %y}
9492 *
9493 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.62"
9494 */
9495 // Template#: 574, Serial#: 574
9496 public void wr(final GPR rs1, final GPR rs2, final StateRegister.Writable rd) {
9497 int instruction = 0x81800000;
9498 instruction |= ((rs1.value() & 0x1f) << 14);
9499 instruction |= (rs2.value() & 0x1f);
9500 instruction |= ((rd.value() & 0x1f) << 25);
9501 emitInt(instruction);
9502 }
9503
9504 /**
9505 * Pseudo-external assembler syntax: {@code wr }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
9506 * Example disassembly syntax: {@code wr %g0, -4096, %y}
9507 * <p>
9508 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
9509 *
9510 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.62"
9511 */
9512 // Template#: 575, Serial#: 575
9513 public void wr(final GPR rs1, final int simm13, final StateRegister.Writable rd) {
9514 int instruction = 0x81802000;
9515 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
9516 instruction |= ((rs1.value() & 0x1f) << 14);
9517 instruction |= (simm13 & 0x1fff);
9518 instruction |= ((rd.value() & 0x1f) << 25);
9519 emitInt(instruction);
9520 }
9521
9522 /**
9523 * Pseudo-external assembler syntax: {@code rdpr }<i>rs1</i>, <i>rd</i>
9524 * Example disassembly syntax: {@code rdpr %tpc, %g0}
9525 *
9526 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.42"
9527 */
9528 // Template#: 576, Serial#: 576
9529 public void rdpr(final PrivilegedRegister rs1, final GPR rd) {
9530 int instruction = 0x81500000;
9531 instruction |= ((rs1.value() & 0x1f) << 14);
9532 instruction |= ((rd.value() & 0x1f) << 25);
9533 emitInt(instruction);
9534 }
9535
9536 /**
9537 * Pseudo-external assembler syntax: {@code wrpr }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
9538 * Example disassembly syntax: {@code wrpr %g0, %g0, %tpc}
9539 *
9540 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
9541 */
9542 // Template#: 577, Serial#: 577
9543 public void wrpr(final GPR rs1, final GPR rs2, final PrivilegedRegister.Writable rd) {
9544 int instruction = 0x81900000;
9545 instruction |= ((rs1.value() & 0x1f) << 14);
9546 instruction |= (rs2.value() & 0x1f);
9547 instruction |= ((rd.value() & 0x1f) << 25);
9548 emitInt(instruction);
9549 }
9550
9551 /**
9552 * Pseudo-external assembler syntax: {@code wrpr }<i>rs1</i>, <i>simm13</i>, <i>rd</i>
9553 * Example disassembly syntax: {@code wrpr %g0, -4096, %tpc}
9554 * <p>
9555 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
9556 *
9557 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.61"
9558 */
9559 // Template#: 578, Serial#: 578
9560 public void wrpr(final GPR rs1, final int simm13, final PrivilegedRegister.Writable rd) {
9561 int instruction = 0x81902000;
9562 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
9563 instruction |= ((rs1.value() & 0x1f) << 14);
9564 instruction |= (simm13 & 0x1fff);
9565 instruction |= ((rd.value() & 0x1f) << 25);
9566 emitInt(instruction);
9567 }
9568
9569 /**
9570 * Pseudo-external assembler syntax: {@code fadds }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
9571 * Example disassembly syntax: {@code fadds %f0, %f0, %f0}
9572 *
9573 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.12"
9574 */
9575 // Template#: 579, Serial#: 579
9576 public void fadds(final SFPR rs1, final SFPR rs2, final SFPR rd) {
9577 int instruction = 0x81A00820;
9578 instruction |= ((rs1.value() & 0x1f) << 14);
9579 instruction |= (rs2.value() & 0x1f);
9580 instruction |= ((rd.value() & 0x1f) << 25);
9581 emitInt(instruction);
9582 }
9583
9584 /**
9585 * Pseudo-external assembler syntax: {@code faddd }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
9586 * Example disassembly syntax: {@code faddd %f0, %f0, %f0}
9587 *
9588 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.12"
9589 */
9590 // Template#: 580, Serial#: 580
9591 public void faddd(final DFPR rs1, final DFPR rs2, final DFPR rd) {
9592 int instruction = 0x81A00840;
9593 instruction |= (((rs1.value() >>> 1) & 0xf) << 15) | (((rs1.value() >>> 5) & 0x1) << 14);
9594 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9595 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
9596 emitInt(instruction);
9597 }
9598
9599 /**
9600 * Pseudo-external assembler syntax: {@code faddq }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
9601 * Example disassembly syntax: {@code faddq %f0, %f0, %f0}
9602 *
9603 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.12"
9604 */
9605 // Template#: 581, Serial#: 581
9606 public void faddq(final QFPR rs1, final QFPR rs2, final QFPR rd) {
9607 int instruction = 0x81A00860;
9608 instruction |= (((rs1.value() >>> 2) & 0x7) << 16) | (((rs1.value() >>> 5) & 0x1) << 14);
9609 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
9610 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
9611 emitInt(instruction);
9612 }
9613
9614 /**
9615 * Pseudo-external assembler syntax: {@code fsubs }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
9616 * Example disassembly syntax: {@code fsubs %f0, %f0, %f0}
9617 *
9618 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.12"
9619 */
9620 // Template#: 582, Serial#: 582
9621 public void fsubs(final SFPR rs1, final SFPR rs2, final SFPR rd) {
9622 int instruction = 0x81A008A0;
9623 instruction |= ((rs1.value() & 0x1f) << 14);
9624 instruction |= (rs2.value() & 0x1f);
9625 instruction |= ((rd.value() & 0x1f) << 25);
9626 emitInt(instruction);
9627 }
9628
9629 /**
9630 * Pseudo-external assembler syntax: {@code fsubd }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
9631 * Example disassembly syntax: {@code fsubd %f0, %f0, %f0}
9632 *
9633 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.12"
9634 */
9635 // Template#: 583, Serial#: 583
9636 public void fsubd(final DFPR rs1, final DFPR rs2, final DFPR rd) {
9637 int instruction = 0x81A008C0;
9638 instruction |= (((rs1.value() >>> 1) & 0xf) << 15) | (((rs1.value() >>> 5) & 0x1) << 14);
9639 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9640 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
9641 emitInt(instruction);
9642 }
9643
9644 /**
9645 * Pseudo-external assembler syntax: {@code fsubq }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
9646 * Example disassembly syntax: {@code fsubq %f0, %f0, %f0}
9647 *
9648 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.12"
9649 */
9650 // Template#: 584, Serial#: 584
9651 public void fsubq(final QFPR rs1, final QFPR rs2, final QFPR rd) {
9652 int instruction = 0x81A008E0;
9653 instruction |= (((rs1.value() >>> 2) & 0x7) << 16) | (((rs1.value() >>> 5) & 0x1) << 14);
9654 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
9655 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
9656 emitInt(instruction);
9657 }
9658
9659 /**
9660 * Pseudo-external assembler syntax: {@code fcmps }<i>n</i>, <i>rs1</i>, <i>rs2</i>
9661 * Example disassembly syntax: {@code fcmps %fcc0, %f0, %f0}
9662 *
9663 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.13"
9664 */
9665 // Template#: 585, Serial#: 585
9666 public void fcmps(final FCCOperand n, final SFPR rs1, final SFPR rs2) {
9667 int instruction = 0x81A80A20;
9668 instruction |= ((n.value() & 0x3) << 25);
9669 instruction |= ((rs1.value() & 0x1f) << 14);
9670 instruction |= (rs2.value() & 0x1f);
9671 emitInt(instruction);
9672 }
9673
9674 /**
9675 * Pseudo-external assembler syntax: {@code fcmpd }<i>n</i>, <i>rs1</i>, <i>rs2</i>
9676 * Example disassembly syntax: {@code fcmpd %fcc0, %f0, %f0}
9677 *
9678 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.13"
9679 */
9680 // Template#: 586, Serial#: 586
9681 public void fcmpd(final FCCOperand n, final DFPR rs1, final DFPR rs2) {
9682 int instruction = 0x81A80A40;
9683 instruction |= ((n.value() & 0x3) << 25);
9684 instruction |= (((rs1.value() >>> 1) & 0xf) << 15) | (((rs1.value() >>> 5) & 0x1) << 14);
9685 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9686 emitInt(instruction);
9687 }
9688
9689 /**
9690 * Pseudo-external assembler syntax: {@code fcmpq }<i>n</i>, <i>rs1</i>, <i>rs2</i>
9691 * Example disassembly syntax: {@code fcmpq %fcc0, %f0, %f0}
9692 *
9693 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.13"
9694 */
9695 // Template#: 587, Serial#: 587
9696 public void fcmpq(final FCCOperand n, final QFPR rs1, final QFPR rs2) {
9697 int instruction = 0x81A80A60;
9698 instruction |= ((n.value() & 0x3) << 25);
9699 instruction |= (((rs1.value() >>> 2) & 0x7) << 16) | (((rs1.value() >>> 5) & 0x1) << 14);
9700 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
9701 emitInt(instruction);
9702 }
9703
9704 /**
9705 * Pseudo-external assembler syntax: {@code fcmpes }<i>n</i>, <i>rs1</i>, <i>rs2</i>
9706 * Example disassembly syntax: {@code fcmpes %fcc0, %f0, %f0}
9707 *
9708 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.13"
9709 */
9710 // Template#: 588, Serial#: 588
9711 public void fcmpes(final FCCOperand n, final SFPR rs1, final SFPR rs2) {
9712 int instruction = 0x81A80AA0;
9713 instruction |= ((n.value() & 0x3) << 25);
9714 instruction |= ((rs1.value() & 0x1f) << 14);
9715 instruction |= (rs2.value() & 0x1f);
9716 emitInt(instruction);
9717 }
9718
9719 /**
9720 * Pseudo-external assembler syntax: {@code fcmped }<i>n</i>, <i>rs1</i>, <i>rs2</i>
9721 * Example disassembly syntax: {@code fcmped %fcc0, %f0, %f0}
9722 *
9723 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.13"
9724 */
9725 // Template#: 589, Serial#: 589
9726 public void fcmped(final FCCOperand n, final DFPR rs1, final DFPR rs2) {
9727 int instruction = 0x81A80AC0;
9728 instruction |= ((n.value() & 0x3) << 25);
9729 instruction |= (((rs1.value() >>> 1) & 0xf) << 15) | (((rs1.value() >>> 5) & 0x1) << 14);
9730 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9731 emitInt(instruction);
9732 }
9733
9734 /**
9735 * Pseudo-external assembler syntax: {@code fcmpeq }<i>n</i>, <i>rs1</i>, <i>rs2</i>
9736 * Example disassembly syntax: {@code fcmpeq %fcc0, %f0, %f0}
9737 *
9738 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.13"
9739 */
9740 // Template#: 590, Serial#: 590
9741 public void fcmpeq(final FCCOperand n, final QFPR rs1, final QFPR rs2) {
9742 int instruction = 0x81A80AE0;
9743 instruction |= ((n.value() & 0x3) << 25);
9744 instruction |= (((rs1.value() >>> 2) & 0x7) << 16) | (((rs1.value() >>> 5) & 0x1) << 14);
9745 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
9746 emitInt(instruction);
9747 }
9748
9749 /**
9750 * Pseudo-external assembler syntax: {@code fstox }<i>rs2</i>, <i>rd</i>
9751 * Example disassembly syntax: {@code fstox %f0, %f0}
9752 *
9753 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.14"
9754 */
9755 // Template#: 591, Serial#: 591
9756 public void fstox(final SFPR rs2, final DFPR rd) {
9757 int instruction = 0x81A01020;
9758 instruction |= (rs2.value() & 0x1f);
9759 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
9760 emitInt(instruction);
9761 }
9762
9763 /**
9764 * Pseudo-external assembler syntax: {@code fdtox }<i>rs2</i>, <i>rd</i>
9765 * Example disassembly syntax: {@code fdtox %f0, %f0}
9766 *
9767 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.14"
9768 */
9769 // Template#: 592, Serial#: 592
9770 public void fdtox(final DFPR rs2, final DFPR rd) {
9771 int instruction = 0x81A01040;
9772 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9773 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
9774 emitInt(instruction);
9775 }
9776
9777 /**
9778 * Pseudo-external assembler syntax: {@code fqtox }<i>rs2</i>, <i>rd</i>
9779 * Example disassembly syntax: {@code fqtox %f0, %f0}
9780 *
9781 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.14"
9782 */
9783 // Template#: 593, Serial#: 593
9784 public void fqtox(final QFPR rs2, final DFPR rd) {
9785 int instruction = 0x81A01060;
9786 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
9787 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
9788 emitInt(instruction);
9789 }
9790
9791 /**
9792 * Pseudo-external assembler syntax: {@code fstoi }<i>rs2</i>, <i>rd</i>
9793 * Example disassembly syntax: {@code fstoi %f0, %f0}
9794 *
9795 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.14"
9796 */
9797 // Template#: 594, Serial#: 594
9798 public void fstoi(final SFPR rs2, final SFPR rd) {
9799 int instruction = 0x81A01A20;
9800 instruction |= (rs2.value() & 0x1f);
9801 instruction |= ((rd.value() & 0x1f) << 25);
9802 emitInt(instruction);
9803 }
9804
9805 /**
9806 * Pseudo-external assembler syntax: {@code fdtoi }<i>rs2</i>, <i>rd</i>
9807 * Example disassembly syntax: {@code fdtoi %f0, %f0}
9808 *
9809 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.14"
9810 */
9811 // Template#: 595, Serial#: 595
9812 public void fdtoi(final DFPR rs2, final SFPR rd) {
9813 int instruction = 0x81A01A40;
9814 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9815 instruction |= ((rd.value() & 0x1f) << 25);
9816 emitInt(instruction);
9817 }
9818
9819 /**
9820 * Pseudo-external assembler syntax: {@code fqtoi }<i>rs2</i>, <i>rd</i>
9821 * Example disassembly syntax: {@code fqtoi %f0, %f0}
9822 *
9823 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.14"
9824 */
9825 // Template#: 596, Serial#: 596
9826 public void fqtoi(final QFPR rs2, final SFPR rd) {
9827 int instruction = 0x81A01A60;
9828 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
9829 instruction |= ((rd.value() & 0x1f) << 25);
9830 emitInt(instruction);
9831 }
9832
9833 /**
9834 * Pseudo-external assembler syntax: {@code fstod }<i>rs2</i>, <i>rd</i>
9835 * Example disassembly syntax: {@code fstod %f0, %f0}
9836 *
9837 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.15"
9838 */
9839 // Template#: 597, Serial#: 597
9840 public void fstod(final SFPR rs2, final DFPR rd) {
9841 int instruction = 0x81A01920;
9842 instruction |= (rs2.value() & 0x1f);
9843 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
9844 emitInt(instruction);
9845 }
9846
9847 /**
9848 * Pseudo-external assembler syntax: {@code fstoq }<i>rs2</i>, <i>rd</i>
9849 * Example disassembly syntax: {@code fstoq %f0, %f0}
9850 *
9851 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.15"
9852 */
9853 // Template#: 598, Serial#: 598
9854 public void fstoq(final SFPR rs2, final QFPR rd) {
9855 int instruction = 0x81A019A0;
9856 instruction |= (rs2.value() & 0x1f);
9857 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
9858 emitInt(instruction);
9859 }
9860
9861 /**
9862 * Pseudo-external assembler syntax: {@code fdtos }<i>rs2</i>, <i>rd</i>
9863 * Example disassembly syntax: {@code fdtos %f0, %f0}
9864 *
9865 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.15"
9866 */
9867 // Template#: 599, Serial#: 599
9868 public void fdtos(final DFPR rs2, final SFPR rd) {
9869 int instruction = 0x81A018C0;
9870 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9871 instruction |= ((rd.value() & 0x1f) << 25);
9872 emitInt(instruction);
9873 }
9874
9875 /**
9876 * Pseudo-external assembler syntax: {@code fdtoq }<i>rs2</i>, <i>rd</i>
9877 * Example disassembly syntax: {@code fdtoq %f0, %f0}
9878 *
9879 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.15"
9880 */
9881 // Template#: 600, Serial#: 600
9882 public void fdtoq(final DFPR rs2, final QFPR rd) {
9883 int instruction = 0x81A019C0;
9884 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9885 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
9886 emitInt(instruction);
9887 }
9888
9889 /**
9890 * Pseudo-external assembler syntax: {@code fqtos }<i>rs2</i>, <i>rd</i>
9891 * Example disassembly syntax: {@code fqtos %f0, %f0}
9892 *
9893 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.15"
9894 */
9895 // Template#: 601, Serial#: 601
9896 public void fqtos(final QFPR rs2, final SFPR rd) {
9897 int instruction = 0x81A018E0;
9898 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
9899 instruction |= ((rd.value() & 0x1f) << 25);
9900 emitInt(instruction);
9901 }
9902
9903 /**
9904 * Pseudo-external assembler syntax: {@code fqtod }<i>rs2</i>, <i>rd</i>
9905 * Example disassembly syntax: {@code fqtod %f0, %f0}
9906 *
9907 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.15"
9908 */
9909 // Template#: 602, Serial#: 602
9910 public void fqtod(final QFPR rs2, final DFPR rd) {
9911 int instruction = 0x81A01960;
9912 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
9913 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
9914 emitInt(instruction);
9915 }
9916
9917 /**
9918 * Pseudo-external assembler syntax: {@code fxtos }<i>rs2</i>, <i>rd</i>
9919 * Example disassembly syntax: {@code fxtos %f0, %f0}
9920 *
9921 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.16"
9922 */
9923 // Template#: 603, Serial#: 603
9924 public void fxtos(final DFPR rs2, final SFPR rd) {
9925 int instruction = 0x81A01080;
9926 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9927 instruction |= ((rd.value() & 0x1f) << 25);
9928 emitInt(instruction);
9929 }
9930
9931 /**
9932 * Pseudo-external assembler syntax: {@code fitos }<i>rs2</i>, <i>rd</i>
9933 * Example disassembly syntax: {@code fitos %f0, %f0}
9934 *
9935 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.16"
9936 */
9937 // Template#: 604, Serial#: 604
9938 public void fitos(final SFPR rs2, final SFPR rd) {
9939 int instruction = 0x81A01880;
9940 instruction |= (rs2.value() & 0x1f);
9941 instruction |= ((rd.value() & 0x1f) << 25);
9942 emitInt(instruction);
9943 }
9944
9945 /**
9946 * Pseudo-external assembler syntax: {@code fxtod }<i>rs2</i>, <i>rd</i>
9947 * Example disassembly syntax: {@code fxtod %f0, %f0}
9948 *
9949 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.16"
9950 */
9951 // Template#: 605, Serial#: 605
9952 public void fxtod(final DFPR rs2, final DFPR rd) {
9953 int instruction = 0x81A01100;
9954 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9955 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
9956 emitInt(instruction);
9957 }
9958
9959 /**
9960 * Pseudo-external assembler syntax: {@code fitod }<i>rs2</i>, <i>rd</i>
9961 * Example disassembly syntax: {@code fitod %f0, %f0}
9962 *
9963 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.16"
9964 */
9965 // Template#: 606, Serial#: 606
9966 public void fitod(final SFPR rs2, final DFPR rd) {
9967 int instruction = 0x81A01900;
9968 instruction |= (rs2.value() & 0x1f);
9969 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
9970 emitInt(instruction);
9971 }
9972
9973 /**
9974 * Pseudo-external assembler syntax: {@code fxtoq }<i>rs2</i>, <i>rd</i>
9975 * Example disassembly syntax: {@code fxtoq %f0, %f0}
9976 *
9977 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.16"
9978 */
9979 // Template#: 607, Serial#: 607
9980 public void fxtoq(final DFPR rs2, final QFPR rd) {
9981 int instruction = 0x81A01180;
9982 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
9983 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
9984 emitInt(instruction);
9985 }
9986
9987 /**
9988 * Pseudo-external assembler syntax: {@code fitoq }<i>rs2</i>, <i>rd</i>
9989 * Example disassembly syntax: {@code fitoq %f0, %f0}
9990 *
9991 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.16"
9992 */
9993 // Template#: 608, Serial#: 608
9994 public void fitoq(final SFPR rs2, final QFPR rd) {
9995 int instruction = 0x81A01980;
9996 instruction |= (rs2.value() & 0x1f);
9997 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
9998 emitInt(instruction);
9999 }
10000
10001 /**
10002 * Pseudo-external assembler syntax: {@code fmovs }<i>rs2</i>, <i>rd</i>
10003 * Example disassembly syntax: {@code fmovs %f0, %f0}
10004 *
10005 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.17"
10006 */
10007 // Template#: 609, Serial#: 609
10008 public void fmovs(final SFPR rs2, final SFPR rd) {
10009 int instruction = 0x81A00020;
10010 instruction |= (rs2.value() & 0x1f);
10011 instruction |= ((rd.value() & 0x1f) << 25);
10012 emitInt(instruction);
10013 }
10014
10015 /**
10016 * Pseudo-external assembler syntax: {@code fmovd }<i>rs2</i>, <i>rd</i>
10017 * Example disassembly syntax: {@code fmovd %f0, %f0}
10018 *
10019 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.17"
10020 */
10021 // Template#: 610, Serial#: 610
10022 public void fmovd(final DFPR rs2, final DFPR rd) {
10023 int instruction = 0x81A00040;
10024 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
10025 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
10026 emitInt(instruction);
10027 }
10028
10029 /**
10030 * Pseudo-external assembler syntax: {@code fmovq }<i>rs2</i>, <i>rd</i>
10031 * Example disassembly syntax: {@code fmovq %f0, %f0}
10032 *
10033 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.17"
10034 */
10035 // Template#: 611, Serial#: 611
10036 public void fmovq(final QFPR rs2, final QFPR rd) {
10037 int instruction = 0x81A00060;
10038 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
10039 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
10040 emitInt(instruction);
10041 }
10042
10043 /**
10044 * Pseudo-external assembler syntax: {@code fnegs }<i>rs2</i>, <i>rd</i>
10045 * Example disassembly syntax: {@code fnegs %f0, %f0}
10046 *
10047 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.17"
10048 */
10049 // Template#: 612, Serial#: 612
10050 public void fnegs(final SFPR rs2, final SFPR rd) {
10051 int instruction = 0x81A000A0;
10052 instruction |= (rs2.value() & 0x1f);
10053 instruction |= ((rd.value() & 0x1f) << 25);
10054 emitInt(instruction);
10055 }
10056
10057 /**
10058 * Pseudo-external assembler syntax: {@code fnegd }<i>rs2</i>, <i>rd</i>
10059 * Example disassembly syntax: {@code fnegd %f0, %f0}
10060 *
10061 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.17"
10062 */
10063 // Template#: 613, Serial#: 613
10064 public void fnegd(final DFPR rs2, final DFPR rd) {
10065 int instruction = 0x81A000C0;
10066 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
10067 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
10068 emitInt(instruction);
10069 }
10070
10071 /**
10072 * Pseudo-external assembler syntax: {@code fnegq }<i>rs2</i>, <i>rd</i>
10073 * Example disassembly syntax: {@code fnegq %f0, %f0}
10074 *
10075 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.17"
10076 */
10077 // Template#: 614, Serial#: 614
10078 public void fnegq(final QFPR rs2, final QFPR rd) {
10079 int instruction = 0x81A000E0;
10080 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
10081 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
10082 emitInt(instruction);
10083 }
10084
10085 /**
10086 * Pseudo-external assembler syntax: {@code fabss }<i>rs2</i>, <i>rd</i>
10087 * Example disassembly syntax: {@code fabss %f0, %f0}
10088 *
10089 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.17"
10090 */
10091 // Template#: 615, Serial#: 615
10092 public void fabss(final SFPR rs2, final SFPR rd) {
10093 int instruction = 0x81A00120;
10094 instruction |= (rs2.value() & 0x1f);
10095 instruction |= ((rd.value() & 0x1f) << 25);
10096 emitInt(instruction);
10097 }
10098
10099 /**
10100 * Pseudo-external assembler syntax: {@code fabsd }<i>rs2</i>, <i>rd</i>
10101 * Example disassembly syntax: {@code fabsd %f0, %f0}
10102 *
10103 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.17"
10104 */
10105 // Template#: 616, Serial#: 616
10106 public void fabsd(final DFPR rs2, final DFPR rd) {
10107 int instruction = 0x81A00140;
10108 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
10109 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
10110 emitInt(instruction);
10111 }
10112
10113 /**
10114 * Pseudo-external assembler syntax: {@code fabsq }<i>rs2</i>, <i>rd</i>
10115 * Example disassembly syntax: {@code fabsq %f0, %f0}
10116 *
10117 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.17"
10118 */
10119 // Template#: 617, Serial#: 617
10120 public void fabsq(final QFPR rs2, final QFPR rd) {
10121 int instruction = 0x81A00160;
10122 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
10123 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
10124 emitInt(instruction);
10125 }
10126
10127 /**
10128 * Pseudo-external assembler syntax: {@code fmuls }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
10129 * Example disassembly syntax: {@code fmuls %f0, %f0, %f0}
10130 *
10131 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.18"
10132 */
10133 // Template#: 618, Serial#: 618
10134 public void fmuls(final SFPR rs1, final SFPR rs2, final SFPR rd) {
10135 int instruction = 0x81A00920;
10136 instruction |= ((rs1.value() & 0x1f) << 14);
10137 instruction |= (rs2.value() & 0x1f);
10138 instruction |= ((rd.value() & 0x1f) << 25);
10139 emitInt(instruction);
10140 }
10141
10142 /**
10143 * Pseudo-external assembler syntax: {@code fmuld }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
10144 * Example disassembly syntax: {@code fmuld %f0, %f0, %f0}
10145 *
10146 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.18"
10147 */
10148 // Template#: 619, Serial#: 619
10149 public void fmuld(final DFPR rs1, final DFPR rs2, final DFPR rd) {
10150 int instruction = 0x81A00940;
10151 instruction |= (((rs1.value() >>> 1) & 0xf) << 15) | (((rs1.value() >>> 5) & 0x1) << 14);
10152 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
10153 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
10154 emitInt(instruction);
10155 }
10156
10157 /**
10158 * Pseudo-external assembler syntax: {@code fmulq }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
10159 * Example disassembly syntax: {@code fmulq %f0, %f0, %f0}
10160 *
10161 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.18"
10162 */
10163 // Template#: 620, Serial#: 620
10164 public void fmulq(final QFPR rs1, final QFPR rs2, final QFPR rd) {
10165 int instruction = 0x81A00960;
10166 instruction |= (((rs1.value() >>> 2) & 0x7) << 16) | (((rs1.value() >>> 5) & 0x1) << 14);
10167 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
10168 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
10169 emitInt(instruction);
10170 }
10171
10172 /**
10173 * Pseudo-external assembler syntax: {@code fdivs }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
10174 * Example disassembly syntax: {@code fdivs %f0, %f0, %f0}
10175 *
10176 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.18"
10177 */
10178 // Template#: 621, Serial#: 621
10179 public void fdivs(final SFPR rs1, final SFPR rs2, final SFPR rd) {
10180 int instruction = 0x81A009A0;
10181 instruction |= ((rs1.value() & 0x1f) << 14);
10182 instruction |= (rs2.value() & 0x1f);
10183 instruction |= ((rd.value() & 0x1f) << 25);
10184 emitInt(instruction);
10185 }
10186
10187 /**
10188 * Pseudo-external assembler syntax: {@code fdivd }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
10189 * Example disassembly syntax: {@code fdivd %f0, %f0, %f0}
10190 *
10191 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.18"
10192 */
10193 // Template#: 622, Serial#: 622
10194 public void fdivd(final DFPR rs1, final DFPR rs2, final DFPR rd) {
10195 int instruction = 0x81A009C0;
10196 instruction |= (((rs1.value() >>> 1) & 0xf) << 15) | (((rs1.value() >>> 5) & 0x1) << 14);
10197 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
10198 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
10199 emitInt(instruction);
10200 }
10201
10202 /**
10203 * Pseudo-external assembler syntax: {@code fdivq }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
10204 * Example disassembly syntax: {@code fdivq %f0, %f0, %f0}
10205 *
10206 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.18"
10207 */
10208 // Template#: 623, Serial#: 623
10209 public void fdivq(final QFPR rs1, final QFPR rs2, final QFPR rd) {
10210 int instruction = 0x81A009E0;
10211 instruction |= (((rs1.value() >>> 2) & 0x7) << 16) | (((rs1.value() >>> 5) & 0x1) << 14);
10212 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
10213 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
10214 emitInt(instruction);
10215 }
10216
10217 /**
10218 * Pseudo-external assembler syntax: {@code fsmuld }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
10219 * Example disassembly syntax: {@code fsmuld %f0, %f0, %f0}
10220 *
10221 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.18"
10222 */
10223 // Template#: 624, Serial#: 624
10224 public void fsmuld(final SFPR rs1, final SFPR rs2, final DFPR rd) {
10225 int instruction = 0x81A00D20;
10226 instruction |= ((rs1.value() & 0x1f) << 14);
10227 instruction |= (rs2.value() & 0x1f);
10228 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
10229 emitInt(instruction);
10230 }
10231
10232 /**
10233 * Pseudo-external assembler syntax: {@code fdmulq }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
10234 * Example disassembly syntax: {@code fdmulq %f0, %f0, %f0}
10235 *
10236 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.18"
10237 */
10238 // Template#: 625, Serial#: 625
10239 public void fdmulq(final DFPR rs1, final DFPR rs2, final QFPR rd) {
10240 int instruction = 0x81A00DC0;
10241 instruction |= (((rs1.value() >>> 1) & 0xf) << 15) | (((rs1.value() >>> 5) & 0x1) << 14);
10242 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
10243 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
10244 emitInt(instruction);
10245 }
10246
10247 /**
10248 * Pseudo-external assembler syntax: {@code fsqrts }<i>rs2</i>, <i>rd</i>
10249 * Example disassembly syntax: {@code fsqrts %f0, %f0}
10250 *
10251 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.19"
10252 */
10253 // Template#: 626, Serial#: 626
10254 public void fsqrts(final SFPR rs2, final SFPR rd) {
10255 int instruction = 0x81A00520;
10256 instruction |= (rs2.value() & 0x1f);
10257 instruction |= ((rd.value() & 0x1f) << 25);
10258 emitInt(instruction);
10259 }
10260
10261 /**
10262 * Pseudo-external assembler syntax: {@code fsqrtd }<i>rs2</i>, <i>rd</i>
10263 * Example disassembly syntax: {@code fsqrtd %f0, %f0}
10264 *
10265 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.19"
10266 */
10267 // Template#: 627, Serial#: 627
10268 public void fsqrtd(final DFPR rs2, final DFPR rd) {
10269 int instruction = 0x81A00540;
10270 instruction |= (((rs2.value() >>> 1) & 0xf) << 1) | ((rs2.value() >>> 5) & 0x1);
10271 instruction |= (((rd.value() >>> 1) & 0xf) << 26) | (((rd.value() >>> 5) & 0x1) << 25);
10272 emitInt(instruction);
10273 }
10274
10275 /**
10276 * Pseudo-external assembler syntax: {@code fsqrtq }<i>rs2</i>, <i>rd</i>
10277 * Example disassembly syntax: {@code fsqrtq %f0, %f0}
10278 *
10279 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.19"
10280 */
10281 // Template#: 628, Serial#: 628
10282 public void fsqrtq(final QFPR rs2, final QFPR rd) {
10283 int instruction = 0x81A00560;
10284 instruction |= (((rs2.value() >>> 2) & 0x7) << 2) | ((rs2.value() >>> 5) & 0x1);
10285 instruction |= (((rd.value() >>> 2) & 0x7) << 27) | (((rd.value() >>> 5) & 0x1) << 25);
10286 emitInt(instruction);
10287 }
10288
10289 /**
10290 * Pseudo-external assembler syntax: {@code impdep1 }
10291 * Example disassembly syntax: {@code impdep1 }
10292 *
10293 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.23"
10294 */
10295 // Template#: 629, Serial#: 629
10296 public void impdep1() {
10297 int instruction = 0x81B00000;
10298 emitInt(instruction);
10299 }
10300
10301 /**
10302 * Pseudo-external assembler syntax: {@code impdep2 }
10303 * Example disassembly syntax: {@code impdep2 }
10304 *
10305 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.23"
10306 */
10307 // Template#: 630, Serial#: 630
10308 public void impdep2() {
10309 int instruction = 0x81B80000;
10310 emitInt(instruction);
10311 }
10312
10313 /**
10314 * Pseudo-external assembler syntax: {@code nop }
10315 * Example disassembly syntax: {@code nop }
10316 * <p>
10317 * This is a synthetic instruction equivalent to: {@code sethi(0, G0)}
10318 *
10319 * @see #sethi(int, GPR)
10320 *
10321 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section A.39"
10322 */
10323 // Template#: 631, Serial#: 631
10324 public void nop() {
10325 int instruction = 0x01000000;
10326 emitInt(instruction);
10327 }
10328
10329 /**
10330 * Pseudo-external assembler syntax: {@code cmp }<i>rs1</i>, <i>rs2</i>
10331 * Example disassembly syntax: {@code cmp %g0, %g0}
10332 * <p>
10333 * This is a synthetic instruction equivalent to: {@code subcc(rs1, rs2, G0)}
10334 *
10335 * @see #subcc(GPR, GPR, GPR)
10336 *
10337 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10338 */
10339 // Template#: 632, Serial#: 632
10340 public void cmp(final GPR rs1, final GPR rs2) {
10341 int instruction = 0x80A00000;
10342 instruction |= ((rs1.value() & 0x1f) << 14);
10343 instruction |= (rs2.value() & 0x1f);
10344 emitInt(instruction);
10345 }
10346
10347 /**
10348 * Pseudo-external assembler syntax: {@code cmp }<i>rs1</i>, <i>simm13</i>
10349 * Example disassembly syntax: {@code cmp %g0, -4096}
10350 * <p>
10351 * This is a synthetic instruction equivalent to: {@code subcc(rs1, simm13, G0)}
10352 * <p>
10353 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
10354 *
10355 * @see #subcc(GPR, int, GPR)
10356 *
10357 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10358 */
10359 // Template#: 633, Serial#: 633
10360 public void cmp(final GPR rs1, final int simm13) {
10361 int instruction = 0x80A02000;
10362 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
10363 instruction |= ((rs1.value() & 0x1f) << 14);
10364 instruction |= (simm13 & 0x1fff);
10365 emitInt(instruction);
10366 }
10367
10368 /**
10369 * Pseudo-external assembler syntax: {@code jmp }<i>rs1</i>, <i>rs2</i>
10370 * Example disassembly syntax: {@code jmp %g0 + %g0}
10371 * <p>
10372 * This is a synthetic instruction equivalent to: {@code jmpl(rs1, rs2, G0)}
10373 *
10374 * @see #jmpl(GPR, GPR, GPR)
10375 *
10376 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10377 */
10378 // Template#: 634, Serial#: 634
10379 public void jmp(final GPR rs1, final GPR rs2) {
10380 int instruction = 0x81C00000;
10381 instruction |= ((rs1.value() & 0x1f) << 14);
10382 instruction |= (rs2.value() & 0x1f);
10383 emitInt(instruction);
10384 }
10385
10386 /**
10387 * Pseudo-external assembler syntax: {@code jmp }<i>rs1</i>, <i>simm13</i>
10388 * Example disassembly syntax: {@code jmp %g0 + -4096}
10389 * <p>
10390 * This is a synthetic instruction equivalent to: {@code jmpl(rs1, simm13, G0)}
10391 * <p>
10392 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
10393 *
10394 * @see #jmpl(GPR, int, GPR)
10395 *
10396 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10397 */
10398 // Template#: 635, Serial#: 635
10399 public void jmp(final GPR rs1, final int simm13) {
10400 int instruction = 0x81C02000;
10401 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
10402 instruction |= ((rs1.value() & 0x1f) << 14);
10403 instruction |= (simm13 & 0x1fff);
10404 emitInt(instruction);
10405 }
10406
10407 /**
10408 * Pseudo-external assembler syntax: {@code call }<i>rs1</i>, <i>rs2</i>
10409 * Example disassembly syntax: {@code call %g0 + %g0}
10410 * <p>
10411 * This is a synthetic instruction equivalent to: {@code jmpl(rs1, rs2, O7)}
10412 *
10413 * @see #jmpl(GPR, GPR, GPR)
10414 *
10415 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10416 */
10417 // Template#: 636, Serial#: 636
10418 public void call(final GPR rs1, final GPR rs2) {
10419 int instruction = 0x9FC00000;
10420 instruction |= ((rs1.value() & 0x1f) << 14);
10421 instruction |= (rs2.value() & 0x1f);
10422 emitInt(instruction);
10423 }
10424
10425 /**
10426 * Pseudo-external assembler syntax: {@code call }<i>rs1</i>, <i>simm13</i>
10427 * Example disassembly syntax: {@code call %g0 + -4096}
10428 * <p>
10429 * This is a synthetic instruction equivalent to: {@code jmpl(rs1, simm13, O7)}
10430 * <p>
10431 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
10432 *
10433 * @see #jmpl(GPR, int, GPR)
10434 *
10435 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10436 */
10437 // Template#: 637, Serial#: 637
10438 public void call(final GPR rs1, final int simm13) {
10439 int instruction = 0x9FC02000;
10440 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
10441 instruction |= ((rs1.value() & 0x1f) << 14);
10442 instruction |= (simm13 & 0x1fff);
10443 emitInt(instruction);
10444 }
10445
10446 /**
10447 * Pseudo-external assembler syntax: {@code iprefetch }<i>label</i>
10448 * Example disassembly syntax: {@code iprefetch L1: -1048576}
10449 * <p>
10450 * This is a synthetic instruction equivalent to: {@code b(N, A, PT, XCC, label)}
10451 * <p>
10452 * Constraint: {@code (-1048576 <= label && label <= 1048572) && ((label % 4) == 0)}<br />
10453 *
10454 * @see #b(Bicc, AnnulBit, BranchPredictionBit, ICCOperand, int)
10455 *
10456 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10457 */
10458 // Template#: 638, Serial#: 638
10459 public void iprefetch(final int label) {
10460 int instruction = 0x20680000;
10461 checkConstraint((-1048576 <= label && label <= 1048572) && ((label % 4) == 0), "(-1048576 <= label && label <= 1048572) && ((label % 4) == 0)");
10462 instruction |= ((label >> 2) & 0x7ffff);
10463 emitInt(instruction);
10464 }
10465
10466 /**
10467 * Pseudo-external assembler syntax: {@code tst }<i>rs2</i>
10468 * Example disassembly syntax: {@code tst %g0}
10469 * <p>
10470 * This is a synthetic instruction equivalent to: {@code orcc(G0, rs2, G0)}
10471 *
10472 * @see #orcc(GPR, GPR, GPR)
10473 *
10474 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10475 */
10476 // Template#: 639, Serial#: 639
10477 public void tst(final GPR rs2) {
10478 int instruction = 0x80900000;
10479 instruction |= (rs2.value() & 0x1f);
10480 emitInt(instruction);
10481 }
10482
10483 /**
10484 * Pseudo-external assembler syntax: {@code ret }
10485 * Example disassembly syntax: {@code ret }
10486 * <p>
10487 * This is a synthetic instruction equivalent to: {@code jmpl(I7, 8, G0)}
10488 *
10489 * @see #jmpl(GPR, int, GPR)
10490 *
10491 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10492 */
10493 // Template#: 640, Serial#: 640
10494 public void ret() {
10495 int instruction = 0x81C7E008;
10496 emitInt(instruction);
10497 }
10498
10499 /**
10500 * Pseudo-external assembler syntax: {@code retl }
10501 * Example disassembly syntax: {@code retl }
10502 * <p>
10503 * This is a synthetic instruction equivalent to: {@code jmpl(O7, 8, G0)}
10504 *
10505 * @see #jmpl(GPR, int, GPR)
10506 *
10507 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10508 */
10509 // Template#: 641, Serial#: 641
10510 public void retl() {
10511 int instruction = 0x81C3E008;
10512 emitInt(instruction);
10513 }
10514
10515 /**
10516 * Pseudo-external assembler syntax: {@code restore }
10517 * Example disassembly syntax: {@code restore }
10518 * <p>
10519 * This is a synthetic instruction equivalent to: {@code restore(G0, G0, G0)}
10520 *
10521 * @see #restore(GPR, GPR, GPR)
10522 *
10523 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10524 */
10525 // Template#: 642, Serial#: 642
10526 public void restore() {
10527 int instruction = 0x81E80000;
10528 emitInt(instruction);
10529 }
10530
10531 /**
10532 * Pseudo-external assembler syntax: {@code save }
10533 * Example disassembly syntax: {@code save }
10534 * <p>
10535 * This is a synthetic instruction equivalent to: {@code save(G0, G0, G0)}
10536 *
10537 * @see #save(GPR, GPR, GPR)
10538 *
10539 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10540 */
10541 // Template#: 643, Serial#: 643
10542 public void save() {
10543 int instruction = 0x81E00000;
10544 emitInt(instruction);
10545 }
10546
10547 /**
10548 * Pseudo-external assembler syntax: {@code signx }<i>rs1</i>, <i>rd</i>
10549 * Example disassembly syntax: {@code signx %g0, %g0}
10550 * <p>
10551 * This is a synthetic instruction equivalent to: {@code sra(rs1, G0, rd)}
10552 *
10553 * @see #sra(GPR, GPR, GPR)
10554 *
10555 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10556 */
10557 // Template#: 644, Serial#: 644
10558 public void signx(final GPR rs1, final GPR rd) {
10559 int instruction = 0x81380000;
10560 instruction |= ((rs1.value() & 0x1f) << 14);
10561 instruction |= ((rd.value() & 0x1f) << 25);
10562 emitInt(instruction);
10563 }
10564
10565 /**
10566 * Pseudo-external assembler syntax: {@code signx }<i>rd</i>
10567 * Example disassembly syntax: {@code signx %g0}
10568 * <p>
10569 * This is a synthetic instruction equivalent to: {@code sra(rd.value(), G0, rd)}
10570 *
10571 * @see #sra(GPR, GPR, GPR)
10572 *
10573 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10574 */
10575 // Template#: 645, Serial#: 645
10576 public void signx(final GPR rd) {
10577 int instruction = 0x81380000;
10578 instruction |= ((rd.value() & 0x1f) << 14);
10579 instruction |= ((rd.value() & 0x1f) << 25);
10580 emitInt(instruction);
10581 }
10582
10583 /**
10584 * Pseudo-external assembler syntax: {@code not }<i>rs1</i>, <i>rd</i>
10585 * Example disassembly syntax: {@code not %g0, %g0}
10586 * <p>
10587 * This is a synthetic instruction equivalent to: {@code xnor(rs1, G0, rd)}
10588 *
10589 * @see #xnor(GPR, GPR, GPR)
10590 *
10591 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10592 */
10593 // Template#: 646, Serial#: 646
10594 public void not(final GPR rs1, final GPR rd) {
10595 int instruction = 0x80380000;
10596 instruction |= ((rs1.value() & 0x1f) << 14);
10597 instruction |= ((rd.value() & 0x1f) << 25);
10598 emitInt(instruction);
10599 }
10600
10601 /**
10602 * Pseudo-external assembler syntax: {@code not }<i>rd</i>
10603 * Example disassembly syntax: {@code not %g0}
10604 * <p>
10605 * This is a synthetic instruction equivalent to: {@code xnor(rd.value(), G0, rd)}
10606 *
10607 * @see #xnor(GPR, GPR, GPR)
10608 *
10609 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10610 */
10611 // Template#: 647, Serial#: 647
10612 public void not(final GPR rd) {
10613 int instruction = 0x80380000;
10614 instruction |= ((rd.value() & 0x1f) << 14);
10615 instruction |= ((rd.value() & 0x1f) << 25);
10616 emitInt(instruction);
10617 }
10618
10619 /**
10620 * Pseudo-external assembler syntax: {@code neg }<i>rs2</i>, <i>rd</i>
10621 * Example disassembly syntax: {@code neg %g0, %g0}
10622 * <p>
10623 * This is a synthetic instruction equivalent to: {@code sub(G0, rs2, rd)}
10624 *
10625 * @see #sub(GPR, GPR, GPR)
10626 *
10627 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10628 */
10629 // Template#: 648, Serial#: 648
10630 public void neg(final GPR rs2, final GPR rd) {
10631 int instruction = 0x80200000;
10632 instruction |= (rs2.value() & 0x1f);
10633 instruction |= ((rd.value() & 0x1f) << 25);
10634 emitInt(instruction);
10635 }
10636
10637 /**
10638 * Pseudo-external assembler syntax: {@code neg }<i>rd</i>
10639 * Example disassembly syntax: {@code neg %g0}
10640 * <p>
10641 * This is a synthetic instruction equivalent to: {@code sub(G0, rd.value(), rd)}
10642 *
10643 * @see #sub(GPR, GPR, GPR)
10644 *
10645 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10646 */
10647 // Template#: 649, Serial#: 649
10648 public void neg(final GPR rd) {
10649 int instruction = 0x80200000;
10650 instruction |= (rd.value() & 0x1f);
10651 instruction |= ((rd.value() & 0x1f) << 25);
10652 emitInt(instruction);
10653 }
10654
10655 /**
10656 * Pseudo-external assembler syntax: {@code cas }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
10657 * Example disassembly syntax: {@code cas [%g0] ,%g0, %g0}
10658 * <p>
10659 * This is a synthetic instruction equivalent to: {@code casa(rs1, 128, rs2, rd)}
10660 *
10661 * @see #casa(GPR, int, GPR, GPR)
10662 *
10663 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10664 */
10665 // Template#: 650, Serial#: 650
10666 public void cas(final GPR rs1, final GPR rs2, final GPR rd) {
10667 int instruction = 0xC1E01000;
10668 instruction |= ((rs1.value() & 0x1f) << 14);
10669 instruction |= (rs2.value() & 0x1f);
10670 instruction |= ((rd.value() & 0x1f) << 25);
10671 emitInt(instruction);
10672 }
10673
10674 /**
10675 * Pseudo-external assembler syntax: {@code casl }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
10676 * Example disassembly syntax: {@code casl [%g0] ,%g0, %g0}
10677 * <p>
10678 * This is a synthetic instruction equivalent to: {@code casa(rs1, 136, rs2, rd)}
10679 *
10680 * @see #casa(GPR, int, GPR, GPR)
10681 *
10682 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10683 */
10684 // Template#: 651, Serial#: 651
10685 public void casl(final GPR rs1, final GPR rs2, final GPR rd) {
10686 int instruction = 0xC1E01100;
10687 instruction |= ((rs1.value() & 0x1f) << 14);
10688 instruction |= (rs2.value() & 0x1f);
10689 instruction |= ((rd.value() & 0x1f) << 25);
10690 emitInt(instruction);
10691 }
10692
10693 /**
10694 * Pseudo-external assembler syntax: {@code casx }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
10695 * Example disassembly syntax: {@code casx [%g0] ,%g0, %g0}
10696 * <p>
10697 * This is a synthetic instruction equivalent to: {@code casxa(rs1, 128, rs2, rd)}
10698 *
10699 * @see #casxa(GPR, int, GPR, GPR)
10700 *
10701 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10702 */
10703 // Template#: 652, Serial#: 652
10704 public void casx(final GPR rs1, final GPR rs2, final GPR rd) {
10705 int instruction = 0xC1F01000;
10706 instruction |= ((rs1.value() & 0x1f) << 14);
10707 instruction |= (rs2.value() & 0x1f);
10708 instruction |= ((rd.value() & 0x1f) << 25);
10709 emitInt(instruction);
10710 }
10711
10712 /**
10713 * Pseudo-external assembler syntax: {@code casxl }<i>rs1</i>, <i>rs2</i>, <i>rd</i>
10714 * Example disassembly syntax: {@code casxl [%g0] ,%g0, %g0}
10715 * <p>
10716 * This is a synthetic instruction equivalent to: {@code casxa(rs1, 136, rs2, rd)}
10717 *
10718 * @see #casxa(GPR, int, GPR, GPR)
10719 *
10720 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10721 */
10722 // Template#: 653, Serial#: 653
10723 public void casxl(final GPR rs1, final GPR rs2, final GPR rd) {
10724 int instruction = 0xC1F01100;
10725 instruction |= ((rs1.value() & 0x1f) << 14);
10726 instruction |= (rs2.value() & 0x1f);
10727 instruction |= ((rd.value() & 0x1f) << 25);
10728 emitInt(instruction);
10729 }
10730
10731 /**
10732 * Pseudo-external assembler syntax: {@code inc }<i>rd</i>
10733 * Example disassembly syntax: {@code inc %g0}
10734 * <p>
10735 * This is a synthetic instruction equivalent to: {@code add(rd.value(), 1, rd)}
10736 *
10737 * @see #add(GPR, int, GPR)
10738 *
10739 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10740 */
10741 // Template#: 654, Serial#: 654
10742 public void inc(final GPR rd) {
10743 int instruction = 0x80002001;
10744 instruction |= ((rd.value() & 0x1f) << 14);
10745 instruction |= ((rd.value() & 0x1f) << 25);
10746 emitInt(instruction);
10747 }
10748
10749 /**
10750 * Pseudo-external assembler syntax: {@code inc }<i>simm13</i>, <i>rd</i>
10751 * Example disassembly syntax: {@code inc -4096, %g0}
10752 * <p>
10753 * This is a synthetic instruction equivalent to: {@code add(rd.value(), simm13, rd)}
10754 * <p>
10755 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
10756 *
10757 * @see #add(GPR, int, GPR)
10758 *
10759 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10760 */
10761 // Template#: 655, Serial#: 655
10762 public void inc(final int simm13, final GPR rd) {
10763 int instruction = 0x80002000;
10764 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
10765 instruction |= ((rd.value() & 0x1f) << 14);
10766 instruction |= (simm13 & 0x1fff);
10767 instruction |= ((rd.value() & 0x1f) << 25);
10768 emitInt(instruction);
10769 }
10770
10771 /**
10772 * Pseudo-external assembler syntax: {@code inccc }<i>rd</i>
10773 * Example disassembly syntax: {@code inccc %g0}
10774 * <p>
10775 * This is a synthetic instruction equivalent to: {@code addcc(rd.value(), 1, rd)}
10776 *
10777 * @see #addcc(GPR, int, GPR)
10778 *
10779 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10780 */
10781 // Template#: 656, Serial#: 656
10782 public void inccc(final GPR rd) {
10783 int instruction = 0x80802001;
10784 instruction |= ((rd.value() & 0x1f) << 14);
10785 instruction |= ((rd.value() & 0x1f) << 25);
10786 emitInt(instruction);
10787 }
10788
10789 /**
10790 * Pseudo-external assembler syntax: {@code inccc }<i>simm13</i>, <i>rd</i>
10791 * Example disassembly syntax: {@code inccc -4096, %g0}
10792 * <p>
10793 * This is a synthetic instruction equivalent to: {@code addcc(rd.value(), simm13, rd)}
10794 * <p>
10795 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
10796 *
10797 * @see #addcc(GPR, int, GPR)
10798 *
10799 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10800 */
10801 // Template#: 657, Serial#: 657
10802 public void inccc(final int simm13, final GPR rd) {
10803 int instruction = 0x80802000;
10804 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
10805 instruction |= ((rd.value() & 0x1f) << 14);
10806 instruction |= (simm13 & 0x1fff);
10807 instruction |= ((rd.value() & 0x1f) << 25);
10808 emitInt(instruction);
10809 }
10810
10811 /**
10812 * Pseudo-external assembler syntax: {@code dec }<i>rd</i>
10813 * Example disassembly syntax: {@code dec %g0}
10814 * <p>
10815 * This is a synthetic instruction equivalent to: {@code sub(rd.value(), 1, rd)}
10816 *
10817 * @see #sub(GPR, int, GPR)
10818 *
10819 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10820 */
10821 // Template#: 658, Serial#: 658
10822 public void dec(final GPR rd) {
10823 int instruction = 0x80202001;
10824 instruction |= ((rd.value() & 0x1f) << 14);
10825 instruction |= ((rd.value() & 0x1f) << 25);
10826 emitInt(instruction);
10827 }
10828
10829 /**
10830 * Pseudo-external assembler syntax: {@code dec }<i>simm13</i>, <i>rd</i>
10831 * Example disassembly syntax: {@code dec -4096, %g0}
10832 * <p>
10833 * This is a synthetic instruction equivalent to: {@code sub(rd.value(), simm13, rd)}
10834 * <p>
10835 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
10836 *
10837 * @see #sub(GPR, int, GPR)
10838 *
10839 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10840 */
10841 // Template#: 659, Serial#: 659
10842 public void dec(final int simm13, final GPR rd) {
10843 int instruction = 0x80202000;
10844 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
10845 instruction |= ((rd.value() & 0x1f) << 14);
10846 instruction |= (simm13 & 0x1fff);
10847 instruction |= ((rd.value() & 0x1f) << 25);
10848 emitInt(instruction);
10849 }
10850
10851 /**
10852 * Pseudo-external assembler syntax: {@code deccc }<i>rd</i>
10853 * Example disassembly syntax: {@code deccc %g0}
10854 * <p>
10855 * This is a synthetic instruction equivalent to: {@code subcc(rd.value(), 1, rd)}
10856 *
10857 * @see #subcc(GPR, int, GPR)
10858 *
10859 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10860 */
10861 // Template#: 660, Serial#: 660
10862 public void deccc(final GPR rd) {
10863 int instruction = 0x80A02001;
10864 instruction |= ((rd.value() & 0x1f) << 14);
10865 instruction |= ((rd.value() & 0x1f) << 25);
10866 emitInt(instruction);
10867 }
10868
10869 /**
10870 * Pseudo-external assembler syntax: {@code deccc }<i>simm13</i>, <i>rd</i>
10871 * Example disassembly syntax: {@code deccc -4096, %g0}
10872 * <p>
10873 * This is a synthetic instruction equivalent to: {@code subcc(rd.value(), simm13, rd)}
10874 * <p>
10875 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
10876 *
10877 * @see #subcc(GPR, int, GPR)
10878 *
10879 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10880 */
10881 // Template#: 661, Serial#: 661
10882 public void deccc(final int simm13, final GPR rd) {
10883 int instruction = 0x80A02000;
10884 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
10885 instruction |= ((rd.value() & 0x1f) << 14);
10886 instruction |= (simm13 & 0x1fff);
10887 instruction |= ((rd.value() & 0x1f) << 25);
10888 emitInt(instruction);
10889 }
10890
10891 /**
10892 * Pseudo-external assembler syntax: {@code btst }<i>rs2</i>, <i>rs1</i>
10893 * Example disassembly syntax: {@code btst %g0, %g0}
10894 * <p>
10895 * This is a synthetic instruction equivalent to: {@code andcc(rs1, rs2, G0)}
10896 *
10897 * @see #andcc(GPR, GPR, GPR)
10898 *
10899 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10900 */
10901 // Template#: 662, Serial#: 662
10902 public void btst(final GPR rs2, final GPR rs1) {
10903 int instruction = 0x80880000;
10904 instruction |= (rs2.value() & 0x1f);
10905 instruction |= ((rs1.value() & 0x1f) << 14);
10906 emitInt(instruction);
10907 }
10908
10909 /**
10910 * Pseudo-external assembler syntax: {@code btst }<i>simm13</i>, <i>rs1</i>
10911 * Example disassembly syntax: {@code btst -4096, %g0}
10912 * <p>
10913 * This is a synthetic instruction equivalent to: {@code andcc(rs1, simm13, G0)}
10914 * <p>
10915 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
10916 *
10917 * @see #andcc(GPR, int, GPR)
10918 *
10919 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10920 */
10921 // Template#: 663, Serial#: 663
10922 public void btst(final int simm13, final GPR rs1) {
10923 int instruction = 0x80882000;
10924 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
10925 instruction |= (simm13 & 0x1fff);
10926 instruction |= ((rs1.value() & 0x1f) << 14);
10927 emitInt(instruction);
10928 }
10929
10930 /**
10931 * Pseudo-external assembler syntax: {@code bset }<i>rs2</i>, <i>rd</i>
10932 * Example disassembly syntax: {@code bset %g0, %g0}
10933 * <p>
10934 * This is a synthetic instruction equivalent to: {@code or(rd.value(), rs2, rd)}
10935 *
10936 * @see #or(GPR, GPR, GPR)
10937 *
10938 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10939 */
10940 // Template#: 664, Serial#: 664
10941 public void bset(final GPR rs2, final GPR rd) {
10942 int instruction = 0x80100000;
10943 instruction |= ((rd.value() & 0x1f) << 14);
10944 instruction |= (rs2.value() & 0x1f);
10945 instruction |= ((rd.value() & 0x1f) << 25);
10946 emitInt(instruction);
10947 }
10948
10949 /**
10950 * Pseudo-external assembler syntax: {@code bset }<i>simm13</i>, <i>rd</i>
10951 * Example disassembly syntax: {@code bset -4096, %g0}
10952 * <p>
10953 * This is a synthetic instruction equivalent to: {@code or(rd.value(), simm13, rd)}
10954 * <p>
10955 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
10956 *
10957 * @see #or(GPR, int, GPR)
10958 *
10959 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10960 */
10961 // Template#: 665, Serial#: 665
10962 public void bset(final int simm13, final GPR rd) {
10963 int instruction = 0x80102000;
10964 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
10965 instruction |= ((rd.value() & 0x1f) << 14);
10966 instruction |= (simm13 & 0x1fff);
10967 instruction |= ((rd.value() & 0x1f) << 25);
10968 emitInt(instruction);
10969 }
10970
10971 /**
10972 * Pseudo-external assembler syntax: {@code bclr }<i>rs2</i>, <i>rd</i>
10973 * Example disassembly syntax: {@code bclr %g0, %g0}
10974 * <p>
10975 * This is a synthetic instruction equivalent to: {@code andn(rd.value(), rs2, rd)}
10976 *
10977 * @see #andn(GPR, GPR, GPR)
10978 *
10979 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
10980 */
10981 // Template#: 666, Serial#: 666
10982 public void bclr(final GPR rs2, final GPR rd) {
10983 int instruction = 0x80280000;
10984 instruction |= ((rd.value() & 0x1f) << 14);
10985 instruction |= (rs2.value() & 0x1f);
10986 instruction |= ((rd.value() & 0x1f) << 25);
10987 emitInt(instruction);
10988 }
10989
10990 /**
10991 * Pseudo-external assembler syntax: {@code bclr }<i>simm13</i>, <i>rd</i>
10992 * Example disassembly syntax: {@code bclr -4096, %g0}
10993 * <p>
10994 * This is a synthetic instruction equivalent to: {@code andn(rd.value(), simm13, rd)}
10995 * <p>
10996 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
10997 *
10998 * @see #andn(GPR, int, GPR)
10999 *
11000 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11001 */
11002 // Template#: 667, Serial#: 667
11003 public void bclr(final int simm13, final GPR rd) {
11004 int instruction = 0x80282000;
11005 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
11006 instruction |= ((rd.value() & 0x1f) << 14);
11007 instruction |= (simm13 & 0x1fff);
11008 instruction |= ((rd.value() & 0x1f) << 25);
11009 emitInt(instruction);
11010 }
11011
11012 /**
11013 * Pseudo-external assembler syntax: {@code btog }<i>rs2</i>, <i>rd</i>
11014 * Example disassembly syntax: {@code btog %g0, %g0}
11015 * <p>
11016 * This is a synthetic instruction equivalent to: {@code xor(rd.value(), rs2, rd)}
11017 *
11018 * @see #xor(GPR, GPR, GPR)
11019 *
11020 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11021 */
11022 // Template#: 668, Serial#: 668
11023 public void btog(final GPR rs2, final GPR rd) {
11024 int instruction = 0x80180000;
11025 instruction |= ((rd.value() & 0x1f) << 14);
11026 instruction |= (rs2.value() & 0x1f);
11027 instruction |= ((rd.value() & 0x1f) << 25);
11028 emitInt(instruction);
11029 }
11030
11031 /**
11032 * Pseudo-external assembler syntax: {@code btog }<i>simm13</i>, <i>rd</i>
11033 * Example disassembly syntax: {@code btog -4096, %g0}
11034 * <p>
11035 * This is a synthetic instruction equivalent to: {@code xor(rd.value(), simm13, rd)}
11036 * <p>
11037 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
11038 *
11039 * @see #xor(GPR, int, GPR)
11040 *
11041 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11042 */
11043 // Template#: 669, Serial#: 669
11044 public void btog(final int simm13, final GPR rd) {
11045 int instruction = 0x80182000;
11046 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
11047 instruction |= ((rd.value() & 0x1f) << 14);
11048 instruction |= (simm13 & 0x1fff);
11049 instruction |= ((rd.value() & 0x1f) << 25);
11050 emitInt(instruction);
11051 }
11052
11053 /**
11054 * Pseudo-external assembler syntax: {@code clr }<i>rd</i>
11055 * Example disassembly syntax: {@code clr %g0}
11056 * <p>
11057 * This is a synthetic instruction equivalent to: {@code or(G0, G0, rd)}
11058 *
11059 * @see #or(GPR, GPR, GPR)
11060 *
11061 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11062 */
11063 // Template#: 670, Serial#: 670
11064 public void clr(final GPR rd) {
11065 int instruction = 0x80100000;
11066 instruction |= ((rd.value() & 0x1f) << 25);
11067 emitInt(instruction);
11068 }
11069
11070 /**
11071 * Pseudo-external assembler syntax: {@code clrb }<i>rs1</i>, <i>rs2</i>
11072 * Example disassembly syntax: {@code clrb [%g0 + %g0]}
11073 * <p>
11074 * This is a synthetic instruction equivalent to: {@code stb(G0, rs1, rs2)}
11075 *
11076 * @see #stb(GPR, GPR, GPR)
11077 *
11078 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11079 */
11080 // Template#: 671, Serial#: 671
11081 public void clrb(final GPR rs1, final GPR rs2) {
11082 int instruction = 0xC0280000;
11083 instruction |= ((rs1.value() & 0x1f) << 14);
11084 instruction |= (rs2.value() & 0x1f);
11085 emitInt(instruction);
11086 }
11087
11088 /**
11089 * Pseudo-external assembler syntax: {@code clrb }<i>rs1</i>, <i>simm13</i>
11090 * Example disassembly syntax: {@code clrb [%g0 + -4096]}
11091 * <p>
11092 * This is a synthetic instruction equivalent to: {@code stb(G0, rs1, simm13)}
11093 * <p>
11094 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
11095 *
11096 * @see #stb(GPR, GPR, int)
11097 *
11098 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11099 */
11100 // Template#: 672, Serial#: 672
11101 public void clrb(final GPR rs1, final int simm13) {
11102 int instruction = 0xC0282000;
11103 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
11104 instruction |= ((rs1.value() & 0x1f) << 14);
11105 instruction |= (simm13 & 0x1fff);
11106 emitInt(instruction);
11107 }
11108
11109 /**
11110 * Pseudo-external assembler syntax: {@code clrh }<i>rs1</i>, <i>rs2</i>
11111 * Example disassembly syntax: {@code clrh [%g0 + %g0]}
11112 * <p>
11113 * This is a synthetic instruction equivalent to: {@code sth(G0, rs1, rs2)}
11114 *
11115 * @see #sth(GPR, GPR, GPR)
11116 *
11117 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11118 */
11119 // Template#: 673, Serial#: 673
11120 public void clrh(final GPR rs1, final GPR rs2) {
11121 int instruction = 0xC0300000;
11122 instruction |= ((rs1.value() & 0x1f) << 14);
11123 instruction |= (rs2.value() & 0x1f);
11124 emitInt(instruction);
11125 }
11126
11127 /**
11128 * Pseudo-external assembler syntax: {@code clrh }<i>rs1</i>, <i>simm13</i>
11129 * Example disassembly syntax: {@code clrh [%g0 + -4096]}
11130 * <p>
11131 * This is a synthetic instruction equivalent to: {@code sth(G0, rs1, simm13)}
11132 * <p>
11133 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
11134 *
11135 * @see #sth(GPR, GPR, int)
11136 *
11137 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11138 */
11139 // Template#: 674, Serial#: 674
11140 public void clrh(final GPR rs1, final int simm13) {
11141 int instruction = 0xC0302000;
11142 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
11143 instruction |= ((rs1.value() & 0x1f) << 14);
11144 instruction |= (simm13 & 0x1fff);
11145 emitInt(instruction);
11146 }
11147
11148 /**
11149 * Pseudo-external assembler syntax: {@code clr }<i>rs1</i>, <i>rs2</i>
11150 * Example disassembly syntax: {@code clr [%g0 + %g0]}
11151 * <p>
11152 * This is a synthetic instruction equivalent to: {@code stw(G0, rs1, rs2)}
11153 *
11154 * @see #stw(GPR, GPR, GPR)
11155 *
11156 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11157 */
11158 // Template#: 675, Serial#: 675
11159 public void clr(final GPR rs1, final GPR rs2) {
11160 int instruction = 0xC0200000;
11161 instruction |= ((rs1.value() & 0x1f) << 14);
11162 instruction |= (rs2.value() & 0x1f);
11163 emitInt(instruction);
11164 }
11165
11166 /**
11167 * Pseudo-external assembler syntax: {@code clr }<i>rs1</i>, <i>simm13</i>
11168 * Example disassembly syntax: {@code clr [%g0 + -4096]}
11169 * <p>
11170 * This is a synthetic instruction equivalent to: {@code stw(G0, rs1, simm13)}
11171 * <p>
11172 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
11173 *
11174 * @see #stw(GPR, GPR, int)
11175 *
11176 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11177 */
11178 // Template#: 676, Serial#: 676
11179 public void clr(final GPR rs1, final int simm13) {
11180 int instruction = 0xC0202000;
11181 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
11182 instruction |= ((rs1.value() & 0x1f) << 14);
11183 instruction |= (simm13 & 0x1fff);
11184 emitInt(instruction);
11185 }
11186
11187 /**
11188 * Pseudo-external assembler syntax: {@code clrx }<i>rs1</i>, <i>rs2</i>
11189 * Example disassembly syntax: {@code clrx [%g0 + %g0]}
11190 * <p>
11191 * This is a synthetic instruction equivalent to: {@code stx(G0, rs1, rs2)}
11192 *
11193 * @see #stx(GPR, GPR, GPR)
11194 *
11195 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11196 */
11197 // Template#: 677, Serial#: 677
11198 public void clrx(final GPR rs1, final GPR rs2) {
11199 int instruction = 0xC0700000;
11200 instruction |= ((rs1.value() & 0x1f) << 14);
11201 instruction |= (rs2.value() & 0x1f);
11202 emitInt(instruction);
11203 }
11204
11205 /**
11206 * Pseudo-external assembler syntax: {@code clrx }<i>rs1</i>, <i>simm13</i>
11207 * Example disassembly syntax: {@code clrx [%g0 + -4096]}
11208 * <p>
11209 * This is a synthetic instruction equivalent to: {@code stx(G0, rs1, simm13)}
11210 * <p>
11211 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
11212 *
11213 * @see #stx(GPR, GPR, int)
11214 *
11215 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11216 */
11217 // Template#: 678, Serial#: 678
11218 public void clrx(final GPR rs1, final int simm13) {
11219 int instruction = 0xC0702000;
11220 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
11221 instruction |= ((rs1.value() & 0x1f) << 14);
11222 instruction |= (simm13 & 0x1fff);
11223 emitInt(instruction);
11224 }
11225
11226 /**
11227 * Pseudo-external assembler syntax: {@code clruw }<i>rs1</i>, <i>rd</i>
11228 * Example disassembly syntax: {@code clruw %g0, %g0}
11229 * <p>
11230 * This is a synthetic instruction equivalent to: {@code srl(rs1, G0, rd)}
11231 *
11232 * @see #srl(GPR, GPR, GPR)
11233 *
11234 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11235 */
11236 // Template#: 679, Serial#: 679
11237 public void clruw(final GPR rs1, final GPR rd) {
11238 int instruction = 0x81300000;
11239 instruction |= ((rs1.value() & 0x1f) << 14);
11240 instruction |= ((rd.value() & 0x1f) << 25);
11241 emitInt(instruction);
11242 }
11243
11244 /**
11245 * Pseudo-external assembler syntax: {@code clruw }<i>rd</i>
11246 * Example disassembly syntax: {@code clruw %g0}
11247 * <p>
11248 * This is a synthetic instruction equivalent to: {@code srl(rd.value(), G0, rd)}
11249 *
11250 * @see #srl(GPR, GPR, GPR)
11251 *
11252 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11253 */
11254 // Template#: 680, Serial#: 680
11255 public void clruw(final GPR rd) {
11256 int instruction = 0x81300000;
11257 instruction |= ((rd.value() & 0x1f) << 14);
11258 instruction |= ((rd.value() & 0x1f) << 25);
11259 emitInt(instruction);
11260 }
11261
11262 /**
11263 * Pseudo-external assembler syntax: {@code mov }<i>rs2</i>, <i>rd</i>
11264 * Example disassembly syntax: {@code mov %g0, %g0}
11265 * <p>
11266 * This is a synthetic instruction equivalent to: {@code or(G0, rs2, rd)}
11267 *
11268 * @see #or(GPR, GPR, GPR)
11269 *
11270 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11271 */
11272 // Template#: 681, Serial#: 681
11273 public void mov(final GPR rs2, final GPR rd) {
11274 int instruction = 0x80100000;
11275 instruction |= (rs2.value() & 0x1f);
11276 instruction |= ((rd.value() & 0x1f) << 25);
11277 emitInt(instruction);
11278 }
11279
11280 /**
11281 * Pseudo-external assembler syntax: {@code mov }<i>simm13</i>, <i>rd</i>
11282 * Example disassembly syntax: {@code mov -4096, %g0}
11283 * <p>
11284 * This is a synthetic instruction equivalent to: {@code or(G0, simm13, rd)}
11285 * <p>
11286 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
11287 *
11288 * @see #or(GPR, int, GPR)
11289 *
11290 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11291 */
11292 // Template#: 682, Serial#: 682
11293 public void mov(final int simm13, final GPR rd) {
11294 int instruction = 0x80102000;
11295 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
11296 instruction |= (simm13 & 0x1fff);
11297 instruction |= ((rd.value() & 0x1f) << 25);
11298 emitInt(instruction);
11299 }
11300
11301 /**
11302 * Pseudo-external assembler syntax: {@code mov }<i>rs1</i>, <i>rd</i>
11303 * Example disassembly syntax: {@code mov %y, %g0}
11304 * <p>
11305 * This is a synthetic instruction equivalent to: {@code rd(rs1, rd)}
11306 * <p>
11307 * Constraint: {@code rs1.isYorASR()}<br />
11308 *
11309 * @see #rd(StateRegister, GPR)
11310 * @see com.sun.max.asm.sparc.StateRegister#isYorASR
11311 *
11312 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11313 */
11314 // Template#: 683, Serial#: 683
11315 public void mov(final StateRegister rs1, final GPR rd) {
11316 int instruction = 0x81400000;
11317 checkConstraint(rs1.isYorASR(), "rs1.isYorASR()");
11318 instruction |= ((rs1.value() & 0x1f) << 14);
11319 instruction |= ((rd.value() & 0x1f) << 25);
11320 emitInt(instruction);
11321 }
11322
11323 /**
11324 * Pseudo-external assembler syntax: {@code mov }<i>rs2</i>, <i>rd</i>
11325 * Example disassembly syntax: {@code mov %g0, %y}
11326 * <p>
11327 * This is a synthetic instruction equivalent to: {@code wr(G0, rs2, rd)}
11328 * <p>
11329 * Constraint: {@code rd.isYorASR()}<br />
11330 *
11331 * @see #wr(GPR, GPR, StateRegister.Writable)
11332 * @see com.sun.max.asm.sparc.StateRegister#isYorASR
11333 *
11334 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11335 */
11336 // Template#: 684, Serial#: 684
11337 public void mov(final GPR rs2, final StateRegister.Writable rd) {
11338 int instruction = 0x81800000;
11339 checkConstraint(rd.isYorASR(), "rd.isYorASR()");
11340 instruction |= (rs2.value() & 0x1f);
11341 instruction |= ((rd.value() & 0x1f) << 25);
11342 emitInt(instruction);
11343 }
11344
11345 /**
11346 * Pseudo-external assembler syntax: {@code mov }<i>simm13</i>, <i>rd</i>
11347 * Example disassembly syntax: {@code mov -4096, %y}
11348 * <p>
11349 * This is a synthetic instruction equivalent to: {@code wr(G0, simm13, rd)}
11350 * <p>
11351 * Constraint: {@code -4096 <= simm13 && simm13 <= 4095}<br />
11352 * Constraint: {@code rd.isYorASR()}<br />
11353 *
11354 * @see #wr(GPR, int, StateRegister.Writable)
11355 * @see com.sun.max.asm.sparc.StateRegister#isYorASR
11356 *
11357 * @see "<a href="http://developers.sun.com/solaris/articles/sparcv9.pdf">The SPARC Architecture Manual, Version 9</a> - Section G.3"
11358 */
11359 // Template#: 685, Serial#: 685
11360 public void mov(final int simm13, final StateRegister.Writable rd) {
11361 int instruction = 0x81802000;
11362 checkConstraint(-4096 <= simm13 && simm13 <= 4095, "-4096 <= simm13 && simm13 <= 4095");
11363 checkConstraint(rd.isYorASR(), "rd.isYorASR()");
11364 instruction |= (simm13 & 0x1fff);
11365 instruction |= ((rd.value() & 0x1f) << 25);
11366 emitInt(instruction);
11367 }
11368
11369 // END GENERATED RAW ASSEMBLER METHODS
11370
11371 }