truffle: src/share/vm/opto/chaitin.cpp comparison

comparison src/share/vm/opto/chaitin.cpp @ 14412:e2722a66aba7

Merge

author	kvn
date	Thu, 05 Sep 2013 11:04:39 -0700
parents	4b2838704fd5
children	650868c062a9

comparison

equal deleted inserted replaced

-:bdd155477289
+:e2722a66aba7
 #include "opto/machnode.hpp"
 #include "opto/memnode.hpp"
 #include "opto/opcodes.hpp"
 #include "opto/rootnode.hpp"
-//=============================================================================
 #ifndef PRODUCT
-void LRG::dump( ) const {
+void LRG::dump() const {
 ttyLocker ttyl;
 tty->print("%d ",num_regs());
 _mask.dump();
 if( _msize_valid ) {
 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size);
 tty->cr();
 }
 #endif
-//------------------------------score------------------------------------------
 // Compute score from cost and area.  Low score is best to spill.
 static double raw_score( double cost, double area ) {
 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5;
 }
 return score + 1e10;        // Likely no progress to spill
 return score;
 }
-//------------------------------LRG_List---------------------------------------
 LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) {
 memset( _lidxs, 0, sizeof(uint)*max );
 }
 void LRG_List::extend( uint nidx, uint lidx ) {
 next = _uf_map[lrg];
 }
 return next;
 }
-//------------------------------Chaitin----------------------------------------
 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher)
 : PhaseRegAlloc(unique, cfg, matcher,
 #ifndef PRODUCT
 print_chaitin_statistics
 #else
 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling"))
 #endif
 {
 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); )
-_high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg._outer_loop_freq);
+_high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency());
 // Build a list of basic blocks, sorted by frequency
-_blks = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks );
+_blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
 // Experiment with sorting strategies to speed compilation
 double  cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket
 Block **buckets[NUMBUCKS];             // Array of buckets
 uint    buckcnt[NUMBUCKS];             // Array of bucket counters
 double  buckval[NUMBUCKS];             // Array of bucket value cutoffs
 for (uint i = 0; i < NUMBUCKS; i++) {
-buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg._num_blocks);
+buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
 buckcnt[i] = 0;
 // Bump by three orders of magnitude each time
 cutoff *= 0.001;
 buckval[i] = cutoff;
-for (uint j = 0; j < _cfg._num_blocks; j++) {
+for (uint j = 0; j < _cfg.number_of_blocks(); j++) {
 buckets[i][j] = NULL;
 }
 }
 // Sort blocks into buckets
-for (uint i = 0; i < _cfg._num_blocks; i++) {
+for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
 for (uint j = 0; j < NUMBUCKS; j++) {
-if ((j == NUMBUCKS - 1) || (_cfg._blocks[i]->_freq > buckval[j])) {
+if ((j == NUMBUCKS - 1) || (_cfg.get_block(i)->_freq > buckval[j])) {
 // Assign block to end of list for appropriate bucket
-buckets[j][buckcnt[j]++] = _cfg._blocks[i];
+buckets[j][buckcnt[j]++] = _cfg.get_block(i);
 break; // kick out of inner loop
 }
 }
 }
 // Dump buckets into final block array
 for (uint j = 0; j < buckcnt[i]; j++) {
 _blks[blkcnt++] = buckets[i][j];
 }
 }
-assert(blkcnt == _cfg._num_blocks, "Block array not totally filled");
+assert(blkcnt == _cfg.number_of_blocks(), "Block array not totally filled");
 }
-//------------------------------Union------------------------------------------
 // union 2 sets together.
 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) {
 uint src = _lrg_map.find(src_n);
 uint dst = _lrg_map.find(dst_n);
 assert(src, "");
 assert(dst < _lrg_map.max_lrg_id(), "oob");
 assert(src < dst, "always union smaller");
 _lrg_map.uf_map(dst, src);
 }
-//------------------------------new_lrg----------------------------------------
 void PhaseChaitin::new_lrg(const Node *x, uint lrg) {
 // Make the Node->LRG mapping
 _lrg_map.extend(x->_idx,lrg);
 // Make the Union-Find mapping an identity function
 _lrg_map.uf_extend(lrg, lrg);
 }
-bool PhaseChaitin::clone_projs_shared(Block *b, uint idx, Node *con, Node *copy, uint max_lrg_id) {
+int PhaseChaitin::clone_projs(Block* b, uint idx, Node* orig, Node* copy, uint& max_lrg_id) {
-Block *bcon = _cfg._bbs[con->_idx];
+assert(b->find_node(copy) == (idx - 1), "incorrect insert index for copy kill projections");
-uint cindex = bcon->find_node(con);
+DEBUG_ONLY( Block* borig = _cfg.get_block_for_node(orig); )
-Node *con_next = bcon->_nodes[cindex+1];
+int found_projs = 0;
-if (con_next->in(0) != con || !con_next->is_MachProj()) {
+uint cnt = orig->outcnt();
-return false;               // No MachProj's follow
+for (uint i = 0; i < cnt; i++) {
-}
+Node* proj = orig->raw_out(i);
+if (proj->is_MachProj()) {
-// Copy kills after the cloned constant
+assert(proj->outcnt() == 0, "only kill projections are expected here");
-Node *kills = con_next->clone();
+assert(_cfg.get_block_for_node(proj) == borig, "incorrect block for kill projections");
-kills->set_req(0, copy);
+found_projs++;
-b->_nodes.insert(idx, kills);
+// Copy kill projections after the cloned node
-_cfg._bbs.map(kills->_idx, b);
+Node* kills = proj->clone();
-new_lrg(kills, max_lrg_id);
+kills->set_req(0, copy);
-return true;
+b->_nodes.insert(idx++, kills);
-}
+_cfg.map_node_to_block(kills, b);
+new_lrg(kills, max_lrg_id++);
-//------------------------------compact----------------------------------------
+}
+}
+return found_projs;
+}
 // Renumber the live ranges to compact them.  Makes the IFG smaller.
 void PhaseChaitin::compact() {
 // Current the _uf_map contains a series of short chains which are headed
 // by a self-cycle.  All the chains run from big numbers to little numbers.
 // The Find() call chases the chains & shortens them for the next Find call.
 _live = NULL;
 _ifg = NULL;
 C->set_indexSet_arena(NULL);  // ResourceArea is at end of scope
 }
-//------------------------------de_ssa-----------------------------------------
 void PhaseChaitin::de_ssa() {
 // Set initial Names for all Nodes.  Most Nodes get the virtual register
 // number.  A few get the ZERO live range number.  These do not
 // get allocated, but instead rely on correct scheduling to ensure that
 // only one instance is simultaneously live at a time.
 uint lr_counter = 1;
-for( uint i = 0; i < _cfg._num_blocks; i++ ) {
+for( uint i = 0; i < _cfg.number_of_blocks(); i++ ) {
-Block *b = _cfg._blocks[i];
+Block* block = _cfg.get_block(i);
-uint cnt = b->_nodes.size();
+uint cnt = block->_nodes.size();
 // Handle all the normal Nodes in the block
 for( uint j = 0; j < cnt; j++ ) {
-Node *n = b->_nodes[j];
+Node *n = block->_nodes[j];
 // Pre-color to the zero live range, or pick virtual register
 const RegMask &rm = n->out_RegMask();
 _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0);
 }
 }
 // Reset the Union-Find mapping to be identity
 _lrg_map.reset_uf_map(lr_counter);
 }
-//------------------------------gather_lrg_masks-------------------------------
 // Gather LiveRanGe information, including register masks.  Modification of
 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce.
 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
 // Nail down the frame pointer live range
-uint fp_lrg = _lrg_map.live_range_id(_cfg._root->in(1)->in(TypeFunc::FramePtr));
+uint fp_lrg = _lrg_map.live_range_id(_cfg.get_root_node()->in(1)->in(TypeFunc::FramePtr));
 lrgs(fp_lrg)._cost += 1e12;   // Cost is infinite
 // For all blocks
-for( uint i = 0; i < _cfg._num_blocks; i++ ) {
+for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
-Block *b = _cfg._blocks[i];
+Block* block = _cfg.get_block(i);
 // For all instructions
-for( uint j = 1; j < b->_nodes.size(); j++ ) {
+for (uint j = 1; j < block->_nodes.size(); j++) {
-Node *n = b->_nodes[j];
+Node* n = block->_nodes[j];
 uint input_edge_start =1; // Skip control most nodes
-if( n->is_Mach() ) input_edge_start = n->as_Mach()->oper_input_base();
+if (n->is_Mach()) {
+input_edge_start = n->as_Mach()->oper_input_base();
+}
 uint idx = n->is_Copy();
 // Get virtual register number, same as LiveRanGe index
 uint vreg = _lrg_map.live_range_id(n);
-LRG &lrg = lrgs(vreg);
+LRG& lrg = lrgs(vreg);
-if( vreg ) {              // No vreg means un-allocable (e.g. memory)
+if (vreg) {              // No vreg means un-allocable (e.g. memory)
 // Collect has-copy bit
-if( idx ) {
+if (idx) {
 lrg._has_copy = 1;
 uint clidx = _lrg_map.live_range_id(n->in(idx));
-LRG &copy_src = lrgs(clidx);
+LRG& copy_src = lrgs(clidx);
 copy_src._has_copy = 1;
 }
 // Check for float-vs-int live range (used in register-pressure
 // calculations)
 const Type *n_type = n->bottom_type();
-if (n_type->is_floatingpoint())
+if (n_type->is_floatingpoint()) {
 lrg._is_float = 1;
+}
 // Check for twice prior spilling.  Once prior spilling might have
 // spilled 'soft', 2nd prior spill should have spilled 'hard' and
 // further spilling is unlikely to make progress.
-if( _spilled_once.test(n->_idx) ) {
+if (_spilled_once.test(n->_idx)) {
 lrg._was_spilled1 = 1;
-if( _spilled_twice.test(n->_idx) )
+if (_spilled_twice.test(n->_idx)) {
 lrg._was_spilled2 = 1;
+}
 }
 #ifndef PRODUCT
 if (trace_spilling() && lrg._def != NULL) {
 // collect defs for MultiDef printing
 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD,
 "vector must be in vector registers");
 // Check for bound register masks
 const RegMask &lrgmask = lrg.mask();
-if (lrgmask.is_bound(ireg))
+if (lrgmask.is_bound(ireg)) {
 lrg._is_bound = 1;
+}
 // Check for maximum frequency value
-if (lrg._maxfreq < b->_freq)
+if (lrg._maxfreq < block->_freq) {
-lrg._maxfreq = b->_freq;
+lrg._maxfreq = block->_freq;
+}
 // Check for oop-iness, or long/double
 // Check for multi-kill projection
-switch( ireg ) {
+switch (ireg) {
 case MachProjNode::fat_proj:
 // Fat projections have size equal to number of registers killed
 lrg.set_num_regs(rm.Size());
 lrg.set_reg_pressure(lrg.num_regs());
 lrg._fat_proj = 1;
 // Limit result register mask to acceptable registers.
 // Do not limit registers from uncommon uses before
 // AggressiveCoalesce.  This effectively pre-virtual-splits
 // around uncommon uses of common defs.
 const RegMask &rm = n->in_RegMask(k);
-if( !after_aggressive &&
+if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) {
-_cfg._bbs[n->in(k)->_idx]->_freq > 1000*b->_freq ) {
 // Since we are BEFORE aggressive coalesce, leave the register
 // mask untrimmed by the call.  This encourages more coalescing.
 // Later, AFTER aggressive, this live range will have to spill
 // but the spiller handles slow-path calls very nicely.
 } else {
 lrgmask.is_misaligned_pair()) {
 lrg.Clear();
 }
 // Check for maximum frequency value
-if( lrg._maxfreq < b->_freq )
+if (lrg._maxfreq < block->_freq) {
-lrg._maxfreq = b->_freq;
+lrg._maxfreq = block->_freq;
+}
 } // End for all allocated inputs
 } // end for all instructions
 } // end for all blocks
 }
 lrg.set_degree(0);          // no neighbors in IFG yet
 }
 }
-//------------------------------set_was_low------------------------------------
 // Set the was-lo-degree bit.  Conservative coalescing should not change the
 // colorability of the graph.  If any live range was of low-degree before
 // coalescing, it should Simplify.  This call sets the was-lo-degree bit.
 // The bit is checked in Simplify.
 void PhaseChaitin::set_was_low() {
 #endif
 }
 #define REGISTER_CONSTRAINED 16
-//------------------------------cache_lrg_info---------------------------------
 // Compute cost/area ratio, in case we spill.  Build the lo-degree list.
 void PhaseChaitin::cache_lrg_info( ) {
 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
 LRG &lrg = lrgs(i);
 _hi_degree = i;
 }
 }
 }
-//------------------------------Pre-Simplify-----------------------------------
 // Simplify the IFG by removing LRGs of low degree that have NO copies
 void PhaseChaitin::Pre_Simplify( ) {
 // Warm up the lo-degree no-copy list
 int lo_no_copy = 0;
 } // End of while lo-degree no_copy worklist not empty
 // No more lo-degree no-copy live ranges to simplify
 }
-//------------------------------Simplify---------------------------------------
 // Simplify the IFG by removing LRGs of low degree.
 void PhaseChaitin::Simplify( ) {
 while( 1 ) {                  // Repeat till simplified it all
 // May want to explore simplifying lo_degree before _lo_stk_degree.
 } // End of while not simplified everything
 }
-//------------------------------is_legal_reg-----------------------------------
 // Is 'reg' register legal for 'lrg'?
 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) {
 if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) &&
 lrg.mask().Member(OptoReg::add(reg,-chunk))) {
 // RA uses OptoReg which represent the highest element of a registers set.
 return true;
 }
 return false;
 }
-//------------------------------bias_color-------------------------------------
 // Choose a color using the biasing heuristic
 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
 // Check for "at_risk" LRG's
 uint risk_lrg = _lrg_map.find(lrg._risk_bias);
 reg = reg2;
 }
 return OptoReg::add( reg, chunk );
 }
-//------------------------------choose_color-----------------------------------
 // Choose a color in the current chunk
 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) {
 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)");
 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)");
 assert( !chunk, "always color in 1st chunk" );
 // Return the highest element in the set.
 return lrg.mask().find_last_elem();
 }
-//------------------------------Select-----------------------------------------
 // Select colors by re-inserting LRGs back into the IFG.  LRGs are re-inserted
 // in reverse order of removal.  As long as nothing of hi-degree was yanked,
 // everything going back is guaranteed a color.  Select that color.  If some
 // hi-degree LRG cannot get a color then we record that we must spill.
 uint PhaseChaitin::Select( ) {
 }
 return spill_reg-LRG::SPILL_REG;      // Return number of spills
 }
-//------------------------------copy_was_spilled-------------------------------
 // Copy 'was_spilled'-edness from the source Node to the dst Node.
 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) {
 if( _spilled_once.test(src->_idx) ) {
 _spilled_once.set(dst->_idx);
 lrgs(_lrg_map.find(dst))._was_spilled1 = 1;
 lrgs(_lrg_map.find(dst))._was_spilled2 = 1;
 }
 }
 }
-//------------------------------set_was_spilled--------------------------------
 // Set the 'spilled_once' or 'spilled_twice' flag on a node.
 void PhaseChaitin::set_was_spilled( Node *n ) {
 if( _spilled_once.test_set(n->_idx) )
 _spilled_twice.set(n->_idx);
 }
-//------------------------------fixup_spills-----------------------------------
 // Convert Ideal spill instructions into proper FramePtr + offset Loads and
 // Stores.  Use-def chains are NOT preserved, but Node->LRG->reg maps are.
 void PhaseChaitin::fixup_spills() {
 // This function does only cisc spill work.
 if( !UseCISCSpill ) return;
 NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); )
 // Grab the Frame Pointer
-Node *fp = _cfg._broot->head()->in(1)->in(TypeFunc::FramePtr);
+Node *fp = _cfg.get_root_block()->head()->in(1)->in(TypeFunc::FramePtr);
 // For all blocks
-for( uint i = 0; i < _cfg._num_blocks; i++ ) {
+for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
-Block *b = _cfg._blocks[i];
+Block* block = _cfg.get_block(i);
 // For all instructions in block
-uint last_inst = b->end_idx();
+uint last_inst = block->end_idx();
-for( uint j = 1; j <= last_inst; j++ ) {
+for (uint j = 1; j <= last_inst; j++) {
-Node *n = b->_nodes[j];
+Node* n = block->_nodes[j];
 // Dead instruction???
 assert( n->outcnt() != 0 ||// Nothing dead after post alloc
 C->top() == n ||  // Or the random TOP node
 n->is_Proj(),     // Or a fat-proj kill node
 cisc->set_req(inp,fp);          // Base register is frame pointer
 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) {
 assert( cisc->oper_input_base() == 2, "Only adding one edge");
 cisc->ins_req(1,src);         // Requires a memory edge
 }
-b->_nodes.map(j,cisc);          // Insert into basic block
+block->_nodes.map(j,cisc);          // Insert into basic block
 n->subsume_by(cisc, C); // Correct graph
 //
 ++_used_cisc_instructions;
 #ifndef PRODUCT
 if( TraceCISCSpill ) {
 } // End of for all instructions
 } // End of for all blocks
 }
-//------------------------------find_base_for_derived--------------------------
 // Helper to stretch above; recursively discover the base Node for a
 // given derived Node.  Easy for AddP-related machine nodes, but needs
 // to be recursive for derived Phis.
 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) {
 // See if already computed; if so return it
 assert(base != NULL, "sanity");
 if (base->in(0) == NULL) {
 // Initialize it once and make it shared:
 // set control to _root and place it into Start block
 // (where top() node is placed).
-base->init_req(0, _cfg._root);
+base->init_req(0, _cfg.get_root_node());
-Block *startb = _cfg._bbs[C->top()->_idx];
+Block *startb = _cfg.get_block_for_node(C->top());
 startb->_nodes.insert(startb->find_node(C->top()), base );
-_cfg._bbs.map( base->_idx, startb );
+_cfg.map_node_to_block(base, startb);
 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet");
 }
 if (_lrg_map.live_range_id(base) == 0) {
 new_lrg(base, maxlrg++);
 }
-assert(base->in(0) == _cfg._root &&
+assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared");
-_cfg._bbs[base->_idx] == _cfg._bbs[C->top()->_idx], "base NULL should be shared");
 derived_base_map[derived->_idx] = base;
 return base;
 }
 // Check for AddP-related opcodes
 t = t->meet(base->in(i)->bottom_type());
 }
 base->as_Phi()->set_type(t);
 // Search the current block for an existing base-Phi
-Block *b = _cfg._bbs[derived->_idx];
+Block *b = _cfg.get_block_for_node(derived);
 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi
 Node *phi = b->_nodes[i];
 if( !phi->is_Phi() ) {      // Found end of Phis with no match?
 b->_nodes.insert( i, base ); // Must insert created Phi here as base
-_cfg._bbs.map( base->_idx, b );
+_cfg.map_node_to_block(base, b);
 new_lrg(base,maxlrg++);
 break;
 }
 // See if Phi matches.
 uint j;
 // Cache info for later passes
 derived_base_map[derived->_idx] = base;
 return base;
 }
-//------------------------------stretch_base_pointer_live_ranges---------------
 // At each Safepoint, insert extra debug edges for each pair of derived value/
 // base pointer that is live across the Safepoint for oopmap building.  The
 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the
 // required edge set.
 bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) {
 uint maxlrg = _lrg_map.max_lrg_id();
 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique());
 memset( derived_base_map, 0, sizeof(Node*)*C->unique() );
 // For all blocks in RPO do...
-for( uint i=0; i<_cfg._num_blocks; i++ ) {
+for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
-Block *b = _cfg._blocks[i];
+Block* block = _cfg.get_block(i);
 // Note use of deep-copy constructor.  I cannot hammer the original
 // liveout bits, because they are needed by the following coalesce pass.
-IndexSet liveout(_live->live(b));
+IndexSet liveout(_live->live(block));
-for( uint j = b->end_idx() + 1; j > 1; j-- ) {
+for (uint j = block->end_idx() + 1; j > 1; j--) {
-Node *n = b->_nodes[j-1];
+Node* n = block->_nodes[j - 1];
 // Pre-split compares of loop-phis.  Loop-phis form a cycle we would
 // like to see in the same register.  Compare uses the loop-phi and so
 // extends its live range BUT cannot be part of the cycle.  If this
 // extended live range overlaps with the update of the loop-phi value
 // one after.  Instead we split the input to the compare just after the
 // phi.
 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
 Node *phi = n->in(1);
 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
-Block *phi_block = _cfg._bbs[phi->_idx];
+Block *phi_block = _cfg.get_block_for_node(phi);
-if( _cfg._bbs[phi_block->pred(2)->_idx] == b ) {
+if (_cfg.get_block_for_node(phi_block->pred(2)) == block) {
 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask );
 insert_proj( phi_block, 1, spill, maxlrg++ );
 n->set_req(1,spill);
 must_recompute_live = true;
 // reaching def's.  So if I find the base's live range then
 // I know the base's def reaches here.
 if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or
 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND
 (_lrg_map.live_range_id(base) > 0) && // not a constant
-_cfg._bbs[base->_idx] != b) { // base not def'd in blk)
+_cfg.get_block_for_node(base) != block) { // base not def'd in blk)
 // Base pointer is not currently live.  Since I stretched
 // the base pointer to here and it crosses basic-block
 // boundaries, the global live info is now incorrect.
 // Recompute live.
 must_recompute_live = true;
 }
 return must_recompute_live != 0;
 }
-//------------------------------add_reference----------------------------------
 // Extend the node to LRG mapping
 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) {
 _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node));
 }
-//------------------------------dump-------------------------------------------
 #ifndef PRODUCT
 void PhaseChaitin::dump(const Node *n) const {
 uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0;
 tty->print("L%d",r);
 if (r && n->Opcode() != Op_Phi) {
 tty->print(" Spill_2");
 }
 tty->print("\n");
 }
-void PhaseChaitin::dump( const Block * b ) const {
+void PhaseChaitin::dump(const Block *b) const {
-b->dump_head( &_cfg._bbs );
+b->dump_head(&_cfg);
 // For all instructions
 for( uint j = 0; j < b->_nodes.size(); j++ )
 dump(b->_nodes[j]);
 // Print live-out info at end of block
 void PhaseChaitin::dump() const {
 tty->print( "--- Chaitin -- argsize: %d  framesize: %d ---\n",
 _matcher._new_SP, _framesize );
 // For all blocks
-for( uint i = 0; i < _cfg._num_blocks; i++ )
+for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
-dump(_cfg._blocks[i]);
+dump(_cfg.get_block(i));
+}
 // End of per-block dump
 tty->print("\n");
 if (!_ifg) {
 tty->print("(No IFG.)\n");
 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next )
 tty->print("L%d ",i5);
 tty->print_cr("");
 }
-//------------------------------dump_degree_lists------------------------------
 void PhaseChaitin::dump_degree_lists() const {
 // Dump lo-degree list
 tty->print("Lo degree: ");
 for( uint i = _lo_degree; i; i = lrgs(i)._next )
 tty->print("L%d ",i);
 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next )
 tty->print("L%d ",i3);
 tty->print_cr("");
 }
-//------------------------------dump_simplified--------------------------------
 void PhaseChaitin::dump_simplified() const {
 tty->print("Simplified: ");
 for( uint i = _simplified; i; i = lrgs(i)._next )
 tty->print("L%d ",i);
 tty->print_cr("");
 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer),
 pc->reg2offset(reg));
 return buf+strlen(buf);
 }
-//------------------------------dump_register----------------------------------
 // Dump a register name into a buffer.  Be intelligent if we get called
 // before allocation is complete.
 char *PhaseChaitin::dump_register( const Node *n, char *buf  ) const {
 if( !this ) {                 // Not got anything?
 sprintf(buf,"N%d",n->_idx); // Then use Node index
 }
 }
 return buf+strlen(buf);
 }
-//----------------------dump_for_spill_split_recycle--------------------------
 void PhaseChaitin::dump_for_spill_split_recycle() const {
 if( WizardMode && (PrintCompilation || PrintOpto) ) {
 // Display which live ranges need to be split and the allocator's state
 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt);
 for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) {
 tty->cr();
 dump();
 }
 }
-//------------------------------dump_frame------------------------------------
 void PhaseChaitin::dump_frame() const {
 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer);
 const TypeTuple *domain = C->tf()->domain();
 const int        argcnt = domain->cnt() - TypeFunc::Parms;
 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg));
 }
 tty->print_cr("#");
 }
-//------------------------------dump_bb----------------------------------------
 void PhaseChaitin::dump_bb( uint pre_order ) const {
 tty->print_cr("---dump of B%d---",pre_order);
-for( uint i = 0; i < _cfg._num_blocks; i++ ) {
+for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
-Block *b = _cfg._blocks[i];
+Block* block = _cfg.get_block(i);
-if( b->_pre_order == pre_order )
+if (block->_pre_order == pre_order) {
-dump(b);
+dump(block);
 }
 }
+}
-//------------------------------dump_lrg---------------------------------------
 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const {
 tty->print_cr("---dump of L%d---",lidx);
 if (_ifg) {
 if (lidx >= _lrg_map.max_lrg_id()) {
 tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx));
 _ifg->neighbors(lidx)->dump();
 tty->cr();
 }
 // For all blocks
-for( uint i = 0; i < _cfg._num_blocks; i++ ) {
+for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
-Block *b = _cfg._blocks[i];
+Block* block = _cfg.get_block(i);
 int dump_once = 0;
 // For all instructions
-for( uint j = 0; j < b->_nodes.size(); j++ ) {
+for( uint j = 0; j < block->_nodes.size(); j++ ) {
-Node *n = b->_nodes[j];
+Node *n = block->_nodes[j];
 if (_lrg_map.find_const(n) == lidx) {
 if (!dump_once++) {
 tty->cr();
-b->dump_head( &_cfg._bbs );
+block->dump_head(&_cfg);
 }
 dump(n);
 continue;
 }
 if (!defs_only) {
 continue;  // be robust in the dumper
 }
 if (_lrg_map.find_const(m) == lidx) {
 if (!dump_once++) {
 tty->cr();
-b->dump_head(&_cfg._bbs);
+block->dump_head(&_cfg);
 }
 dump(n);
 }
 }
 }
 } // End of per-block dump
 tty->cr();
 }
 #endif // not PRODUCT
-//------------------------------print_chaitin_statistics-------------------------------
 int PhaseChaitin::_final_loads  = 0;
 int PhaseChaitin::_final_stores = 0;
 int PhaseChaitin::_final_memoves= 0;
 int PhaseChaitin::_final_copies = 0;
 double PhaseChaitin::_final_load_cost  = 0;

Mercurial > hg > truffle

comparison src/share/vm/opto/chaitin.cpp @ 14412:e2722a66aba7