Mercurial > hg > truffle
comparison src/share/vm/opto/chaitin.cpp @ 14412:e2722a66aba7
Merge
author | kvn |
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date | Thu, 05 Sep 2013 11:04:39 -0700 |
parents | 4b2838704fd5 |
children | 650868c062a9 |
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14411:bdd155477289 | 14412:e2722a66aba7 |
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38 #include "opto/machnode.hpp" | 38 #include "opto/machnode.hpp" |
39 #include "opto/memnode.hpp" | 39 #include "opto/memnode.hpp" |
40 #include "opto/opcodes.hpp" | 40 #include "opto/opcodes.hpp" |
41 #include "opto/rootnode.hpp" | 41 #include "opto/rootnode.hpp" |
42 | 42 |
43 //============================================================================= | |
44 | |
45 #ifndef PRODUCT | 43 #ifndef PRODUCT |
46 void LRG::dump( ) const { | 44 void LRG::dump() const { |
47 ttyLocker ttyl; | 45 ttyLocker ttyl; |
48 tty->print("%d ",num_regs()); | 46 tty->print("%d ",num_regs()); |
49 _mask.dump(); | 47 _mask.dump(); |
50 if( _msize_valid ) { | 48 if( _msize_valid ) { |
51 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size); | 49 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size); |
92 | 90 |
93 tty->cr(); | 91 tty->cr(); |
94 } | 92 } |
95 #endif | 93 #endif |
96 | 94 |
97 //------------------------------score------------------------------------------ | |
98 // Compute score from cost and area. Low score is best to spill. | 95 // Compute score from cost and area. Low score is best to spill. |
99 static double raw_score( double cost, double area ) { | 96 static double raw_score( double cost, double area ) { |
100 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5; | 97 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5; |
101 } | 98 } |
102 | 99 |
123 return score + 1e10; // Likely no progress to spill | 120 return score + 1e10; // Likely no progress to spill |
124 | 121 |
125 return score; | 122 return score; |
126 } | 123 } |
127 | 124 |
128 //------------------------------LRG_List--------------------------------------- | |
129 LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) { | 125 LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) { |
130 memset( _lidxs, 0, sizeof(uint)*max ); | 126 memset( _lidxs, 0, sizeof(uint)*max ); |
131 } | 127 } |
132 | 128 |
133 void LRG_List::extend( uint nidx, uint lidx ) { | 129 void LRG_List::extend( uint nidx, uint lidx ) { |
209 next = _uf_map[lrg]; | 205 next = _uf_map[lrg]; |
210 } | 206 } |
211 return next; | 207 return next; |
212 } | 208 } |
213 | 209 |
214 //------------------------------Chaitin---------------------------------------- | |
215 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher) | 210 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher) |
216 : PhaseRegAlloc(unique, cfg, matcher, | 211 : PhaseRegAlloc(unique, cfg, matcher, |
217 #ifndef PRODUCT | 212 #ifndef PRODUCT |
218 print_chaitin_statistics | 213 print_chaitin_statistics |
219 #else | 214 #else |
230 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling")) | 225 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling")) |
231 #endif | 226 #endif |
232 { | 227 { |
233 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); ) | 228 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); ) |
234 | 229 |
235 _high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg._outer_loop_freq); | 230 _high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency()); |
236 | 231 |
237 // Build a list of basic blocks, sorted by frequency | 232 // Build a list of basic blocks, sorted by frequency |
238 _blks = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks ); | 233 _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks()); |
239 // Experiment with sorting strategies to speed compilation | 234 // Experiment with sorting strategies to speed compilation |
240 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket | 235 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket |
241 Block **buckets[NUMBUCKS]; // Array of buckets | 236 Block **buckets[NUMBUCKS]; // Array of buckets |
242 uint buckcnt[NUMBUCKS]; // Array of bucket counters | 237 uint buckcnt[NUMBUCKS]; // Array of bucket counters |
243 double buckval[NUMBUCKS]; // Array of bucket value cutoffs | 238 double buckval[NUMBUCKS]; // Array of bucket value cutoffs |
244 for (uint i = 0; i < NUMBUCKS; i++) { | 239 for (uint i = 0; i < NUMBUCKS; i++) { |
245 buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg._num_blocks); | 240 buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks()); |
246 buckcnt[i] = 0; | 241 buckcnt[i] = 0; |
247 // Bump by three orders of magnitude each time | 242 // Bump by three orders of magnitude each time |
248 cutoff *= 0.001; | 243 cutoff *= 0.001; |
249 buckval[i] = cutoff; | 244 buckval[i] = cutoff; |
250 for (uint j = 0; j < _cfg._num_blocks; j++) { | 245 for (uint j = 0; j < _cfg.number_of_blocks(); j++) { |
251 buckets[i][j] = NULL; | 246 buckets[i][j] = NULL; |
252 } | 247 } |
253 } | 248 } |
254 // Sort blocks into buckets | 249 // Sort blocks into buckets |
255 for (uint i = 0; i < _cfg._num_blocks; i++) { | 250 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
256 for (uint j = 0; j < NUMBUCKS; j++) { | 251 for (uint j = 0; j < NUMBUCKS; j++) { |
257 if ((j == NUMBUCKS - 1) || (_cfg._blocks[i]->_freq > buckval[j])) { | 252 if ((j == NUMBUCKS - 1) || (_cfg.get_block(i)->_freq > buckval[j])) { |
258 // Assign block to end of list for appropriate bucket | 253 // Assign block to end of list for appropriate bucket |
259 buckets[j][buckcnt[j]++] = _cfg._blocks[i]; | 254 buckets[j][buckcnt[j]++] = _cfg.get_block(i); |
260 break; // kick out of inner loop | 255 break; // kick out of inner loop |
261 } | 256 } |
262 } | 257 } |
263 } | 258 } |
264 // Dump buckets into final block array | 259 // Dump buckets into final block array |
267 for (uint j = 0; j < buckcnt[i]; j++) { | 262 for (uint j = 0; j < buckcnt[i]; j++) { |
268 _blks[blkcnt++] = buckets[i][j]; | 263 _blks[blkcnt++] = buckets[i][j]; |
269 } | 264 } |
270 } | 265 } |
271 | 266 |
272 assert(blkcnt == _cfg._num_blocks, "Block array not totally filled"); | 267 assert(blkcnt == _cfg.number_of_blocks(), "Block array not totally filled"); |
273 } | 268 } |
274 | 269 |
275 //------------------------------Union------------------------------------------ | |
276 // union 2 sets together. | 270 // union 2 sets together. |
277 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) { | 271 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) { |
278 uint src = _lrg_map.find(src_n); | 272 uint src = _lrg_map.find(src_n); |
279 uint dst = _lrg_map.find(dst_n); | 273 uint dst = _lrg_map.find(dst_n); |
280 assert(src, ""); | 274 assert(src, ""); |
283 assert(dst < _lrg_map.max_lrg_id(), "oob"); | 277 assert(dst < _lrg_map.max_lrg_id(), "oob"); |
284 assert(src < dst, "always union smaller"); | 278 assert(src < dst, "always union smaller"); |
285 _lrg_map.uf_map(dst, src); | 279 _lrg_map.uf_map(dst, src); |
286 } | 280 } |
287 | 281 |
288 //------------------------------new_lrg---------------------------------------- | |
289 void PhaseChaitin::new_lrg(const Node *x, uint lrg) { | 282 void PhaseChaitin::new_lrg(const Node *x, uint lrg) { |
290 // Make the Node->LRG mapping | 283 // Make the Node->LRG mapping |
291 _lrg_map.extend(x->_idx,lrg); | 284 _lrg_map.extend(x->_idx,lrg); |
292 // Make the Union-Find mapping an identity function | 285 // Make the Union-Find mapping an identity function |
293 _lrg_map.uf_extend(lrg, lrg); | 286 _lrg_map.uf_extend(lrg, lrg); |
294 } | 287 } |
295 | 288 |
296 | 289 |
297 bool PhaseChaitin::clone_projs_shared(Block *b, uint idx, Node *con, Node *copy, uint max_lrg_id) { | 290 int PhaseChaitin::clone_projs(Block* b, uint idx, Node* orig, Node* copy, uint& max_lrg_id) { |
298 Block *bcon = _cfg._bbs[con->_idx]; | 291 assert(b->find_node(copy) == (idx - 1), "incorrect insert index for copy kill projections"); |
299 uint cindex = bcon->find_node(con); | 292 DEBUG_ONLY( Block* borig = _cfg.get_block_for_node(orig); ) |
300 Node *con_next = bcon->_nodes[cindex+1]; | 293 int found_projs = 0; |
301 if (con_next->in(0) != con || !con_next->is_MachProj()) { | 294 uint cnt = orig->outcnt(); |
302 return false; // No MachProj's follow | 295 for (uint i = 0; i < cnt; i++) { |
303 } | 296 Node* proj = orig->raw_out(i); |
304 | 297 if (proj->is_MachProj()) { |
305 // Copy kills after the cloned constant | 298 assert(proj->outcnt() == 0, "only kill projections are expected here"); |
306 Node *kills = con_next->clone(); | 299 assert(_cfg.get_block_for_node(proj) == borig, "incorrect block for kill projections"); |
307 kills->set_req(0, copy); | 300 found_projs++; |
308 b->_nodes.insert(idx, kills); | 301 // Copy kill projections after the cloned node |
309 _cfg._bbs.map(kills->_idx, b); | 302 Node* kills = proj->clone(); |
310 new_lrg(kills, max_lrg_id); | 303 kills->set_req(0, copy); |
311 return true; | 304 b->_nodes.insert(idx++, kills); |
312 } | 305 _cfg.map_node_to_block(kills, b); |
313 | 306 new_lrg(kills, max_lrg_id++); |
314 //------------------------------compact---------------------------------------- | 307 } |
308 } | |
309 return found_projs; | |
310 } | |
311 | |
315 // Renumber the live ranges to compact them. Makes the IFG smaller. | 312 // Renumber the live ranges to compact them. Makes the IFG smaller. |
316 void PhaseChaitin::compact() { | 313 void PhaseChaitin::compact() { |
317 // Current the _uf_map contains a series of short chains which are headed | 314 // Current the _uf_map contains a series of short chains which are headed |
318 // by a self-cycle. All the chains run from big numbers to little numbers. | 315 // by a self-cycle. All the chains run from big numbers to little numbers. |
319 // The Find() call chases the chains & shortens them for the next Find call. | 316 // The Find() call chases the chains & shortens them for the next Find call. |
675 _live = NULL; | 672 _live = NULL; |
676 _ifg = NULL; | 673 _ifg = NULL; |
677 C->set_indexSet_arena(NULL); // ResourceArea is at end of scope | 674 C->set_indexSet_arena(NULL); // ResourceArea is at end of scope |
678 } | 675 } |
679 | 676 |
680 //------------------------------de_ssa----------------------------------------- | |
681 void PhaseChaitin::de_ssa() { | 677 void PhaseChaitin::de_ssa() { |
682 // Set initial Names for all Nodes. Most Nodes get the virtual register | 678 // Set initial Names for all Nodes. Most Nodes get the virtual register |
683 // number. A few get the ZERO live range number. These do not | 679 // number. A few get the ZERO live range number. These do not |
684 // get allocated, but instead rely on correct scheduling to ensure that | 680 // get allocated, but instead rely on correct scheduling to ensure that |
685 // only one instance is simultaneously live at a time. | 681 // only one instance is simultaneously live at a time. |
686 uint lr_counter = 1; | 682 uint lr_counter = 1; |
687 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | 683 for( uint i = 0; i < _cfg.number_of_blocks(); i++ ) { |
688 Block *b = _cfg._blocks[i]; | 684 Block* block = _cfg.get_block(i); |
689 uint cnt = b->_nodes.size(); | 685 uint cnt = block->_nodes.size(); |
690 | 686 |
691 // Handle all the normal Nodes in the block | 687 // Handle all the normal Nodes in the block |
692 for( uint j = 0; j < cnt; j++ ) { | 688 for( uint j = 0; j < cnt; j++ ) { |
693 Node *n = b->_nodes[j]; | 689 Node *n = block->_nodes[j]; |
694 // Pre-color to the zero live range, or pick virtual register | 690 // Pre-color to the zero live range, or pick virtual register |
695 const RegMask &rm = n->out_RegMask(); | 691 const RegMask &rm = n->out_RegMask(); |
696 _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0); | 692 _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0); |
697 } | 693 } |
698 } | 694 } |
699 // Reset the Union-Find mapping to be identity | 695 // Reset the Union-Find mapping to be identity |
700 _lrg_map.reset_uf_map(lr_counter); | 696 _lrg_map.reset_uf_map(lr_counter); |
701 } | 697 } |
702 | 698 |
703 | 699 |
704 //------------------------------gather_lrg_masks------------------------------- | |
705 // Gather LiveRanGe information, including register masks. Modification of | 700 // Gather LiveRanGe information, including register masks. Modification of |
706 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce. | 701 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce. |
707 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) { | 702 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) { |
708 | 703 |
709 // Nail down the frame pointer live range | 704 // Nail down the frame pointer live range |
710 uint fp_lrg = _lrg_map.live_range_id(_cfg._root->in(1)->in(TypeFunc::FramePtr)); | 705 uint fp_lrg = _lrg_map.live_range_id(_cfg.get_root_node()->in(1)->in(TypeFunc::FramePtr)); |
711 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite | 706 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite |
712 | 707 |
713 // For all blocks | 708 // For all blocks |
714 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | 709 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
715 Block *b = _cfg._blocks[i]; | 710 Block* block = _cfg.get_block(i); |
716 | 711 |
717 // For all instructions | 712 // For all instructions |
718 for( uint j = 1; j < b->_nodes.size(); j++ ) { | 713 for (uint j = 1; j < block->_nodes.size(); j++) { |
719 Node *n = b->_nodes[j]; | 714 Node* n = block->_nodes[j]; |
720 uint input_edge_start =1; // Skip control most nodes | 715 uint input_edge_start =1; // Skip control most nodes |
721 if( n->is_Mach() ) input_edge_start = n->as_Mach()->oper_input_base(); | 716 if (n->is_Mach()) { |
717 input_edge_start = n->as_Mach()->oper_input_base(); | |
718 } | |
722 uint idx = n->is_Copy(); | 719 uint idx = n->is_Copy(); |
723 | 720 |
724 // Get virtual register number, same as LiveRanGe index | 721 // Get virtual register number, same as LiveRanGe index |
725 uint vreg = _lrg_map.live_range_id(n); | 722 uint vreg = _lrg_map.live_range_id(n); |
726 LRG &lrg = lrgs(vreg); | 723 LRG& lrg = lrgs(vreg); |
727 if( vreg ) { // No vreg means un-allocable (e.g. memory) | 724 if (vreg) { // No vreg means un-allocable (e.g. memory) |
728 | 725 |
729 // Collect has-copy bit | 726 // Collect has-copy bit |
730 if( idx ) { | 727 if (idx) { |
731 lrg._has_copy = 1; | 728 lrg._has_copy = 1; |
732 uint clidx = _lrg_map.live_range_id(n->in(idx)); | 729 uint clidx = _lrg_map.live_range_id(n->in(idx)); |
733 LRG ©_src = lrgs(clidx); | 730 LRG& copy_src = lrgs(clidx); |
734 copy_src._has_copy = 1; | 731 copy_src._has_copy = 1; |
735 } | 732 } |
736 | 733 |
737 // Check for float-vs-int live range (used in register-pressure | 734 // Check for float-vs-int live range (used in register-pressure |
738 // calculations) | 735 // calculations) |
739 const Type *n_type = n->bottom_type(); | 736 const Type *n_type = n->bottom_type(); |
740 if (n_type->is_floatingpoint()) | 737 if (n_type->is_floatingpoint()) { |
741 lrg._is_float = 1; | 738 lrg._is_float = 1; |
739 } | |
742 | 740 |
743 // Check for twice prior spilling. Once prior spilling might have | 741 // Check for twice prior spilling. Once prior spilling might have |
744 // spilled 'soft', 2nd prior spill should have spilled 'hard' and | 742 // spilled 'soft', 2nd prior spill should have spilled 'hard' and |
745 // further spilling is unlikely to make progress. | 743 // further spilling is unlikely to make progress. |
746 if( _spilled_once.test(n->_idx) ) { | 744 if (_spilled_once.test(n->_idx)) { |
747 lrg._was_spilled1 = 1; | 745 lrg._was_spilled1 = 1; |
748 if( _spilled_twice.test(n->_idx) ) | 746 if (_spilled_twice.test(n->_idx)) { |
749 lrg._was_spilled2 = 1; | 747 lrg._was_spilled2 = 1; |
748 } | |
750 } | 749 } |
751 | 750 |
752 #ifndef PRODUCT | 751 #ifndef PRODUCT |
753 if (trace_spilling() && lrg._def != NULL) { | 752 if (trace_spilling() && lrg._def != NULL) { |
754 // collect defs for MultiDef printing | 753 // collect defs for MultiDef printing |
781 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD, | 780 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD, |
782 "vector must be in vector registers"); | 781 "vector must be in vector registers"); |
783 | 782 |
784 // Check for bound register masks | 783 // Check for bound register masks |
785 const RegMask &lrgmask = lrg.mask(); | 784 const RegMask &lrgmask = lrg.mask(); |
786 if (lrgmask.is_bound(ireg)) | 785 if (lrgmask.is_bound(ireg)) { |
787 lrg._is_bound = 1; | 786 lrg._is_bound = 1; |
787 } | |
788 | 788 |
789 // Check for maximum frequency value | 789 // Check for maximum frequency value |
790 if (lrg._maxfreq < b->_freq) | 790 if (lrg._maxfreq < block->_freq) { |
791 lrg._maxfreq = b->_freq; | 791 lrg._maxfreq = block->_freq; |
792 } | |
792 | 793 |
793 // Check for oop-iness, or long/double | 794 // Check for oop-iness, or long/double |
794 // Check for multi-kill projection | 795 // Check for multi-kill projection |
795 switch( ireg ) { | 796 switch (ireg) { |
796 case MachProjNode::fat_proj: | 797 case MachProjNode::fat_proj: |
797 // Fat projections have size equal to number of registers killed | 798 // Fat projections have size equal to number of registers killed |
798 lrg.set_num_regs(rm.Size()); | 799 lrg.set_num_regs(rm.Size()); |
799 lrg.set_reg_pressure(lrg.num_regs()); | 800 lrg.set_reg_pressure(lrg.num_regs()); |
800 lrg._fat_proj = 1; | 801 lrg._fat_proj = 1; |
960 // Limit result register mask to acceptable registers. | 961 // Limit result register mask to acceptable registers. |
961 // Do not limit registers from uncommon uses before | 962 // Do not limit registers from uncommon uses before |
962 // AggressiveCoalesce. This effectively pre-virtual-splits | 963 // AggressiveCoalesce. This effectively pre-virtual-splits |
963 // around uncommon uses of common defs. | 964 // around uncommon uses of common defs. |
964 const RegMask &rm = n->in_RegMask(k); | 965 const RegMask &rm = n->in_RegMask(k); |
965 if( !after_aggressive && | 966 if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) { |
966 _cfg._bbs[n->in(k)->_idx]->_freq > 1000*b->_freq ) { | |
967 // Since we are BEFORE aggressive coalesce, leave the register | 967 // Since we are BEFORE aggressive coalesce, leave the register |
968 // mask untrimmed by the call. This encourages more coalescing. | 968 // mask untrimmed by the call. This encourages more coalescing. |
969 // Later, AFTER aggressive, this live range will have to spill | 969 // Later, AFTER aggressive, this live range will have to spill |
970 // but the spiller handles slow-path calls very nicely. | 970 // but the spiller handles slow-path calls very nicely. |
971 } else { | 971 } else { |
1005 lrgmask.is_misaligned_pair()) { | 1005 lrgmask.is_misaligned_pair()) { |
1006 lrg.Clear(); | 1006 lrg.Clear(); |
1007 } | 1007 } |
1008 | 1008 |
1009 // Check for maximum frequency value | 1009 // Check for maximum frequency value |
1010 if( lrg._maxfreq < b->_freq ) | 1010 if (lrg._maxfreq < block->_freq) { |
1011 lrg._maxfreq = b->_freq; | 1011 lrg._maxfreq = block->_freq; |
1012 } | |
1012 | 1013 |
1013 } // End for all allocated inputs | 1014 } // End for all allocated inputs |
1014 } // end for all instructions | 1015 } // end for all instructions |
1015 } // end for all blocks | 1016 } // end for all blocks |
1016 | 1017 |
1028 } | 1029 } |
1029 lrg.set_degree(0); // no neighbors in IFG yet | 1030 lrg.set_degree(0); // no neighbors in IFG yet |
1030 } | 1031 } |
1031 } | 1032 } |
1032 | 1033 |
1033 //------------------------------set_was_low------------------------------------ | |
1034 // Set the was-lo-degree bit. Conservative coalescing should not change the | 1034 // Set the was-lo-degree bit. Conservative coalescing should not change the |
1035 // colorability of the graph. If any live range was of low-degree before | 1035 // colorability of the graph. If any live range was of low-degree before |
1036 // coalescing, it should Simplify. This call sets the was-lo-degree bit. | 1036 // coalescing, it should Simplify. This call sets the was-lo-degree bit. |
1037 // The bit is checked in Simplify. | 1037 // The bit is checked in Simplify. |
1038 void PhaseChaitin::set_was_low() { | 1038 void PhaseChaitin::set_was_low() { |
1065 #endif | 1065 #endif |
1066 } | 1066 } |
1067 | 1067 |
1068 #define REGISTER_CONSTRAINED 16 | 1068 #define REGISTER_CONSTRAINED 16 |
1069 | 1069 |
1070 //------------------------------cache_lrg_info--------------------------------- | |
1071 // Compute cost/area ratio, in case we spill. Build the lo-degree list. | 1070 // Compute cost/area ratio, in case we spill. Build the lo-degree list. |
1072 void PhaseChaitin::cache_lrg_info( ) { | 1071 void PhaseChaitin::cache_lrg_info( ) { |
1073 | 1072 |
1074 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { | 1073 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { |
1075 LRG &lrg = lrgs(i); | 1074 LRG &lrg = lrgs(i); |
1099 _hi_degree = i; | 1098 _hi_degree = i; |
1100 } | 1099 } |
1101 } | 1100 } |
1102 } | 1101 } |
1103 | 1102 |
1104 //------------------------------Pre-Simplify----------------------------------- | |
1105 // Simplify the IFG by removing LRGs of low degree that have NO copies | 1103 // Simplify the IFG by removing LRGs of low degree that have NO copies |
1106 void PhaseChaitin::Pre_Simplify( ) { | 1104 void PhaseChaitin::Pre_Simplify( ) { |
1107 | 1105 |
1108 // Warm up the lo-degree no-copy list | 1106 // Warm up the lo-degree no-copy list |
1109 int lo_no_copy = 0; | 1107 int lo_no_copy = 0; |
1150 } // End of while lo-degree no_copy worklist not empty | 1148 } // End of while lo-degree no_copy worklist not empty |
1151 | 1149 |
1152 // No more lo-degree no-copy live ranges to simplify | 1150 // No more lo-degree no-copy live ranges to simplify |
1153 } | 1151 } |
1154 | 1152 |
1155 //------------------------------Simplify--------------------------------------- | |
1156 // Simplify the IFG by removing LRGs of low degree. | 1153 // Simplify the IFG by removing LRGs of low degree. |
1157 void PhaseChaitin::Simplify( ) { | 1154 void PhaseChaitin::Simplify( ) { |
1158 | 1155 |
1159 while( 1 ) { // Repeat till simplified it all | 1156 while( 1 ) { // Repeat till simplified it all |
1160 // May want to explore simplifying lo_degree before _lo_stk_degree. | 1157 // May want to explore simplifying lo_degree before _lo_stk_degree. |
1287 | 1284 |
1288 } // End of while not simplified everything | 1285 } // End of while not simplified everything |
1289 | 1286 |
1290 } | 1287 } |
1291 | 1288 |
1292 //------------------------------is_legal_reg----------------------------------- | |
1293 // Is 'reg' register legal for 'lrg'? | 1289 // Is 'reg' register legal for 'lrg'? |
1294 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) { | 1290 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) { |
1295 if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) && | 1291 if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) && |
1296 lrg.mask().Member(OptoReg::add(reg,-chunk))) { | 1292 lrg.mask().Member(OptoReg::add(reg,-chunk))) { |
1297 // RA uses OptoReg which represent the highest element of a registers set. | 1293 // RA uses OptoReg which represent the highest element of a registers set. |
1314 return true; | 1310 return true; |
1315 } | 1311 } |
1316 return false; | 1312 return false; |
1317 } | 1313 } |
1318 | 1314 |
1319 //------------------------------bias_color------------------------------------- | |
1320 // Choose a color using the biasing heuristic | 1315 // Choose a color using the biasing heuristic |
1321 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { | 1316 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { |
1322 | 1317 |
1323 // Check for "at_risk" LRG's | 1318 // Check for "at_risk" LRG's |
1324 uint risk_lrg = _lrg_map.find(lrg._risk_bias); | 1319 uint risk_lrg = _lrg_map.find(lrg._risk_bias); |
1376 reg = reg2; | 1371 reg = reg2; |
1377 } | 1372 } |
1378 return OptoReg::add( reg, chunk ); | 1373 return OptoReg::add( reg, chunk ); |
1379 } | 1374 } |
1380 | 1375 |
1381 //------------------------------choose_color----------------------------------- | |
1382 // Choose a color in the current chunk | 1376 // Choose a color in the current chunk |
1383 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) { | 1377 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) { |
1384 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)"); | 1378 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)"); |
1385 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)"); | 1379 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)"); |
1386 | 1380 |
1398 assert( !chunk, "always color in 1st chunk" ); | 1392 assert( !chunk, "always color in 1st chunk" ); |
1399 // Return the highest element in the set. | 1393 // Return the highest element in the set. |
1400 return lrg.mask().find_last_elem(); | 1394 return lrg.mask().find_last_elem(); |
1401 } | 1395 } |
1402 | 1396 |
1403 //------------------------------Select----------------------------------------- | |
1404 // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted | 1397 // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted |
1405 // in reverse order of removal. As long as nothing of hi-degree was yanked, | 1398 // in reverse order of removal. As long as nothing of hi-degree was yanked, |
1406 // everything going back is guaranteed a color. Select that color. If some | 1399 // everything going back is guaranteed a color. Select that color. If some |
1407 // hi-degree LRG cannot get a color then we record that we must spill. | 1400 // hi-degree LRG cannot get a color then we record that we must spill. |
1408 uint PhaseChaitin::Select( ) { | 1401 uint PhaseChaitin::Select( ) { |
1573 } | 1566 } |
1574 | 1567 |
1575 return spill_reg-LRG::SPILL_REG; // Return number of spills | 1568 return spill_reg-LRG::SPILL_REG; // Return number of spills |
1576 } | 1569 } |
1577 | 1570 |
1578 | |
1579 //------------------------------copy_was_spilled------------------------------- | |
1580 // Copy 'was_spilled'-edness from the source Node to the dst Node. | 1571 // Copy 'was_spilled'-edness from the source Node to the dst Node. |
1581 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) { | 1572 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) { |
1582 if( _spilled_once.test(src->_idx) ) { | 1573 if( _spilled_once.test(src->_idx) ) { |
1583 _spilled_once.set(dst->_idx); | 1574 _spilled_once.set(dst->_idx); |
1584 lrgs(_lrg_map.find(dst))._was_spilled1 = 1; | 1575 lrgs(_lrg_map.find(dst))._was_spilled1 = 1; |
1587 lrgs(_lrg_map.find(dst))._was_spilled2 = 1; | 1578 lrgs(_lrg_map.find(dst))._was_spilled2 = 1; |
1588 } | 1579 } |
1589 } | 1580 } |
1590 } | 1581 } |
1591 | 1582 |
1592 //------------------------------set_was_spilled-------------------------------- | |
1593 // Set the 'spilled_once' or 'spilled_twice' flag on a node. | 1583 // Set the 'spilled_once' or 'spilled_twice' flag on a node. |
1594 void PhaseChaitin::set_was_spilled( Node *n ) { | 1584 void PhaseChaitin::set_was_spilled( Node *n ) { |
1595 if( _spilled_once.test_set(n->_idx) ) | 1585 if( _spilled_once.test_set(n->_idx) ) |
1596 _spilled_twice.set(n->_idx); | 1586 _spilled_twice.set(n->_idx); |
1597 } | 1587 } |
1598 | 1588 |
1599 //------------------------------fixup_spills----------------------------------- | |
1600 // Convert Ideal spill instructions into proper FramePtr + offset Loads and | 1589 // Convert Ideal spill instructions into proper FramePtr + offset Loads and |
1601 // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are. | 1590 // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are. |
1602 void PhaseChaitin::fixup_spills() { | 1591 void PhaseChaitin::fixup_spills() { |
1603 // This function does only cisc spill work. | 1592 // This function does only cisc spill work. |
1604 if( !UseCISCSpill ) return; | 1593 if( !UseCISCSpill ) return; |
1605 | 1594 |
1606 NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); ) | 1595 NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); ) |
1607 | 1596 |
1608 // Grab the Frame Pointer | 1597 // Grab the Frame Pointer |
1609 Node *fp = _cfg._broot->head()->in(1)->in(TypeFunc::FramePtr); | 1598 Node *fp = _cfg.get_root_block()->head()->in(1)->in(TypeFunc::FramePtr); |
1610 | 1599 |
1611 // For all blocks | 1600 // For all blocks |
1612 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | 1601 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
1613 Block *b = _cfg._blocks[i]; | 1602 Block* block = _cfg.get_block(i); |
1614 | 1603 |
1615 // For all instructions in block | 1604 // For all instructions in block |
1616 uint last_inst = b->end_idx(); | 1605 uint last_inst = block->end_idx(); |
1617 for( uint j = 1; j <= last_inst; j++ ) { | 1606 for (uint j = 1; j <= last_inst; j++) { |
1618 Node *n = b->_nodes[j]; | 1607 Node* n = block->_nodes[j]; |
1619 | 1608 |
1620 // Dead instruction??? | 1609 // Dead instruction??? |
1621 assert( n->outcnt() != 0 ||// Nothing dead after post alloc | 1610 assert( n->outcnt() != 0 ||// Nothing dead after post alloc |
1622 C->top() == n || // Or the random TOP node | 1611 C->top() == n || // Or the random TOP node |
1623 n->is_Proj(), // Or a fat-proj kill node | 1612 n->is_Proj(), // Or a fat-proj kill node |
1650 cisc->set_req(inp,fp); // Base register is frame pointer | 1639 cisc->set_req(inp,fp); // Base register is frame pointer |
1651 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) { | 1640 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) { |
1652 assert( cisc->oper_input_base() == 2, "Only adding one edge"); | 1641 assert( cisc->oper_input_base() == 2, "Only adding one edge"); |
1653 cisc->ins_req(1,src); // Requires a memory edge | 1642 cisc->ins_req(1,src); // Requires a memory edge |
1654 } | 1643 } |
1655 b->_nodes.map(j,cisc); // Insert into basic block | 1644 block->_nodes.map(j,cisc); // Insert into basic block |
1656 n->subsume_by(cisc, C); // Correct graph | 1645 n->subsume_by(cisc, C); // Correct graph |
1657 // | 1646 // |
1658 ++_used_cisc_instructions; | 1647 ++_used_cisc_instructions; |
1659 #ifndef PRODUCT | 1648 #ifndef PRODUCT |
1660 if( TraceCISCSpill ) { | 1649 if( TraceCISCSpill ) { |
1676 } // End of for all instructions | 1665 } // End of for all instructions |
1677 | 1666 |
1678 } // End of for all blocks | 1667 } // End of for all blocks |
1679 } | 1668 } |
1680 | 1669 |
1681 //------------------------------find_base_for_derived-------------------------- | |
1682 // Helper to stretch above; recursively discover the base Node for a | 1670 // Helper to stretch above; recursively discover the base Node for a |
1683 // given derived Node. Easy for AddP-related machine nodes, but needs | 1671 // given derived Node. Easy for AddP-related machine nodes, but needs |
1684 // to be recursive for derived Phis. | 1672 // to be recursive for derived Phis. |
1685 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) { | 1673 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) { |
1686 // See if already computed; if so return it | 1674 // See if already computed; if so return it |
1706 assert(base != NULL, "sanity"); | 1694 assert(base != NULL, "sanity"); |
1707 if (base->in(0) == NULL) { | 1695 if (base->in(0) == NULL) { |
1708 // Initialize it once and make it shared: | 1696 // Initialize it once and make it shared: |
1709 // set control to _root and place it into Start block | 1697 // set control to _root and place it into Start block |
1710 // (where top() node is placed). | 1698 // (where top() node is placed). |
1711 base->init_req(0, _cfg._root); | 1699 base->init_req(0, _cfg.get_root_node()); |
1712 Block *startb = _cfg._bbs[C->top()->_idx]; | 1700 Block *startb = _cfg.get_block_for_node(C->top()); |
1713 startb->_nodes.insert(startb->find_node(C->top()), base ); | 1701 startb->_nodes.insert(startb->find_node(C->top()), base ); |
1714 _cfg._bbs.map( base->_idx, startb ); | 1702 _cfg.map_node_to_block(base, startb); |
1715 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet"); | 1703 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet"); |
1716 } | 1704 } |
1717 if (_lrg_map.live_range_id(base) == 0) { | 1705 if (_lrg_map.live_range_id(base) == 0) { |
1718 new_lrg(base, maxlrg++); | 1706 new_lrg(base, maxlrg++); |
1719 } | 1707 } |
1720 assert(base->in(0) == _cfg._root && | 1708 assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared"); |
1721 _cfg._bbs[base->_idx] == _cfg._bbs[C->top()->_idx], "base NULL should be shared"); | |
1722 derived_base_map[derived->_idx] = base; | 1709 derived_base_map[derived->_idx] = base; |
1723 return base; | 1710 return base; |
1724 } | 1711 } |
1725 | 1712 |
1726 // Check for AddP-related opcodes | 1713 // Check for AddP-related opcodes |
1752 t = t->meet(base->in(i)->bottom_type()); | 1739 t = t->meet(base->in(i)->bottom_type()); |
1753 } | 1740 } |
1754 base->as_Phi()->set_type(t); | 1741 base->as_Phi()->set_type(t); |
1755 | 1742 |
1756 // Search the current block for an existing base-Phi | 1743 // Search the current block for an existing base-Phi |
1757 Block *b = _cfg._bbs[derived->_idx]; | 1744 Block *b = _cfg.get_block_for_node(derived); |
1758 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi | 1745 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi |
1759 Node *phi = b->_nodes[i]; | 1746 Node *phi = b->_nodes[i]; |
1760 if( !phi->is_Phi() ) { // Found end of Phis with no match? | 1747 if( !phi->is_Phi() ) { // Found end of Phis with no match? |
1761 b->_nodes.insert( i, base ); // Must insert created Phi here as base | 1748 b->_nodes.insert( i, base ); // Must insert created Phi here as base |
1762 _cfg._bbs.map( base->_idx, b ); | 1749 _cfg.map_node_to_block(base, b); |
1763 new_lrg(base,maxlrg++); | 1750 new_lrg(base,maxlrg++); |
1764 break; | 1751 break; |
1765 } | 1752 } |
1766 // See if Phi matches. | 1753 // See if Phi matches. |
1767 uint j; | 1754 uint j; |
1779 // Cache info for later passes | 1766 // Cache info for later passes |
1780 derived_base_map[derived->_idx] = base; | 1767 derived_base_map[derived->_idx] = base; |
1781 return base; | 1768 return base; |
1782 } | 1769 } |
1783 | 1770 |
1784 | |
1785 //------------------------------stretch_base_pointer_live_ranges--------------- | |
1786 // At each Safepoint, insert extra debug edges for each pair of derived value/ | 1771 // At each Safepoint, insert extra debug edges for each pair of derived value/ |
1787 // base pointer that is live across the Safepoint for oopmap building. The | 1772 // base pointer that is live across the Safepoint for oopmap building. The |
1788 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the | 1773 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the |
1789 // required edge set. | 1774 // required edge set. |
1790 bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) { | 1775 bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) { |
1792 uint maxlrg = _lrg_map.max_lrg_id(); | 1777 uint maxlrg = _lrg_map.max_lrg_id(); |
1793 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique()); | 1778 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique()); |
1794 memset( derived_base_map, 0, sizeof(Node*)*C->unique() ); | 1779 memset( derived_base_map, 0, sizeof(Node*)*C->unique() ); |
1795 | 1780 |
1796 // For all blocks in RPO do... | 1781 // For all blocks in RPO do... |
1797 for( uint i=0; i<_cfg._num_blocks; i++ ) { | 1782 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
1798 Block *b = _cfg._blocks[i]; | 1783 Block* block = _cfg.get_block(i); |
1799 // Note use of deep-copy constructor. I cannot hammer the original | 1784 // Note use of deep-copy constructor. I cannot hammer the original |
1800 // liveout bits, because they are needed by the following coalesce pass. | 1785 // liveout bits, because they are needed by the following coalesce pass. |
1801 IndexSet liveout(_live->live(b)); | 1786 IndexSet liveout(_live->live(block)); |
1802 | 1787 |
1803 for( uint j = b->end_idx() + 1; j > 1; j-- ) { | 1788 for (uint j = block->end_idx() + 1; j > 1; j--) { |
1804 Node *n = b->_nodes[j-1]; | 1789 Node* n = block->_nodes[j - 1]; |
1805 | 1790 |
1806 // Pre-split compares of loop-phis. Loop-phis form a cycle we would | 1791 // Pre-split compares of loop-phis. Loop-phis form a cycle we would |
1807 // like to see in the same register. Compare uses the loop-phi and so | 1792 // like to see in the same register. Compare uses the loop-phi and so |
1808 // extends its live range BUT cannot be part of the cycle. If this | 1793 // extends its live range BUT cannot be part of the cycle. If this |
1809 // extended live range overlaps with the update of the loop-phi value | 1794 // extended live range overlaps with the update of the loop-phi value |
1813 // one after. Instead we split the input to the compare just after the | 1798 // one after. Instead we split the input to the compare just after the |
1814 // phi. | 1799 // phi. |
1815 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) { | 1800 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) { |
1816 Node *phi = n->in(1); | 1801 Node *phi = n->in(1); |
1817 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) { | 1802 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) { |
1818 Block *phi_block = _cfg._bbs[phi->_idx]; | 1803 Block *phi_block = _cfg.get_block_for_node(phi); |
1819 if( _cfg._bbs[phi_block->pred(2)->_idx] == b ) { | 1804 if (_cfg.get_block_for_node(phi_block->pred(2)) == block) { |
1820 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI]; | 1805 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI]; |
1821 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask ); | 1806 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask ); |
1822 insert_proj( phi_block, 1, spill, maxlrg++ ); | 1807 insert_proj( phi_block, 1, spill, maxlrg++ ); |
1823 n->set_req(1,spill); | 1808 n->set_req(1,spill); |
1824 must_recompute_live = true; | 1809 must_recompute_live = true; |
1868 // reaching def's. So if I find the base's live range then | 1853 // reaching def's. So if I find the base's live range then |
1869 // I know the base's def reaches here. | 1854 // I know the base's def reaches here. |
1870 if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or | 1855 if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or |
1871 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND | 1856 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND |
1872 (_lrg_map.live_range_id(base) > 0) && // not a constant | 1857 (_lrg_map.live_range_id(base) > 0) && // not a constant |
1873 _cfg._bbs[base->_idx] != b) { // base not def'd in blk) | 1858 _cfg.get_block_for_node(base) != block) { // base not def'd in blk) |
1874 // Base pointer is not currently live. Since I stretched | 1859 // Base pointer is not currently live. Since I stretched |
1875 // the base pointer to here and it crosses basic-block | 1860 // the base pointer to here and it crosses basic-block |
1876 // boundaries, the global live info is now incorrect. | 1861 // boundaries, the global live info is now incorrect. |
1877 // Recompute live. | 1862 // Recompute live. |
1878 must_recompute_live = true; | 1863 must_recompute_live = true; |
1903 } | 1888 } |
1904 | 1889 |
1905 return must_recompute_live != 0; | 1890 return must_recompute_live != 0; |
1906 } | 1891 } |
1907 | 1892 |
1908 | |
1909 //------------------------------add_reference---------------------------------- | |
1910 // Extend the node to LRG mapping | 1893 // Extend the node to LRG mapping |
1911 | 1894 |
1912 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) { | 1895 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) { |
1913 _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node)); | 1896 _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node)); |
1914 } | 1897 } |
1915 | 1898 |
1916 //------------------------------dump------------------------------------------- | |
1917 #ifndef PRODUCT | 1899 #ifndef PRODUCT |
1918 void PhaseChaitin::dump(const Node *n) const { | 1900 void PhaseChaitin::dump(const Node *n) const { |
1919 uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0; | 1901 uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0; |
1920 tty->print("L%d",r); | 1902 tty->print("L%d",r); |
1921 if (r && n->Opcode() != Op_Phi) { | 1903 if (r && n->Opcode() != Op_Phi) { |
1991 tty->print(" Spill_2"); | 1973 tty->print(" Spill_2"); |
1992 } | 1974 } |
1993 tty->print("\n"); | 1975 tty->print("\n"); |
1994 } | 1976 } |
1995 | 1977 |
1996 void PhaseChaitin::dump( const Block * b ) const { | 1978 void PhaseChaitin::dump(const Block *b) const { |
1997 b->dump_head( &_cfg._bbs ); | 1979 b->dump_head(&_cfg); |
1998 | 1980 |
1999 // For all instructions | 1981 // For all instructions |
2000 for( uint j = 0; j < b->_nodes.size(); j++ ) | 1982 for( uint j = 0; j < b->_nodes.size(); j++ ) |
2001 dump(b->_nodes[j]); | 1983 dump(b->_nodes[j]); |
2002 // Print live-out info at end of block | 1984 // Print live-out info at end of block |
2017 void PhaseChaitin::dump() const { | 1999 void PhaseChaitin::dump() const { |
2018 tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n", | 2000 tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n", |
2019 _matcher._new_SP, _framesize ); | 2001 _matcher._new_SP, _framesize ); |
2020 | 2002 |
2021 // For all blocks | 2003 // For all blocks |
2022 for( uint i = 0; i < _cfg._num_blocks; i++ ) | 2004 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
2023 dump(_cfg._blocks[i]); | 2005 dump(_cfg.get_block(i)); |
2006 } | |
2024 // End of per-block dump | 2007 // End of per-block dump |
2025 tty->print("\n"); | 2008 tty->print("\n"); |
2026 | 2009 |
2027 if (!_ifg) { | 2010 if (!_ifg) { |
2028 tty->print("(No IFG.)\n"); | 2011 tty->print("(No IFG.)\n"); |
2059 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next ) | 2042 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next ) |
2060 tty->print("L%d ",i5); | 2043 tty->print("L%d ",i5); |
2061 tty->print_cr(""); | 2044 tty->print_cr(""); |
2062 } | 2045 } |
2063 | 2046 |
2064 //------------------------------dump_degree_lists------------------------------ | |
2065 void PhaseChaitin::dump_degree_lists() const { | 2047 void PhaseChaitin::dump_degree_lists() const { |
2066 // Dump lo-degree list | 2048 // Dump lo-degree list |
2067 tty->print("Lo degree: "); | 2049 tty->print("Lo degree: "); |
2068 for( uint i = _lo_degree; i; i = lrgs(i)._next ) | 2050 for( uint i = _lo_degree; i; i = lrgs(i)._next ) |
2069 tty->print("L%d ",i); | 2051 tty->print("L%d ",i); |
2080 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next ) | 2062 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next ) |
2081 tty->print("L%d ",i3); | 2063 tty->print("L%d ",i3); |
2082 tty->print_cr(""); | 2064 tty->print_cr(""); |
2083 } | 2065 } |
2084 | 2066 |
2085 //------------------------------dump_simplified-------------------------------- | |
2086 void PhaseChaitin::dump_simplified() const { | 2067 void PhaseChaitin::dump_simplified() const { |
2087 tty->print("Simplified: "); | 2068 tty->print("Simplified: "); |
2088 for( uint i = _simplified; i; i = lrgs(i)._next ) | 2069 for( uint i = _simplified; i; i = lrgs(i)._next ) |
2089 tty->print("L%d ",i); | 2070 tty->print("L%d ",i); |
2090 tty->print_cr(""); | 2071 tty->print_cr(""); |
2099 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer), | 2080 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer), |
2100 pc->reg2offset(reg)); | 2081 pc->reg2offset(reg)); |
2101 return buf+strlen(buf); | 2082 return buf+strlen(buf); |
2102 } | 2083 } |
2103 | 2084 |
2104 //------------------------------dump_register---------------------------------- | |
2105 // Dump a register name into a buffer. Be intelligent if we get called | 2085 // Dump a register name into a buffer. Be intelligent if we get called |
2106 // before allocation is complete. | 2086 // before allocation is complete. |
2107 char *PhaseChaitin::dump_register( const Node *n, char *buf ) const { | 2087 char *PhaseChaitin::dump_register( const Node *n, char *buf ) const { |
2108 if( !this ) { // Not got anything? | 2088 if( !this ) { // Not got anything? |
2109 sprintf(buf,"N%d",n->_idx); // Then use Node index | 2089 sprintf(buf,"N%d",n->_idx); // Then use Node index |
2133 } | 2113 } |
2134 } | 2114 } |
2135 return buf+strlen(buf); | 2115 return buf+strlen(buf); |
2136 } | 2116 } |
2137 | 2117 |
2138 //----------------------dump_for_spill_split_recycle-------------------------- | |
2139 void PhaseChaitin::dump_for_spill_split_recycle() const { | 2118 void PhaseChaitin::dump_for_spill_split_recycle() const { |
2140 if( WizardMode && (PrintCompilation || PrintOpto) ) { | 2119 if( WizardMode && (PrintCompilation || PrintOpto) ) { |
2141 // Display which live ranges need to be split and the allocator's state | 2120 // Display which live ranges need to be split and the allocator's state |
2142 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt); | 2121 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt); |
2143 for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) { | 2122 for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) { |
2149 tty->cr(); | 2128 tty->cr(); |
2150 dump(); | 2129 dump(); |
2151 } | 2130 } |
2152 } | 2131 } |
2153 | 2132 |
2154 //------------------------------dump_frame------------------------------------ | |
2155 void PhaseChaitin::dump_frame() const { | 2133 void PhaseChaitin::dump_frame() const { |
2156 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer); | 2134 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer); |
2157 const TypeTuple *domain = C->tf()->domain(); | 2135 const TypeTuple *domain = C->tf()->domain(); |
2158 const int argcnt = domain->cnt() - TypeFunc::Parms; | 2136 const int argcnt = domain->cnt() - TypeFunc::Parms; |
2159 | 2137 |
2255 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg)); | 2233 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg)); |
2256 } | 2234 } |
2257 tty->print_cr("#"); | 2235 tty->print_cr("#"); |
2258 } | 2236 } |
2259 | 2237 |
2260 //------------------------------dump_bb---------------------------------------- | |
2261 void PhaseChaitin::dump_bb( uint pre_order ) const { | 2238 void PhaseChaitin::dump_bb( uint pre_order ) const { |
2262 tty->print_cr("---dump of B%d---",pre_order); | 2239 tty->print_cr("---dump of B%d---",pre_order); |
2263 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | 2240 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
2264 Block *b = _cfg._blocks[i]; | 2241 Block* block = _cfg.get_block(i); |
2265 if( b->_pre_order == pre_order ) | 2242 if (block->_pre_order == pre_order) { |
2266 dump(b); | 2243 dump(block); |
2267 } | 2244 } |
2268 } | 2245 } |
2269 | 2246 } |
2270 //------------------------------dump_lrg--------------------------------------- | 2247 |
2271 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const { | 2248 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const { |
2272 tty->print_cr("---dump of L%d---",lidx); | 2249 tty->print_cr("---dump of L%d---",lidx); |
2273 | 2250 |
2274 if (_ifg) { | 2251 if (_ifg) { |
2275 if (lidx >= _lrg_map.max_lrg_id()) { | 2252 if (lidx >= _lrg_map.max_lrg_id()) { |
2287 tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx)); | 2264 tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx)); |
2288 _ifg->neighbors(lidx)->dump(); | 2265 _ifg->neighbors(lidx)->dump(); |
2289 tty->cr(); | 2266 tty->cr(); |
2290 } | 2267 } |
2291 // For all blocks | 2268 // For all blocks |
2292 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | 2269 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
2293 Block *b = _cfg._blocks[i]; | 2270 Block* block = _cfg.get_block(i); |
2294 int dump_once = 0; | 2271 int dump_once = 0; |
2295 | 2272 |
2296 // For all instructions | 2273 // For all instructions |
2297 for( uint j = 0; j < b->_nodes.size(); j++ ) { | 2274 for( uint j = 0; j < block->_nodes.size(); j++ ) { |
2298 Node *n = b->_nodes[j]; | 2275 Node *n = block->_nodes[j]; |
2299 if (_lrg_map.find_const(n) == lidx) { | 2276 if (_lrg_map.find_const(n) == lidx) { |
2300 if (!dump_once++) { | 2277 if (!dump_once++) { |
2301 tty->cr(); | 2278 tty->cr(); |
2302 b->dump_head( &_cfg._bbs ); | 2279 block->dump_head(&_cfg); |
2303 } | 2280 } |
2304 dump(n); | 2281 dump(n); |
2305 continue; | 2282 continue; |
2306 } | 2283 } |
2307 if (!defs_only) { | 2284 if (!defs_only) { |
2312 continue; // be robust in the dumper | 2289 continue; // be robust in the dumper |
2313 } | 2290 } |
2314 if (_lrg_map.find_const(m) == lidx) { | 2291 if (_lrg_map.find_const(m) == lidx) { |
2315 if (!dump_once++) { | 2292 if (!dump_once++) { |
2316 tty->cr(); | 2293 tty->cr(); |
2317 b->dump_head(&_cfg._bbs); | 2294 block->dump_head(&_cfg); |
2318 } | 2295 } |
2319 dump(n); | 2296 dump(n); |
2320 } | 2297 } |
2321 } | 2298 } |
2322 } | 2299 } |
2324 } // End of per-block dump | 2301 } // End of per-block dump |
2325 tty->cr(); | 2302 tty->cr(); |
2326 } | 2303 } |
2327 #endif // not PRODUCT | 2304 #endif // not PRODUCT |
2328 | 2305 |
2329 //------------------------------print_chaitin_statistics------------------------------- | |
2330 int PhaseChaitin::_final_loads = 0; | 2306 int PhaseChaitin::_final_loads = 0; |
2331 int PhaseChaitin::_final_stores = 0; | 2307 int PhaseChaitin::_final_stores = 0; |
2332 int PhaseChaitin::_final_memoves= 0; | 2308 int PhaseChaitin::_final_memoves= 0; |
2333 int PhaseChaitin::_final_copies = 0; | 2309 int PhaseChaitin::_final_copies = 0; |
2334 double PhaseChaitin::_final_load_cost = 0; | 2310 double PhaseChaitin::_final_load_cost = 0; |