Mercurial > hg > truffle
comparison src/cpu/x86/vm/vm_version_x86.cpp @ 6948:e522a00b91aa
Merge with http://hg.openjdk.java.net/hsx/hsx25/hotspot/ after NPG - C++ build works
author | Doug Simon <doug.simon@oracle.com> |
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date | Mon, 12 Nov 2012 23:14:12 +0100 |
parents | 957c266d8bc5 dbeaeee28bc2 |
children | 291ffc492eb6 |
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6711:ae13cc658b80 | 6948:e522a00b91aa |
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361 _logical_processors_per_package = logical_processor_count(); | 361 _logical_processors_per_package = logical_processor_count(); |
362 } | 362 } |
363 } | 363 } |
364 | 364 |
365 _supports_cx8 = supports_cmpxchg8(); | 365 _supports_cx8 = supports_cmpxchg8(); |
366 // xchg and xadd instructions | |
367 _supports_atomic_getset4 = true; | |
368 _supports_atomic_getadd4 = true; | |
369 LP64_ONLY(_supports_atomic_getset8 = true); | |
370 LP64_ONLY(_supports_atomic_getadd8 = true); | |
366 | 371 |
367 #ifdef _LP64 | 372 #ifdef _LP64 |
368 // OS should support SSE for x64 and hardware should support at least SSE2. | 373 // OS should support SSE for x64 and hardware should support at least SSE2. |
369 if (!VM_Version::supports_sse2()) { | 374 if (!VM_Version::supports_sse2()) { |
370 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); | 375 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); |
412 _cpuFeatures &= ~CPU_AVX2; | 417 _cpuFeatures &= ~CPU_AVX2; |
413 | 418 |
414 if (UseAVX < 1) | 419 if (UseAVX < 1) |
415 _cpuFeatures &= ~CPU_AVX; | 420 _cpuFeatures &= ~CPU_AVX; |
416 | 421 |
422 if (!UseAES && !FLAG_IS_DEFAULT(UseAES)) | |
423 _cpuFeatures &= ~CPU_AES; | |
424 | |
417 if (logical_processors_per_package() == 1) { | 425 if (logical_processors_per_package() == 1) { |
418 // HT processor could be installed on a system which doesn't support HT. | 426 // HT processor could be installed on a system which doesn't support HT. |
419 _cpuFeatures &= ~CPU_HT; | 427 _cpuFeatures &= ~CPU_HT; |
420 } | 428 } |
421 | 429 |
422 char buf[256]; | 430 char buf[256]; |
423 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", | 431 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
424 cores_per_cpu(), threads_per_core(), | 432 cores_per_cpu(), threads_per_core(), |
425 cpu_family(), _model, _stepping, | 433 cpu_family(), _model, _stepping, |
426 (supports_cmov() ? ", cmov" : ""), | 434 (supports_cmov() ? ", cmov" : ""), |
427 (supports_cmpxchg8() ? ", cx8" : ""), | 435 (supports_cmpxchg8() ? ", cx8" : ""), |
428 (supports_fxsr() ? ", fxsr" : ""), | 436 (supports_fxsr() ? ", fxsr" : ""), |
434 (supports_sse4_1() ? ", sse4.1" : ""), | 442 (supports_sse4_1() ? ", sse4.1" : ""), |
435 (supports_sse4_2() ? ", sse4.2" : ""), | 443 (supports_sse4_2() ? ", sse4.2" : ""), |
436 (supports_popcnt() ? ", popcnt" : ""), | 444 (supports_popcnt() ? ", popcnt" : ""), |
437 (supports_avx() ? ", avx" : ""), | 445 (supports_avx() ? ", avx" : ""), |
438 (supports_avx2() ? ", avx2" : ""), | 446 (supports_avx2() ? ", avx2" : ""), |
447 (supports_aes() ? ", aes" : ""), | |
439 (supports_mmx_ext() ? ", mmxext" : ""), | 448 (supports_mmx_ext() ? ", mmxext" : ""), |
440 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), | 449 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), |
441 (supports_lzcnt() ? ", lzcnt": ""), | 450 (supports_lzcnt() ? ", lzcnt": ""), |
442 (supports_sse4a() ? ", sse4a": ""), | 451 (supports_sse4a() ? ", sse4a": ""), |
443 (supports_ht() ? ", ht": ""), | 452 (supports_ht() ? ", ht": ""), |
465 if (!supports_avx2()) // Drop to 1 if no AVX2 support | 474 if (!supports_avx2()) // Drop to 1 if no AVX2 support |
466 UseAVX = MIN2((intx)1,UseAVX); | 475 UseAVX = MIN2((intx)1,UseAVX); |
467 if (!supports_avx ()) // Drop to 0 if no AVX support | 476 if (!supports_avx ()) // Drop to 0 if no AVX support |
468 UseAVX = 0; | 477 UseAVX = 0; |
469 | 478 |
479 // Use AES instructions if available. | |
480 if (supports_aes()) { | |
481 if (FLAG_IS_DEFAULT(UseAES)) { | |
482 UseAES = true; | |
483 } | |
484 } else if (UseAES) { | |
485 if (!FLAG_IS_DEFAULT(UseAES)) | |
486 warning("AES instructions not available on this CPU"); | |
487 FLAG_SET_DEFAULT(UseAES, false); | |
488 } | |
489 | |
490 // The AES intrinsic stubs require AES instruction support (of course) | |
491 // but also require AVX and sse3 modes for instructions it use. | |
492 if (UseAES && (UseAVX > 0) && (UseSSE > 2)) { | |
493 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { | |
494 UseAESIntrinsics = true; | |
495 } | |
496 } else if (UseAESIntrinsics) { | |
497 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) | |
498 warning("AES intrinsics not available on this CPU"); | |
499 FLAG_SET_DEFAULT(UseAESIntrinsics, false); | |
500 } | |
501 | |
470 #ifdef COMPILER2 | 502 #ifdef COMPILER2 |
471 if (UseFPUForSpilling) { | 503 if (UseFPUForSpilling) { |
472 if (UseSSE < 2) { | 504 if (UseSSE < 2) { |
473 // Only supported with SSE2+ | 505 // Only supported with SSE2+ |
474 FLAG_SET_DEFAULT(UseFPUForSpilling, false); | 506 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
560 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW | 592 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW |
561 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { | 593 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
562 AllocatePrefetchInstr = 3; | 594 AllocatePrefetchInstr = 3; |
563 } | 595 } |
564 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy | 596 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy |
565 if( supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { | 597 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
566 UseXMMForArrayCopy = true; | 598 UseXMMForArrayCopy = true; |
567 } | 599 } |
568 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { | 600 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
569 UseUnalignedLoadStores = true; | 601 UseUnalignedLoadStores = true; |
570 } | 602 } |
571 } | 603 } |
572 | 604 |
573 #ifdef COMPILER2 | 605 #ifdef COMPILER2 |
610 // generated NOP instructions. 11 is the largest size of one | 642 // generated NOP instructions. 11 is the largest size of one |
611 // address NOP instruction '0F 1F' (see Assembler::nop(i)). | 643 // address NOP instruction '0F 1F' (see Assembler::nop(i)). |
612 MaxLoopPad = 11; | 644 MaxLoopPad = 11; |
613 } | 645 } |
614 #endif // COMPILER2 | 646 #endif // COMPILER2 |
615 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { | 647 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
616 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus | 648 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus |
617 } | 649 } |
618 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus | 650 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus |
619 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { | 651 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
620 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus | 652 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus |
621 } | 653 } |
622 } | 654 } |
623 if( supports_sse4_2() && UseSSE >= 4 ) { | 655 if (supports_sse4_2() && UseSSE >= 4) { |
624 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { | 656 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { |
625 UseSSE42Intrinsics = true; | 657 UseSSE42Intrinsics = true; |
626 } | 658 } |
627 } | 659 } |
628 } | 660 } |
629 } | 661 } |
635 } | 667 } |
636 } else if (UsePopCountInstruction) { | 668 } else if (UsePopCountInstruction) { |
637 warning("POPCNT instruction is not available on this CPU"); | 669 warning("POPCNT instruction is not available on this CPU"); |
638 FLAG_SET_DEFAULT(UsePopCountInstruction, false); | 670 FLAG_SET_DEFAULT(UsePopCountInstruction, false); |
639 } | 671 } |
672 | |
673 #ifdef COMPILER2 | |
674 if (FLAG_IS_DEFAULT(AlignVector)) { | |
675 // Modern processors allow misaligned memory operations for vectors. | |
676 AlignVector = !UseUnalignedLoadStores; | |
677 } | |
678 #endif // COMPILER2 | |
640 | 679 |
641 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); | 680 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
642 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); | 681 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); |
643 | 682 |
644 // set valid Prefetch instruction | 683 // set valid Prefetch instruction |
699 tty->print_cr("Logical CPUs per core: %u", | 738 tty->print_cr("Logical CPUs per core: %u", |
700 logical_processors_per_package()); | 739 logical_processors_per_package()); |
701 tty->print("UseSSE=%d",UseSSE); | 740 tty->print("UseSSE=%d",UseSSE); |
702 if (UseAVX > 0) { | 741 if (UseAVX > 0) { |
703 tty->print(" UseAVX=%d",UseAVX); | 742 tty->print(" UseAVX=%d",UseAVX); |
743 } | |
744 if (UseAES) { | |
745 tty->print(" UseAES=1"); | |
704 } | 746 } |
705 tty->cr(); | 747 tty->cr(); |
706 tty->print("Allocation"); | 748 tty->print("Allocation"); |
707 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { | 749 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { |
708 tty->print_cr(": no prefetching"); | 750 tty->print_cr(": no prefetching"); |