Mercurial > hg > truffle
comparison src/cpu/ppc/vm/assembler_ppc.hpp @ 14408:ec28f9c041ff
8019972: PPC64 (part 9): platform files for interpreter only VM.
Summary: With this change the HotSpot core build works on Linux/PPC64. The VM succesfully executes simple test programs.
Reviewed-by: kvn
author | goetz |
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date | Fri, 02 Aug 2013 16:46:45 +0200 |
parents | |
children | 67fa91961822 |
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1 /* | |
2 * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved. | |
3 * Copyright 2012, 2013 SAP AG. All rights reserved. | |
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
5 * | |
6 * This code is free software; you can redistribute it and/or modify it | |
7 * under the terms of the GNU General Public License version 2 only, as | |
8 * published by the Free Software Foundation. | |
9 * | |
10 * This code is distributed in the hope that it will be useful, but WITHOUT | |
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
13 * version 2 for more details (a copy is included in the LICENSE file that | |
14 * accompanied this code). | |
15 * | |
16 * You should have received a copy of the GNU General Public License version | |
17 * 2 along with this work; if not, write to the Free Software Foundation, | |
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
19 * | |
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA | |
21 * or visit www.oracle.com if you need additional information or have any | |
22 * questions. | |
23 * | |
24 */ | |
25 | |
26 #ifndef CPU_PPC_VM_ASSEMBLER_PPC_HPP | |
27 #define CPU_PPC_VM_ASSEMBLER_PPC_HPP | |
28 | |
29 #include "asm/register.hpp" | |
30 | |
31 // Address is an abstraction used to represent a memory location | |
32 // as used in assembler instructions. | |
33 // PPC instructions grok either baseReg + indexReg or baseReg + disp. | |
34 // So far we do not use this as simplification by this class is low | |
35 // on PPC with its simple addressing mode. Use RegisterOrConstant to | |
36 // represent an offset. | |
37 class Address VALUE_OBJ_CLASS_SPEC { | |
38 }; | |
39 | |
40 class AddressLiteral VALUE_OBJ_CLASS_SPEC { | |
41 private: | |
42 address _address; | |
43 RelocationHolder _rspec; | |
44 | |
45 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { | |
46 switch (rtype) { | |
47 case relocInfo::external_word_type: | |
48 return external_word_Relocation::spec(addr); | |
49 case relocInfo::internal_word_type: | |
50 return internal_word_Relocation::spec(addr); | |
51 case relocInfo::opt_virtual_call_type: | |
52 return opt_virtual_call_Relocation::spec(); | |
53 case relocInfo::static_call_type: | |
54 return static_call_Relocation::spec(); | |
55 case relocInfo::runtime_call_type: | |
56 return runtime_call_Relocation::spec(); | |
57 case relocInfo::none: | |
58 return RelocationHolder(); | |
59 default: | |
60 ShouldNotReachHere(); | |
61 return RelocationHolder(); | |
62 } | |
63 } | |
64 | |
65 protected: | |
66 // creation | |
67 AddressLiteral() : _address(NULL), _rspec(NULL) {} | |
68 | |
69 public: | |
70 AddressLiteral(address addr, RelocationHolder const& rspec) | |
71 : _address(addr), | |
72 _rspec(rspec) {} | |
73 | |
74 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) | |
75 : _address((address) addr), | |
76 _rspec(rspec_from_rtype(rtype, (address) addr)) {} | |
77 | |
78 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none) | |
79 : _address((address) addr), | |
80 _rspec(rspec_from_rtype(rtype, (address) addr)) {} | |
81 | |
82 intptr_t value() const { return (intptr_t) _address; } | |
83 | |
84 const RelocationHolder& rspec() const { return _rspec; } | |
85 }; | |
86 | |
87 // Argument is an abstraction used to represent an outgoing | |
88 // actual argument or an incoming formal parameter, whether | |
89 // it resides in memory or in a register, in a manner consistent | |
90 // with the PPC Application Binary Interface, or ABI. This is | |
91 // often referred to as the native or C calling convention. | |
92 | |
93 class Argument VALUE_OBJ_CLASS_SPEC { | |
94 private: | |
95 int _number; // The number of the argument. | |
96 public: | |
97 enum { | |
98 // Only 8 registers may contain integer parameters. | |
99 n_register_parameters = 8, | |
100 // Can have up to 8 floating registers. | |
101 n_float_register_parameters = 8 | |
102 }; | |
103 // creation | |
104 Argument(int number) : _number(number) {} | |
105 | |
106 int number() const { return _number; } | |
107 | |
108 // Locating register-based arguments: | |
109 bool is_register() const { return _number < n_register_parameters; } | |
110 | |
111 Register as_register() const { | |
112 assert(is_register(), "must be a register argument"); | |
113 return as_Register(number() + R3_ARG1->encoding()); | |
114 } | |
115 }; | |
116 | |
117 // A ppc64 function descriptor. | |
118 struct FunctionDescriptor VALUE_OBJ_CLASS_SPEC { | |
119 private: | |
120 address _entry; | |
121 address _toc; | |
122 address _env; | |
123 | |
124 public: | |
125 inline address entry() const { return _entry; } | |
126 inline address toc() const { return _toc; } | |
127 inline address env() const { return _env; } | |
128 | |
129 inline void set_entry(address entry) { _entry = entry; } | |
130 inline void set_toc( address toc) { _toc = toc; } | |
131 inline void set_env( address env) { _env = env; } | |
132 | |
133 inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); } | |
134 inline static ByteSize toc_offset() { return byte_offset_of(FunctionDescriptor, _toc); } | |
135 inline static ByteSize env_offset() { return byte_offset_of(FunctionDescriptor, _env); } | |
136 | |
137 // Friend functions can be called without loading toc and env. | |
138 enum { | |
139 friend_toc = 0xcafe, | |
140 friend_env = 0xc0de | |
141 }; | |
142 | |
143 inline bool is_friend_function() const { | |
144 return (toc() == (address) friend_toc) && (env() == (address) friend_env); | |
145 } | |
146 | |
147 // Constructor for stack-allocated instances. | |
148 FunctionDescriptor() { | |
149 _entry = (address) 0xbad; | |
150 _toc = (address) 0xbad; | |
151 _env = (address) 0xbad; | |
152 } | |
153 }; | |
154 | |
155 class Assembler : public AbstractAssembler { | |
156 protected: | |
157 // Displacement routines | |
158 static void print_instruction(int inst); | |
159 static int patched_branch(int dest_pos, int inst, int inst_pos); | |
160 static int branch_destination(int inst, int pos); | |
161 | |
162 friend class AbstractAssembler; | |
163 | |
164 // Code patchers need various routines like inv_wdisp() | |
165 friend class NativeInstruction; | |
166 friend class NativeGeneralJump; | |
167 friend class Relocation; | |
168 | |
169 public: | |
170 | |
171 enum shifts { | |
172 XO_21_29_SHIFT = 2, | |
173 XO_21_30_SHIFT = 1, | |
174 XO_27_29_SHIFT = 2, | |
175 XO_30_31_SHIFT = 0, | |
176 SPR_5_9_SHIFT = 11u, // SPR_5_9 field in bits 11 -- 15 | |
177 SPR_0_4_SHIFT = 16u, // SPR_0_4 field in bits 16 -- 20 | |
178 RS_SHIFT = 21u, // RS field in bits 21 -- 25 | |
179 OPCODE_SHIFT = 26u, // opcode in bits 26 -- 31 | |
180 }; | |
181 | |
182 enum opcdxos_masks { | |
183 XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), | |
184 ADDI_OPCODE_MASK = (63u << OPCODE_SHIFT), | |
185 ADDIS_OPCODE_MASK = (63u << OPCODE_SHIFT), | |
186 BXX_OPCODE_MASK = (63u << OPCODE_SHIFT), | |
187 BCXX_OPCODE_MASK = (63u << OPCODE_SHIFT), | |
188 // trap instructions | |
189 TDI_OPCODE_MASK = (63u << OPCODE_SHIFT), | |
190 TWI_OPCODE_MASK = (63u << OPCODE_SHIFT), | |
191 TD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), | |
192 TW_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), | |
193 LD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM | |
194 STD_OPCODE_MASK = LD_OPCODE_MASK, | |
195 STDU_OPCODE_MASK = STD_OPCODE_MASK, | |
196 STDX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), | |
197 STDUX_OPCODE_MASK = STDX_OPCODE_MASK, | |
198 STW_OPCODE_MASK = (63u << OPCODE_SHIFT), | |
199 STWU_OPCODE_MASK = STW_OPCODE_MASK, | |
200 STWX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), | |
201 STWUX_OPCODE_MASK = STWX_OPCODE_MASK, | |
202 MTCTR_OPCODE_MASK = ~(31u << RS_SHIFT), | |
203 ORI_OPCODE_MASK = (63u << OPCODE_SHIFT), | |
204 ORIS_OPCODE_MASK = (63u << OPCODE_SHIFT), | |
205 RLDICR_OPCODE_MASK = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT) | |
206 }; | |
207 | |
208 enum opcdxos { | |
209 ADD_OPCODE = (31u << OPCODE_SHIFT | 266u << 1), | |
210 ADDC_OPCODE = (31u << OPCODE_SHIFT | 10u << 1), | |
211 ADDI_OPCODE = (14u << OPCODE_SHIFT), | |
212 ADDIS_OPCODE = (15u << OPCODE_SHIFT), | |
213 ADDIC__OPCODE = (13u << OPCODE_SHIFT), | |
214 ADDE_OPCODE = (31u << OPCODE_SHIFT | 138u << 1), | |
215 SUBF_OPCODE = (31u << OPCODE_SHIFT | 40u << 1), | |
216 SUBFC_OPCODE = (31u << OPCODE_SHIFT | 8u << 1), | |
217 SUBFE_OPCODE = (31u << OPCODE_SHIFT | 136u << 1), | |
218 SUBFIC_OPCODE = (8u << OPCODE_SHIFT), | |
219 SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1), | |
220 DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1), | |
221 MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1), | |
222 MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1), | |
223 MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1), | |
224 MULLI_OPCODE = (7u << OPCODE_SHIFT), | |
225 AND_OPCODE = (31u << OPCODE_SHIFT | 28u << 1), | |
226 ANDI_OPCODE = (28u << OPCODE_SHIFT), | |
227 ANDIS_OPCODE = (29u << OPCODE_SHIFT), | |
228 ANDC_OPCODE = (31u << OPCODE_SHIFT | 60u << 1), | |
229 ORC_OPCODE = (31u << OPCODE_SHIFT | 412u << 1), | |
230 OR_OPCODE = (31u << OPCODE_SHIFT | 444u << 1), | |
231 ORI_OPCODE = (24u << OPCODE_SHIFT), | |
232 ORIS_OPCODE = (25u << OPCODE_SHIFT), | |
233 XOR_OPCODE = (31u << OPCODE_SHIFT | 316u << 1), | |
234 XORI_OPCODE = (26u << OPCODE_SHIFT), | |
235 XORIS_OPCODE = (27u << OPCODE_SHIFT), | |
236 | |
237 NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1), | |
238 | |
239 RLWINM_OPCODE = (21u << OPCODE_SHIFT), | |
240 CLRRWI_OPCODE = RLWINM_OPCODE, | |
241 CLRLWI_OPCODE = RLWINM_OPCODE, | |
242 | |
243 RLWIMI_OPCODE = (20u << OPCODE_SHIFT), | |
244 | |
245 SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1), | |
246 SLWI_OPCODE = RLWINM_OPCODE, | |
247 SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1), | |
248 SRWI_OPCODE = RLWINM_OPCODE, | |
249 SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1), | |
250 SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1), | |
251 | |
252 CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1), | |
253 CMPI_OPCODE = (11u << OPCODE_SHIFT), | |
254 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1), | |
255 CMPLI_OPCODE = (10u << OPCODE_SHIFT), | |
256 | |
257 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1), | |
258 | |
259 MTLR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 8 << SPR_0_4_SHIFT), | |
260 MFLR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 8 << SPR_0_4_SHIFT), | |
261 | |
262 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1), | |
263 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1), | |
264 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1), | |
265 | |
266 // condition register logic instructions | |
267 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1), | |
268 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1), | |
269 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1), | |
270 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1), | |
271 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1), | |
272 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1), | |
273 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1), | |
274 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1), | |
275 | |
276 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1), | |
277 BXX_OPCODE = (18u << OPCODE_SHIFT), | |
278 BCXX_OPCODE = (16u << OPCODE_SHIFT), | |
279 | |
280 // CTR-related opcodes | |
281 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1), | |
282 MTCTR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 9 << SPR_0_4_SHIFT), | |
283 MFCTR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 9 << SPR_0_4_SHIFT), | |
284 | |
285 | |
286 LWZ_OPCODE = (32u << OPCODE_SHIFT), | |
287 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1), | |
288 LWZU_OPCODE = (33u << OPCODE_SHIFT), | |
289 | |
290 LHA_OPCODE = (42u << OPCODE_SHIFT), | |
291 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1), | |
292 LHAU_OPCODE = (43u << OPCODE_SHIFT), | |
293 | |
294 LHZ_OPCODE = (40u << OPCODE_SHIFT), | |
295 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1), | |
296 LHZU_OPCODE = (41u << OPCODE_SHIFT), | |
297 | |
298 LBZ_OPCODE = (34u << OPCODE_SHIFT), | |
299 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1), | |
300 LBZU_OPCODE = (35u << OPCODE_SHIFT), | |
301 | |
302 STW_OPCODE = (36u << OPCODE_SHIFT), | |
303 STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1), | |
304 STWU_OPCODE = (37u << OPCODE_SHIFT), | |
305 STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1), | |
306 | |
307 STH_OPCODE = (44u << OPCODE_SHIFT), | |
308 STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1), | |
309 STHU_OPCODE = (45u << OPCODE_SHIFT), | |
310 | |
311 STB_OPCODE = (38u << OPCODE_SHIFT), | |
312 STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1), | |
313 STBU_OPCODE = (39u << OPCODE_SHIFT), | |
314 | |
315 EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1), | |
316 EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1), | |
317 EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1), // X-FORM | |
318 | |
319 // 32 bit opcode encodings | |
320 | |
321 LWA_OPCODE = (58u << OPCODE_SHIFT | 2u << XO_30_31_SHIFT), // DS-FORM | |
322 LWAX_OPCODE = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM | |
323 | |
324 CNTLZW_OPCODE = (31u << OPCODE_SHIFT | 26u << XO_21_30_SHIFT), // X-FORM | |
325 | |
326 // 64 bit opcode encodings | |
327 | |
328 LD_OPCODE = (58u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM | |
329 LDU_OPCODE = (58u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM | |
330 LDX_OPCODE = (31u << OPCODE_SHIFT | 21u << XO_21_30_SHIFT), // X-FORM | |
331 | |
332 STD_OPCODE = (62u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM | |
333 STDU_OPCODE = (62u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM | |
334 STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM | |
335 STDX_OPCODE = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM | |
336 | |
337 RLDICR_OPCODE = (30u << OPCODE_SHIFT | 1u << XO_27_29_SHIFT), // MD-FORM | |
338 RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM | |
339 RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM | |
340 RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM | |
341 | |
342 SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM | |
343 | |
344 SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM | |
345 SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM | |
346 SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM | |
347 | |
348 MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM | |
349 MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM | |
350 MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM | |
351 DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM | |
352 | |
353 CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM | |
354 NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM | |
355 NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM | |
356 | |
357 | |
358 // opcodes only used for floating arithmetic | |
359 FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1), | |
360 FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1), | |
361 FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1), | |
362 FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1), | |
363 FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1), | |
364 FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1), | |
365 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx" | |
366 // on Power7. Do not use. | |
367 // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1), | |
368 // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1), | |
369 CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1), | |
370 POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1), | |
371 POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1), | |
372 POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1), | |
373 FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1), | |
374 FNABS_OPCODE = (63u << OPCODE_SHIFT | 136u << 1), | |
375 FMUL_OPCODE = (63u << OPCODE_SHIFT | 25u << 1), | |
376 FMULS_OPCODE = (59u << OPCODE_SHIFT | 25u << 1), | |
377 FNEG_OPCODE = (63u << OPCODE_SHIFT | 40u << 1), | |
378 FSUB_OPCODE = (63u << OPCODE_SHIFT | 20u << 1), | |
379 FSUBS_OPCODE = (59u << OPCODE_SHIFT | 20u << 1), | |
380 | |
381 // PPC64-internal FPU conversion opcodes | |
382 FCFID_OPCODE = (63u << OPCODE_SHIFT | 846u << 1), | |
383 FCFIDS_OPCODE = (59u << OPCODE_SHIFT | 846u << 1), | |
384 FCTID_OPCODE = (63u << OPCODE_SHIFT | 814u << 1), | |
385 FCTIDZ_OPCODE = (63u << OPCODE_SHIFT | 815u << 1), | |
386 FCTIW_OPCODE = (63u << OPCODE_SHIFT | 14u << 1), | |
387 FCTIWZ_OPCODE = (63u << OPCODE_SHIFT | 15u << 1), | |
388 FRSP_OPCODE = (63u << OPCODE_SHIFT | 12u << 1), | |
389 | |
390 // WARNING: using fmadd results in a non-compliant vm. Some floating | |
391 // point tck tests will fail. | |
392 FMADD_OPCODE = (59u << OPCODE_SHIFT | 29u << 1), | |
393 DMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1), | |
394 FMSUB_OPCODE = (59u << OPCODE_SHIFT | 28u << 1), | |
395 DMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1), | |
396 FNMADD_OPCODE = (59u << OPCODE_SHIFT | 31u << 1), | |
397 DNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1), | |
398 FNMSUB_OPCODE = (59u << OPCODE_SHIFT | 30u << 1), | |
399 DNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1), | |
400 | |
401 LFD_OPCODE = (50u << OPCODE_SHIFT | 00u << 1), | |
402 LFDU_OPCODE = (51u << OPCODE_SHIFT | 00u << 1), | |
403 LFDX_OPCODE = (31u << OPCODE_SHIFT | 599u << 1), | |
404 LFS_OPCODE = (48u << OPCODE_SHIFT | 00u << 1), | |
405 LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1), | |
406 LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1), | |
407 | |
408 STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1), | |
409 STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1), | |
410 STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1), | |
411 STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1), | |
412 STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1), | |
413 STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1), | |
414 | |
415 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM | |
416 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM | |
417 | |
418 // Vector instruction support for >= Power6 | |
419 // Vector Storage Access | |
420 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1), | |
421 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1), | |
422 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1), | |
423 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1), | |
424 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1), | |
425 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1), | |
426 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1), | |
427 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1), | |
428 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1), | |
429 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1), | |
430 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1), | |
431 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1), | |
432 | |
433 // Vector Permute and Formatting | |
434 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ), | |
435 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ), | |
436 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ), | |
437 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ), | |
438 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ), | |
439 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ), | |
440 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ), | |
441 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ), | |
442 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ), | |
443 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ), | |
444 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ), | |
445 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ), | |
446 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ), | |
447 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ), | |
448 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ), | |
449 | |
450 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ), | |
451 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ), | |
452 VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ), | |
453 VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ), | |
454 VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ), | |
455 VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ), | |
456 | |
457 VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ), | |
458 VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ), | |
459 VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ), | |
460 VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ), | |
461 VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ), | |
462 VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ), | |
463 | |
464 VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ), | |
465 VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ), | |
466 | |
467 VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ), | |
468 VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ), | |
469 VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ), | |
470 VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ), | |
471 VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ), | |
472 | |
473 // Vector Integer | |
474 VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ), | |
475 VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ), | |
476 VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ), | |
477 VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ), | |
478 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ), | |
479 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ), | |
480 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ), | |
481 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ), | |
482 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ), | |
483 VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ), | |
484 VSUBCUW_OPCODE = (4u << OPCODE_SHIFT | 1408u ), | |
485 VSUBSHS_OPCODE = (4u << OPCODE_SHIFT | 1856u ), | |
486 VSUBSBS_OPCODE = (4u << OPCODE_SHIFT | 1792u ), | |
487 VSUBSWS_OPCODE = (4u << OPCODE_SHIFT | 1920u ), | |
488 VSUBUBM_OPCODE = (4u << OPCODE_SHIFT | 1024u ), | |
489 VSUBUWM_OPCODE = (4u << OPCODE_SHIFT | 1152u ), | |
490 VSUBUHM_OPCODE = (4u << OPCODE_SHIFT | 1088u ), | |
491 VSUBUBS_OPCODE = (4u << OPCODE_SHIFT | 1536u ), | |
492 VSUBUWS_OPCODE = (4u << OPCODE_SHIFT | 1664u ), | |
493 VSUBUHS_OPCODE = (4u << OPCODE_SHIFT | 1600u ), | |
494 | |
495 VMULESB_OPCODE = (4u << OPCODE_SHIFT | 776u ), | |
496 VMULEUB_OPCODE = (4u << OPCODE_SHIFT | 520u ), | |
497 VMULESH_OPCODE = (4u << OPCODE_SHIFT | 840u ), | |
498 VMULEUH_OPCODE = (4u << OPCODE_SHIFT | 584u ), | |
499 VMULOSB_OPCODE = (4u << OPCODE_SHIFT | 264u ), | |
500 VMULOUB_OPCODE = (4u << OPCODE_SHIFT | 8u ), | |
501 VMULOSH_OPCODE = (4u << OPCODE_SHIFT | 328u ), | |
502 VMULOUH_OPCODE = (4u << OPCODE_SHIFT | 72u ), | |
503 VMHADDSHS_OPCODE=(4u << OPCODE_SHIFT | 32u ), | |
504 VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT | 33u ), | |
505 VMLADDUHM_OPCODE=(4u << OPCODE_SHIFT | 34u ), | |
506 VMSUBUHM_OPCODE= (4u << OPCODE_SHIFT | 36u ), | |
507 VMSUMMBM_OPCODE= (4u << OPCODE_SHIFT | 37u ), | |
508 VMSUMSHM_OPCODE= (4u << OPCODE_SHIFT | 40u ), | |
509 VMSUMSHS_OPCODE= (4u << OPCODE_SHIFT | 41u ), | |
510 VMSUMUHM_OPCODE= (4u << OPCODE_SHIFT | 38u ), | |
511 VMSUMUHS_OPCODE= (4u << OPCODE_SHIFT | 39u ), | |
512 | |
513 VSUMSWS_OPCODE = (4u << OPCODE_SHIFT | 1928u ), | |
514 VSUM2SWS_OPCODE= (4u << OPCODE_SHIFT | 1672u ), | |
515 VSUM4SBS_OPCODE= (4u << OPCODE_SHIFT | 1800u ), | |
516 VSUM4UBS_OPCODE= (4u << OPCODE_SHIFT | 1544u ), | |
517 VSUM4SHS_OPCODE= (4u << OPCODE_SHIFT | 1608u ), | |
518 | |
519 VAVGSB_OPCODE = (4u << OPCODE_SHIFT | 1282u ), | |
520 VAVGSW_OPCODE = (4u << OPCODE_SHIFT | 1410u ), | |
521 VAVGSH_OPCODE = (4u << OPCODE_SHIFT | 1346u ), | |
522 VAVGUB_OPCODE = (4u << OPCODE_SHIFT | 1026u ), | |
523 VAVGUW_OPCODE = (4u << OPCODE_SHIFT | 1154u ), | |
524 VAVGUH_OPCODE = (4u << OPCODE_SHIFT | 1090u ), | |
525 | |
526 VMAXSB_OPCODE = (4u << OPCODE_SHIFT | 258u ), | |
527 VMAXSW_OPCODE = (4u << OPCODE_SHIFT | 386u ), | |
528 VMAXSH_OPCODE = (4u << OPCODE_SHIFT | 322u ), | |
529 VMAXUB_OPCODE = (4u << OPCODE_SHIFT | 2u ), | |
530 VMAXUW_OPCODE = (4u << OPCODE_SHIFT | 130u ), | |
531 VMAXUH_OPCODE = (4u << OPCODE_SHIFT | 66u ), | |
532 VMINSB_OPCODE = (4u << OPCODE_SHIFT | 770u ), | |
533 VMINSW_OPCODE = (4u << OPCODE_SHIFT | 898u ), | |
534 VMINSH_OPCODE = (4u << OPCODE_SHIFT | 834u ), | |
535 VMINUB_OPCODE = (4u << OPCODE_SHIFT | 514u ), | |
536 VMINUW_OPCODE = (4u << OPCODE_SHIFT | 642u ), | |
537 VMINUH_OPCODE = (4u << OPCODE_SHIFT | 578u ), | |
538 | |
539 VCMPEQUB_OPCODE= (4u << OPCODE_SHIFT | 6u ), | |
540 VCMPEQUH_OPCODE= (4u << OPCODE_SHIFT | 70u ), | |
541 VCMPEQUW_OPCODE= (4u << OPCODE_SHIFT | 134u ), | |
542 VCMPGTSH_OPCODE= (4u << OPCODE_SHIFT | 838u ), | |
543 VCMPGTSB_OPCODE= (4u << OPCODE_SHIFT | 774u ), | |
544 VCMPGTSW_OPCODE= (4u << OPCODE_SHIFT | 902u ), | |
545 VCMPGTUB_OPCODE= (4u << OPCODE_SHIFT | 518u ), | |
546 VCMPGTUH_OPCODE= (4u << OPCODE_SHIFT | 582u ), | |
547 VCMPGTUW_OPCODE= (4u << OPCODE_SHIFT | 646u ), | |
548 | |
549 VAND_OPCODE = (4u << OPCODE_SHIFT | 1028u ), | |
550 VANDC_OPCODE = (4u << OPCODE_SHIFT | 1092u ), | |
551 VNOR_OPCODE = (4u << OPCODE_SHIFT | 1284u ), | |
552 VOR_OPCODE = (4u << OPCODE_SHIFT | 1156u ), | |
553 VXOR_OPCODE = (4u << OPCODE_SHIFT | 1220u ), | |
554 VRLB_OPCODE = (4u << OPCODE_SHIFT | 4u ), | |
555 VRLW_OPCODE = (4u << OPCODE_SHIFT | 132u ), | |
556 VRLH_OPCODE = (4u << OPCODE_SHIFT | 68u ), | |
557 VSLB_OPCODE = (4u << OPCODE_SHIFT | 260u ), | |
558 VSKW_OPCODE = (4u << OPCODE_SHIFT | 388u ), | |
559 VSLH_OPCODE = (4u << OPCODE_SHIFT | 324u ), | |
560 VSRB_OPCODE = (4u << OPCODE_SHIFT | 516u ), | |
561 VSRW_OPCODE = (4u << OPCODE_SHIFT | 644u ), | |
562 VSRH_OPCODE = (4u << OPCODE_SHIFT | 580u ), | |
563 VSRAB_OPCODE = (4u << OPCODE_SHIFT | 772u ), | |
564 VSRAW_OPCODE = (4u << OPCODE_SHIFT | 900u ), | |
565 VSRAH_OPCODE = (4u << OPCODE_SHIFT | 836u ), | |
566 | |
567 // Vector Floating-Point | |
568 // not implemented yet | |
569 | |
570 // Vector Status and Control | |
571 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ), | |
572 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ), | |
573 | |
574 // Icache and dcache related instructions | |
575 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1), | |
576 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1), | |
577 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1), | |
578 DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1), | |
579 | |
580 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1), | |
581 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1), | |
582 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1), | |
583 | |
584 // Instruction synchronization | |
585 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1), | |
586 // Memory barriers | |
587 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1), | |
588 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1), | |
589 | |
590 // Trap instructions | |
591 TDI_OPCODE = (2u << OPCODE_SHIFT), | |
592 TWI_OPCODE = (3u << OPCODE_SHIFT), | |
593 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1), | |
594 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1), | |
595 | |
596 // Atomics. | |
597 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1), | |
598 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1), | |
599 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1), | |
600 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1) | |
601 | |
602 }; | |
603 | |
604 // Trap instructions TO bits | |
605 enum trap_to_bits { | |
606 // single bits | |
607 traptoLessThanSigned = 1 << 4, // 0, left end | |
608 traptoGreaterThanSigned = 1 << 3, | |
609 traptoEqual = 1 << 2, | |
610 traptoLessThanUnsigned = 1 << 1, | |
611 traptoGreaterThanUnsigned = 1 << 0, // 4, right end | |
612 | |
613 // compound ones | |
614 traptoUnconditional = (traptoLessThanSigned | | |
615 traptoGreaterThanSigned | | |
616 traptoEqual | | |
617 traptoLessThanUnsigned | | |
618 traptoGreaterThanUnsigned) | |
619 }; | |
620 | |
621 // Branch hints BH field | |
622 enum branch_hint_bh { | |
623 // bclr cases: | |
624 bhintbhBCLRisReturn = 0, | |
625 bhintbhBCLRisNotReturnButSame = 1, | |
626 bhintbhBCLRisNotPredictable = 3, | |
627 | |
628 // bcctr cases: | |
629 bhintbhBCCTRisNotReturnButSame = 0, | |
630 bhintbhBCCTRisNotPredictable = 3 | |
631 }; | |
632 | |
633 // Branch prediction hints AT field | |
634 enum branch_hint_at { | |
635 bhintatNoHint = 0, // at=00 | |
636 bhintatIsNotTaken = 2, // at=10 | |
637 bhintatIsTaken = 3 // at=11 | |
638 }; | |
639 | |
640 // Branch prediction hints | |
641 enum branch_hint_concept { | |
642 // Use the same encoding as branch_hint_at to simply code. | |
643 bhintNoHint = bhintatNoHint, | |
644 bhintIsNotTaken = bhintatIsNotTaken, | |
645 bhintIsTaken = bhintatIsTaken | |
646 }; | |
647 | |
648 // Used in BO field of branch instruction. | |
649 enum branch_condition { | |
650 bcondCRbiIs0 = 4, // bo=001at | |
651 bcondCRbiIs1 = 12, // bo=011at | |
652 bcondAlways = 20 // bo=10100 | |
653 }; | |
654 | |
655 // Branch condition with combined prediction hints. | |
656 enum branch_condition_with_hint { | |
657 bcondCRbiIs0_bhintNoHint = bcondCRbiIs0 | bhintatNoHint, | |
658 bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken, | |
659 bcondCRbiIs0_bhintIsTaken = bcondCRbiIs0 | bhintatIsTaken, | |
660 bcondCRbiIs1_bhintNoHint = bcondCRbiIs1 | bhintatNoHint, | |
661 bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken, | |
662 bcondCRbiIs1_bhintIsTaken = bcondCRbiIs1 | bhintatIsTaken, | |
663 }; | |
664 | |
665 // Branch prediction hints. | |
666 inline static int add_bhint_to_boint(const int bhint, const int boint) { | |
667 switch (boint) { | |
668 case bcondCRbiIs0: | |
669 case bcondCRbiIs1: | |
670 // branch_hint and branch_hint_at have same encodings | |
671 assert( (int)bhintNoHint == (int)bhintatNoHint | |
672 && (int)bhintIsNotTaken == (int)bhintatIsNotTaken | |
673 && (int)bhintIsTaken == (int)bhintatIsTaken, | |
674 "wrong encodings"); | |
675 assert((bhint & 0x03) == bhint, "wrong encodings"); | |
676 return (boint & ~0x03) | bhint; | |
677 case bcondAlways: | |
678 // no branch_hint | |
679 return boint; | |
680 default: | |
681 ShouldNotReachHere(); | |
682 return 0; | |
683 } | |
684 } | |
685 | |
686 // Extract bcond from boint. | |
687 inline static int inv_boint_bcond(const int boint) { | |
688 int r_bcond = boint & ~0x03; | |
689 assert(r_bcond == bcondCRbiIs0 || | |
690 r_bcond == bcondCRbiIs1 || | |
691 r_bcond == bcondAlways, | |
692 "bad branch condition"); | |
693 return r_bcond; | |
694 } | |
695 | |
696 // Extract bhint from boint. | |
697 inline static int inv_boint_bhint(const int boint) { | |
698 int r_bhint = boint & 0x03; | |
699 assert(r_bhint == bhintatNoHint || | |
700 r_bhint == bhintatIsNotTaken || | |
701 r_bhint == bhintatIsTaken, | |
702 "bad branch hint"); | |
703 return r_bhint; | |
704 } | |
705 | |
706 // Calculate opposite of given bcond. | |
707 inline static int opposite_bcond(const int bcond) { | |
708 switch (bcond) { | |
709 case bcondCRbiIs0: | |
710 return bcondCRbiIs1; | |
711 case bcondCRbiIs1: | |
712 return bcondCRbiIs0; | |
713 default: | |
714 ShouldNotReachHere(); | |
715 return 0; | |
716 } | |
717 } | |
718 | |
719 // Calculate opposite of given bhint. | |
720 inline static int opposite_bhint(const int bhint) { | |
721 switch (bhint) { | |
722 case bhintatNoHint: | |
723 return bhintatNoHint; | |
724 case bhintatIsNotTaken: | |
725 return bhintatIsTaken; | |
726 case bhintatIsTaken: | |
727 return bhintatIsNotTaken; | |
728 default: | |
729 ShouldNotReachHere(); | |
730 return 0; | |
731 } | |
732 } | |
733 | |
734 // PPC branch instructions | |
735 enum ppcops { | |
736 b_op = 18, | |
737 bc_op = 16, | |
738 bcr_op = 19 | |
739 }; | |
740 | |
741 enum Condition { | |
742 negative = 0, | |
743 less = 0, | |
744 positive = 1, | |
745 greater = 1, | |
746 zero = 2, | |
747 equal = 2, | |
748 summary_overflow = 3, | |
749 }; | |
750 | |
751 public: | |
752 // Helper functions for groups of instructions | |
753 | |
754 enum Predict { pt = 1, pn = 0 }; // pt = predict taken | |
755 | |
756 enum Membar_mask_bits { // page 184, v9 | |
757 StoreStore = 1 << 3, | |
758 LoadStore = 1 << 2, | |
759 StoreLoad = 1 << 1, | |
760 LoadLoad = 1 << 0, | |
761 | |
762 Sync = 1 << 6, | |
763 MemIssue = 1 << 5, | |
764 Lookaside = 1 << 4 | |
765 }; | |
766 | |
767 // instruction must start at passed address | |
768 static int instr_len(unsigned char *instr) { return BytesPerInstWord; } | |
769 | |
770 // instruction must be left-justified in argument | |
771 static int instr_len(unsigned long instr) { return BytesPerInstWord; } | |
772 | |
773 // longest instructions | |
774 static int instr_maxlen() { return BytesPerInstWord; } | |
775 | |
776 // Test if x is within signed immediate range for nbits. | |
777 static bool is_simm(int x, unsigned int nbits) { | |
778 assert(0 < nbits && nbits < 32, "out of bounds"); | |
779 const int min = -( ((int)1) << nbits-1 ); | |
780 const int maxplus1 = ( ((int)1) << nbits-1 ); | |
781 return min <= x && x < maxplus1; | |
782 } | |
783 | |
784 static bool is_simm(jlong x, unsigned int nbits) { | |
785 assert(0 < nbits && nbits < 64, "out of bounds"); | |
786 const jlong min = -( ((jlong)1) << nbits-1 ); | |
787 const jlong maxplus1 = ( ((jlong)1) << nbits-1 ); | |
788 return min <= x && x < maxplus1; | |
789 } | |
790 | |
791 // Test if x is within unsigned immediate range for nbits | |
792 static bool is_uimm(int x, unsigned int nbits) { | |
793 assert(0 < nbits && nbits < 32, "out of bounds"); | |
794 const int maxplus1 = ( ((int)1) << nbits ); | |
795 return 0 <= x && x < maxplus1; | |
796 } | |
797 | |
798 static bool is_uimm(jlong x, unsigned int nbits) { | |
799 assert(0 < nbits && nbits < 64, "out of bounds"); | |
800 const jlong maxplus1 = ( ((jlong)1) << nbits ); | |
801 return 0 <= x && x < maxplus1; | |
802 } | |
803 | |
804 protected: | |
805 // helpers | |
806 | |
807 // X is supposed to fit in a field "nbits" wide | |
808 // and be sign-extended. Check the range. | |
809 static void assert_signed_range(intptr_t x, int nbits) { | |
810 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)), | |
811 "value out of range"); | |
812 } | |
813 | |
814 static void assert_signed_word_disp_range(intptr_t x, int nbits) { | |
815 assert((x & 3) == 0, "not word aligned"); | |
816 assert_signed_range(x, nbits + 2); | |
817 } | |
818 | |
819 static void assert_unsigned_const(int x, int nbits) { | |
820 assert(juint(x) < juint(1 << nbits), "unsigned constant out of range"); | |
821 } | |
822 | |
823 static int fmask(juint hi_bit, juint lo_bit) { | |
824 assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits"); | |
825 return (1 << ( hi_bit-lo_bit + 1 )) - 1; | |
826 } | |
827 | |
828 // inverse of u_field | |
829 static int inv_u_field(int x, int hi_bit, int lo_bit) { | |
830 juint r = juint(x) >> lo_bit; | |
831 r &= fmask(hi_bit, lo_bit); | |
832 return int(r); | |
833 } | |
834 | |
835 // signed version: extract from field and sign-extend | |
836 static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) { | |
837 x = x << (31-hi_bit); | |
838 x = x >> (31-hi_bit+lo_bit); | |
839 return x; | |
840 } | |
841 | |
842 static int u_field(int x, int hi_bit, int lo_bit) { | |
843 assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range"); | |
844 int r = x << lo_bit; | |
845 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); | |
846 return r; | |
847 } | |
848 | |
849 // Same as u_field for signed values | |
850 static int s_field(int x, int hi_bit, int lo_bit) { | |
851 int nbits = hi_bit - lo_bit + 1; | |
852 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)), | |
853 "value out of range"); | |
854 x &= fmask(hi_bit, lo_bit); | |
855 int r = x << lo_bit; | |
856 return r; | |
857 } | |
858 | |
859 // inv_op for ppc instructions | |
860 static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); } | |
861 | |
862 // Determine target address from li, bd field of branch instruction. | |
863 static intptr_t inv_li_field(int x) { | |
864 intptr_t r = inv_s_field_ppc(x, 25, 2); | |
865 r = (r << 2); | |
866 return r; | |
867 } | |
868 static intptr_t inv_bd_field(int x, intptr_t pos) { | |
869 intptr_t r = inv_s_field_ppc(x, 15, 2); | |
870 r = (r << 2) + pos; | |
871 return r; | |
872 } | |
873 | |
874 #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit)) | |
875 #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit)) | |
876 // Extract instruction fields from instruction words. | |
877 public: | |
878 static int inv_ra_field(int x) { return inv_opp_u_field(x, 15, 11); } | |
879 static int inv_rb_field(int x) { return inv_opp_u_field(x, 20, 16); } | |
880 static int inv_rt_field(int x) { return inv_opp_u_field(x, 10, 6); } | |
881 static int inv_rs_field(int x) { return inv_opp_u_field(x, 10, 6); } | |
882 // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0. | |
883 // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0. | |
884 static int inv_ds_field(int x) { return inv_opp_s_field(x, 29, 16) << 2; } | |
885 static int inv_d1_field(int x) { return inv_opp_s_field(x, 31, 16); } | |
886 static int inv_si_field(int x) { return inv_opp_s_field(x, 31, 16); } | |
887 static int inv_to_field(int x) { return inv_opp_u_field(x, 10, 6); } | |
888 static int inv_lk_field(int x) { return inv_opp_u_field(x, 31, 31); } | |
889 static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); } | |
890 static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); } | |
891 | |
892 #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit)) | |
893 #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit)) | |
894 | |
895 // instruction fields | |
896 static int aa( int x) { return opp_u_field(x, 30, 30); } | |
897 static int ba( int x) { return opp_u_field(x, 15, 11); } | |
898 static int bb( int x) { return opp_u_field(x, 20, 16); } | |
899 static int bc( int x) { return opp_u_field(x, 25, 21); } | |
900 static int bd( int x) { return opp_s_field(x, 29, 16); } | |
901 static int bf( ConditionRegister cr) { return bf(cr->encoding()); } | |
902 static int bf( int x) { return opp_u_field(x, 8, 6); } | |
903 static int bfa(ConditionRegister cr) { return bfa(cr->encoding()); } | |
904 static int bfa( int x) { return opp_u_field(x, 13, 11); } | |
905 static int bh( int x) { return opp_u_field(x, 20, 19); } | |
906 static int bi( int x) { return opp_u_field(x, 15, 11); } | |
907 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; } | |
908 static int bo( int x) { return opp_u_field(x, 10, 6); } | |
909 static int bt( int x) { return opp_u_field(x, 10, 6); } | |
910 static int d1( int x) { return opp_s_field(x, 31, 16); } | |
911 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); } | |
912 static int eh( int x) { return opp_u_field(x, 31, 31); } | |
913 static int flm( int x) { return opp_u_field(x, 14, 7); } | |
914 static int fra( FloatRegister r) { return fra(r->encoding());} | |
915 static int frb( FloatRegister r) { return frb(r->encoding());} | |
916 static int frc( FloatRegister r) { return frc(r->encoding());} | |
917 static int frs( FloatRegister r) { return frs(r->encoding());} | |
918 static int frt( FloatRegister r) { return frt(r->encoding());} | |
919 static int fra( int x) { return opp_u_field(x, 15, 11); } | |
920 static int frb( int x) { return opp_u_field(x, 20, 16); } | |
921 static int frc( int x) { return opp_u_field(x, 25, 21); } | |
922 static int frs( int x) { return opp_u_field(x, 10, 6); } | |
923 static int frt( int x) { return opp_u_field(x, 10, 6); } | |
924 static int fxm( int x) { return opp_u_field(x, 19, 12); } | |
925 static int l10( int x) { return opp_u_field(x, 10, 10); } | |
926 static int l15( int x) { return opp_u_field(x, 15, 15); } | |
927 static int l910( int x) { return opp_u_field(x, 10, 9); } | |
928 static int lev( int x) { return opp_u_field(x, 26, 20); } | |
929 static int li( int x) { return opp_s_field(x, 29, 6); } | |
930 static int lk( int x) { return opp_u_field(x, 31, 31); } | |
931 static int mb2125( int x) { return opp_u_field(x, 25, 21); } | |
932 static int me2630( int x) { return opp_u_field(x, 30, 26); } | |
933 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); } | |
934 static int me2126( int x) { return mb2126(x); } | |
935 static int nb( int x) { return opp_u_field(x, 20, 16); } | |
936 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes | |
937 static int oe( int x) { return opp_u_field(x, 21, 21); } | |
938 static int ra( Register r) { return ra(r->encoding()); } | |
939 static int ra( int x) { return opp_u_field(x, 15, 11); } | |
940 static int rb( Register r) { return rb(r->encoding()); } | |
941 static int rb( int x) { return opp_u_field(x, 20, 16); } | |
942 static int rc( int x) { return opp_u_field(x, 31, 31); } | |
943 static int rs( Register r) { return rs(r->encoding()); } | |
944 static int rs( int x) { return opp_u_field(x, 10, 6); } | |
945 // we don't want to use R0 in memory accesses, because it has value `0' then | |
946 static int ra0mem( Register r) { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); } | |
947 static int ra0mem( int x) { assert(x != 0, "cannot use register 0 in memory access"); return ra(x); } | |
948 | |
949 // register r is target | |
950 static int rt( Register r) { return rs(r); } | |
951 static int rt( int x) { return rs(x); } | |
952 static int rta( Register r) { return ra(r); } | |
953 static int rta0mem( Register r) { rta(r); return ra0mem(r); } | |
954 | |
955 static int sh1620( int x) { return opp_u_field(x, 20, 16); } | |
956 static int sh30( int x) { return opp_u_field(x, 30, 30); } | |
957 static int sh162030( int x) { return sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); } | |
958 static int si( int x) { return opp_s_field(x, 31, 16); } | |
959 static int spr( int x) { return opp_u_field(x, 20, 11); } | |
960 static int sr( int x) { return opp_u_field(x, 15, 12); } | |
961 static int tbr( int x) { return opp_u_field(x, 20, 11); } | |
962 static int th( int x) { return opp_u_field(x, 10, 7); } | |
963 static int thct( int x) { assert((x&8)==0, "must be valid cache specification"); return th(x); } | |
964 static int thds( int x) { assert((x&8)==8, "must be valid stream specification"); return th(x); } | |
965 static int to( int x) { return opp_u_field(x, 10, 6); } | |
966 static int u( int x) { return opp_u_field(x, 19, 16); } | |
967 static int ui( int x) { return opp_u_field(x, 31, 16); } | |
968 | |
969 // support vector instructions for >= Power6 | |
970 static int vra( int x) { return opp_u_field(x, 15, 11); } | |
971 static int vrb( int x) { return opp_u_field(x, 20, 16); } | |
972 static int vrc( int x) { return opp_u_field(x, 25, 21); } | |
973 static int vrs( int x) { return opp_u_field(x, 10, 6); } | |
974 static int vrt( int x) { return opp_u_field(x, 10, 6); } | |
975 | |
976 static int vra( VectorRegister r) { return vra(r->encoding());} | |
977 static int vrb( VectorRegister r) { return vrb(r->encoding());} | |
978 static int vrc( VectorRegister r) { return vrc(r->encoding());} | |
979 static int vrs( VectorRegister r) { return vrs(r->encoding());} | |
980 static int vrt( VectorRegister r) { return vrt(r->encoding());} | |
981 | |
982 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions | |
983 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions | |
984 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction | |
985 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions | |
986 | |
987 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes | |
988 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes | |
989 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes | |
990 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes | |
991 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes | |
992 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes | |
993 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes | |
994 | |
995 protected: | |
996 // Compute relative address for branch. | |
997 static intptr_t disp(intptr_t x, intptr_t off) { | |
998 int xx = x - off; | |
999 xx = xx >> 2; | |
1000 return xx; | |
1001 } | |
1002 | |
1003 public: | |
1004 // signed immediate, in low bits, nbits long | |
1005 static int simm(int x, int nbits) { | |
1006 assert_signed_range(x, nbits); | |
1007 return x & ((1 << nbits) - 1); | |
1008 } | |
1009 | |
1010 // unsigned immediate, in low bits, nbits long | |
1011 static int uimm(int x, int nbits) { | |
1012 assert_unsigned_const(x, nbits); | |
1013 return x & ((1 << nbits) - 1); | |
1014 } | |
1015 | |
1016 static void set_imm(int* instr, short s) { | |
1017 short* p = ((short *)instr) + 1; | |
1018 *p = s; | |
1019 } | |
1020 | |
1021 static int get_imm(address a, int instruction_number) { | |
1022 short imm; | |
1023 short *p =((short *)a)+2*instruction_number+1; | |
1024 imm = *p; | |
1025 return (int)imm; | |
1026 } | |
1027 | |
1028 static inline int hi16_signed( int x) { return (int)(int16_t)(x >> 16); } | |
1029 static inline int lo16_unsigned(int x) { return x & 0xffff; } | |
1030 | |
1031 protected: | |
1032 | |
1033 // Extract the top 32 bits in a 64 bit word. | |
1034 static int32_t hi32(int64_t x) { | |
1035 int32_t r = int32_t((uint64_t)x >> 32); | |
1036 return r; | |
1037 } | |
1038 | |
1039 public: | |
1040 | |
1041 static inline unsigned int align_addr(unsigned int addr, unsigned int a) { | |
1042 return ((addr + (a - 1)) & ~(a - 1)); | |
1043 } | |
1044 | |
1045 static inline bool is_aligned(unsigned int addr, unsigned int a) { | |
1046 return (0 == addr % a); | |
1047 } | |
1048 | |
1049 void flush() { | |
1050 AbstractAssembler::flush(); | |
1051 } | |
1052 | |
1053 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32 | |
1054 inline void emit_data(int); | |
1055 inline void emit_data(int, RelocationHolder const&); | |
1056 inline void emit_data(int, relocInfo::relocType rtype); | |
1057 | |
1058 // Emit an address. | |
1059 inline address emit_addr(const address addr = NULL); | |
1060 | |
1061 // Emit a function descriptor with the specified entry point, TOC, | |
1062 // and ENV. If the entry point is NULL, the descriptor will point | |
1063 // just past the descriptor. | |
1064 // Use values from friend functions as defaults. | |
1065 inline address emit_fd(address entry = NULL, | |
1066 address toc = (address) FunctionDescriptor::friend_toc, | |
1067 address env = (address) FunctionDescriptor::friend_env); | |
1068 | |
1069 ///////////////////////////////////////////////////////////////////////////////////// | |
1070 // PPC instructions | |
1071 ///////////////////////////////////////////////////////////////////////////////////// | |
1072 | |
1073 // Memory instructions use r0 as hard coded 0, e.g. to simulate loading | |
1074 // immediates. The normal instruction encoders enforce that r0 is not | |
1075 // passed to them. Use either extended mnemonics encoders or the special ra0 | |
1076 // versions. | |
1077 | |
1078 // Issue an illegal instruction. | |
1079 inline void illtrap(); | |
1080 static inline bool is_illtrap(int x); | |
1081 | |
1082 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions | |
1083 inline void addi( Register d, Register a, int si16); | |
1084 inline void addis(Register d, Register a, int si16); | |
1085 private: | |
1086 inline void addi_r0ok( Register d, Register a, int si16); | |
1087 inline void addis_r0ok(Register d, Register a, int si16); | |
1088 public: | |
1089 inline void addic_( Register d, Register a, int si16); | |
1090 inline void subfic( Register d, Register a, int si16); | |
1091 inline void add( Register d, Register a, Register b); | |
1092 inline void add_( Register d, Register a, Register b); | |
1093 inline void subf( Register d, Register a, Register b); | |
1094 inline void sub( Register d, Register a, Register b); | |
1095 inline void subf_( Register d, Register a, Register b); | |
1096 inline void addc( Register d, Register a, Register b); | |
1097 inline void addc_( Register d, Register a, Register b); | |
1098 inline void subfc( Register d, Register a, Register b); | |
1099 inline void subfc_( Register d, Register a, Register b); | |
1100 inline void adde( Register d, Register a, Register b); | |
1101 inline void adde_( Register d, Register a, Register b); | |
1102 inline void subfe( Register d, Register a, Register b); | |
1103 inline void subfe_( Register d, Register a, Register b); | |
1104 inline void neg( Register d, Register a); | |
1105 inline void neg_( Register d, Register a); | |
1106 inline void mulli( Register d, Register a, int si16); | |
1107 inline void mulld( Register d, Register a, Register b); | |
1108 inline void mulld_( Register d, Register a, Register b); | |
1109 inline void mullw( Register d, Register a, Register b); | |
1110 inline void mullw_( Register d, Register a, Register b); | |
1111 inline void mulhw( Register d, Register a, Register b); | |
1112 inline void mulhw_( Register d, Register a, Register b); | |
1113 inline void mulhd( Register d, Register a, Register b); | |
1114 inline void mulhd_( Register d, Register a, Register b); | |
1115 inline void mulhdu( Register d, Register a, Register b); | |
1116 inline void mulhdu_(Register d, Register a, Register b); | |
1117 inline void divd( Register d, Register a, Register b); | |
1118 inline void divd_( Register d, Register a, Register b); | |
1119 inline void divw( Register d, Register a, Register b); | |
1120 inline void divw_( Register d, Register a, Register b); | |
1121 | |
1122 // extended mnemonics | |
1123 inline void li( Register d, int si16); | |
1124 inline void lis( Register d, int si16); | |
1125 inline void addir(Register d, int si16, Register a); | |
1126 | |
1127 static bool is_addi(int x) { | |
1128 return ADDI_OPCODE == (x & ADDI_OPCODE_MASK); | |
1129 } | |
1130 static bool is_addis(int x) { | |
1131 return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK); | |
1132 } | |
1133 static bool is_bxx(int x) { | |
1134 return BXX_OPCODE == (x & BXX_OPCODE_MASK); | |
1135 } | |
1136 static bool is_b(int x) { | |
1137 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0; | |
1138 } | |
1139 static bool is_bl(int x) { | |
1140 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1; | |
1141 } | |
1142 static bool is_bcxx(int x) { | |
1143 return BCXX_OPCODE == (x & BCXX_OPCODE_MASK); | |
1144 } | |
1145 static bool is_bxx_or_bcxx(int x) { | |
1146 return is_bxx(x) || is_bcxx(x); | |
1147 } | |
1148 static bool is_bctrl(int x) { | |
1149 return x == 0x4e800421; | |
1150 } | |
1151 static bool is_bctr(int x) { | |
1152 return x == 0x4e800420; | |
1153 } | |
1154 static bool is_bclr(int x) { | |
1155 return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK); | |
1156 } | |
1157 static bool is_li(int x) { | |
1158 return is_addi(x) && inv_ra_field(x)==0; | |
1159 } | |
1160 static bool is_lis(int x) { | |
1161 return is_addis(x) && inv_ra_field(x)==0; | |
1162 } | |
1163 static bool is_mtctr(int x) { | |
1164 return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK); | |
1165 } | |
1166 static bool is_ld(int x) { | |
1167 return LD_OPCODE == (x & LD_OPCODE_MASK); | |
1168 } | |
1169 static bool is_std(int x) { | |
1170 return STD_OPCODE == (x & STD_OPCODE_MASK); | |
1171 } | |
1172 static bool is_stdu(int x) { | |
1173 return STDU_OPCODE == (x & STDU_OPCODE_MASK); | |
1174 } | |
1175 static bool is_stdx(int x) { | |
1176 return STDX_OPCODE == (x & STDX_OPCODE_MASK); | |
1177 } | |
1178 static bool is_stdux(int x) { | |
1179 return STDUX_OPCODE == (x & STDUX_OPCODE_MASK); | |
1180 } | |
1181 static bool is_stwx(int x) { | |
1182 return STWX_OPCODE == (x & STWX_OPCODE_MASK); | |
1183 } | |
1184 static bool is_stwux(int x) { | |
1185 return STWUX_OPCODE == (x & STWUX_OPCODE_MASK); | |
1186 } | |
1187 static bool is_stw(int x) { | |
1188 return STW_OPCODE == (x & STW_OPCODE_MASK); | |
1189 } | |
1190 static bool is_stwu(int x) { | |
1191 return STWU_OPCODE == (x & STWU_OPCODE_MASK); | |
1192 } | |
1193 static bool is_ori(int x) { | |
1194 return ORI_OPCODE == (x & ORI_OPCODE_MASK); | |
1195 }; | |
1196 static bool is_oris(int x) { | |
1197 return ORIS_OPCODE == (x & ORIS_OPCODE_MASK); | |
1198 }; | |
1199 static bool is_rldicr(int x) { | |
1200 return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK)); | |
1201 }; | |
1202 static bool is_nop(int x) { | |
1203 return x == 0x60000000; | |
1204 } | |
1205 // endgroup opcode for Power6 | |
1206 static bool is_endgroup(int x) { | |
1207 return is_ori(x) && inv_ra_field(x)==1 && inv_rs_field(x)==1 && inv_d1_field(x)==0; | |
1208 } | |
1209 | |
1210 | |
1211 private: | |
1212 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions | |
1213 inline void cmpi( ConditionRegister bf, int l, Register a, int si16); | |
1214 inline void cmp( ConditionRegister bf, int l, Register a, Register b); | |
1215 inline void cmpli(ConditionRegister bf, int l, Register a, int ui16); | |
1216 inline void cmpl( ConditionRegister bf, int l, Register a, Register b); | |
1217 | |
1218 public: | |
1219 // extended mnemonics of Compare Instructions | |
1220 inline void cmpwi( ConditionRegister crx, Register a, int si16); | |
1221 inline void cmpdi( ConditionRegister crx, Register a, int si16); | |
1222 inline void cmpw( ConditionRegister crx, Register a, Register b); | |
1223 inline void cmpd( ConditionRegister crx, Register a, Register b); | |
1224 inline void cmplwi(ConditionRegister crx, Register a, int ui16); | |
1225 inline void cmpldi(ConditionRegister crx, Register a, int ui16); | |
1226 inline void cmplw( ConditionRegister crx, Register a, Register b); | |
1227 inline void cmpld( ConditionRegister crx, Register a, Register b); | |
1228 | |
1229 inline void isel( Register d, Register a, Register b, int bc); | |
1230 | |
1231 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions | |
1232 void andi( Register a, Register s, int ui16); // optimized version | |
1233 inline void andi_( Register a, Register s, int ui16); | |
1234 inline void andis_( Register a, Register s, int ui16); | |
1235 inline void ori( Register a, Register s, int ui16); | |
1236 inline void oris( Register a, Register s, int ui16); | |
1237 inline void xori( Register a, Register s, int ui16); | |
1238 inline void xoris( Register a, Register s, int ui16); | |
1239 inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword | |
1240 inline void and_( Register a, Register s, Register b); | |
1241 // Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a | |
1242 // SMT-priority change instruction (see SMT instructions below). | |
1243 inline void or_unchecked(Register a, Register s, Register b); | |
1244 inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword | |
1245 inline void or_( Register a, Register s, Register b); | |
1246 inline void xorr( Register a, Register s, Register b); // suffixed by 'r' as 'xor' is C++ keyword | |
1247 inline void xor_( Register a, Register s, Register b); | |
1248 inline void nand( Register a, Register s, Register b); | |
1249 inline void nand_( Register a, Register s, Register b); | |
1250 inline void nor( Register a, Register s, Register b); | |
1251 inline void nor_( Register a, Register s, Register b); | |
1252 inline void andc( Register a, Register s, Register b); | |
1253 inline void andc_( Register a, Register s, Register b); | |
1254 inline void orc( Register a, Register s, Register b); | |
1255 inline void orc_( Register a, Register s, Register b); | |
1256 inline void extsb( Register a, Register s); | |
1257 inline void extsh( Register a, Register s); | |
1258 inline void extsw( Register a, Register s); | |
1259 | |
1260 // extended mnemonics | |
1261 inline void nop(); | |
1262 // NOP for FP and BR units (different versions to allow them to be in one group) | |
1263 inline void fpnop0(); | |
1264 inline void fpnop1(); | |
1265 inline void brnop0(); | |
1266 inline void brnop1(); | |
1267 inline void brnop2(); | |
1268 | |
1269 inline void mr( Register d, Register s); | |
1270 inline void ori_opt( Register d, int ui16); | |
1271 inline void oris_opt(Register d, int ui16); | |
1272 | |
1273 // endgroup opcode for Power6 | |
1274 inline void endgroup(); | |
1275 | |
1276 // count instructions | |
1277 inline void cntlzw( Register a, Register s); | |
1278 inline void cntlzw_( Register a, Register s); | |
1279 inline void cntlzd( Register a, Register s); | |
1280 inline void cntlzd_( Register a, Register s); | |
1281 | |
1282 // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions | |
1283 inline void sld( Register a, Register s, Register b); | |
1284 inline void sld_( Register a, Register s, Register b); | |
1285 inline void slw( Register a, Register s, Register b); | |
1286 inline void slw_( Register a, Register s, Register b); | |
1287 inline void srd( Register a, Register s, Register b); | |
1288 inline void srd_( Register a, Register s, Register b); | |
1289 inline void srw( Register a, Register s, Register b); | |
1290 inline void srw_( Register a, Register s, Register b); | |
1291 inline void srad( Register a, Register s, Register b); | |
1292 inline void srad_( Register a, Register s, Register b); | |
1293 inline void sraw( Register a, Register s, Register b); | |
1294 inline void sraw_( Register a, Register s, Register b); | |
1295 inline void sradi( Register a, Register s, int sh6); | |
1296 inline void sradi_( Register a, Register s, int sh6); | |
1297 inline void srawi( Register a, Register s, int sh5); | |
1298 inline void srawi_( Register a, Register s, int sh5); | |
1299 | |
1300 // extended mnemonics for Shift Instructions | |
1301 inline void sldi( Register a, Register s, int sh6); | |
1302 inline void sldi_( Register a, Register s, int sh6); | |
1303 inline void slwi( Register a, Register s, int sh5); | |
1304 inline void slwi_( Register a, Register s, int sh5); | |
1305 inline void srdi( Register a, Register s, int sh6); | |
1306 inline void srdi_( Register a, Register s, int sh6); | |
1307 inline void srwi( Register a, Register s, int sh5); | |
1308 inline void srwi_( Register a, Register s, int sh5); | |
1309 | |
1310 inline void clrrdi( Register a, Register s, int ui6); | |
1311 inline void clrrdi_( Register a, Register s, int ui6); | |
1312 inline void clrldi( Register a, Register s, int ui6); | |
1313 inline void clrldi_( Register a, Register s, int ui6); | |
1314 inline void clrlsldi(Register a, Register s, int clrl6, int shl6); | |
1315 inline void clrlsldi_(Register a, Register s, int clrl6, int shl6); | |
1316 inline void extrdi( Register a, Register s, int n, int b); | |
1317 // testbit with condition register | |
1318 inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6); | |
1319 | |
1320 // rotate instructions | |
1321 inline void rotldi( Register a, Register s, int n); | |
1322 inline void rotrdi( Register a, Register s, int n); | |
1323 inline void rotlwi( Register a, Register s, int n); | |
1324 inline void rotrwi( Register a, Register s, int n); | |
1325 | |
1326 // Rotate Instructions | |
1327 inline void rldic( Register a, Register s, int sh6, int mb6); | |
1328 inline void rldic_( Register a, Register s, int sh6, int mb6); | |
1329 inline void rldicr( Register a, Register s, int sh6, int mb6); | |
1330 inline void rldicr_( Register a, Register s, int sh6, int mb6); | |
1331 inline void rldicl( Register a, Register s, int sh6, int mb6); | |
1332 inline void rldicl_( Register a, Register s, int sh6, int mb6); | |
1333 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5); | |
1334 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5); | |
1335 inline void rldimi( Register a, Register s, int sh6, int mb6); | |
1336 inline void rldimi_( Register a, Register s, int sh6, int mb6); | |
1337 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5); | |
1338 inline void insrdi( Register a, Register s, int n, int b); | |
1339 inline void insrwi( Register a, Register s, int n, int b); | |
1340 | |
1341 // PPC 1, section 3.3.2 Fixed-Point Load Instructions | |
1342 // 4 bytes | |
1343 inline void lwzx( Register d, Register s1, Register s2); | |
1344 inline void lwz( Register d, int si16, Register s1); | |
1345 inline void lwzu( Register d, int si16, Register s1); | |
1346 | |
1347 // 4 bytes | |
1348 inline void lwax( Register d, Register s1, Register s2); | |
1349 inline void lwa( Register d, int si16, Register s1); | |
1350 | |
1351 // 2 bytes | |
1352 inline void lhzx( Register d, Register s1, Register s2); | |
1353 inline void lhz( Register d, int si16, Register s1); | |
1354 inline void lhzu( Register d, int si16, Register s1); | |
1355 | |
1356 // 2 bytes | |
1357 inline void lhax( Register d, Register s1, Register s2); | |
1358 inline void lha( Register d, int si16, Register s1); | |
1359 inline void lhau( Register d, int si16, Register s1); | |
1360 | |
1361 // 1 byte | |
1362 inline void lbzx( Register d, Register s1, Register s2); | |
1363 inline void lbz( Register d, int si16, Register s1); | |
1364 inline void lbzu( Register d, int si16, Register s1); | |
1365 | |
1366 // 8 bytes | |
1367 inline void ldx( Register d, Register s1, Register s2); | |
1368 inline void ld( Register d, int si16, Register s1); | |
1369 inline void ldu( Register d, int si16, Register s1); | |
1370 | |
1371 // PPC 1, section 3.3.3 Fixed-Point Store Instructions | |
1372 inline void stwx( Register d, Register s1, Register s2); | |
1373 inline void stw( Register d, int si16, Register s1); | |
1374 inline void stwu( Register d, int si16, Register s1); | |
1375 | |
1376 inline void sthx( Register d, Register s1, Register s2); | |
1377 inline void sth( Register d, int si16, Register s1); | |
1378 inline void sthu( Register d, int si16, Register s1); | |
1379 | |
1380 inline void stbx( Register d, Register s1, Register s2); | |
1381 inline void stb( Register d, int si16, Register s1); | |
1382 inline void stbu( Register d, int si16, Register s1); | |
1383 | |
1384 inline void stdx( Register d, Register s1, Register s2); | |
1385 inline void std( Register d, int si16, Register s1); | |
1386 inline void stdu( Register d, int si16, Register s1); | |
1387 inline void stdux(Register s, Register a, Register b); | |
1388 | |
1389 // PPC 1, section 3.3.13 Move To/From System Register Instructions | |
1390 inline void mtlr( Register s1); | |
1391 inline void mflr( Register d); | |
1392 inline void mtctr(Register s1); | |
1393 inline void mfctr(Register d); | |
1394 inline void mtcrf(int fxm, Register s); | |
1395 inline void mfcr( Register d); | |
1396 inline void mcrf( ConditionRegister crd, ConditionRegister cra); | |
1397 inline void mtcr( Register s); | |
1398 | |
1399 // PPC 1, section 2.4.1 Branch Instructions | |
1400 inline void b( address a, relocInfo::relocType rt = relocInfo::none); | |
1401 inline void b( Label& L); | |
1402 inline void bl( address a, relocInfo::relocType rt = relocInfo::none); | |
1403 inline void bl( Label& L); | |
1404 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none); | |
1405 inline void bc( int boint, int biint, Label& L); | |
1406 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none); | |
1407 inline void bcl(int boint, int biint, Label& L); | |
1408 | |
1409 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none); | |
1410 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none); | |
1411 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame, | |
1412 relocInfo::relocType rt = relocInfo::none); | |
1413 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn, | |
1414 relocInfo::relocType rt = relocInfo::none); | |
1415 | |
1416 // helper function for b, bcxx | |
1417 inline bool is_within_range_of_b(address a, address pc); | |
1418 inline bool is_within_range_of_bcxx(address a, address pc); | |
1419 | |
1420 // get the destination of a bxx branch (b, bl, ba, bla) | |
1421 static inline address bxx_destination(address baddr); | |
1422 static inline address bxx_destination(int instr, address pc); | |
1423 static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos); | |
1424 | |
1425 // extended mnemonics for branch instructions | |
1426 inline void blt(ConditionRegister crx, Label& L); | |
1427 inline void bgt(ConditionRegister crx, Label& L); | |
1428 inline void beq(ConditionRegister crx, Label& L); | |
1429 inline void bso(ConditionRegister crx, Label& L); | |
1430 inline void bge(ConditionRegister crx, Label& L); | |
1431 inline void ble(ConditionRegister crx, Label& L); | |
1432 inline void bne(ConditionRegister crx, Label& L); | |
1433 inline void bns(ConditionRegister crx, Label& L); | |
1434 | |
1435 // Branch instructions with static prediction hints. | |
1436 inline void blt_predict_taken( ConditionRegister crx, Label& L); | |
1437 inline void bgt_predict_taken( ConditionRegister crx, Label& L); | |
1438 inline void beq_predict_taken( ConditionRegister crx, Label& L); | |
1439 inline void bso_predict_taken( ConditionRegister crx, Label& L); | |
1440 inline void bge_predict_taken( ConditionRegister crx, Label& L); | |
1441 inline void ble_predict_taken( ConditionRegister crx, Label& L); | |
1442 inline void bne_predict_taken( ConditionRegister crx, Label& L); | |
1443 inline void bns_predict_taken( ConditionRegister crx, Label& L); | |
1444 inline void blt_predict_not_taken(ConditionRegister crx, Label& L); | |
1445 inline void bgt_predict_not_taken(ConditionRegister crx, Label& L); | |
1446 inline void beq_predict_not_taken(ConditionRegister crx, Label& L); | |
1447 inline void bso_predict_not_taken(ConditionRegister crx, Label& L); | |
1448 inline void bge_predict_not_taken(ConditionRegister crx, Label& L); | |
1449 inline void ble_predict_not_taken(ConditionRegister crx, Label& L); | |
1450 inline void bne_predict_not_taken(ConditionRegister crx, Label& L); | |
1451 inline void bns_predict_not_taken(ConditionRegister crx, Label& L); | |
1452 | |
1453 // for use in conjunction with testbitdi: | |
1454 inline void btrue( ConditionRegister crx, Label& L); | |
1455 inline void bfalse(ConditionRegister crx, Label& L); | |
1456 | |
1457 inline void bltl(ConditionRegister crx, Label& L); | |
1458 inline void bgtl(ConditionRegister crx, Label& L); | |
1459 inline void beql(ConditionRegister crx, Label& L); | |
1460 inline void bsol(ConditionRegister crx, Label& L); | |
1461 inline void bgel(ConditionRegister crx, Label& L); | |
1462 inline void blel(ConditionRegister crx, Label& L); | |
1463 inline void bnel(ConditionRegister crx, Label& L); | |
1464 inline void bnsl(ConditionRegister crx, Label& L); | |
1465 | |
1466 // extended mnemonics for Branch Instructions via LR | |
1467 // We use `blr' for returns. | |
1468 inline void blr(relocInfo::relocType rt = relocInfo::none); | |
1469 | |
1470 // extended mnemonics for Branch Instructions with CTR | |
1471 // bdnz means `decrement CTR and jump to L if CTR is not zero' | |
1472 inline void bdnz(Label& L); | |
1473 // Decrement and branch if result is zero. | |
1474 inline void bdz(Label& L); | |
1475 // we use `bctr[l]' for jumps/calls in function descriptor glue | |
1476 // code, e.g. calls to runtime functions | |
1477 inline void bctr( relocInfo::relocType rt = relocInfo::none); | |
1478 inline void bctrl(relocInfo::relocType rt = relocInfo::none); | |
1479 // conditional jumps/branches via CTR | |
1480 inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); | |
1481 inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); | |
1482 inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); | |
1483 inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); | |
1484 | |
1485 // condition register logic instructions | |
1486 inline void crand( int d, int s1, int s2); | |
1487 inline void crnand(int d, int s1, int s2); | |
1488 inline void cror( int d, int s1, int s2); | |
1489 inline void crxor( int d, int s1, int s2); | |
1490 inline void crnor( int d, int s1, int s2); | |
1491 inline void creqv( int d, int s1, int s2); | |
1492 inline void crandc(int d, int s1, int s2); | |
1493 inline void crorc( int d, int s1, int s2); | |
1494 | |
1495 // icache and dcache related instructions | |
1496 inline void icbi( Register s1, Register s2); | |
1497 //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only. | |
1498 inline void dcbz( Register s1, Register s2); | |
1499 inline void dcbst( Register s1, Register s2); | |
1500 inline void dcbf( Register s1, Register s2); | |
1501 | |
1502 enum ct_cache_specification { | |
1503 ct_primary_cache = 0, | |
1504 ct_secondary_cache = 2 | |
1505 }; | |
1506 // dcache read hint | |
1507 inline void dcbt( Register s1, Register s2); | |
1508 inline void dcbtct( Register s1, Register s2, int ct); | |
1509 inline void dcbtds( Register s1, Register s2, int ds); | |
1510 // dcache write hint | |
1511 inline void dcbtst( Register s1, Register s2); | |
1512 inline void dcbtstct(Register s1, Register s2, int ct); | |
1513 | |
1514 // machine barrier instructions: | |
1515 // | |
1516 // - sync two-way memory barrier, aka fence | |
1517 // - lwsync orders Store|Store, | |
1518 // Load|Store, | |
1519 // Load|Load, | |
1520 // but not Store|Load | |
1521 // - eieio orders memory accesses for device memory (only) | |
1522 // - isync invalidates speculatively executed instructions | |
1523 // From the Power ISA 2.06 documentation: | |
1524 // "[...] an isync instruction prevents the execution of | |
1525 // instructions following the isync until instructions | |
1526 // preceding the isync have completed, [...]" | |
1527 // From IBM's AIX assembler reference: | |
1528 // "The isync [...] instructions causes the processor to | |
1529 // refetch any instructions that might have been fetched | |
1530 // prior to the isync instruction. The instruction isync | |
1531 // causes the processor to wait for all previous instructions | |
1532 // to complete. Then any instructions already fetched are | |
1533 // discarded and instruction processing continues in the | |
1534 // environment established by the previous instructions." | |
1535 // | |
1536 // semantic barrier instructions: | |
1537 // (as defined in orderAccess.hpp) | |
1538 // | |
1539 // - release orders Store|Store, (maps to lwsync) | |
1540 // Load|Store | |
1541 // - acquire orders Load|Store, (maps to lwsync) | |
1542 // Load|Load | |
1543 // - fence orders Store|Store, (maps to sync) | |
1544 // Load|Store, | |
1545 // Load|Load, | |
1546 // Store|Load | |
1547 // | |
1548 private: | |
1549 inline void sync(int l); | |
1550 public: | |
1551 inline void sync(); | |
1552 inline void lwsync(); | |
1553 inline void ptesync(); | |
1554 inline void eieio(); | |
1555 inline void isync(); | |
1556 | |
1557 inline void release(); | |
1558 inline void acquire(); | |
1559 inline void fence(); | |
1560 | |
1561 // atomics | |
1562 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0); | |
1563 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0); | |
1564 inline bool lxarx_hint_exclusive_access(); | |
1565 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false); | |
1566 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false); | |
1567 inline void stwcx_( Register s, Register a, Register b); | |
1568 inline void stdcx_( Register s, Register a, Register b); | |
1569 | |
1570 // Instructions for adjusting thread priority for simultaneous | |
1571 // multithreading (SMT) on Power5. | |
1572 private: | |
1573 inline void smt_prio_very_low(); | |
1574 inline void smt_prio_medium_high(); | |
1575 inline void smt_prio_high(); | |
1576 | |
1577 public: | |
1578 inline void smt_prio_low(); | |
1579 inline void smt_prio_medium_low(); | |
1580 inline void smt_prio_medium(); | |
1581 | |
1582 // trap instructions | |
1583 inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur) | |
1584 // NOT FOR DIRECT USE!! | |
1585 protected: | |
1586 inline void tdi_unchecked(int tobits, Register a, int si16); | |
1587 inline void twi_unchecked(int tobits, Register a, int si16); | |
1588 inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP | |
1589 inline void twi( int tobits, Register a, int si16); // asserts UseSIGTRAP | |
1590 inline void td( int tobits, Register a, Register b); // asserts UseSIGTRAP | |
1591 inline void tw( int tobits, Register a, Register b); // asserts UseSIGTRAP | |
1592 | |
1593 static bool is_tdi(int x, int tobits, int ra, int si16) { | |
1594 return (TDI_OPCODE == (x & TDI_OPCODE_MASK)) | |
1595 && (tobits == inv_to_field(x)) | |
1596 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) | |
1597 && (si16 == inv_si_field(x)); | |
1598 } | |
1599 | |
1600 static bool is_twi(int x, int tobits, int ra, int si16) { | |
1601 return (TWI_OPCODE == (x & TWI_OPCODE_MASK)) | |
1602 && (tobits == inv_to_field(x)) | |
1603 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) | |
1604 && (si16 == inv_si_field(x)); | |
1605 } | |
1606 | |
1607 static bool is_twi(int x, int tobits, int ra) { | |
1608 return (TWI_OPCODE == (x & TWI_OPCODE_MASK)) | |
1609 && (tobits == inv_to_field(x)) | |
1610 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)); | |
1611 } | |
1612 | |
1613 static bool is_td(int x, int tobits, int ra, int rb) { | |
1614 return (TD_OPCODE == (x & TD_OPCODE_MASK)) | |
1615 && (tobits == inv_to_field(x)) | |
1616 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) | |
1617 && (rb == -1/*any reg*/ || rb == inv_rb_field(x)); | |
1618 } | |
1619 | |
1620 static bool is_tw(int x, int tobits, int ra, int rb) { | |
1621 return (TW_OPCODE == (x & TW_OPCODE_MASK)) | |
1622 && (tobits == inv_to_field(x)) | |
1623 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) | |
1624 && (rb == -1/*any reg*/ || rb == inv_rb_field(x)); | |
1625 } | |
1626 | |
1627 public: | |
1628 // PPC floating point instructions | |
1629 // PPC 1, section 4.6.2 Floating-Point Load Instructions | |
1630 inline void lfs( FloatRegister d, int si16, Register a); | |
1631 inline void lfsu( FloatRegister d, int si16, Register a); | |
1632 inline void lfsx( FloatRegister d, Register a, Register b); | |
1633 inline void lfd( FloatRegister d, int si16, Register a); | |
1634 inline void lfdu( FloatRegister d, int si16, Register a); | |
1635 inline void lfdx( FloatRegister d, Register a, Register b); | |
1636 | |
1637 // PPC 1, section 4.6.3 Floating-Point Store Instructions | |
1638 inline void stfs( FloatRegister s, int si16, Register a); | |
1639 inline void stfsu( FloatRegister s, int si16, Register a); | |
1640 inline void stfsx( FloatRegister s, Register a, Register b); | |
1641 inline void stfd( FloatRegister s, int si16, Register a); | |
1642 inline void stfdu( FloatRegister s, int si16, Register a); | |
1643 inline void stfdx( FloatRegister s, Register a, Register b); | |
1644 | |
1645 // PPC 1, section 4.6.4 Floating-Point Move Instructions | |
1646 inline void fmr( FloatRegister d, FloatRegister b); | |
1647 inline void fmr_( FloatRegister d, FloatRegister b); | |
1648 | |
1649 // inline void mffgpr( FloatRegister d, Register b); | |
1650 // inline void mftgpr( Register d, FloatRegister b); | |
1651 inline void cmpb( Register a, Register s, Register b); | |
1652 inline void popcntb(Register a, Register s); | |
1653 inline void popcntw(Register a, Register s); | |
1654 inline void popcntd(Register a, Register s); | |
1655 | |
1656 inline void fneg( FloatRegister d, FloatRegister b); | |
1657 inline void fneg_( FloatRegister d, FloatRegister b); | |
1658 inline void fabs( FloatRegister d, FloatRegister b); | |
1659 inline void fabs_( FloatRegister d, FloatRegister b); | |
1660 inline void fnabs( FloatRegister d, FloatRegister b); | |
1661 inline void fnabs_(FloatRegister d, FloatRegister b); | |
1662 | |
1663 // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions | |
1664 inline void fadd( FloatRegister d, FloatRegister a, FloatRegister b); | |
1665 inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b); | |
1666 inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b); | |
1667 inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b); | |
1668 inline void fsub( FloatRegister d, FloatRegister a, FloatRegister b); | |
1669 inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b); | |
1670 inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b); | |
1671 inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b); | |
1672 inline void fmul( FloatRegister d, FloatRegister a, FloatRegister c); | |
1673 inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c); | |
1674 inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c); | |
1675 inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c); | |
1676 inline void fdiv( FloatRegister d, FloatRegister a, FloatRegister b); | |
1677 inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b); | |
1678 inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b); | |
1679 inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b); | |
1680 | |
1681 // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions | |
1682 inline void frsp( FloatRegister d, FloatRegister b); | |
1683 inline void fctid( FloatRegister d, FloatRegister b); | |
1684 inline void fctidz(FloatRegister d, FloatRegister b); | |
1685 inline void fctiw( FloatRegister d, FloatRegister b); | |
1686 inline void fctiwz(FloatRegister d, FloatRegister b); | |
1687 inline void fcfid( FloatRegister d, FloatRegister b); | |
1688 inline void fcfids(FloatRegister d, FloatRegister b); | |
1689 | |
1690 // PPC 1, section 4.6.7 Floating-Point Compare Instructions | |
1691 inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b); | |
1692 | |
1693 inline void fsqrt( FloatRegister d, FloatRegister b); | |
1694 inline void fsqrts(FloatRegister d, FloatRegister b); | |
1695 | |
1696 // Vector instructions for >= Power6. | |
1697 inline void lvebx( VectorRegister d, Register s1, Register s2); | |
1698 inline void lvehx( VectorRegister d, Register s1, Register s2); | |
1699 inline void lvewx( VectorRegister d, Register s1, Register s2); | |
1700 inline void lvx( VectorRegister d, Register s1, Register s2); | |
1701 inline void lvxl( VectorRegister d, Register s1, Register s2); | |
1702 inline void stvebx( VectorRegister d, Register s1, Register s2); | |
1703 inline void stvehx( VectorRegister d, Register s1, Register s2); | |
1704 inline void stvewx( VectorRegister d, Register s1, Register s2); | |
1705 inline void stvx( VectorRegister d, Register s1, Register s2); | |
1706 inline void stvxl( VectorRegister d, Register s1, Register s2); | |
1707 inline void lvsl( VectorRegister d, Register s1, Register s2); | |
1708 inline void lvsr( VectorRegister d, Register s1, Register s2); | |
1709 inline void vpkpx( VectorRegister d, VectorRegister a, VectorRegister b); | |
1710 inline void vpkshss( VectorRegister d, VectorRegister a, VectorRegister b); | |
1711 inline void vpkswss( VectorRegister d, VectorRegister a, VectorRegister b); | |
1712 inline void vpkshus( VectorRegister d, VectorRegister a, VectorRegister b); | |
1713 inline void vpkswus( VectorRegister d, VectorRegister a, VectorRegister b); | |
1714 inline void vpkuhum( VectorRegister d, VectorRegister a, VectorRegister b); | |
1715 inline void vpkuwum( VectorRegister d, VectorRegister a, VectorRegister b); | |
1716 inline void vpkuhus( VectorRegister d, VectorRegister a, VectorRegister b); | |
1717 inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b); | |
1718 inline void vupkhpx( VectorRegister d, VectorRegister b); | |
1719 inline void vupkhsb( VectorRegister d, VectorRegister b); | |
1720 inline void vupkhsh( VectorRegister d, VectorRegister b); | |
1721 inline void vupklpx( VectorRegister d, VectorRegister b); | |
1722 inline void vupklsb( VectorRegister d, VectorRegister b); | |
1723 inline void vupklsh( VectorRegister d, VectorRegister b); | |
1724 inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b); | |
1725 inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1726 inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1727 inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b); | |
1728 inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1729 inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1730 inline void vsplt( VectorRegister d, int ui4, VectorRegister b); | |
1731 inline void vsplth( VectorRegister d, int ui3, VectorRegister b); | |
1732 inline void vspltw( VectorRegister d, int ui2, VectorRegister b); | |
1733 inline void vspltisb( VectorRegister d, int si5); | |
1734 inline void vspltish( VectorRegister d, int si5); | |
1735 inline void vspltisw( VectorRegister d, int si5); | |
1736 inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); | |
1737 inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); | |
1738 inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b); | |
1739 inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int si4); | |
1740 inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b); | |
1741 inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b); | |
1742 inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b); | |
1743 inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1744 inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b); | |
1745 inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b); | |
1746 inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b); | |
1747 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b); | |
1748 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b); | |
1749 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b); | |
1750 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b); | |
1751 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b); | |
1752 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b); | |
1753 inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1754 inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b); | |
1755 inline void vsubsbs( VectorRegister d, VectorRegister a, VectorRegister b); | |
1756 inline void vsubsws( VectorRegister d, VectorRegister a, VectorRegister b); | |
1757 inline void vsububm( VectorRegister d, VectorRegister a, VectorRegister b); | |
1758 inline void vsubuwm( VectorRegister d, VectorRegister a, VectorRegister b); | |
1759 inline void vsubuhm( VectorRegister d, VectorRegister a, VectorRegister b); | |
1760 inline void vsububs( VectorRegister d, VectorRegister a, VectorRegister b); | |
1761 inline void vsubuws( VectorRegister d, VectorRegister a, VectorRegister b); | |
1762 inline void vsubuhs( VectorRegister d, VectorRegister a, VectorRegister b); | |
1763 inline void vmulesb( VectorRegister d, VectorRegister a, VectorRegister b); | |
1764 inline void vmuleub( VectorRegister d, VectorRegister a, VectorRegister b); | |
1765 inline void vmulesh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1766 inline void vmuleuh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1767 inline void vmulosb( VectorRegister d, VectorRegister a, VectorRegister b); | |
1768 inline void vmuloub( VectorRegister d, VectorRegister a, VectorRegister b); | |
1769 inline void vmulosh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1770 inline void vmulouh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1771 inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); | |
1772 inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c); | |
1773 inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); | |
1774 inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); | |
1775 inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); | |
1776 inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); | |
1777 inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); | |
1778 inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); | |
1779 inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); | |
1780 inline void vsumsws( VectorRegister d, VectorRegister a, VectorRegister b); | |
1781 inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b); | |
1782 inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b); | |
1783 inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b); | |
1784 inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b); | |
1785 inline void vavgsb( VectorRegister d, VectorRegister a, VectorRegister b); | |
1786 inline void vavgsw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1787 inline void vavgsh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1788 inline void vavgub( VectorRegister d, VectorRegister a, VectorRegister b); | |
1789 inline void vavguw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1790 inline void vavguh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1791 inline void vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b); | |
1792 inline void vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1793 inline void vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1794 inline void vmaxub( VectorRegister d, VectorRegister a, VectorRegister b); | |
1795 inline void vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1796 inline void vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1797 inline void vminsb( VectorRegister d, VectorRegister a, VectorRegister b); | |
1798 inline void vminsw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1799 inline void vminsh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1800 inline void vminub( VectorRegister d, VectorRegister a, VectorRegister b); | |
1801 inline void vminuw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1802 inline void vminuh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1803 inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b); | |
1804 inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1805 inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1806 inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1807 inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b); | |
1808 inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1809 inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b); | |
1810 inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1811 inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1812 inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b); | |
1813 inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b); | |
1814 inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b); | |
1815 inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b); | |
1816 inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b); | |
1817 inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b); | |
1818 inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b); | |
1819 inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b); | |
1820 inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b); | |
1821 inline void vand( VectorRegister d, VectorRegister a, VectorRegister b); | |
1822 inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b); | |
1823 inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b); | |
1824 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b); | |
1825 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b); | |
1826 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b); | |
1827 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1828 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1829 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b); | |
1830 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1831 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1832 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b); | |
1833 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1834 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b); | |
1835 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b); | |
1836 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b); | |
1837 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b); | |
1838 // Vector Floating-Point not implemented yet | |
1839 inline void mtvscr( VectorRegister b); | |
1840 inline void mfvscr( VectorRegister d); | |
1841 | |
1842 // The following encoders use r0 as second operand. These instructions | |
1843 // read r0 as '0'. | |
1844 inline void lwzx( Register d, Register s2); | |
1845 inline void lwz( Register d, int si16); | |
1846 inline void lwax( Register d, Register s2); | |
1847 inline void lwa( Register d, int si16); | |
1848 inline void lhzx( Register d, Register s2); | |
1849 inline void lhz( Register d, int si16); | |
1850 inline void lhax( Register d, Register s2); | |
1851 inline void lha( Register d, int si16); | |
1852 inline void lbzx( Register d, Register s2); | |
1853 inline void lbz( Register d, int si16); | |
1854 inline void ldx( Register d, Register s2); | |
1855 inline void ld( Register d, int si16); | |
1856 inline void stwx( Register d, Register s2); | |
1857 inline void stw( Register d, int si16); | |
1858 inline void sthx( Register d, Register s2); | |
1859 inline void sth( Register d, int si16); | |
1860 inline void stbx( Register d, Register s2); | |
1861 inline void stb( Register d, int si16); | |
1862 inline void stdx( Register d, Register s2); | |
1863 inline void std( Register d, int si16); | |
1864 | |
1865 // PPC 2, section 3.2.1 Instruction Cache Instructions | |
1866 inline void icbi( Register s2); | |
1867 // PPC 2, section 3.2.2 Data Cache Instructions | |
1868 //inlinevoid dcba( Register s2); // Instruction for embedded processor only. | |
1869 inline void dcbz( Register s2); | |
1870 inline void dcbst( Register s2); | |
1871 inline void dcbf( Register s2); | |
1872 // dcache read hint | |
1873 inline void dcbt( Register s2); | |
1874 inline void dcbtct( Register s2, int ct); | |
1875 inline void dcbtds( Register s2, int ds); | |
1876 // dcache write hint | |
1877 inline void dcbtst( Register s2); | |
1878 inline void dcbtstct(Register s2, int ct); | |
1879 | |
1880 // Atomics: use ra0mem to disallow R0 as base. | |
1881 inline void lwarx_unchecked(Register d, Register b, int eh1); | |
1882 inline void ldarx_unchecked(Register d, Register b, int eh1); | |
1883 inline void lwarx( Register d, Register b, bool hint_exclusive_access); | |
1884 inline void ldarx( Register d, Register b, bool hint_exclusive_access); | |
1885 inline void stwcx_(Register s, Register b); | |
1886 inline void stdcx_(Register s, Register b); | |
1887 inline void lfs( FloatRegister d, int si16); | |
1888 inline void lfsx( FloatRegister d, Register b); | |
1889 inline void lfd( FloatRegister d, int si16); | |
1890 inline void lfdx( FloatRegister d, Register b); | |
1891 inline void stfs( FloatRegister s, int si16); | |
1892 inline void stfsx( FloatRegister s, Register b); | |
1893 inline void stfd( FloatRegister s, int si16); | |
1894 inline void stfdx( FloatRegister s, Register b); | |
1895 inline void lvebx( VectorRegister d, Register s2); | |
1896 inline void lvehx( VectorRegister d, Register s2); | |
1897 inline void lvewx( VectorRegister d, Register s2); | |
1898 inline void lvx( VectorRegister d, Register s2); | |
1899 inline void lvxl( VectorRegister d, Register s2); | |
1900 inline void stvebx(VectorRegister d, Register s2); | |
1901 inline void stvehx(VectorRegister d, Register s2); | |
1902 inline void stvewx(VectorRegister d, Register s2); | |
1903 inline void stvx( VectorRegister d, Register s2); | |
1904 inline void stvxl( VectorRegister d, Register s2); | |
1905 inline void lvsl( VectorRegister d, Register s2); | |
1906 inline void lvsr( VectorRegister d, Register s2); | |
1907 | |
1908 // RegisterOrConstant versions. | |
1909 // These emitters choose between the versions using two registers and | |
1910 // those with register and immediate, depending on the content of roc. | |
1911 // If the constant is not encodable as immediate, instructions to | |
1912 // load the constant are emitted beforehand. Store instructions need a | |
1913 // tmp reg if the constant is not encodable as immediate. | |
1914 // Size unpredictable. | |
1915 void ld( Register d, RegisterOrConstant roc, Register s1 = noreg); | |
1916 void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg); | |
1917 void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg); | |
1918 void lha( Register d, RegisterOrConstant roc, Register s1 = noreg); | |
1919 void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg); | |
1920 void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg); | |
1921 void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); | |
1922 void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); | |
1923 void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); | |
1924 void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); | |
1925 void add( Register d, RegisterOrConstant roc, Register s1); | |
1926 void subf(Register d, RegisterOrConstant roc, Register s1); | |
1927 void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1); | |
1928 | |
1929 | |
1930 // Emit several instructions to load a 64 bit constant. This issues a fixed | |
1931 // instruction pattern so that the constant can be patched later on. | |
1932 enum { | |
1933 load_const_size = 5 * BytesPerInstWord | |
1934 }; | |
1935 void load_const(Register d, long a, Register tmp = noreg); | |
1936 inline void load_const(Register d, void* a, Register tmp = noreg); | |
1937 inline void load_const(Register d, Label& L, Register tmp = noreg); | |
1938 inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg); | |
1939 | |
1940 // Load a 64 bit constant, optimized, not identifyable. | |
1941 // Tmp can be used to increase ILP. Set return_simm16_rest=true to get a | |
1942 // 16 bit immediate offset. This is useful if the offset can be encoded in | |
1943 // a succeeding instruction. | |
1944 int load_const_optimized(Register d, long a, Register tmp = noreg, bool return_simm16_rest = false); | |
1945 inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) { | |
1946 return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest); | |
1947 } | |
1948 | |
1949 // Creation | |
1950 Assembler(CodeBuffer* code) : AbstractAssembler(code) { | |
1951 #ifdef CHECK_DELAY | |
1952 delay_state = no_delay; | |
1953 #endif | |
1954 } | |
1955 | |
1956 // Testing | |
1957 #ifndef PRODUCT | |
1958 void test_asm(); | |
1959 #endif | |
1960 }; | |
1961 | |
1962 | |
1963 #endif // CPU_PPC_VM_ASSEMBLER_PPC_HPP |