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comparison src/cpu/sparc/vm/sparc.ad @ 17798:f040cf9fc9c0

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Merge
author kvn
date Wed, 19 Feb 2014 20:12:43 -0800
parents a9becfeecd1b 984401824c5e
children 752ba2e5f6d0
comparison
equal deleted inserted replaced
17797:2fcab8ba885a 17798:f040cf9fc9c0
3361 op_cost(0); 3361 op_cost(0);
3362 format %{ %} 3362 format %{ %}
3363 interface(CONST_INTER); 3363 interface(CONST_INTER);
3364 %} 3364 %}
3365 3365
3366 // Unsigned (positive) Integer Immediate: 13-bit 3366 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3367 operand immU13() %{ 3367 operand immU12() %{
3368 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3368 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3369 match(ConI); 3369 match(ConI);
3370 op_cost(0); 3370 op_cost(0);
3371 3371
3372 format %{ %} 3372 format %{ %}
3393 3393
3394 // Integer Immediate: 5-bit 3394 // Integer Immediate: 5-bit
3395 operand immI5() %{ 3395 operand immI5() %{
3396 predicate(Assembler::is_simm5(n->get_int())); 3396 predicate(Assembler::is_simm5(n->get_int()));
3397 match(ConI); 3397 match(ConI);
3398 op_cost(0);
3399 format %{ %}
3400 interface(CONST_INTER);
3401 %}
3402
3403 // Int Immediate non-negative
3404 operand immU31()
3405 %{
3406 predicate(n->get_int() >= 0);
3407 match(ConI);
3408
3398 op_cost(0); 3409 op_cost(0);
3399 format %{ %} 3410 format %{ %}
3400 interface(CONST_INTER); 3411 interface(CONST_INTER);
3401 %} 3412 %}
3402 3413
5726 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ 5737 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5727 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5738 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5728 effect(TEMP dst, TEMP tmp); 5739 effect(TEMP dst, TEMP tmp);
5729 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5740 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5730 5741
5731 size((3+1)*4); // set may use two instructions.
5732 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" 5742 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5733 "SET $mask,$tmp\n\t" 5743 "SET $mask,$tmp\n\t"
5734 "AND $dst,$tmp,$dst" %} 5744 "AND $dst,$tmp,$dst" %}
5735 ins_encode %{ 5745 ins_encode %{
5736 Register Rdst = $dst$$Register; 5746 Register Rdst = $dst$$Register;
5848 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5858 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5849 %} 5859 %}
5850 ins_pipe(iload_mem); 5860 ins_pipe(iload_mem);
5851 %} 5861 %}
5852 5862
5853 // Load Integer with a 13-bit mask into a Long Register 5863 // Load Integer with a 12-bit mask into a Long Register
5854 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5864 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5855 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5865 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5856 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5866 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5857 5867
5858 size(2*4); 5868 size(2*4);
5859 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" 5869 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5860 "AND $dst,$mask,$dst" %} 5870 "AND $dst,$mask,$dst" %}
5861 ins_encode %{ 5871 ins_encode %{
5862 Register Rdst = $dst$$Register; 5872 Register Rdst = $dst$$Register;
5863 __ lduw($mem$$Address, Rdst); 5873 __ lduw($mem$$Address, Rdst);
5864 __ and3(Rdst, $mask$$constant, Rdst); 5874 __ and3(Rdst, $mask$$constant, Rdst);
5865 %} 5875 %}
5866 ins_pipe(iload_mem); 5876 ins_pipe(iload_mem);
5867 %} 5877 %}
5868 5878
5869 // Load Integer with a 32-bit mask into a Long Register 5879 // Load Integer with a 31-bit mask into a Long Register
5870 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5880 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5871 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5881 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5872 effect(TEMP dst, TEMP tmp); 5882 effect(TEMP dst, TEMP tmp);
5873 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5883 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5874 5884
5875 size((3+1)*4); // set may use two instructions. 5885 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5876 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5877 "SET $mask,$tmp\n\t" 5886 "SET $mask,$tmp\n\t"
5878 "AND $dst,$tmp,$dst" %} 5887 "AND $dst,$tmp,$dst" %}
5879 ins_encode %{ 5888 ins_encode %{
5880 Register Rdst = $dst$$Register; 5889 Register Rdst = $dst$$Register;
5881 Register Rtmp = $tmp$$Register; 5890 Register Rtmp = $tmp$$Register;
8968 opcode(Assembler::andcc_op3, Assembler::arith_op); 8977 opcode(Assembler::andcc_op3, Assembler::arith_op);
8969 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8978 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8970 ins_pipe(ialu_cconly_reg_reg); 8979 ins_pipe(ialu_cconly_reg_reg);
8971 %} 8980 %}
8972 8981
8973 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ 8982 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8974 match(Set icc (CmpU op1 op2)); 8983 match(Set icc (CmpU op1 op2));
8975 8984
8976 size(4); 8985 size(4);
8977 format %{ "CMP $op1,$op2\t! unsigned" %} 8986 format %{ "CMP $op1,$op2\t! unsigned" %}
8978 opcode(Assembler::subcc_op3, Assembler::arith_op); 8987 opcode(Assembler::subcc_op3, Assembler::arith_op);