Mercurial > hg > truffle
comparison src/cpu/sparc/vm/assembler_sparc.cpp @ 7204:f0c2369fda5a
8003250: SPARC: move MacroAssembler into separate file
Reviewed-by: jrose, kvn
author | twisti |
---|---|
date | Thu, 06 Dec 2012 09:57:41 -0800 |
parents | cd3d6a6b95d9 |
children | 291ffc492eb6 |
comparison
equal
deleted
inserted
replaced
7201:c5d414e98fd4 | 7204:f0c2369fda5a |
---|---|
22 * | 22 * |
23 */ | 23 */ |
24 | 24 |
25 #include "precompiled.hpp" | 25 #include "precompiled.hpp" |
26 #include "asm/assembler.hpp" | 26 #include "asm/assembler.hpp" |
27 #include "assembler_sparc.inline.hpp" | 27 #include "asm/assembler.inline.hpp" |
28 #include "compiler/disassembler.hpp" | |
29 #include "gc_interface/collectedHeap.inline.hpp" | |
30 #include "interpreter/interpreter.hpp" | |
31 #include "memory/cardTableModRefBS.hpp" | |
32 #include "memory/resourceArea.hpp" | |
33 #include "prims/methodHandles.hpp" | |
34 #include "runtime/biasedLocking.hpp" | |
35 #include "runtime/interfaceSupport.hpp" | |
36 #include "runtime/objectMonitor.hpp" | |
37 #include "runtime/os.hpp" | |
38 #include "runtime/sharedRuntime.hpp" | |
39 #include "runtime/stubRoutines.hpp" | |
40 #ifndef SERIALGC | |
41 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" | |
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
43 #include "gc_implementation/g1/heapRegion.hpp" | |
44 #endif | |
45 | |
46 #ifdef PRODUCT | |
47 #define BLOCK_COMMENT(str) /* nothing */ | |
48 #define STOP(error) stop(error) | |
49 #else | |
50 #define BLOCK_COMMENT(str) block_comment(str) | |
51 #define STOP(error) block_comment(error); stop(error) | |
52 #endif | |
53 | |
54 // Convert the raw encoding form into the form expected by the | |
55 // constructor for Address. | |
56 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { | |
57 assert(scale == 0, "not supported"); | |
58 RelocationHolder rspec; | |
59 if (disp_reloc != relocInfo::none) { | |
60 rspec = Relocation::spec_simple(disp_reloc); | |
61 } | |
62 | |
63 Register rindex = as_Register(index); | |
64 if (rindex != G0) { | |
65 Address madr(as_Register(base), rindex); | |
66 madr._rspec = rspec; | |
67 return madr; | |
68 } else { | |
69 Address madr(as_Register(base), disp); | |
70 madr._rspec = rspec; | |
71 return madr; | |
72 } | |
73 } | |
74 | |
75 Address Argument::address_in_frame() const { | |
76 // Warning: In LP64 mode disp will occupy more than 10 bits, but | |
77 // op codes such as ld or ldx, only access disp() to get | |
78 // their simm13 argument. | |
79 int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS; | |
80 if (is_in()) | |
81 return Address(FP, disp); // In argument. | |
82 else | |
83 return Address(SP, disp); // Out argument. | |
84 } | |
85 | |
86 static const char* argumentNames[][2] = { | |
87 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"}, | |
88 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"}, | |
89 {"A(n>9)","P(n>9)"} | |
90 }; | |
91 | |
92 const char* Argument::name() const { | |
93 int nofArgs = sizeof argumentNames / sizeof argumentNames[0]; | |
94 int num = number(); | |
95 if (num >= nofArgs) num = nofArgs - 1; | |
96 return argumentNames[num][is_in() ? 1 : 0]; | |
97 } | |
98 | |
99 void Assembler::print_instruction(int inst) { | |
100 const char* s; | |
101 switch (inv_op(inst)) { | |
102 default: s = "????"; break; | |
103 case call_op: s = "call"; break; | |
104 case branch_op: | |
105 switch (inv_op2(inst)) { | |
106 case fb_op2: s = "fb"; break; | |
107 case fbp_op2: s = "fbp"; break; | |
108 case br_op2: s = "br"; break; | |
109 case bp_op2: s = "bp"; break; | |
110 case cb_op2: s = "cb"; break; | |
111 case bpr_op2: { | |
112 if (is_cbcond(inst)) { | |
113 s = is_cxb(inst) ? "cxb" : "cwb"; | |
114 } else { | |
115 s = "bpr"; | |
116 } | |
117 break; | |
118 } | |
119 default: s = "????"; break; | |
120 } | |
121 } | |
122 ::tty->print("%s", s); | |
123 } | |
124 | |
125 | |
126 // Patch instruction inst at offset inst_pos to refer to dest_pos | |
127 // and return the resulting instruction. | |
128 // We should have pcs, not offsets, but since all is relative, it will work out | |
129 // OK. | |
130 int Assembler::patched_branch(int dest_pos, int inst, int inst_pos) { | |
131 | |
132 int m; // mask for displacement field | |
133 int v; // new value for displacement field | |
134 const int word_aligned_ones = -4; | |
135 switch (inv_op(inst)) { | |
136 default: ShouldNotReachHere(); | |
137 case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break; | |
138 case branch_op: | |
139 switch (inv_op2(inst)) { | |
140 case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; | |
141 case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; | |
142 case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; | |
143 case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; | |
144 case cb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; | |
145 case bpr_op2: { | |
146 if (is_cbcond(inst)) { | |
147 m = wdisp10(word_aligned_ones, 0); | |
148 v = wdisp10(dest_pos, inst_pos); | |
149 } else { | |
150 m = wdisp16(word_aligned_ones, 0); | |
151 v = wdisp16(dest_pos, inst_pos); | |
152 } | |
153 break; | |
154 } | |
155 default: ShouldNotReachHere(); | |
156 } | |
157 } | |
158 return inst & ~m | v; | |
159 } | |
160 | |
161 // Return the offset of the branch destionation of instruction inst | |
162 // at offset pos. | |
163 // Should have pcs, but since all is relative, it works out. | |
164 int Assembler::branch_destination(int inst, int pos) { | |
165 int r; | |
166 switch (inv_op(inst)) { | |
167 default: ShouldNotReachHere(); | |
168 case call_op: r = inv_wdisp(inst, pos, 30); break; | |
169 case branch_op: | |
170 switch (inv_op2(inst)) { | |
171 case fbp_op2: r = inv_wdisp( inst, pos, 19); break; | |
172 case bp_op2: r = inv_wdisp( inst, pos, 19); break; | |
173 case fb_op2: r = inv_wdisp( inst, pos, 22); break; | |
174 case br_op2: r = inv_wdisp( inst, pos, 22); break; | |
175 case cb_op2: r = inv_wdisp( inst, pos, 22); break; | |
176 case bpr_op2: { | |
177 if (is_cbcond(inst)) { | |
178 r = inv_wdisp10(inst, pos); | |
179 } else { | |
180 r = inv_wdisp16(inst, pos); | |
181 } | |
182 break; | |
183 } | |
184 default: ShouldNotReachHere(); | |
185 } | |
186 } | |
187 return r; | |
188 } | |
189 | 28 |
190 int AbstractAssembler::code_fill_byte() { | 29 int AbstractAssembler::code_fill_byte() { |
191 return 0x00; // illegal instruction 0x00000000 | 30 return 0x00; // illegal instruction 0x00000000 |
192 } | 31 } |
193 | |
194 Assembler::Condition Assembler::reg_cond_to_cc_cond(Assembler::RCondition in) { | |
195 switch (in) { | |
196 case rc_z: return equal; | |
197 case rc_lez: return lessEqual; | |
198 case rc_lz: return less; | |
199 case rc_nz: return notEqual; | |
200 case rc_gz: return greater; | |
201 case rc_gez: return greaterEqual; | |
202 default: | |
203 ShouldNotReachHere(); | |
204 } | |
205 return equal; | |
206 } | |
207 | |
208 // Generate a bunch 'o stuff (including v9's | |
209 #ifndef PRODUCT | |
210 void Assembler::test_v9() { | |
211 add( G0, G1, G2 ); | |
212 add( G3, 0, G4 ); | |
213 | |
214 addcc( G5, G6, G7 ); | |
215 addcc( I0, 1, I1 ); | |
216 addc( I2, I3, I4 ); | |
217 addc( I5, -1, I6 ); | |
218 addccc( I7, L0, L1 ); | |
219 addccc( L2, (1 << 12) - 2, L3 ); | |
220 | |
221 Label lbl1, lbl2, lbl3; | |
222 | |
223 bind(lbl1); | |
224 | |
225 bpr( rc_z, true, pn, L4, pc(), relocInfo::oop_type ); | |
226 delayed()->nop(); | |
227 bpr( rc_lez, false, pt, L5, lbl1); | |
228 delayed()->nop(); | |
229 | |
230 fb( f_never, true, pc() + 4, relocInfo::none); | |
231 delayed()->nop(); | |
232 fb( f_notEqual, false, lbl2 ); | |
233 delayed()->nop(); | |
234 | |
235 fbp( f_notZero, true, fcc0, pn, pc() - 4, relocInfo::none); | |
236 delayed()->nop(); | |
237 fbp( f_lessOrGreater, false, fcc1, pt, lbl3 ); | |
238 delayed()->nop(); | |
239 | |
240 br( equal, true, pc() + 1024, relocInfo::none); | |
241 delayed()->nop(); | |
242 br( lessEqual, false, lbl1 ); | |
243 delayed()->nop(); | |
244 br( never, false, lbl1 ); | |
245 delayed()->nop(); | |
246 | |
247 bp( less, true, icc, pn, pc(), relocInfo::none); | |
248 delayed()->nop(); | |
249 bp( lessEqualUnsigned, false, xcc, pt, lbl2 ); | |
250 delayed()->nop(); | |
251 | |
252 call( pc(), relocInfo::none); | |
253 delayed()->nop(); | |
254 call( lbl3 ); | |
255 delayed()->nop(); | |
256 | |
257 | |
258 casa( L6, L7, O0 ); | |
259 casxa( O1, O2, O3, 0 ); | |
260 | |
261 udiv( O4, O5, O7 ); | |
262 udiv( G0, (1 << 12) - 1, G1 ); | |
263 sdiv( G1, G2, G3 ); | |
264 sdiv( G4, -((1 << 12) - 1), G5 ); | |
265 udivcc( G6, G7, I0 ); | |
266 udivcc( I1, -((1 << 12) - 2), I2 ); | |
267 sdivcc( I3, I4, I5 ); | |
268 sdivcc( I6, -((1 << 12) - 0), I7 ); | |
269 | |
270 done(); | |
271 retry(); | |
272 | |
273 fadd( FloatRegisterImpl::S, F0, F1, F2 ); | |
274 fsub( FloatRegisterImpl::D, F34, F0, F62 ); | |
275 | |
276 fcmp( FloatRegisterImpl::Q, fcc0, F0, F60); | |
277 fcmpe( FloatRegisterImpl::S, fcc1, F31, F30); | |
278 | |
279 ftox( FloatRegisterImpl::D, F2, F4 ); | |
280 ftoi( FloatRegisterImpl::Q, F4, F8 ); | |
281 | |
282 ftof( FloatRegisterImpl::S, FloatRegisterImpl::Q, F3, F12 ); | |
283 | |
284 fxtof( FloatRegisterImpl::S, F4, F5 ); | |
285 fitof( FloatRegisterImpl::D, F6, F8 ); | |
286 | |
287 fmov( FloatRegisterImpl::Q, F16, F20 ); | |
288 fneg( FloatRegisterImpl::S, F6, F7 ); | |
289 fabs( FloatRegisterImpl::D, F10, F12 ); | |
290 | |
291 fmul( FloatRegisterImpl::Q, F24, F28, F32 ); | |
292 fmul( FloatRegisterImpl::S, FloatRegisterImpl::D, F8, F9, F14 ); | |
293 fdiv( FloatRegisterImpl::S, F10, F11, F12 ); | |
294 | |
295 fsqrt( FloatRegisterImpl::S, F13, F14 ); | |
296 | |
297 flush( L0, L1 ); | |
298 flush( L2, -1 ); | |
299 | |
300 flushw(); | |
301 | |
302 illtrap( (1 << 22) - 2); | |
303 | |
304 impdep1( 17, (1 << 19) - 1 ); | |
305 impdep2( 3, 0 ); | |
306 | |
307 jmpl( L3, L4, L5 ); | |
308 delayed()->nop(); | |
309 jmpl( L6, -1, L7, Relocation::spec_simple(relocInfo::none)); | |
310 delayed()->nop(); | |
311 | |
312 | |
313 ldf( FloatRegisterImpl::S, O0, O1, F15 ); | |
314 ldf( FloatRegisterImpl::D, O2, -1, F14 ); | |
315 | |
316 | |
317 ldfsr( O3, O4 ); | |
318 ldfsr( O5, -1 ); | |
319 ldxfsr( O6, O7 ); | |
320 ldxfsr( I0, -1 ); | |
321 | |
322 ldfa( FloatRegisterImpl::D, I1, I2, 1, F16 ); | |
323 ldfa( FloatRegisterImpl::Q, I3, -1, F36 ); | |
324 | |
325 ldsb( I4, I5, I6 ); | |
326 ldsb( I7, -1, G0 ); | |
327 ldsh( G1, G3, G4 ); | |
328 ldsh( G5, -1, G6 ); | |
329 ldsw( G7, L0, L1 ); | |
330 ldsw( L2, -1, L3 ); | |
331 ldub( L4, L5, L6 ); | |
332 ldub( L7, -1, O0 ); | |
333 lduh( O1, O2, O3 ); | |
334 lduh( O4, -1, O5 ); | |
335 lduw( O6, O7, G0 ); | |
336 lduw( G1, -1, G2 ); | |
337 ldx( G3, G4, G5 ); | |
338 ldx( G6, -1, G7 ); | |
339 ldd( I0, I1, I2 ); | |
340 ldd( I3, -1, I4 ); | |
341 | |
342 ldsba( I5, I6, 2, I7 ); | |
343 ldsba( L0, -1, L1 ); | |
344 ldsha( L2, L3, 3, L4 ); | |
345 ldsha( L5, -1, L6 ); | |
346 ldswa( L7, O0, (1 << 8) - 1, O1 ); | |
347 ldswa( O2, -1, O3 ); | |
348 lduba( O4, O5, 0, O6 ); | |
349 lduba( O7, -1, I0 ); | |
350 lduha( I1, I2, 1, I3 ); | |
351 lduha( I4, -1, I5 ); | |
352 lduwa( I6, I7, 2, L0 ); | |
353 lduwa( L1, -1, L2 ); | |
354 ldxa( L3, L4, 3, L5 ); | |
355 ldxa( L6, -1, L7 ); | |
356 ldda( G0, G1, 4, G2 ); | |
357 ldda( G3, -1, G4 ); | |
358 | |
359 ldstub( G5, G6, G7 ); | |
360 ldstub( O0, -1, O1 ); | |
361 | |
362 ldstuba( O2, O3, 5, O4 ); | |
363 ldstuba( O5, -1, O6 ); | |
364 | |
365 and3( I0, L0, O0 ); | |
366 and3( G7, -1, O7 ); | |
367 andcc( L2, I2, G2 ); | |
368 andcc( L4, -1, G4 ); | |
369 andn( I5, I6, I7 ); | |
370 andn( I6, -1, I7 ); | |
371 andncc( I5, I6, I7 ); | |
372 andncc( I7, -1, I6 ); | |
373 or3( I5, I6, I7 ); | |
374 or3( I7, -1, I6 ); | |
375 orcc( I5, I6, I7 ); | |
376 orcc( I7, -1, I6 ); | |
377 orn( I5, I6, I7 ); | |
378 orn( I7, -1, I6 ); | |
379 orncc( I5, I6, I7 ); | |
380 orncc( I7, -1, I6 ); | |
381 xor3( I5, I6, I7 ); | |
382 xor3( I7, -1, I6 ); | |
383 xorcc( I5, I6, I7 ); | |
384 xorcc( I7, -1, I6 ); | |
385 xnor( I5, I6, I7 ); | |
386 xnor( I7, -1, I6 ); | |
387 xnorcc( I5, I6, I7 ); | |
388 xnorcc( I7, -1, I6 ); | |
389 | |
390 membar( Membar_mask_bits(StoreStore | LoadStore | StoreLoad | LoadLoad | Sync | MemIssue | Lookaside ) ); | |
391 membar( StoreStore ); | |
392 membar( LoadStore ); | |
393 membar( StoreLoad ); | |
394 membar( LoadLoad ); | |
395 membar( Sync ); | |
396 membar( MemIssue ); | |
397 membar( Lookaside ); | |
398 | |
399 fmov( FloatRegisterImpl::S, f_ordered, true, fcc2, F16, F17 ); | |
400 fmov( FloatRegisterImpl::D, rc_lz, L5, F18, F20 ); | |
401 | |
402 movcc( overflowClear, false, icc, I6, L4 ); | |
403 movcc( f_unorderedOrEqual, true, fcc2, (1 << 10) - 1, O0 ); | |
404 | |
405 movr( rc_nz, I5, I6, I7 ); | |
406 movr( rc_gz, L1, -1, L2 ); | |
407 | |
408 mulx( I5, I6, I7 ); | |
409 mulx( I7, -1, I6 ); | |
410 sdivx( I5, I6, I7 ); | |
411 sdivx( I7, -1, I6 ); | |
412 udivx( I5, I6, I7 ); | |
413 udivx( I7, -1, I6 ); | |
414 | |
415 umul( I5, I6, I7 ); | |
416 umul( I7, -1, I6 ); | |
417 smul( I5, I6, I7 ); | |
418 smul( I7, -1, I6 ); | |
419 umulcc( I5, I6, I7 ); | |
420 umulcc( I7, -1, I6 ); | |
421 smulcc( I5, I6, I7 ); | |
422 smulcc( I7, -1, I6 ); | |
423 | |
424 mulscc( I5, I6, I7 ); | |
425 mulscc( I7, -1, I6 ); | |
426 | |
427 nop(); | |
428 | |
429 | |
430 popc( G0, G1); | |
431 popc( -1, G2); | |
432 | |
433 prefetch( L1, L2, severalReads ); | |
434 prefetch( L3, -1, oneRead ); | |
435 prefetcha( O3, O2, 6, severalWritesAndPossiblyReads ); | |
436 prefetcha( G2, -1, oneWrite ); | |
437 | |
438 rett( I7, I7); | |
439 delayed()->nop(); | |
440 rett( G0, -1, relocInfo::none); | |
441 delayed()->nop(); | |
442 | |
443 save( I5, I6, I7 ); | |
444 save( I7, -1, I6 ); | |
445 restore( I5, I6, I7 ); | |
446 restore( I7, -1, I6 ); | |
447 | |
448 saved(); | |
449 restored(); | |
450 | |
451 sethi( 0xaaaaaaaa, I3, Relocation::spec_simple(relocInfo::none)); | |
452 | |
453 sll( I5, I6, I7 ); | |
454 sll( I7, 31, I6 ); | |
455 srl( I5, I6, I7 ); | |
456 srl( I7, 0, I6 ); | |
457 sra( I5, I6, I7 ); | |
458 sra( I7, 30, I6 ); | |
459 sllx( I5, I6, I7 ); | |
460 sllx( I7, 63, I6 ); | |
461 srlx( I5, I6, I7 ); | |
462 srlx( I7, 0, I6 ); | |
463 srax( I5, I6, I7 ); | |
464 srax( I7, 62, I6 ); | |
465 | |
466 sir( -1 ); | |
467 | |
468 stbar(); | |
469 | |
470 stf( FloatRegisterImpl::Q, F40, G0, I7 ); | |
471 stf( FloatRegisterImpl::S, F18, I3, -1 ); | |
472 | |
473 stfsr( L1, L2 ); | |
474 stfsr( I7, -1 ); | |
475 stxfsr( I6, I5 ); | |
476 stxfsr( L4, -1 ); | |
477 | |
478 stfa( FloatRegisterImpl::D, F22, I6, I7, 7 ); | |
479 stfa( FloatRegisterImpl::Q, F44, G0, -1 ); | |
480 | |
481 stb( L5, O2, I7 ); | |
482 stb( I7, I6, -1 ); | |
483 sth( L5, O2, I7 ); | |
484 sth( I7, I6, -1 ); | |
485 stw( L5, O2, I7 ); | |
486 stw( I7, I6, -1 ); | |
487 stx( L5, O2, I7 ); | |
488 stx( I7, I6, -1 ); | |
489 std( L5, O2, I7 ); | |
490 std( I7, I6, -1 ); | |
491 | |
492 stba( L5, O2, I7, 8 ); | |
493 stba( I7, I6, -1 ); | |
494 stha( L5, O2, I7, 9 ); | |
495 stha( I7, I6, -1 ); | |
496 stwa( L5, O2, I7, 0 ); | |
497 stwa( I7, I6, -1 ); | |
498 stxa( L5, O2, I7, 11 ); | |
499 stxa( I7, I6, -1 ); | |
500 stda( L5, O2, I7, 12 ); | |
501 stda( I7, I6, -1 ); | |
502 | |
503 sub( I5, I6, I7 ); | |
504 sub( I7, -1, I6 ); | |
505 subcc( I5, I6, I7 ); | |
506 subcc( I7, -1, I6 ); | |
507 subc( I5, I6, I7 ); | |
508 subc( I7, -1, I6 ); | |
509 subccc( I5, I6, I7 ); | |
510 subccc( I7, -1, I6 ); | |
511 | |
512 swap( I5, I6, I7 ); | |
513 swap( I7, -1, I6 ); | |
514 | |
515 swapa( G0, G1, 13, G2 ); | |
516 swapa( I7, -1, I6 ); | |
517 | |
518 taddcc( I5, I6, I7 ); | |
519 taddcc( I7, -1, I6 ); | |
520 taddcctv( I5, I6, I7 ); | |
521 taddcctv( I7, -1, I6 ); | |
522 | |
523 tsubcc( I5, I6, I7 ); | |
524 tsubcc( I7, -1, I6 ); | |
525 tsubcctv( I5, I6, I7 ); | |
526 tsubcctv( I7, -1, I6 ); | |
527 | |
528 trap( overflowClear, xcc, G0, G1 ); | |
529 trap( lessEqual, icc, I7, 17 ); | |
530 | |
531 bind(lbl2); | |
532 bind(lbl3); | |
533 | |
534 code()->decode(); | |
535 } | |
536 | |
537 // Generate a bunch 'o stuff unique to V8 | |
538 void Assembler::test_v8_onlys() { | |
539 Label lbl1; | |
540 | |
541 cb( cp_0or1or2, false, pc() - 4, relocInfo::none); | |
542 delayed()->nop(); | |
543 cb( cp_never, true, lbl1); | |
544 delayed()->nop(); | |
545 | |
546 cpop1(1, 2, 3, 4); | |
547 cpop2(5, 6, 7, 8); | |
548 | |
549 ldc( I0, I1, 31); | |
550 ldc( I2, -1, 0); | |
551 | |
552 lddc( I4, I4, 30); | |
553 lddc( I6, 0, 1 ); | |
554 | |
555 ldcsr( L0, L1, 0); | |
556 ldcsr( L1, (1 << 12) - 1, 17 ); | |
557 | |
558 stc( 31, L4, L5); | |
559 stc( 30, L6, -(1 << 12) ); | |
560 | |
561 stdc( 0, L7, G0); | |
562 stdc( 1, G1, 0 ); | |
563 | |
564 stcsr( 16, G2, G3); | |
565 stcsr( 17, G4, 1 ); | |
566 | |
567 stdcq( 4, G5, G6); | |
568 stdcq( 5, G7, -1 ); | |
569 | |
570 bind(lbl1); | |
571 | |
572 code()->decode(); | |
573 } | |
574 #endif | |
575 | |
576 // Implementation of MacroAssembler | |
577 | |
578 void MacroAssembler::null_check(Register reg, int offset) { | |
579 if (needs_explicit_null_check((intptr_t)offset)) { | |
580 // provoke OS NULL exception if reg = NULL by | |
581 // accessing M[reg] w/o changing any registers | |
582 ld_ptr(reg, 0, G0); | |
583 } | |
584 else { | |
585 // nothing to do, (later) access of M[reg + offset] | |
586 // will provoke OS NULL exception if reg = NULL | |
587 } | |
588 } | |
589 | |
590 // Ring buffer jumps | |
591 | |
592 #ifndef PRODUCT | |
593 void MacroAssembler::ret( bool trace ) { if (trace) { | |
594 mov(I7, O7); // traceable register | |
595 JMP(O7, 2 * BytesPerInstWord); | |
596 } else { | |
597 jmpl( I7, 2 * BytesPerInstWord, G0 ); | |
598 } | |
599 } | |
600 | |
601 void MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord); | |
602 else jmpl( O7, 2 * BytesPerInstWord, G0 ); } | |
603 #endif /* PRODUCT */ | |
604 | |
605 | |
606 void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) { | |
607 assert_not_delayed(); | |
608 // This can only be traceable if r1 & r2 are visible after a window save | |
609 if (TraceJumps) { | |
610 #ifndef PRODUCT | |
611 save_frame(0); | |
612 verify_thread(); | |
613 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); | |
614 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); | |
615 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); | |
616 add(O2, O1, O1); | |
617 | |
618 add(r1->after_save(), r2->after_save(), O2); | |
619 set((intptr_t)file, O3); | |
620 set(line, O4); | |
621 Label L; | |
622 // get nearby pc, store jmp target | |
623 call(L, relocInfo::none); // No relocation for call to pc+0x8 | |
624 delayed()->st(O2, O1, 0); | |
625 bind(L); | |
626 | |
627 // store nearby pc | |
628 st(O7, O1, sizeof(intptr_t)); | |
629 // store file | |
630 st(O3, O1, 2*sizeof(intptr_t)); | |
631 // store line | |
632 st(O4, O1, 3*sizeof(intptr_t)); | |
633 add(O0, 1, O0); | |
634 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); | |
635 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); | |
636 restore(); | |
637 #endif /* PRODUCT */ | |
638 } | |
639 jmpl(r1, r2, G0); | |
640 } | |
641 void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) { | |
642 assert_not_delayed(); | |
643 // This can only be traceable if r1 is visible after a window save | |
644 if (TraceJumps) { | |
645 #ifndef PRODUCT | |
646 save_frame(0); | |
647 verify_thread(); | |
648 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); | |
649 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); | |
650 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); | |
651 add(O2, O1, O1); | |
652 | |
653 add(r1->after_save(), offset, O2); | |
654 set((intptr_t)file, O3); | |
655 set(line, O4); | |
656 Label L; | |
657 // get nearby pc, store jmp target | |
658 call(L, relocInfo::none); // No relocation for call to pc+0x8 | |
659 delayed()->st(O2, O1, 0); | |
660 bind(L); | |
661 | |
662 // store nearby pc | |
663 st(O7, O1, sizeof(intptr_t)); | |
664 // store file | |
665 st(O3, O1, 2*sizeof(intptr_t)); | |
666 // store line | |
667 st(O4, O1, 3*sizeof(intptr_t)); | |
668 add(O0, 1, O0); | |
669 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); | |
670 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); | |
671 restore(); | |
672 #endif /* PRODUCT */ | |
673 } | |
674 jmp(r1, offset); | |
675 } | |
676 | |
677 // This code sequence is relocatable to any address, even on LP64. | |
678 void MacroAssembler::jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) { | |
679 assert_not_delayed(); | |
680 // Force fixed length sethi because NativeJump and NativeFarCall don't handle | |
681 // variable length instruction streams. | |
682 patchable_sethi(addrlit, temp); | |
683 Address a(temp, addrlit.low10() + offset); // Add the offset to the displacement. | |
684 if (TraceJumps) { | |
685 #ifndef PRODUCT | |
686 // Must do the add here so relocation can find the remainder of the | |
687 // value to be relocated. | |
688 add(a.base(), a.disp(), a.base(), addrlit.rspec(offset)); | |
689 save_frame(0); | |
690 verify_thread(); | |
691 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); | |
692 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); | |
693 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); | |
694 add(O2, O1, O1); | |
695 | |
696 set((intptr_t)file, O3); | |
697 set(line, O4); | |
698 Label L; | |
699 | |
700 // get nearby pc, store jmp target | |
701 call(L, relocInfo::none); // No relocation for call to pc+0x8 | |
702 delayed()->st(a.base()->after_save(), O1, 0); | |
703 bind(L); | |
704 | |
705 // store nearby pc | |
706 st(O7, O1, sizeof(intptr_t)); | |
707 // store file | |
708 st(O3, O1, 2*sizeof(intptr_t)); | |
709 // store line | |
710 st(O4, O1, 3*sizeof(intptr_t)); | |
711 add(O0, 1, O0); | |
712 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); | |
713 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); | |
714 restore(); | |
715 jmpl(a.base(), G0, d); | |
716 #else | |
717 jmpl(a.base(), a.disp(), d); | |
718 #endif /* PRODUCT */ | |
719 } else { | |
720 jmpl(a.base(), a.disp(), d); | |
721 } | |
722 } | |
723 | |
724 void MacroAssembler::jump(const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) { | |
725 jumpl(addrlit, temp, G0, offset, file, line); | |
726 } | |
727 | |
728 | |
729 // Conditional breakpoint (for assertion checks in assembly code) | |
730 void MacroAssembler::breakpoint_trap(Condition c, CC cc) { | |
731 trap(c, cc, G0, ST_RESERVED_FOR_USER_0); | |
732 } | |
733 | |
734 // We want to use ST_BREAKPOINT here, but the debugger is confused by it. | |
735 void MacroAssembler::breakpoint_trap() { | |
736 trap(ST_RESERVED_FOR_USER_0); | |
737 } | |
738 | |
739 // flush windows (except current) using flushw instruction if avail. | |
740 void MacroAssembler::flush_windows() { | |
741 if (VM_Version::v9_instructions_work()) flushw(); | |
742 else flush_windows_trap(); | |
743 } | |
744 | |
745 // Write serialization page so VM thread can do a pseudo remote membar | |
746 // We use the current thread pointer to calculate a thread specific | |
747 // offset to write to within the page. This minimizes bus traffic | |
748 // due to cache line collision. | |
749 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) { | |
750 srl(thread, os::get_serialize_page_shift_count(), tmp2); | |
751 if (Assembler::is_simm13(os::vm_page_size())) { | |
752 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2); | |
753 } | |
754 else { | |
755 set((os::vm_page_size() - sizeof(int)), tmp1); | |
756 and3(tmp2, tmp1, tmp2); | |
757 } | |
758 set(os::get_memory_serialize_page(), tmp1); | |
759 st(G0, tmp1, tmp2); | |
760 } | |
761 | |
762 | |
763 | |
764 void MacroAssembler::enter() { | |
765 Unimplemented(); | |
766 } | |
767 | |
768 void MacroAssembler::leave() { | |
769 Unimplemented(); | |
770 } | |
771 | |
772 void MacroAssembler::mult(Register s1, Register s2, Register d) { | |
773 if(VM_Version::v9_instructions_work()) { | |
774 mulx (s1, s2, d); | |
775 } else { | |
776 smul (s1, s2, d); | |
777 } | |
778 } | |
779 | |
780 void MacroAssembler::mult(Register s1, int simm13a, Register d) { | |
781 if(VM_Version::v9_instructions_work()) { | |
782 mulx (s1, simm13a, d); | |
783 } else { | |
784 smul (s1, simm13a, d); | |
785 } | |
786 } | |
787 | |
788 | |
789 #ifdef ASSERT | |
790 void MacroAssembler::read_ccr_v8_assert(Register ccr_save) { | |
791 const Register s1 = G3_scratch; | |
792 const Register s2 = G4_scratch; | |
793 Label get_psr_test; | |
794 // Get the condition codes the V8 way. | |
795 read_ccr_trap(s1); | |
796 mov(ccr_save, s2); | |
797 // This is a test of V8 which has icc but not xcc | |
798 // so mask off the xcc bits | |
799 and3(s2, 0xf, s2); | |
800 // Compare condition codes from the V8 and V9 ways. | |
801 subcc(s2, s1, G0); | |
802 br(Assembler::notEqual, true, Assembler::pt, get_psr_test); | |
803 delayed()->breakpoint_trap(); | |
804 bind(get_psr_test); | |
805 } | |
806 | |
807 void MacroAssembler::write_ccr_v8_assert(Register ccr_save) { | |
808 const Register s1 = G3_scratch; | |
809 const Register s2 = G4_scratch; | |
810 Label set_psr_test; | |
811 // Write out the saved condition codes the V8 way | |
812 write_ccr_trap(ccr_save, s1, s2); | |
813 // Read back the condition codes using the V9 instruction | |
814 rdccr(s1); | |
815 mov(ccr_save, s2); | |
816 // This is a test of V8 which has icc but not xcc | |
817 // so mask off the xcc bits | |
818 and3(s2, 0xf, s2); | |
819 and3(s1, 0xf, s1); | |
820 // Compare the V8 way with the V9 way. | |
821 subcc(s2, s1, G0); | |
822 br(Assembler::notEqual, true, Assembler::pt, set_psr_test); | |
823 delayed()->breakpoint_trap(); | |
824 bind(set_psr_test); | |
825 } | |
826 #else | |
827 #define read_ccr_v8_assert(x) | |
828 #define write_ccr_v8_assert(x) | |
829 #endif // ASSERT | |
830 | |
831 void MacroAssembler::read_ccr(Register ccr_save) { | |
832 if (VM_Version::v9_instructions_work()) { | |
833 rdccr(ccr_save); | |
834 // Test code sequence used on V8. Do not move above rdccr. | |
835 read_ccr_v8_assert(ccr_save); | |
836 } else { | |
837 read_ccr_trap(ccr_save); | |
838 } | |
839 } | |
840 | |
841 void MacroAssembler::write_ccr(Register ccr_save) { | |
842 if (VM_Version::v9_instructions_work()) { | |
843 // Test code sequence used on V8. Do not move below wrccr. | |
844 write_ccr_v8_assert(ccr_save); | |
845 wrccr(ccr_save); | |
846 } else { | |
847 const Register temp_reg1 = G3_scratch; | |
848 const Register temp_reg2 = G4_scratch; | |
849 write_ccr_trap(ccr_save, temp_reg1, temp_reg2); | |
850 } | |
851 } | |
852 | |
853 | |
854 // Calls to C land | |
855 | |
856 #ifdef ASSERT | |
857 // a hook for debugging | |
858 static Thread* reinitialize_thread() { | |
859 return ThreadLocalStorage::thread(); | |
860 } | |
861 #else | |
862 #define reinitialize_thread ThreadLocalStorage::thread | |
863 #endif | |
864 | |
865 #ifdef ASSERT | |
866 address last_get_thread = NULL; | |
867 #endif | |
868 | |
869 // call this when G2_thread is not known to be valid | |
870 void MacroAssembler::get_thread() { | |
871 save_frame(0); // to avoid clobbering O0 | |
872 mov(G1, L0); // avoid clobbering G1 | |
873 mov(G5_method, L1); // avoid clobbering G5 | |
874 mov(G3, L2); // avoid clobbering G3 also | |
875 mov(G4, L5); // avoid clobbering G4 | |
876 #ifdef ASSERT | |
877 AddressLiteral last_get_thread_addrlit(&last_get_thread); | |
878 set(last_get_thread_addrlit, L3); | |
879 inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call | |
880 st_ptr(L4, L3, 0); | |
881 #endif | |
882 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type); | |
883 delayed()->nop(); | |
884 mov(L0, G1); | |
885 mov(L1, G5_method); | |
886 mov(L2, G3); | |
887 mov(L5, G4); | |
888 restore(O0, 0, G2_thread); | |
889 } | |
890 | |
891 static Thread* verify_thread_subroutine(Thread* gthread_value) { | |
892 Thread* correct_value = ThreadLocalStorage::thread(); | |
893 guarantee(gthread_value == correct_value, "G2_thread value must be the thread"); | |
894 return correct_value; | |
895 } | |
896 | |
897 void MacroAssembler::verify_thread() { | |
898 if (VerifyThread) { | |
899 // NOTE: this chops off the heads of the 64-bit O registers. | |
900 #ifdef CC_INTERP | |
901 save_frame(0); | |
902 #else | |
903 // make sure G2_thread contains the right value | |
904 save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof) | |
905 mov(G1, L1); // avoid clobbering G1 | |
906 // G2 saved below | |
907 mov(G3, L3); // avoid clobbering G3 | |
908 mov(G4, L4); // avoid clobbering G4 | |
909 mov(G5_method, L5); // avoid clobbering G5_method | |
910 #endif /* CC_INTERP */ | |
911 #if defined(COMPILER2) && !defined(_LP64) | |
912 // Save & restore possible 64-bit Long arguments in G-regs | |
913 srlx(G1,32,L0); | |
914 srlx(G4,32,L6); | |
915 #endif | |
916 call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type); | |
917 delayed()->mov(G2_thread, O0); | |
918 | |
919 mov(L1, G1); // Restore G1 | |
920 // G2 restored below | |
921 mov(L3, G3); // restore G3 | |
922 mov(L4, G4); // restore G4 | |
923 mov(L5, G5_method); // restore G5_method | |
924 #if defined(COMPILER2) && !defined(_LP64) | |
925 // Save & restore possible 64-bit Long arguments in G-regs | |
926 sllx(L0,32,G2); // Move old high G1 bits high in G2 | |
927 srl(G1, 0,G1); // Clear current high G1 bits | |
928 or3 (G1,G2,G1); // Recover 64-bit G1 | |
929 sllx(L6,32,G2); // Move old high G4 bits high in G2 | |
930 srl(G4, 0,G4); // Clear current high G4 bits | |
931 or3 (G4,G2,G4); // Recover 64-bit G4 | |
932 #endif | |
933 restore(O0, 0, G2_thread); | |
934 } | |
935 } | |
936 | |
937 | |
938 void MacroAssembler::save_thread(const Register thread_cache) { | |
939 verify_thread(); | |
940 if (thread_cache->is_valid()) { | |
941 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); | |
942 mov(G2_thread, thread_cache); | |
943 } | |
944 if (VerifyThread) { | |
945 // smash G2_thread, as if the VM were about to anyway | |
946 set(0x67676767, G2_thread); | |
947 } | |
948 } | |
949 | |
950 | |
951 void MacroAssembler::restore_thread(const Register thread_cache) { | |
952 if (thread_cache->is_valid()) { | |
953 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); | |
954 mov(thread_cache, G2_thread); | |
955 verify_thread(); | |
956 } else { | |
957 // do it the slow way | |
958 get_thread(); | |
959 } | |
960 } | |
961 | |
962 | |
963 // %%% maybe get rid of [re]set_last_Java_frame | |
964 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) { | |
965 assert_not_delayed(); | |
966 Address flags(G2_thread, JavaThread::frame_anchor_offset() + | |
967 JavaFrameAnchor::flags_offset()); | |
968 Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset()); | |
969 | |
970 // Always set last_Java_pc and flags first because once last_Java_sp is visible | |
971 // has_last_Java_frame is true and users will look at the rest of the fields. | |
972 // (Note: flags should always be zero before we get here so doesn't need to be set.) | |
973 | |
974 #ifdef ASSERT | |
975 // Verify that flags was zeroed on return to Java | |
976 Label PcOk; | |
977 save_frame(0); // to avoid clobbering O0 | |
978 ld_ptr(pc_addr, L0); | |
979 br_null_short(L0, Assembler::pt, PcOk); | |
980 STOP("last_Java_pc not zeroed before leaving Java"); | |
981 bind(PcOk); | |
982 | |
983 // Verify that flags was zeroed on return to Java | |
984 Label FlagsOk; | |
985 ld(flags, L0); | |
986 tst(L0); | |
987 br(Assembler::zero, false, Assembler::pt, FlagsOk); | |
988 delayed() -> restore(); | |
989 STOP("flags not zeroed before leaving Java"); | |
990 bind(FlagsOk); | |
991 #endif /* ASSERT */ | |
992 // | |
993 // When returning from calling out from Java mode the frame anchor's last_Java_pc | |
994 // will always be set to NULL. It is set here so that if we are doing a call to | |
995 // native (not VM) that we capture the known pc and don't have to rely on the | |
996 // native call having a standard frame linkage where we can find the pc. | |
997 | |
998 if (last_Java_pc->is_valid()) { | |
999 st_ptr(last_Java_pc, pc_addr); | |
1000 } | |
1001 | |
1002 #ifdef _LP64 | |
1003 #ifdef ASSERT | |
1004 // Make sure that we have an odd stack | |
1005 Label StackOk; | |
1006 andcc(last_java_sp, 0x01, G0); | |
1007 br(Assembler::notZero, false, Assembler::pt, StackOk); | |
1008 delayed()->nop(); | |
1009 STOP("Stack Not Biased in set_last_Java_frame"); | |
1010 bind(StackOk); | |
1011 #endif // ASSERT | |
1012 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame"); | |
1013 add( last_java_sp, STACK_BIAS, G4_scratch ); | |
1014 st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset()); | |
1015 #else | |
1016 st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset()); | |
1017 #endif // _LP64 | |
1018 } | |
1019 | |
1020 void MacroAssembler::reset_last_Java_frame(void) { | |
1021 assert_not_delayed(); | |
1022 | |
1023 Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset()); | |
1024 Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); | |
1025 Address flags (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset()); | |
1026 | |
1027 #ifdef ASSERT | |
1028 // check that it WAS previously set | |
1029 #ifdef CC_INTERP | |
1030 save_frame(0); | |
1031 #else | |
1032 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof | |
1033 #endif /* CC_INTERP */ | |
1034 ld_ptr(sp_addr, L0); | |
1035 tst(L0); | |
1036 breakpoint_trap(Assembler::zero, Assembler::ptr_cc); | |
1037 restore(); | |
1038 #endif // ASSERT | |
1039 | |
1040 st_ptr(G0, sp_addr); | |
1041 // Always return last_Java_pc to zero | |
1042 st_ptr(G0, pc_addr); | |
1043 // Always null flags after return to Java | |
1044 st(G0, flags); | |
1045 } | |
1046 | |
1047 | |
1048 void MacroAssembler::call_VM_base( | |
1049 Register oop_result, | |
1050 Register thread_cache, | |
1051 Register last_java_sp, | |
1052 address entry_point, | |
1053 int number_of_arguments, | |
1054 bool check_exceptions) | |
1055 { | |
1056 assert_not_delayed(); | |
1057 | |
1058 // determine last_java_sp register | |
1059 if (!last_java_sp->is_valid()) { | |
1060 last_java_sp = SP; | |
1061 } | |
1062 // debugging support | |
1063 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
1064 | |
1065 // 64-bit last_java_sp is biased! | |
1066 set_last_Java_frame(last_java_sp, noreg); | |
1067 if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early | |
1068 save_thread(thread_cache); | |
1069 // do the call | |
1070 call(entry_point, relocInfo::runtime_call_type); | |
1071 if (!VerifyThread) | |
1072 delayed()->mov(G2_thread, O0); // pass thread as first argument | |
1073 else | |
1074 delayed()->nop(); // (thread already passed) | |
1075 restore_thread(thread_cache); | |
1076 reset_last_Java_frame(); | |
1077 | |
1078 // check for pending exceptions. use Gtemp as scratch register. | |
1079 if (check_exceptions) { | |
1080 check_and_forward_exception(Gtemp); | |
1081 } | |
1082 | |
1083 #ifdef ASSERT | |
1084 set(badHeapWordVal, G3); | |
1085 set(badHeapWordVal, G4); | |
1086 set(badHeapWordVal, G5); | |
1087 #endif | |
1088 | |
1089 // get oop result if there is one and reset the value in the thread | |
1090 if (oop_result->is_valid()) { | |
1091 get_vm_result(oop_result); | |
1092 } | |
1093 } | |
1094 | |
1095 void MacroAssembler::check_and_forward_exception(Register scratch_reg) | |
1096 { | |
1097 Label L; | |
1098 | |
1099 check_and_handle_popframe(scratch_reg); | |
1100 check_and_handle_earlyret(scratch_reg); | |
1101 | |
1102 Address exception_addr(G2_thread, Thread::pending_exception_offset()); | |
1103 ld_ptr(exception_addr, scratch_reg); | |
1104 br_null_short(scratch_reg, pt, L); | |
1105 // we use O7 linkage so that forward_exception_entry has the issuing PC | |
1106 call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type); | |
1107 delayed()->nop(); | |
1108 bind(L); | |
1109 } | |
1110 | |
1111 | |
1112 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) { | |
1113 } | |
1114 | |
1115 | |
1116 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) { | |
1117 } | |
1118 | |
1119 | |
1120 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
1121 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); | |
1122 } | |
1123 | |
1124 | |
1125 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) { | |
1126 // O0 is reserved for the thread | |
1127 mov(arg_1, O1); | |
1128 call_VM(oop_result, entry_point, 1, check_exceptions); | |
1129 } | |
1130 | |
1131 | |
1132 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { | |
1133 // O0 is reserved for the thread | |
1134 mov(arg_1, O1); | |
1135 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1136 call_VM(oop_result, entry_point, 2, check_exceptions); | |
1137 } | |
1138 | |
1139 | |
1140 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { | |
1141 // O0 is reserved for the thread | |
1142 mov(arg_1, O1); | |
1143 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1144 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); | |
1145 call_VM(oop_result, entry_point, 3, check_exceptions); | |
1146 } | |
1147 | |
1148 | |
1149 | |
1150 // Note: The following call_VM overloadings are useful when a "save" | |
1151 // has already been performed by a stub, and the last Java frame is | |
1152 // the previous one. In that case, last_java_sp must be passed as FP | |
1153 // instead of SP. | |
1154 | |
1155 | |
1156 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) { | |
1157 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
1158 } | |
1159 | |
1160 | |
1161 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) { | |
1162 // O0 is reserved for the thread | |
1163 mov(arg_1, O1); | |
1164 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
1165 } | |
1166 | |
1167 | |
1168 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { | |
1169 // O0 is reserved for the thread | |
1170 mov(arg_1, O1); | |
1171 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1172 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
1173 } | |
1174 | |
1175 | |
1176 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { | |
1177 // O0 is reserved for the thread | |
1178 mov(arg_1, O1); | |
1179 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1180 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); | |
1181 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
1182 } | |
1183 | |
1184 | |
1185 | |
1186 void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) { | |
1187 assert_not_delayed(); | |
1188 save_thread(thread_cache); | |
1189 // do the call | |
1190 call(entry_point, relocInfo::runtime_call_type); | |
1191 delayed()->nop(); | |
1192 restore_thread(thread_cache); | |
1193 #ifdef ASSERT | |
1194 set(badHeapWordVal, G3); | |
1195 set(badHeapWordVal, G4); | |
1196 set(badHeapWordVal, G5); | |
1197 #endif | |
1198 } | |
1199 | |
1200 | |
1201 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) { | |
1202 call_VM_leaf_base(thread_cache, entry_point, number_of_arguments); | |
1203 } | |
1204 | |
1205 | |
1206 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) { | |
1207 mov(arg_1, O0); | |
1208 call_VM_leaf(thread_cache, entry_point, 1); | |
1209 } | |
1210 | |
1211 | |
1212 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) { | |
1213 mov(arg_1, O0); | |
1214 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); | |
1215 call_VM_leaf(thread_cache, entry_point, 2); | |
1216 } | |
1217 | |
1218 | |
1219 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) { | |
1220 mov(arg_1, O0); | |
1221 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); | |
1222 mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument"); | |
1223 call_VM_leaf(thread_cache, entry_point, 3); | |
1224 } | |
1225 | |
1226 | |
1227 void MacroAssembler::get_vm_result(Register oop_result) { | |
1228 verify_thread(); | |
1229 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset()); | |
1230 ld_ptr( vm_result_addr, oop_result); | |
1231 st_ptr(G0, vm_result_addr); | |
1232 verify_oop(oop_result); | |
1233 } | |
1234 | |
1235 | |
1236 void MacroAssembler::get_vm_result_2(Register metadata_result) { | |
1237 verify_thread(); | |
1238 Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset()); | |
1239 ld_ptr(vm_result_addr_2, metadata_result); | |
1240 st_ptr(G0, vm_result_addr_2); | |
1241 } | |
1242 | |
1243 | |
1244 // We require that C code which does not return a value in vm_result will | |
1245 // leave it undisturbed. | |
1246 void MacroAssembler::set_vm_result(Register oop_result) { | |
1247 verify_thread(); | |
1248 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset()); | |
1249 verify_oop(oop_result); | |
1250 | |
1251 # ifdef ASSERT | |
1252 // Check that we are not overwriting any other oop. | |
1253 #ifdef CC_INTERP | |
1254 save_frame(0); | |
1255 #else | |
1256 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof | |
1257 #endif /* CC_INTERP */ | |
1258 ld_ptr(vm_result_addr, L0); | |
1259 tst(L0); | |
1260 restore(); | |
1261 breakpoint_trap(notZero, Assembler::ptr_cc); | |
1262 // } | |
1263 # endif | |
1264 | |
1265 st_ptr(oop_result, vm_result_addr); | |
1266 } | |
1267 | |
1268 | |
1269 void MacroAssembler::ic_call(address entry, bool emit_delay) { | |
1270 RelocationHolder rspec = virtual_call_Relocation::spec(pc()); | |
1271 patchable_set((intptr_t)Universe::non_oop_word(), G5_inline_cache_reg); | |
1272 relocate(rspec); | |
1273 call(entry, relocInfo::none); | |
1274 if (emit_delay) { | |
1275 delayed()->nop(); | |
1276 } | |
1277 } | |
1278 | |
1279 | |
1280 void MacroAssembler::card_table_write(jbyte* byte_map_base, | |
1281 Register tmp, Register obj) { | |
1282 #ifdef _LP64 | |
1283 srlx(obj, CardTableModRefBS::card_shift, obj); | |
1284 #else | |
1285 srl(obj, CardTableModRefBS::card_shift, obj); | |
1286 #endif | |
1287 assert(tmp != obj, "need separate temp reg"); | |
1288 set((address) byte_map_base, tmp); | |
1289 stb(G0, tmp, obj); | |
1290 } | |
1291 | |
1292 | |
1293 void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) { | |
1294 address save_pc; | |
1295 int shiftcnt; | |
1296 #ifdef _LP64 | |
1297 # ifdef CHECK_DELAY | |
1298 assert_not_delayed((char*) "cannot put two instructions in delay slot"); | |
1299 # endif | |
1300 v9_dep(); | |
1301 save_pc = pc(); | |
1302 | |
1303 int msb32 = (int) (addrlit.value() >> 32); | |
1304 int lsb32 = (int) (addrlit.value()); | |
1305 | |
1306 if (msb32 == 0 && lsb32 >= 0) { | |
1307 Assembler::sethi(lsb32, d, addrlit.rspec()); | |
1308 } | |
1309 else if (msb32 == -1) { | |
1310 Assembler::sethi(~lsb32, d, addrlit.rspec()); | |
1311 xor3(d, ~low10(~0), d); | |
1312 } | |
1313 else { | |
1314 Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits | |
1315 if (msb32 & 0x3ff) // Any bits? | |
1316 or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32 | |
1317 if (lsb32 & 0xFFFFFC00) { // done? | |
1318 if ((lsb32 >> 20) & 0xfff) { // Any bits set? | |
1319 sllx(d, 12, d); // Make room for next 12 bits | |
1320 or3(d, (lsb32 >> 20) & 0xfff, d); // Or in next 12 | |
1321 shiftcnt = 0; // We already shifted | |
1322 } | |
1323 else | |
1324 shiftcnt = 12; | |
1325 if ((lsb32 >> 10) & 0x3ff) { | |
1326 sllx(d, shiftcnt + 10, d); // Make room for last 10 bits | |
1327 or3(d, (lsb32 >> 10) & 0x3ff, d); // Or in next 10 | |
1328 shiftcnt = 0; | |
1329 } | |
1330 else | |
1331 shiftcnt = 10; | |
1332 sllx(d, shiftcnt + 10, d); // Shift leaving disp field 0'd | |
1333 } | |
1334 else | |
1335 sllx(d, 32, d); | |
1336 } | |
1337 // Pad out the instruction sequence so it can be patched later. | |
1338 if (ForceRelocatable || (addrlit.rtype() != relocInfo::none && | |
1339 addrlit.rtype() != relocInfo::runtime_call_type)) { | |
1340 while (pc() < (save_pc + (7 * BytesPerInstWord))) | |
1341 nop(); | |
1342 } | |
1343 #else | |
1344 Assembler::sethi(addrlit.value(), d, addrlit.rspec()); | |
1345 #endif | |
1346 } | |
1347 | |
1348 | |
1349 void MacroAssembler::sethi(const AddressLiteral& addrlit, Register d) { | |
1350 internal_sethi(addrlit, d, false); | |
1351 } | |
1352 | |
1353 | |
1354 void MacroAssembler::patchable_sethi(const AddressLiteral& addrlit, Register d) { | |
1355 internal_sethi(addrlit, d, true); | |
1356 } | |
1357 | |
1358 | |
1359 int MacroAssembler::insts_for_sethi(address a, bool worst_case) { | |
1360 #ifdef _LP64 | |
1361 if (worst_case) return 7; | |
1362 intptr_t iaddr = (intptr_t) a; | |
1363 int msb32 = (int) (iaddr >> 32); | |
1364 int lsb32 = (int) (iaddr); | |
1365 int count; | |
1366 if (msb32 == 0 && lsb32 >= 0) | |
1367 count = 1; | |
1368 else if (msb32 == -1) | |
1369 count = 2; | |
1370 else { | |
1371 count = 2; | |
1372 if (msb32 & 0x3ff) | |
1373 count++; | |
1374 if (lsb32 & 0xFFFFFC00 ) { | |
1375 if ((lsb32 >> 20) & 0xfff) count += 2; | |
1376 if ((lsb32 >> 10) & 0x3ff) count += 2; | |
1377 } | |
1378 } | |
1379 return count; | |
1380 #else | |
1381 return 1; | |
1382 #endif | |
1383 } | |
1384 | |
1385 int MacroAssembler::worst_case_insts_for_set() { | |
1386 return insts_for_sethi(NULL, true) + 1; | |
1387 } | |
1388 | |
1389 | |
1390 // Keep in sync with MacroAssembler::insts_for_internal_set | |
1391 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) { | |
1392 intptr_t value = addrlit.value(); | |
1393 | |
1394 if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) { | |
1395 // can optimize | |
1396 if (-4096 <= value && value <= 4095) { | |
1397 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended) | |
1398 return; | |
1399 } | |
1400 if (inv_hi22(hi22(value)) == value) { | |
1401 sethi(addrlit, d); | |
1402 return; | |
1403 } | |
1404 } | |
1405 assert_not_delayed((char*) "cannot put two instructions in delay slot"); | |
1406 internal_sethi(addrlit, d, ForceRelocatable); | |
1407 if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) { | |
1408 add(d, addrlit.low10(), d, addrlit.rspec()); | |
1409 } | |
1410 } | |
1411 | |
1412 // Keep in sync with MacroAssembler::internal_set | |
1413 int MacroAssembler::insts_for_internal_set(intptr_t value) { | |
1414 // can optimize | |
1415 if (-4096 <= value && value <= 4095) { | |
1416 return 1; | |
1417 } | |
1418 if (inv_hi22(hi22(value)) == value) { | |
1419 return insts_for_sethi((address) value); | |
1420 } | |
1421 int count = insts_for_sethi((address) value); | |
1422 AddressLiteral al(value); | |
1423 if (al.low10() != 0) { | |
1424 count++; | |
1425 } | |
1426 return count; | |
1427 } | |
1428 | |
1429 void MacroAssembler::set(const AddressLiteral& al, Register d) { | |
1430 internal_set(al, d, false); | |
1431 } | |
1432 | |
1433 void MacroAssembler::set(intptr_t value, Register d) { | |
1434 AddressLiteral al(value); | |
1435 internal_set(al, d, false); | |
1436 } | |
1437 | |
1438 void MacroAssembler::set(address addr, Register d, RelocationHolder const& rspec) { | |
1439 AddressLiteral al(addr, rspec); | |
1440 internal_set(al, d, false); | |
1441 } | |
1442 | |
1443 void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) { | |
1444 internal_set(al, d, true); | |
1445 } | |
1446 | |
1447 void MacroAssembler::patchable_set(intptr_t value, Register d) { | |
1448 AddressLiteral al(value); | |
1449 internal_set(al, d, true); | |
1450 } | |
1451 | |
1452 | |
1453 void MacroAssembler::set64(jlong value, Register d, Register tmp) { | |
1454 assert_not_delayed(); | |
1455 v9_dep(); | |
1456 | |
1457 int hi = (int)(value >> 32); | |
1458 int lo = (int)(value & ~0); | |
1459 // (Matcher::isSimpleConstant64 knows about the following optimizations.) | |
1460 if (Assembler::is_simm13(lo) && value == lo) { | |
1461 or3(G0, lo, d); | |
1462 } else if (hi == 0) { | |
1463 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32 | |
1464 if (low10(lo) != 0) | |
1465 or3(d, low10(lo), d); | |
1466 } | |
1467 else if (hi == -1) { | |
1468 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32 | |
1469 xor3(d, low10(lo) ^ ~low10(~0), d); | |
1470 } | |
1471 else if (lo == 0) { | |
1472 if (Assembler::is_simm13(hi)) { | |
1473 or3(G0, hi, d); | |
1474 } else { | |
1475 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32 | |
1476 if (low10(hi) != 0) | |
1477 or3(d, low10(hi), d); | |
1478 } | |
1479 sllx(d, 32, d); | |
1480 } | |
1481 else { | |
1482 Assembler::sethi(hi, tmp); | |
1483 Assembler::sethi(lo, d); // macro assembler version sign-extends | |
1484 if (low10(hi) != 0) | |
1485 or3 (tmp, low10(hi), tmp); | |
1486 if (low10(lo) != 0) | |
1487 or3 ( d, low10(lo), d); | |
1488 sllx(tmp, 32, tmp); | |
1489 or3 (d, tmp, d); | |
1490 } | |
1491 } | |
1492 | |
1493 int MacroAssembler::insts_for_set64(jlong value) { | |
1494 v9_dep(); | |
1495 | |
1496 int hi = (int) (value >> 32); | |
1497 int lo = (int) (value & ~0); | |
1498 int count = 0; | |
1499 | |
1500 // (Matcher::isSimpleConstant64 knows about the following optimizations.) | |
1501 if (Assembler::is_simm13(lo) && value == lo) { | |
1502 count++; | |
1503 } else if (hi == 0) { | |
1504 count++; | |
1505 if (low10(lo) != 0) | |
1506 count++; | |
1507 } | |
1508 else if (hi == -1) { | |
1509 count += 2; | |
1510 } | |
1511 else if (lo == 0) { | |
1512 if (Assembler::is_simm13(hi)) { | |
1513 count++; | |
1514 } else { | |
1515 count++; | |
1516 if (low10(hi) != 0) | |
1517 count++; | |
1518 } | |
1519 count++; | |
1520 } | |
1521 else { | |
1522 count += 2; | |
1523 if (low10(hi) != 0) | |
1524 count++; | |
1525 if (low10(lo) != 0) | |
1526 count++; | |
1527 count += 2; | |
1528 } | |
1529 return count; | |
1530 } | |
1531 | |
1532 // compute size in bytes of sparc frame, given | |
1533 // number of extraWords | |
1534 int MacroAssembler::total_frame_size_in_bytes(int extraWords) { | |
1535 | |
1536 int nWords = frame::memory_parameter_word_sp_offset; | |
1537 | |
1538 nWords += extraWords; | |
1539 | |
1540 if (nWords & 1) ++nWords; // round up to double-word | |
1541 | |
1542 return nWords * BytesPerWord; | |
1543 } | |
1544 | |
1545 | |
1546 // save_frame: given number of "extra" words in frame, | |
1547 // issue approp. save instruction (p 200, v8 manual) | |
1548 | |
1549 void MacroAssembler::save_frame(int extraWords) { | |
1550 int delta = -total_frame_size_in_bytes(extraWords); | |
1551 if (is_simm13(delta)) { | |
1552 save(SP, delta, SP); | |
1553 } else { | |
1554 set(delta, G3_scratch); | |
1555 save(SP, G3_scratch, SP); | |
1556 } | |
1557 } | |
1558 | |
1559 | |
1560 void MacroAssembler::save_frame_c1(int size_in_bytes) { | |
1561 if (is_simm13(-size_in_bytes)) { | |
1562 save(SP, -size_in_bytes, SP); | |
1563 } else { | |
1564 set(-size_in_bytes, G3_scratch); | |
1565 save(SP, G3_scratch, SP); | |
1566 } | |
1567 } | |
1568 | |
1569 | |
1570 void MacroAssembler::save_frame_and_mov(int extraWords, | |
1571 Register s1, Register d1, | |
1572 Register s2, Register d2) { | |
1573 assert_not_delayed(); | |
1574 | |
1575 // The trick here is to use precisely the same memory word | |
1576 // that trap handlers also use to save the register. | |
1577 // This word cannot be used for any other purpose, but | |
1578 // it works fine to save the register's value, whether or not | |
1579 // an interrupt flushes register windows at any given moment! | |
1580 Address s1_addr; | |
1581 if (s1->is_valid() && (s1->is_in() || s1->is_local())) { | |
1582 s1_addr = s1->address_in_saved_window(); | |
1583 st_ptr(s1, s1_addr); | |
1584 } | |
1585 | |
1586 Address s2_addr; | |
1587 if (s2->is_valid() && (s2->is_in() || s2->is_local())) { | |
1588 s2_addr = s2->address_in_saved_window(); | |
1589 st_ptr(s2, s2_addr); | |
1590 } | |
1591 | |
1592 save_frame(extraWords); | |
1593 | |
1594 if (s1_addr.base() == SP) { | |
1595 ld_ptr(s1_addr.after_save(), d1); | |
1596 } else if (s1->is_valid()) { | |
1597 mov(s1->after_save(), d1); | |
1598 } | |
1599 | |
1600 if (s2_addr.base() == SP) { | |
1601 ld_ptr(s2_addr.after_save(), d2); | |
1602 } else if (s2->is_valid()) { | |
1603 mov(s2->after_save(), d2); | |
1604 } | |
1605 } | |
1606 | |
1607 | |
1608 AddressLiteral MacroAssembler::allocate_metadata_address(Metadata* obj) { | |
1609 assert(oop_recorder() != NULL, "this assembler needs a Recorder"); | |
1610 int index = oop_recorder()->allocate_metadata_index(obj); | |
1611 RelocationHolder rspec = metadata_Relocation::spec(index); | |
1612 return AddressLiteral((address)obj, rspec); | |
1613 } | |
1614 | |
1615 AddressLiteral MacroAssembler::constant_metadata_address(Metadata* obj) { | |
1616 assert(oop_recorder() != NULL, "this assembler needs a Recorder"); | |
1617 int index = oop_recorder()->find_index(obj); | |
1618 RelocationHolder rspec = metadata_Relocation::spec(index); | |
1619 return AddressLiteral((address)obj, rspec); | |
1620 } | |
1621 | |
1622 | |
1623 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) { | |
1624 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); | |
1625 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop"); | |
1626 int oop_index = oop_recorder()->find_index(obj); | |
1627 return AddressLiteral(obj, oop_Relocation::spec(oop_index)); | |
1628 } | |
1629 | |
1630 void MacroAssembler::set_narrow_oop(jobject obj, Register d) { | |
1631 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); | |
1632 int oop_index = oop_recorder()->find_index(obj); | |
1633 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
1634 | |
1635 assert_not_delayed(); | |
1636 // Relocation with special format (see relocInfo_sparc.hpp). | |
1637 relocate(rspec, 1); | |
1638 // Assembler::sethi(0x3fffff, d); | |
1639 emit_long( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) ); | |
1640 // Don't add relocation for 'add'. Do patching during 'sethi' processing. | |
1641 add(d, 0x3ff, d); | |
1642 | |
1643 } | |
1644 | |
1645 void MacroAssembler::set_narrow_klass(Klass* k, Register d) { | |
1646 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); | |
1647 int klass_index = oop_recorder()->find_index(k); | |
1648 RelocationHolder rspec = metadata_Relocation::spec(klass_index); | |
1649 narrowOop encoded_k = oopDesc::encode_klass(k); | |
1650 | |
1651 assert_not_delayed(); | |
1652 // Relocation with special format (see relocInfo_sparc.hpp). | |
1653 relocate(rspec, 1); | |
1654 // Assembler::sethi(encoded_k, d); | |
1655 emit_long( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(encoded_k) ); | |
1656 // Don't add relocation for 'add'. Do patching during 'sethi' processing. | |
1657 add(d, low10(encoded_k), d); | |
1658 | |
1659 } | |
1660 | |
1661 void MacroAssembler::align(int modulus) { | |
1662 while (offset() % modulus != 0) nop(); | |
1663 } | |
1664 | |
1665 | |
1666 void MacroAssembler::safepoint() { | |
1667 relocate(breakpoint_Relocation::spec(breakpoint_Relocation::safepoint)); | |
1668 } | |
1669 | |
1670 | |
1671 void RegistersForDebugging::print(outputStream* s) { | |
1672 FlagSetting fs(Debugging, true); | |
1673 int j; | |
1674 for (j = 0; j < 8; ++j) { | |
1675 if (j != 6) { s->print("i%d = ", j); os::print_location(s, i[j]); } | |
1676 else { s->print( "fp = " ); os::print_location(s, i[j]); } | |
1677 } | |
1678 s->cr(); | |
1679 | |
1680 for (j = 0; j < 8; ++j) { | |
1681 s->print("l%d = ", j); os::print_location(s, l[j]); | |
1682 } | |
1683 s->cr(); | |
1684 | |
1685 for (j = 0; j < 8; ++j) { | |
1686 if (j != 6) { s->print("o%d = ", j); os::print_location(s, o[j]); } | |
1687 else { s->print( "sp = " ); os::print_location(s, o[j]); } | |
1688 } | |
1689 s->cr(); | |
1690 | |
1691 for (j = 0; j < 8; ++j) { | |
1692 s->print("g%d = ", j); os::print_location(s, g[j]); | |
1693 } | |
1694 s->cr(); | |
1695 | |
1696 // print out floats with compression | |
1697 for (j = 0; j < 32; ) { | |
1698 jfloat val = f[j]; | |
1699 int last = j; | |
1700 for ( ; last+1 < 32; ++last ) { | |
1701 char b1[1024], b2[1024]; | |
1702 sprintf(b1, "%f", val); | |
1703 sprintf(b2, "%f", f[last+1]); | |
1704 if (strcmp(b1, b2)) | |
1705 break; | |
1706 } | |
1707 s->print("f%d", j); | |
1708 if ( j != last ) s->print(" - f%d", last); | |
1709 s->print(" = %f", val); | |
1710 s->fill_to(25); | |
1711 s->print_cr(" (0x%x)", val); | |
1712 j = last + 1; | |
1713 } | |
1714 s->cr(); | |
1715 | |
1716 // and doubles (evens only) | |
1717 for (j = 0; j < 32; ) { | |
1718 jdouble val = d[j]; | |
1719 int last = j; | |
1720 for ( ; last+1 < 32; ++last ) { | |
1721 char b1[1024], b2[1024]; | |
1722 sprintf(b1, "%f", val); | |
1723 sprintf(b2, "%f", d[last+1]); | |
1724 if (strcmp(b1, b2)) | |
1725 break; | |
1726 } | |
1727 s->print("d%d", 2 * j); | |
1728 if ( j != last ) s->print(" - d%d", last); | |
1729 s->print(" = %f", val); | |
1730 s->fill_to(30); | |
1731 s->print("(0x%x)", *(int*)&val); | |
1732 s->fill_to(42); | |
1733 s->print_cr("(0x%x)", *(1 + (int*)&val)); | |
1734 j = last + 1; | |
1735 } | |
1736 s->cr(); | |
1737 } | |
1738 | |
1739 void RegistersForDebugging::save_registers(MacroAssembler* a) { | |
1740 a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0); | |
1741 a->flush_windows(); | |
1742 int i; | |
1743 for (i = 0; i < 8; ++i) { | |
1744 a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i)); | |
1745 a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i)); | |
1746 a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i)); | |
1747 a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i)); | |
1748 } | |
1749 for (i = 0; i < 32; ++i) { | |
1750 a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i)); | |
1751 } | |
1752 for (i = 0; i < (VM_Version::v9_instructions_work() ? 64 : 32); i += 2) { | |
1753 a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i)); | |
1754 } | |
1755 } | |
1756 | |
1757 void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) { | |
1758 for (int i = 1; i < 8; ++i) { | |
1759 a->ld_ptr(r, g_offset(i), as_gRegister(i)); | |
1760 } | |
1761 for (int j = 0; j < 32; ++j) { | |
1762 a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j)); | |
1763 } | |
1764 for (int k = 0; k < (VM_Version::v9_instructions_work() ? 64 : 32); k += 2) { | |
1765 a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k)); | |
1766 } | |
1767 } | |
1768 | |
1769 | |
1770 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack | |
1771 void MacroAssembler::push_fTOS() { | |
1772 // %%%%%% need to implement this | |
1773 } | |
1774 | |
1775 // pops double TOS element from CPU stack and pushes on FPU stack | |
1776 void MacroAssembler::pop_fTOS() { | |
1777 // %%%%%% need to implement this | |
1778 } | |
1779 | |
1780 void MacroAssembler::empty_FPU_stack() { | |
1781 // %%%%%% need to implement this | |
1782 } | |
1783 | |
1784 void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) { | |
1785 // plausibility check for oops | |
1786 if (!VerifyOops) return; | |
1787 | |
1788 if (reg == G0) return; // always NULL, which is always an oop | |
1789 | |
1790 BLOCK_COMMENT("verify_oop {"); | |
1791 char buffer[64]; | |
1792 #ifdef COMPILER1 | |
1793 if (CommentedAssembly) { | |
1794 snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset()); | |
1795 block_comment(buffer); | |
1796 } | |
1797 #endif | |
1798 | |
1799 int len = strlen(file) + strlen(msg) + 1 + 4; | |
1800 sprintf(buffer, "%d", line); | |
1801 len += strlen(buffer); | |
1802 sprintf(buffer, " at offset %d ", offset()); | |
1803 len += strlen(buffer); | |
1804 char * real_msg = new char[len]; | |
1805 sprintf(real_msg, "%s%s(%s:%d)", msg, buffer, file, line); | |
1806 | |
1807 // Call indirectly to solve generation ordering problem | |
1808 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address()); | |
1809 | |
1810 // Make some space on stack above the current register window. | |
1811 // Enough to hold 8 64-bit registers. | |
1812 add(SP,-8*8,SP); | |
1813 | |
1814 // Save some 64-bit registers; a normal 'save' chops the heads off | |
1815 // of 64-bit longs in the 32-bit build. | |
1816 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); | |
1817 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); | |
1818 mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed | |
1819 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); | |
1820 | |
1821 // Size of set() should stay the same | |
1822 patchable_set((intptr_t)real_msg, O1); | |
1823 // Load address to call to into O7 | |
1824 load_ptr_contents(a, O7); | |
1825 // Register call to verify_oop_subroutine | |
1826 callr(O7, G0); | |
1827 delayed()->nop(); | |
1828 // recover frame size | |
1829 add(SP, 8*8,SP); | |
1830 BLOCK_COMMENT("} verify_oop"); | |
1831 } | |
1832 | |
1833 void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) { | |
1834 // plausibility check for oops | |
1835 if (!VerifyOops) return; | |
1836 | |
1837 char buffer[64]; | |
1838 sprintf(buffer, "%d", line); | |
1839 int len = strlen(file) + strlen(msg) + 1 + 4 + strlen(buffer); | |
1840 sprintf(buffer, " at SP+%d ", addr.disp()); | |
1841 len += strlen(buffer); | |
1842 char * real_msg = new char[len]; | |
1843 sprintf(real_msg, "%s at SP+%d (%s:%d)", msg, addr.disp(), file, line); | |
1844 | |
1845 // Call indirectly to solve generation ordering problem | |
1846 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address()); | |
1847 | |
1848 // Make some space on stack above the current register window. | |
1849 // Enough to hold 8 64-bit registers. | |
1850 add(SP,-8*8,SP); | |
1851 | |
1852 // Save some 64-bit registers; a normal 'save' chops the heads off | |
1853 // of 64-bit longs in the 32-bit build. | |
1854 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); | |
1855 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); | |
1856 ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed | |
1857 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); | |
1858 | |
1859 // Size of set() should stay the same | |
1860 patchable_set((intptr_t)real_msg, O1); | |
1861 // Load address to call to into O7 | |
1862 load_ptr_contents(a, O7); | |
1863 // Register call to verify_oop_subroutine | |
1864 callr(O7, G0); | |
1865 delayed()->nop(); | |
1866 // recover frame size | |
1867 add(SP, 8*8,SP); | |
1868 } | |
1869 | |
1870 // side-door communication with signalHandler in os_solaris.cpp | |
1871 address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL }; | |
1872 | |
1873 // This macro is expanded just once; it creates shared code. Contract: | |
1874 // receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY | |
1875 // registers, including flags. May not use a register 'save', as this blows | |
1876 // the high bits of the O-regs if they contain Long values. Acts as a 'leaf' | |
1877 // call. | |
1878 void MacroAssembler::verify_oop_subroutine() { | |
1879 assert( VM_Version::v9_instructions_work(), "VerifyOops not supported for V8" ); | |
1880 | |
1881 // Leaf call; no frame. | |
1882 Label succeed, fail, null_or_fail; | |
1883 | |
1884 // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home). | |
1885 // O0 is now the oop to be checked. O7 is the return address. | |
1886 Register O0_obj = O0; | |
1887 | |
1888 // Save some more registers for temps. | |
1889 stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8); | |
1890 stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8); | |
1891 stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8); | |
1892 stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8); | |
1893 | |
1894 // Save flags | |
1895 Register O5_save_flags = O5; | |
1896 rdccr( O5_save_flags ); | |
1897 | |
1898 { // count number of verifies | |
1899 Register O2_adr = O2; | |
1900 Register O3_accum = O3; | |
1901 inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum); | |
1902 } | |
1903 | |
1904 Register O2_mask = O2; | |
1905 Register O3_bits = O3; | |
1906 Register O4_temp = O4; | |
1907 | |
1908 // mark lower end of faulting range | |
1909 assert(_verify_oop_implicit_branch[0] == NULL, "set once"); | |
1910 _verify_oop_implicit_branch[0] = pc(); | |
1911 | |
1912 // We can't check the mark oop because it could be in the process of | |
1913 // locking or unlocking while this is running. | |
1914 set(Universe::verify_oop_mask (), O2_mask); | |
1915 set(Universe::verify_oop_bits (), O3_bits); | |
1916 | |
1917 // assert((obj & oop_mask) == oop_bits); | |
1918 and3(O0_obj, O2_mask, O4_temp); | |
1919 cmp_and_brx_short(O4_temp, O3_bits, notEqual, pn, null_or_fail); | |
1920 | |
1921 if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) { | |
1922 // the null_or_fail case is useless; must test for null separately | |
1923 br_null_short(O0_obj, pn, succeed); | |
1924 } | |
1925 | |
1926 // Check the Klass* of this object for being in the right area of memory. | |
1927 // Cannot do the load in the delay above slot in case O0 is null | |
1928 load_klass(O0_obj, O0_obj); | |
1929 // assert((klass != NULL) | |
1930 br_null_short(O0_obj, pn, fail); | |
1931 // TODO: Future assert that klass is lower 4g memory for UseCompressedKlassPointers | |
1932 | |
1933 wrccr( O5_save_flags ); // Restore CCR's | |
1934 | |
1935 // mark upper end of faulting range | |
1936 _verify_oop_implicit_branch[1] = pc(); | |
1937 | |
1938 //----------------------- | |
1939 // all tests pass | |
1940 bind(succeed); | |
1941 | |
1942 // Restore prior 64-bit registers | |
1943 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0); | |
1944 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1); | |
1945 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2); | |
1946 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3); | |
1947 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4); | |
1948 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5); | |
1949 | |
1950 retl(); // Leaf return; restore prior O7 in delay slot | |
1951 delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7); | |
1952 | |
1953 //----------------------- | |
1954 bind(null_or_fail); // nulls are less common but OK | |
1955 br_null(O0_obj, false, pt, succeed); | |
1956 delayed()->wrccr( O5_save_flags ); // Restore CCR's | |
1957 | |
1958 //----------------------- | |
1959 // report failure: | |
1960 bind(fail); | |
1961 _verify_oop_implicit_branch[2] = pc(); | |
1962 | |
1963 wrccr( O5_save_flags ); // Restore CCR's | |
1964 | |
1965 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); | |
1966 | |
1967 // stop_subroutine expects message pointer in I1. | |
1968 mov(I1, O1); | |
1969 | |
1970 // Restore prior 64-bit registers | |
1971 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0); | |
1972 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1); | |
1973 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2); | |
1974 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3); | |
1975 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4); | |
1976 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5); | |
1977 | |
1978 // factor long stop-sequence into subroutine to save space | |
1979 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); | |
1980 | |
1981 // call indirectly to solve generation ordering problem | |
1982 AddressLiteral al(StubRoutines::Sparc::stop_subroutine_entry_address()); | |
1983 load_ptr_contents(al, O5); | |
1984 jmpl(O5, 0, O7); | |
1985 delayed()->nop(); | |
1986 } | |
1987 | |
1988 | |
1989 void MacroAssembler::stop(const char* msg) { | |
1990 // save frame first to get O7 for return address | |
1991 // add one word to size in case struct is odd number of words long | |
1992 // It must be doubleword-aligned for storing doubles into it. | |
1993 | |
1994 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); | |
1995 | |
1996 // stop_subroutine expects message pointer in I1. | |
1997 // Size of set() should stay the same | |
1998 patchable_set((intptr_t)msg, O1); | |
1999 | |
2000 // factor long stop-sequence into subroutine to save space | |
2001 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); | |
2002 | |
2003 // call indirectly to solve generation ordering problem | |
2004 AddressLiteral a(StubRoutines::Sparc::stop_subroutine_entry_address()); | |
2005 load_ptr_contents(a, O5); | |
2006 jmpl(O5, 0, O7); | |
2007 delayed()->nop(); | |
2008 | |
2009 breakpoint_trap(); // make stop actually stop rather than writing | |
2010 // unnoticeable results in the output files. | |
2011 | |
2012 // restore(); done in callee to save space! | |
2013 } | |
2014 | |
2015 | |
2016 void MacroAssembler::warn(const char* msg) { | |
2017 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); | |
2018 RegistersForDebugging::save_registers(this); | |
2019 mov(O0, L0); | |
2020 // Size of set() should stay the same | |
2021 patchable_set((intptr_t)msg, O0); | |
2022 call( CAST_FROM_FN_PTR(address, warning) ); | |
2023 delayed()->nop(); | |
2024 // ret(); | |
2025 // delayed()->restore(); | |
2026 RegistersForDebugging::restore_registers(this, L0); | |
2027 restore(); | |
2028 } | |
2029 | |
2030 | |
2031 void MacroAssembler::untested(const char* what) { | |
2032 // We must be able to turn interactive prompting off | |
2033 // in order to run automated test scripts on the VM | |
2034 // Use the flag ShowMessageBoxOnError | |
2035 | |
2036 char* b = new char[1024]; | |
2037 sprintf(b, "untested: %s", what); | |
2038 | |
2039 if (ShowMessageBoxOnError) { STOP(b); } | |
2040 else { warn(b); } | |
2041 } | |
2042 | |
2043 | |
2044 void MacroAssembler::stop_subroutine() { | |
2045 RegistersForDebugging::save_registers(this); | |
2046 | |
2047 // for the sake of the debugger, stick a PC on the current frame | |
2048 // (this assumes that the caller has performed an extra "save") | |
2049 mov(I7, L7); | |
2050 add(O7, -7 * BytesPerInt, I7); | |
2051 | |
2052 save_frame(); // one more save to free up another O7 register | |
2053 mov(I0, O1); // addr of reg save area | |
2054 | |
2055 // We expect pointer to message in I1. Caller must set it up in O1 | |
2056 mov(I1, O0); // get msg | |
2057 call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type); | |
2058 delayed()->nop(); | |
2059 | |
2060 restore(); | |
2061 | |
2062 RegistersForDebugging::restore_registers(this, O0); | |
2063 | |
2064 save_frame(0); | |
2065 call(CAST_FROM_FN_PTR(address,breakpoint)); | |
2066 delayed()->nop(); | |
2067 restore(); | |
2068 | |
2069 mov(L7, I7); | |
2070 retl(); | |
2071 delayed()->restore(); // see stop above | |
2072 } | |
2073 | |
2074 | |
2075 void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) { | |
2076 if ( ShowMessageBoxOnError ) { | |
2077 JavaThread* thread = JavaThread::current(); | |
2078 JavaThreadState saved_state = thread->thread_state(); | |
2079 thread->set_thread_state(_thread_in_vm); | |
2080 { | |
2081 // In order to get locks work, we need to fake a in_VM state | |
2082 ttyLocker ttyl; | |
2083 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg); | |
2084 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
2085 BytecodeCounter::print(); | |
2086 } | |
2087 if (os::message_box(msg, "Execution stopped, print registers?")) | |
2088 regs->print(::tty); | |
2089 } | |
2090 BREAKPOINT; | |
2091 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state); | |
2092 } | |
2093 else { | |
2094 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
2095 } | |
2096 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); | |
2097 } | |
2098 | |
2099 #ifndef PRODUCT | |
2100 void MacroAssembler::test() { | |
2101 ResourceMark rm; | |
2102 | |
2103 CodeBuffer cb("test", 10000, 10000); | |
2104 MacroAssembler* a = new MacroAssembler(&cb); | |
2105 VM_Version::allow_all(); | |
2106 a->test_v9(); | |
2107 a->test_v8_onlys(); | |
2108 VM_Version::revert(); | |
2109 | |
2110 StubRoutines::Sparc::test_stop_entry()(); | |
2111 } | |
2112 #endif | |
2113 | |
2114 | |
2115 void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) { | |
2116 subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words? | |
2117 Label no_extras; | |
2118 br( negative, true, pt, no_extras ); // if neg, clear reg | |
2119 delayed()->set(0, Rresult); // annuled, so only if taken | |
2120 bind( no_extras ); | |
2121 } | |
2122 | |
2123 | |
2124 void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) { | |
2125 #ifdef _LP64 | |
2126 add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult); | |
2127 #else | |
2128 add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult); | |
2129 #endif | |
2130 bclr(1, Rresult); | |
2131 sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes | |
2132 } | |
2133 | |
2134 | |
2135 void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) { | |
2136 calc_frame_size(Rextra_words, Rresult); | |
2137 neg(Rresult); | |
2138 save(SP, Rresult, SP); | |
2139 } | |
2140 | |
2141 | |
2142 // --------------------------------------------------------- | |
2143 Assembler::RCondition cond2rcond(Assembler::Condition c) { | |
2144 switch (c) { | |
2145 /*case zero: */ | |
2146 case Assembler::equal: return Assembler::rc_z; | |
2147 case Assembler::lessEqual: return Assembler::rc_lez; | |
2148 case Assembler::less: return Assembler::rc_lz; | |
2149 /*case notZero:*/ | |
2150 case Assembler::notEqual: return Assembler::rc_nz; | |
2151 case Assembler::greater: return Assembler::rc_gz; | |
2152 case Assembler::greaterEqual: return Assembler::rc_gez; | |
2153 } | |
2154 ShouldNotReachHere(); | |
2155 return Assembler::rc_z; | |
2156 } | |
2157 | |
2158 // compares (32 bit) register with zero and branches. NOT FOR USE WITH 64-bit POINTERS | |
2159 void MacroAssembler::cmp_zero_and_br(Condition c, Register s1, Label& L, bool a, Predict p) { | |
2160 tst(s1); | |
2161 br (c, a, p, L); | |
2162 } | |
2163 | |
2164 // Compares a pointer register with zero and branches on null. | |
2165 // Does a test & branch on 32-bit systems and a register-branch on 64-bit. | |
2166 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) { | |
2167 assert_not_delayed(); | |
2168 #ifdef _LP64 | |
2169 bpr( rc_z, a, p, s1, L ); | |
2170 #else | |
2171 tst(s1); | |
2172 br ( zero, a, p, L ); | |
2173 #endif | |
2174 } | |
2175 | |
2176 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) { | |
2177 assert_not_delayed(); | |
2178 #ifdef _LP64 | |
2179 bpr( rc_nz, a, p, s1, L ); | |
2180 #else | |
2181 tst(s1); | |
2182 br ( notZero, a, p, L ); | |
2183 #endif | |
2184 } | |
2185 | |
2186 // Compare registers and branch with nop in delay slot or cbcond without delay slot. | |
2187 | |
2188 // Compare integer (32 bit) values (icc only). | |
2189 void MacroAssembler::cmp_and_br_short(Register s1, Register s2, Condition c, | |
2190 Predict p, Label& L) { | |
2191 assert_not_delayed(); | |
2192 if (use_cbcond(L)) { | |
2193 Assembler::cbcond(c, icc, s1, s2, L); | |
2194 } else { | |
2195 cmp(s1, s2); | |
2196 br(c, false, p, L); | |
2197 delayed()->nop(); | |
2198 } | |
2199 } | |
2200 | |
2201 // Compare integer (32 bit) values (icc only). | |
2202 void MacroAssembler::cmp_and_br_short(Register s1, int simm13a, Condition c, | |
2203 Predict p, Label& L) { | |
2204 assert_not_delayed(); | |
2205 if (is_simm(simm13a,5) && use_cbcond(L)) { | |
2206 Assembler::cbcond(c, icc, s1, simm13a, L); | |
2207 } else { | |
2208 cmp(s1, simm13a); | |
2209 br(c, false, p, L); | |
2210 delayed()->nop(); | |
2211 } | |
2212 } | |
2213 | |
2214 // Branch that tests xcc in LP64 and icc in !LP64 | |
2215 void MacroAssembler::cmp_and_brx_short(Register s1, Register s2, Condition c, | |
2216 Predict p, Label& L) { | |
2217 assert_not_delayed(); | |
2218 if (use_cbcond(L)) { | |
2219 Assembler::cbcond(c, ptr_cc, s1, s2, L); | |
2220 } else { | |
2221 cmp(s1, s2); | |
2222 brx(c, false, p, L); | |
2223 delayed()->nop(); | |
2224 } | |
2225 } | |
2226 | |
2227 // Branch that tests xcc in LP64 and icc in !LP64 | |
2228 void MacroAssembler::cmp_and_brx_short(Register s1, int simm13a, Condition c, | |
2229 Predict p, Label& L) { | |
2230 assert_not_delayed(); | |
2231 if (is_simm(simm13a,5) && use_cbcond(L)) { | |
2232 Assembler::cbcond(c, ptr_cc, s1, simm13a, L); | |
2233 } else { | |
2234 cmp(s1, simm13a); | |
2235 brx(c, false, p, L); | |
2236 delayed()->nop(); | |
2237 } | |
2238 } | |
2239 | |
2240 // Short branch version for compares a pointer with zero. | |
2241 | |
2242 void MacroAssembler::br_null_short(Register s1, Predict p, Label& L) { | |
2243 assert_not_delayed(); | |
2244 if (use_cbcond(L)) { | |
2245 Assembler::cbcond(zero, ptr_cc, s1, 0, L); | |
2246 return; | |
2247 } | |
2248 br_null(s1, false, p, L); | |
2249 delayed()->nop(); | |
2250 } | |
2251 | |
2252 void MacroAssembler::br_notnull_short(Register s1, Predict p, Label& L) { | |
2253 assert_not_delayed(); | |
2254 if (use_cbcond(L)) { | |
2255 Assembler::cbcond(notZero, ptr_cc, s1, 0, L); | |
2256 return; | |
2257 } | |
2258 br_notnull(s1, false, p, L); | |
2259 delayed()->nop(); | |
2260 } | |
2261 | |
2262 // Unconditional short branch | |
2263 void MacroAssembler::ba_short(Label& L) { | |
2264 if (use_cbcond(L)) { | |
2265 Assembler::cbcond(equal, icc, G0, G0, L); | |
2266 return; | |
2267 } | |
2268 br(always, false, pt, L); | |
2269 delayed()->nop(); | |
2270 } | |
2271 | |
2272 // instruction sequences factored across compiler & interpreter | |
2273 | |
2274 | |
2275 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low, | |
2276 Register Rb_hi, Register Rb_low, | |
2277 Register Rresult) { | |
2278 | |
2279 Label check_low_parts, done; | |
2280 | |
2281 cmp(Ra_hi, Rb_hi ); // compare hi parts | |
2282 br(equal, true, pt, check_low_parts); | |
2283 delayed()->cmp(Ra_low, Rb_low); // test low parts | |
2284 | |
2285 // And, with an unsigned comparison, it does not matter if the numbers | |
2286 // are negative or not. | |
2287 // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff. | |
2288 // The second one is bigger (unsignedly). | |
2289 | |
2290 // Other notes: The first move in each triplet can be unconditional | |
2291 // (and therefore probably prefetchable). | |
2292 // And the equals case for the high part does not need testing, | |
2293 // since that triplet is reached only after finding the high halves differ. | |
2294 | |
2295 if (VM_Version::v9_instructions_work()) { | |
2296 mov(-1, Rresult); | |
2297 ba(done); delayed()-> movcc(greater, false, icc, 1, Rresult); | |
2298 } else { | |
2299 br(less, true, pt, done); delayed()-> set(-1, Rresult); | |
2300 br(greater, true, pt, done); delayed()-> set( 1, Rresult); | |
2301 } | |
2302 | |
2303 bind( check_low_parts ); | |
2304 | |
2305 if (VM_Version::v9_instructions_work()) { | |
2306 mov( -1, Rresult); | |
2307 movcc(equal, false, icc, 0, Rresult); | |
2308 movcc(greaterUnsigned, false, icc, 1, Rresult); | |
2309 } else { | |
2310 set(-1, Rresult); | |
2311 br(equal, true, pt, done); delayed()->set( 0, Rresult); | |
2312 br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult); | |
2313 } | |
2314 bind( done ); | |
2315 } | |
2316 | |
2317 void MacroAssembler::lneg( Register Rhi, Register Rlow ) { | |
2318 subcc( G0, Rlow, Rlow ); | |
2319 subc( G0, Rhi, Rhi ); | |
2320 } | |
2321 | |
2322 void MacroAssembler::lshl( Register Rin_high, Register Rin_low, | |
2323 Register Rcount, | |
2324 Register Rout_high, Register Rout_low, | |
2325 Register Rtemp ) { | |
2326 | |
2327 | |
2328 Register Ralt_count = Rtemp; | |
2329 Register Rxfer_bits = Rtemp; | |
2330 | |
2331 assert( Ralt_count != Rin_high | |
2332 && Ralt_count != Rin_low | |
2333 && Ralt_count != Rcount | |
2334 && Rxfer_bits != Rin_low | |
2335 && Rxfer_bits != Rin_high | |
2336 && Rxfer_bits != Rcount | |
2337 && Rxfer_bits != Rout_low | |
2338 && Rout_low != Rin_high, | |
2339 "register alias checks"); | |
2340 | |
2341 Label big_shift, done; | |
2342 | |
2343 // This code can be optimized to use the 64 bit shifts in V9. | |
2344 // Here we use the 32 bit shifts. | |
2345 | |
2346 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits | |
2347 subcc(Rcount, 31, Ralt_count); | |
2348 br(greater, true, pn, big_shift); | |
2349 delayed()->dec(Ralt_count); | |
2350 | |
2351 // shift < 32 bits, Ralt_count = Rcount-31 | |
2352 | |
2353 // We get the transfer bits by shifting right by 32-count the low | |
2354 // register. This is done by shifting right by 31-count and then by one | |
2355 // more to take care of the special (rare) case where count is zero | |
2356 // (shifting by 32 would not work). | |
2357 | |
2358 neg(Ralt_count); | |
2359 | |
2360 // The order of the next two instructions is critical in the case where | |
2361 // Rin and Rout are the same and should not be reversed. | |
2362 | |
2363 srl(Rin_low, Ralt_count, Rxfer_bits); // shift right by 31-count | |
2364 if (Rcount != Rout_low) { | |
2365 sll(Rin_low, Rcount, Rout_low); // low half | |
2366 } | |
2367 sll(Rin_high, Rcount, Rout_high); | |
2368 if (Rcount == Rout_low) { | |
2369 sll(Rin_low, Rcount, Rout_low); // low half | |
2370 } | |
2371 srl(Rxfer_bits, 1, Rxfer_bits ); // shift right by one more | |
2372 ba(done); | |
2373 delayed()->or3(Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low | |
2374 | |
2375 // shift >= 32 bits, Ralt_count = Rcount-32 | |
2376 bind(big_shift); | |
2377 sll(Rin_low, Ralt_count, Rout_high ); | |
2378 clr(Rout_low); | |
2379 | |
2380 bind(done); | |
2381 } | |
2382 | |
2383 | |
2384 void MacroAssembler::lshr( Register Rin_high, Register Rin_low, | |
2385 Register Rcount, | |
2386 Register Rout_high, Register Rout_low, | |
2387 Register Rtemp ) { | |
2388 | |
2389 Register Ralt_count = Rtemp; | |
2390 Register Rxfer_bits = Rtemp; | |
2391 | |
2392 assert( Ralt_count != Rin_high | |
2393 && Ralt_count != Rin_low | |
2394 && Ralt_count != Rcount | |
2395 && Rxfer_bits != Rin_low | |
2396 && Rxfer_bits != Rin_high | |
2397 && Rxfer_bits != Rcount | |
2398 && Rxfer_bits != Rout_high | |
2399 && Rout_high != Rin_low, | |
2400 "register alias checks"); | |
2401 | |
2402 Label big_shift, done; | |
2403 | |
2404 // This code can be optimized to use the 64 bit shifts in V9. | |
2405 // Here we use the 32 bit shifts. | |
2406 | |
2407 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits | |
2408 subcc(Rcount, 31, Ralt_count); | |
2409 br(greater, true, pn, big_shift); | |
2410 delayed()->dec(Ralt_count); | |
2411 | |
2412 // shift < 32 bits, Ralt_count = Rcount-31 | |
2413 | |
2414 // We get the transfer bits by shifting left by 32-count the high | |
2415 // register. This is done by shifting left by 31-count and then by one | |
2416 // more to take care of the special (rare) case where count is zero | |
2417 // (shifting by 32 would not work). | |
2418 | |
2419 neg(Ralt_count); | |
2420 if (Rcount != Rout_low) { | |
2421 srl(Rin_low, Rcount, Rout_low); | |
2422 } | |
2423 | |
2424 // The order of the next two instructions is critical in the case where | |
2425 // Rin and Rout are the same and should not be reversed. | |
2426 | |
2427 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count | |
2428 sra(Rin_high, Rcount, Rout_high ); // high half | |
2429 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more | |
2430 if (Rcount == Rout_low) { | |
2431 srl(Rin_low, Rcount, Rout_low); | |
2432 } | |
2433 ba(done); | |
2434 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high | |
2435 | |
2436 // shift >= 32 bits, Ralt_count = Rcount-32 | |
2437 bind(big_shift); | |
2438 | |
2439 sra(Rin_high, Ralt_count, Rout_low); | |
2440 sra(Rin_high, 31, Rout_high); // sign into hi | |
2441 | |
2442 bind( done ); | |
2443 } | |
2444 | |
2445 | |
2446 | |
2447 void MacroAssembler::lushr( Register Rin_high, Register Rin_low, | |
2448 Register Rcount, | |
2449 Register Rout_high, Register Rout_low, | |
2450 Register Rtemp ) { | |
2451 | |
2452 Register Ralt_count = Rtemp; | |
2453 Register Rxfer_bits = Rtemp; | |
2454 | |
2455 assert( Ralt_count != Rin_high | |
2456 && Ralt_count != Rin_low | |
2457 && Ralt_count != Rcount | |
2458 && Rxfer_bits != Rin_low | |
2459 && Rxfer_bits != Rin_high | |
2460 && Rxfer_bits != Rcount | |
2461 && Rxfer_bits != Rout_high | |
2462 && Rout_high != Rin_low, | |
2463 "register alias checks"); | |
2464 | |
2465 Label big_shift, done; | |
2466 | |
2467 // This code can be optimized to use the 64 bit shifts in V9. | |
2468 // Here we use the 32 bit shifts. | |
2469 | |
2470 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits | |
2471 subcc(Rcount, 31, Ralt_count); | |
2472 br(greater, true, pn, big_shift); | |
2473 delayed()->dec(Ralt_count); | |
2474 | |
2475 // shift < 32 bits, Ralt_count = Rcount-31 | |
2476 | |
2477 // We get the transfer bits by shifting left by 32-count the high | |
2478 // register. This is done by shifting left by 31-count and then by one | |
2479 // more to take care of the special (rare) case where count is zero | |
2480 // (shifting by 32 would not work). | |
2481 | |
2482 neg(Ralt_count); | |
2483 if (Rcount != Rout_low) { | |
2484 srl(Rin_low, Rcount, Rout_low); | |
2485 } | |
2486 | |
2487 // The order of the next two instructions is critical in the case where | |
2488 // Rin and Rout are the same and should not be reversed. | |
2489 | |
2490 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count | |
2491 srl(Rin_high, Rcount, Rout_high ); // high half | |
2492 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more | |
2493 if (Rcount == Rout_low) { | |
2494 srl(Rin_low, Rcount, Rout_low); | |
2495 } | |
2496 ba(done); | |
2497 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high | |
2498 | |
2499 // shift >= 32 bits, Ralt_count = Rcount-32 | |
2500 bind(big_shift); | |
2501 | |
2502 srl(Rin_high, Ralt_count, Rout_low); | |
2503 clr(Rout_high); | |
2504 | |
2505 bind( done ); | |
2506 } | |
2507 | |
2508 #ifdef _LP64 | |
2509 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) { | |
2510 cmp(Ra, Rb); | |
2511 mov(-1, Rresult); | |
2512 movcc(equal, false, xcc, 0, Rresult); | |
2513 movcc(greater, false, xcc, 1, Rresult); | |
2514 } | |
2515 #endif | |
2516 | |
2517 | |
2518 void MacroAssembler::load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed) { | |
2519 switch (size_in_bytes) { | |
2520 case 8: ld_long(src, dst); break; | |
2521 case 4: ld( src, dst); break; | |
2522 case 2: is_signed ? ldsh(src, dst) : lduh(src, dst); break; | |
2523 case 1: is_signed ? ldsb(src, dst) : ldub(src, dst); break; | |
2524 default: ShouldNotReachHere(); | |
2525 } | |
2526 } | |
2527 | |
2528 void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) { | |
2529 switch (size_in_bytes) { | |
2530 case 8: st_long(src, dst); break; | |
2531 case 4: st( src, dst); break; | |
2532 case 2: sth( src, dst); break; | |
2533 case 1: stb( src, dst); break; | |
2534 default: ShouldNotReachHere(); | |
2535 } | |
2536 } | |
2537 | |
2538 | |
2539 void MacroAssembler::float_cmp( bool is_float, int unordered_result, | |
2540 FloatRegister Fa, FloatRegister Fb, | |
2541 Register Rresult) { | |
2542 | |
2543 fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb); | |
2544 | |
2545 Condition lt = unordered_result == -1 ? f_unorderedOrLess : f_less; | |
2546 Condition eq = f_equal; | |
2547 Condition gt = unordered_result == 1 ? f_unorderedOrGreater : f_greater; | |
2548 | |
2549 if (VM_Version::v9_instructions_work()) { | |
2550 | |
2551 mov(-1, Rresult); | |
2552 movcc(eq, true, fcc0, 0, Rresult); | |
2553 movcc(gt, true, fcc0, 1, Rresult); | |
2554 | |
2555 } else { | |
2556 Label done; | |
2557 | |
2558 set( -1, Rresult ); | |
2559 //fb(lt, true, pn, done); delayed()->set( -1, Rresult ); | |
2560 fb( eq, true, pn, done); delayed()->set( 0, Rresult ); | |
2561 fb( gt, true, pn, done); delayed()->set( 1, Rresult ); | |
2562 | |
2563 bind (done); | |
2564 } | |
2565 } | |
2566 | |
2567 | |
2568 void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) | |
2569 { | |
2570 if (VM_Version::v9_instructions_work()) { | |
2571 Assembler::fneg(w, s, d); | |
2572 } else { | |
2573 if (w == FloatRegisterImpl::S) { | |
2574 Assembler::fneg(w, s, d); | |
2575 } else if (w == FloatRegisterImpl::D) { | |
2576 // number() does a sanity check on the alignment. | |
2577 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && | |
2578 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); | |
2579 | |
2580 Assembler::fneg(FloatRegisterImpl::S, s, d); | |
2581 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2582 } else { | |
2583 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); | |
2584 | |
2585 // number() does a sanity check on the alignment. | |
2586 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && | |
2587 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); | |
2588 | |
2589 Assembler::fneg(FloatRegisterImpl::S, s, d); | |
2590 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2591 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); | |
2592 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); | |
2593 } | |
2594 } | |
2595 } | |
2596 | |
2597 void MacroAssembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) | |
2598 { | |
2599 if (VM_Version::v9_instructions_work()) { | |
2600 Assembler::fmov(w, s, d); | |
2601 } else { | |
2602 if (w == FloatRegisterImpl::S) { | |
2603 Assembler::fmov(w, s, d); | |
2604 } else if (w == FloatRegisterImpl::D) { | |
2605 // number() does a sanity check on the alignment. | |
2606 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && | |
2607 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); | |
2608 | |
2609 Assembler::fmov(FloatRegisterImpl::S, s, d); | |
2610 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2611 } else { | |
2612 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); | |
2613 | |
2614 // number() does a sanity check on the alignment. | |
2615 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && | |
2616 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); | |
2617 | |
2618 Assembler::fmov(FloatRegisterImpl::S, s, d); | |
2619 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2620 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); | |
2621 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); | |
2622 } | |
2623 } | |
2624 } | |
2625 | |
2626 void MacroAssembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) | |
2627 { | |
2628 if (VM_Version::v9_instructions_work()) { | |
2629 Assembler::fabs(w, s, d); | |
2630 } else { | |
2631 if (w == FloatRegisterImpl::S) { | |
2632 Assembler::fabs(w, s, d); | |
2633 } else if (w == FloatRegisterImpl::D) { | |
2634 // number() does a sanity check on the alignment. | |
2635 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && | |
2636 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); | |
2637 | |
2638 Assembler::fabs(FloatRegisterImpl::S, s, d); | |
2639 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2640 } else { | |
2641 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); | |
2642 | |
2643 // number() does a sanity check on the alignment. | |
2644 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && | |
2645 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); | |
2646 | |
2647 Assembler::fabs(FloatRegisterImpl::S, s, d); | |
2648 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2649 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); | |
2650 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); | |
2651 } | |
2652 } | |
2653 } | |
2654 | |
2655 void MacroAssembler::save_all_globals_into_locals() { | |
2656 mov(G1,L1); | |
2657 mov(G2,L2); | |
2658 mov(G3,L3); | |
2659 mov(G4,L4); | |
2660 mov(G5,L5); | |
2661 mov(G6,L6); | |
2662 mov(G7,L7); | |
2663 } | |
2664 | |
2665 void MacroAssembler::restore_globals_from_locals() { | |
2666 mov(L1,G1); | |
2667 mov(L2,G2); | |
2668 mov(L3,G3); | |
2669 mov(L4,G4); | |
2670 mov(L5,G5); | |
2671 mov(L6,G6); | |
2672 mov(L7,G7); | |
2673 } | |
2674 | |
2675 // Use for 64 bit operation. | |
2676 void MacroAssembler::casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm) | |
2677 { | |
2678 // store ptr_reg as the new top value | |
2679 #ifdef _LP64 | |
2680 casx(top_ptr_reg, top_reg, ptr_reg); | |
2681 #else | |
2682 cas_under_lock(top_ptr_reg, top_reg, ptr_reg, lock_addr, use_call_vm); | |
2683 #endif // _LP64 | |
2684 } | |
2685 | |
2686 // [RGV] This routine does not handle 64 bit operations. | |
2687 // use casx_under_lock() or casx directly!!! | |
2688 void MacroAssembler::cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm) | |
2689 { | |
2690 // store ptr_reg as the new top value | |
2691 if (VM_Version::v9_instructions_work()) { | |
2692 cas(top_ptr_reg, top_reg, ptr_reg); | |
2693 } else { | |
2694 | |
2695 // If the register is not an out nor global, it is not visible | |
2696 // after the save. Allocate a register for it, save its | |
2697 // value in the register save area (the save may not flush | |
2698 // registers to the save area). | |
2699 | |
2700 Register top_ptr_reg_after_save; | |
2701 Register top_reg_after_save; | |
2702 Register ptr_reg_after_save; | |
2703 | |
2704 if (top_ptr_reg->is_out() || top_ptr_reg->is_global()) { | |
2705 top_ptr_reg_after_save = top_ptr_reg->after_save(); | |
2706 } else { | |
2707 Address reg_save_addr = top_ptr_reg->address_in_saved_window(); | |
2708 top_ptr_reg_after_save = L0; | |
2709 st(top_ptr_reg, reg_save_addr); | |
2710 } | |
2711 | |
2712 if (top_reg->is_out() || top_reg->is_global()) { | |
2713 top_reg_after_save = top_reg->after_save(); | |
2714 } else { | |
2715 Address reg_save_addr = top_reg->address_in_saved_window(); | |
2716 top_reg_after_save = L1; | |
2717 st(top_reg, reg_save_addr); | |
2718 } | |
2719 | |
2720 if (ptr_reg->is_out() || ptr_reg->is_global()) { | |
2721 ptr_reg_after_save = ptr_reg->after_save(); | |
2722 } else { | |
2723 Address reg_save_addr = ptr_reg->address_in_saved_window(); | |
2724 ptr_reg_after_save = L2; | |
2725 st(ptr_reg, reg_save_addr); | |
2726 } | |
2727 | |
2728 const Register& lock_reg = L3; | |
2729 const Register& lock_ptr_reg = L4; | |
2730 const Register& value_reg = L5; | |
2731 const Register& yield_reg = L6; | |
2732 const Register& yieldall_reg = L7; | |
2733 | |
2734 save_frame(); | |
2735 | |
2736 if (top_ptr_reg_after_save == L0) { | |
2737 ld(top_ptr_reg->address_in_saved_window().after_save(), top_ptr_reg_after_save); | |
2738 } | |
2739 | |
2740 if (top_reg_after_save == L1) { | |
2741 ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save); | |
2742 } | |
2743 | |
2744 if (ptr_reg_after_save == L2) { | |
2745 ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save); | |
2746 } | |
2747 | |
2748 Label(retry_get_lock); | |
2749 Label(not_same); | |
2750 Label(dont_yield); | |
2751 | |
2752 assert(lock_addr, "lock_address should be non null for v8"); | |
2753 set((intptr_t)lock_addr, lock_ptr_reg); | |
2754 // Initialize yield counter | |
2755 mov(G0,yield_reg); | |
2756 mov(G0, yieldall_reg); | |
2757 set(StubRoutines::Sparc::locked, lock_reg); | |
2758 | |
2759 bind(retry_get_lock); | |
2760 cmp_and_br_short(yield_reg, V8AtomicOperationUnderLockSpinCount, Assembler::less, Assembler::pt, dont_yield); | |
2761 | |
2762 if(use_call_vm) { | |
2763 Untested("Need to verify global reg consistancy"); | |
2764 call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg); | |
2765 } else { | |
2766 // Save the regs and make space for a C call | |
2767 save(SP, -96, SP); | |
2768 save_all_globals_into_locals(); | |
2769 call(CAST_FROM_FN_PTR(address,os::yield_all)); | |
2770 delayed()->mov(yieldall_reg, O0); | |
2771 restore_globals_from_locals(); | |
2772 restore(); | |
2773 } | |
2774 | |
2775 // reset the counter | |
2776 mov(G0,yield_reg); | |
2777 add(yieldall_reg, 1, yieldall_reg); | |
2778 | |
2779 bind(dont_yield); | |
2780 // try to get lock | |
2781 swap(lock_ptr_reg, 0, lock_reg); | |
2782 | |
2783 // did we get the lock? | |
2784 cmp(lock_reg, StubRoutines::Sparc::unlocked); | |
2785 br(Assembler::notEqual, true, Assembler::pn, retry_get_lock); | |
2786 delayed()->add(yield_reg,1,yield_reg); | |
2787 | |
2788 // yes, got lock. do we have the same top? | |
2789 ld(top_ptr_reg_after_save, 0, value_reg); | |
2790 cmp_and_br_short(value_reg, top_reg_after_save, Assembler::notEqual, Assembler::pn, not_same); | |
2791 | |
2792 // yes, same top. | |
2793 st(ptr_reg_after_save, top_ptr_reg_after_save, 0); | |
2794 membar(Assembler::StoreStore); | |
2795 | |
2796 bind(not_same); | |
2797 mov(value_reg, ptr_reg_after_save); | |
2798 st(lock_reg, lock_ptr_reg, 0); // unlock | |
2799 | |
2800 restore(); | |
2801 } | |
2802 } | |
2803 | |
2804 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, | |
2805 Register tmp, | |
2806 int offset) { | |
2807 intptr_t value = *delayed_value_addr; | |
2808 if (value != 0) | |
2809 return RegisterOrConstant(value + offset); | |
2810 | |
2811 // load indirectly to solve generation ordering problem | |
2812 AddressLiteral a(delayed_value_addr); | |
2813 load_ptr_contents(a, tmp); | |
2814 | |
2815 #ifdef ASSERT | |
2816 tst(tmp); | |
2817 breakpoint_trap(zero, xcc); | |
2818 #endif | |
2819 | |
2820 if (offset != 0) | |
2821 add(tmp, offset, tmp); | |
2822 | |
2823 return RegisterOrConstant(tmp); | |
2824 } | |
2825 | |
2826 | |
2827 RegisterOrConstant MacroAssembler::regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { | |
2828 assert(d.register_or_noreg() != G0, "lost side effect"); | |
2829 if ((s2.is_constant() && s2.as_constant() == 0) || | |
2830 (s2.is_register() && s2.as_register() == G0)) { | |
2831 // Do nothing, just move value. | |
2832 if (s1.is_register()) { | |
2833 if (d.is_constant()) d = temp; | |
2834 mov(s1.as_register(), d.as_register()); | |
2835 return d; | |
2836 } else { | |
2837 return s1; | |
2838 } | |
2839 } | |
2840 | |
2841 if (s1.is_register()) { | |
2842 assert_different_registers(s1.as_register(), temp); | |
2843 if (d.is_constant()) d = temp; | |
2844 andn(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); | |
2845 return d; | |
2846 } else { | |
2847 if (s2.is_register()) { | |
2848 assert_different_registers(s2.as_register(), temp); | |
2849 if (d.is_constant()) d = temp; | |
2850 set(s1.as_constant(), temp); | |
2851 andn(temp, s2.as_register(), d.as_register()); | |
2852 return d; | |
2853 } else { | |
2854 intptr_t res = s1.as_constant() & ~s2.as_constant(); | |
2855 return res; | |
2856 } | |
2857 } | |
2858 } | |
2859 | |
2860 RegisterOrConstant MacroAssembler::regcon_inc_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { | |
2861 assert(d.register_or_noreg() != G0, "lost side effect"); | |
2862 if ((s2.is_constant() && s2.as_constant() == 0) || | |
2863 (s2.is_register() && s2.as_register() == G0)) { | |
2864 // Do nothing, just move value. | |
2865 if (s1.is_register()) { | |
2866 if (d.is_constant()) d = temp; | |
2867 mov(s1.as_register(), d.as_register()); | |
2868 return d; | |
2869 } else { | |
2870 return s1; | |
2871 } | |
2872 } | |
2873 | |
2874 if (s1.is_register()) { | |
2875 assert_different_registers(s1.as_register(), temp); | |
2876 if (d.is_constant()) d = temp; | |
2877 add(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); | |
2878 return d; | |
2879 } else { | |
2880 if (s2.is_register()) { | |
2881 assert_different_registers(s2.as_register(), temp); | |
2882 if (d.is_constant()) d = temp; | |
2883 add(s2.as_register(), ensure_simm13_or_reg(s1, temp), d.as_register()); | |
2884 return d; | |
2885 } else { | |
2886 intptr_t res = s1.as_constant() + s2.as_constant(); | |
2887 return res; | |
2888 } | |
2889 } | |
2890 } | |
2891 | |
2892 RegisterOrConstant MacroAssembler::regcon_sll_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { | |
2893 assert(d.register_or_noreg() != G0, "lost side effect"); | |
2894 if (!is_simm13(s2.constant_or_zero())) | |
2895 s2 = (s2.as_constant() & 0xFF); | |
2896 if ((s2.is_constant() && s2.as_constant() == 0) || | |
2897 (s2.is_register() && s2.as_register() == G0)) { | |
2898 // Do nothing, just move value. | |
2899 if (s1.is_register()) { | |
2900 if (d.is_constant()) d = temp; | |
2901 mov(s1.as_register(), d.as_register()); | |
2902 return d; | |
2903 } else { | |
2904 return s1; | |
2905 } | |
2906 } | |
2907 | |
2908 if (s1.is_register()) { | |
2909 assert_different_registers(s1.as_register(), temp); | |
2910 if (d.is_constant()) d = temp; | |
2911 sll_ptr(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); | |
2912 return d; | |
2913 } else { | |
2914 if (s2.is_register()) { | |
2915 assert_different_registers(s2.as_register(), temp); | |
2916 if (d.is_constant()) d = temp; | |
2917 set(s1.as_constant(), temp); | |
2918 sll_ptr(temp, s2.as_register(), d.as_register()); | |
2919 return d; | |
2920 } else { | |
2921 intptr_t res = s1.as_constant() << s2.as_constant(); | |
2922 return res; | |
2923 } | |
2924 } | |
2925 } | |
2926 | |
2927 | |
2928 // Look up the method for a megamorphic invokeinterface call. | |
2929 // The target method is determined by <intf_klass, itable_index>. | |
2930 // The receiver klass is in recv_klass. | |
2931 // On success, the result will be in method_result, and execution falls through. | |
2932 // On failure, execution transfers to the given label. | |
2933 void MacroAssembler::lookup_interface_method(Register recv_klass, | |
2934 Register intf_klass, | |
2935 RegisterOrConstant itable_index, | |
2936 Register method_result, | |
2937 Register scan_temp, | |
2938 Register sethi_temp, | |
2939 Label& L_no_such_interface) { | |
2940 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); | |
2941 assert(itable_index.is_constant() || itable_index.as_register() == method_result, | |
2942 "caller must use same register for non-constant itable index as for method"); | |
2943 | |
2944 Label L_no_such_interface_restore; | |
2945 bool did_save = false; | |
2946 if (scan_temp == noreg || sethi_temp == noreg) { | |
2947 Register recv_2 = recv_klass->is_global() ? recv_klass : L0; | |
2948 Register intf_2 = intf_klass->is_global() ? intf_klass : L1; | |
2949 assert(method_result->is_global(), "must be able to return value"); | |
2950 scan_temp = L2; | |
2951 sethi_temp = L3; | |
2952 save_frame_and_mov(0, recv_klass, recv_2, intf_klass, intf_2); | |
2953 recv_klass = recv_2; | |
2954 intf_klass = intf_2; | |
2955 did_save = true; | |
2956 } | |
2957 | |
2958 // Compute start of first itableOffsetEntry (which is at the end of the vtable) | |
2959 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize; | |
2960 int scan_step = itableOffsetEntry::size() * wordSize; | |
2961 int vte_size = vtableEntry::size() * wordSize; | |
2962 | |
2963 lduw(recv_klass, InstanceKlass::vtable_length_offset() * wordSize, scan_temp); | |
2964 // %%% We should store the aligned, prescaled offset in the klassoop. | |
2965 // Then the next several instructions would fold away. | |
2966 | |
2967 int round_to_unit = ((HeapWordsPerLong > 1) ? BytesPerLong : 0); | |
2968 int itb_offset = vtable_base; | |
2969 if (round_to_unit != 0) { | |
2970 // hoist first instruction of round_to(scan_temp, BytesPerLong): | |
2971 itb_offset += round_to_unit - wordSize; | |
2972 } | |
2973 int itb_scale = exact_log2(vtableEntry::size() * wordSize); | |
2974 sll(scan_temp, itb_scale, scan_temp); | |
2975 add(scan_temp, itb_offset, scan_temp); | |
2976 if (round_to_unit != 0) { | |
2977 // Round up to align_object_offset boundary | |
2978 // see code for InstanceKlass::start_of_itable! | |
2979 // Was: round_to(scan_temp, BytesPerLong); | |
2980 // Hoisted: add(scan_temp, BytesPerLong-1, scan_temp); | |
2981 and3(scan_temp, -round_to_unit, scan_temp); | |
2982 } | |
2983 add(recv_klass, scan_temp, scan_temp); | |
2984 | |
2985 // Adjust recv_klass by scaled itable_index, so we can free itable_index. | |
2986 RegisterOrConstant itable_offset = itable_index; | |
2987 itable_offset = regcon_sll_ptr(itable_index, exact_log2(itableMethodEntry::size() * wordSize), itable_offset); | |
2988 itable_offset = regcon_inc_ptr(itable_offset, itableMethodEntry::method_offset_in_bytes(), itable_offset); | |
2989 add(recv_klass, ensure_simm13_or_reg(itable_offset, sethi_temp), recv_klass); | |
2990 | |
2991 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { | |
2992 // if (scan->interface() == intf) { | |
2993 // result = (klass + scan->offset() + itable_index); | |
2994 // } | |
2995 // } | |
2996 Label L_search, L_found_method; | |
2997 | |
2998 for (int peel = 1; peel >= 0; peel--) { | |
2999 // %%%% Could load both offset and interface in one ldx, if they were | |
3000 // in the opposite order. This would save a load. | |
3001 ld_ptr(scan_temp, itableOffsetEntry::interface_offset_in_bytes(), method_result); | |
3002 | |
3003 // Check that this entry is non-null. A null entry means that | |
3004 // the receiver class doesn't implement the interface, and wasn't the | |
3005 // same as when the caller was compiled. | |
3006 bpr(Assembler::rc_z, false, Assembler::pn, method_result, did_save ? L_no_such_interface_restore : L_no_such_interface); | |
3007 delayed()->cmp(method_result, intf_klass); | |
3008 | |
3009 if (peel) { | |
3010 brx(Assembler::equal, false, Assembler::pt, L_found_method); | |
3011 } else { | |
3012 brx(Assembler::notEqual, false, Assembler::pn, L_search); | |
3013 // (invert the test to fall through to found_method...) | |
3014 } | |
3015 delayed()->add(scan_temp, scan_step, scan_temp); | |
3016 | |
3017 if (!peel) break; | |
3018 | |
3019 bind(L_search); | |
3020 } | |
3021 | |
3022 bind(L_found_method); | |
3023 | |
3024 // Got a hit. | |
3025 int ito_offset = itableOffsetEntry::offset_offset_in_bytes(); | |
3026 // scan_temp[-scan_step] points to the vtable offset we need | |
3027 ito_offset -= scan_step; | |
3028 lduw(scan_temp, ito_offset, scan_temp); | |
3029 ld_ptr(recv_klass, scan_temp, method_result); | |
3030 | |
3031 if (did_save) { | |
3032 Label L_done; | |
3033 ba(L_done); | |
3034 delayed()->restore(); | |
3035 | |
3036 bind(L_no_such_interface_restore); | |
3037 ba(L_no_such_interface); | |
3038 delayed()->restore(); | |
3039 | |
3040 bind(L_done); | |
3041 } | |
3042 } | |
3043 | |
3044 | |
3045 // virtual method calling | |
3046 void MacroAssembler::lookup_virtual_method(Register recv_klass, | |
3047 RegisterOrConstant vtable_index, | |
3048 Register method_result) { | |
3049 assert_different_registers(recv_klass, method_result, vtable_index.register_or_noreg()); | |
3050 Register sethi_temp = method_result; | |
3051 const int base = (InstanceKlass::vtable_start_offset() * wordSize + | |
3052 // method pointer offset within the vtable entry: | |
3053 vtableEntry::method_offset_in_bytes()); | |
3054 RegisterOrConstant vtable_offset = vtable_index; | |
3055 // Each of the following three lines potentially generates an instruction. | |
3056 // But the total number of address formation instructions will always be | |
3057 // at most two, and will often be zero. In any case, it will be optimal. | |
3058 // If vtable_index is a register, we will have (sll_ptr N,x; inc_ptr B,x; ld_ptr k,x). | |
3059 // If vtable_index is a constant, we will have at most (set B+X<<N,t; ld_ptr k,t). | |
3060 vtable_offset = regcon_sll_ptr(vtable_index, exact_log2(vtableEntry::size() * wordSize), vtable_offset); | |
3061 vtable_offset = regcon_inc_ptr(vtable_offset, base, vtable_offset, sethi_temp); | |
3062 Address vtable_entry_addr(recv_klass, ensure_simm13_or_reg(vtable_offset, sethi_temp)); | |
3063 ld_ptr(vtable_entry_addr, method_result); | |
3064 } | |
3065 | |
3066 | |
3067 void MacroAssembler::check_klass_subtype(Register sub_klass, | |
3068 Register super_klass, | |
3069 Register temp_reg, | |
3070 Register temp2_reg, | |
3071 Label& L_success) { | |
3072 Register sub_2 = sub_klass; | |
3073 Register sup_2 = super_klass; | |
3074 if (!sub_2->is_global()) sub_2 = L0; | |
3075 if (!sup_2->is_global()) sup_2 = L1; | |
3076 bool did_save = false; | |
3077 if (temp_reg == noreg || temp2_reg == noreg) { | |
3078 temp_reg = L2; | |
3079 temp2_reg = L3; | |
3080 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2); | |
3081 sub_klass = sub_2; | |
3082 super_klass = sup_2; | |
3083 did_save = true; | |
3084 } | |
3085 Label L_failure, L_pop_to_failure, L_pop_to_success; | |
3086 check_klass_subtype_fast_path(sub_klass, super_klass, | |
3087 temp_reg, temp2_reg, | |
3088 (did_save ? &L_pop_to_success : &L_success), | |
3089 (did_save ? &L_pop_to_failure : &L_failure), NULL); | |
3090 | |
3091 if (!did_save) | |
3092 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2); | |
3093 check_klass_subtype_slow_path(sub_2, sup_2, | |
3094 L2, L3, L4, L5, | |
3095 NULL, &L_pop_to_failure); | |
3096 | |
3097 // on success: | |
3098 bind(L_pop_to_success); | |
3099 restore(); | |
3100 ba_short(L_success); | |
3101 | |
3102 // on failure: | |
3103 bind(L_pop_to_failure); | |
3104 restore(); | |
3105 bind(L_failure); | |
3106 } | |
3107 | |
3108 | |
3109 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, | |
3110 Register super_klass, | |
3111 Register temp_reg, | |
3112 Register temp2_reg, | |
3113 Label* L_success, | |
3114 Label* L_failure, | |
3115 Label* L_slow_path, | |
3116 RegisterOrConstant super_check_offset) { | |
3117 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); | |
3118 int sco_offset = in_bytes(Klass::super_check_offset_offset()); | |
3119 | |
3120 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); | |
3121 bool need_slow_path = (must_load_sco || | |
3122 super_check_offset.constant_or_zero() == sco_offset); | |
3123 | |
3124 assert_different_registers(sub_klass, super_klass, temp_reg); | |
3125 if (super_check_offset.is_register()) { | |
3126 assert_different_registers(sub_klass, super_klass, temp_reg, | |
3127 super_check_offset.as_register()); | |
3128 } else if (must_load_sco) { | |
3129 assert(temp2_reg != noreg, "supply either a temp or a register offset"); | |
3130 } | |
3131 | |
3132 Label L_fallthrough; | |
3133 int label_nulls = 0; | |
3134 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } | |
3135 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } | |
3136 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } | |
3137 assert(label_nulls <= 1 || | |
3138 (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path), | |
3139 "at most one NULL in the batch, usually"); | |
3140 | |
3141 // If the pointers are equal, we are done (e.g., String[] elements). | |
3142 // This self-check enables sharing of secondary supertype arrays among | |
3143 // non-primary types such as array-of-interface. Otherwise, each such | |
3144 // type would need its own customized SSA. | |
3145 // We move this check to the front of the fast path because many | |
3146 // type checks are in fact trivially successful in this manner, | |
3147 // so we get a nicely predicted branch right at the start of the check. | |
3148 cmp(super_klass, sub_klass); | |
3149 brx(Assembler::equal, false, Assembler::pn, *L_success); | |
3150 delayed()->nop(); | |
3151 | |
3152 // Check the supertype display: | |
3153 if (must_load_sco) { | |
3154 // The super check offset is always positive... | |
3155 lduw(super_klass, sco_offset, temp2_reg); | |
3156 super_check_offset = RegisterOrConstant(temp2_reg); | |
3157 // super_check_offset is register. | |
3158 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset.as_register()); | |
3159 } | |
3160 ld_ptr(sub_klass, super_check_offset, temp_reg); | |
3161 cmp(super_klass, temp_reg); | |
3162 | |
3163 // This check has worked decisively for primary supers. | |
3164 // Secondary supers are sought in the super_cache ('super_cache_addr'). | |
3165 // (Secondary supers are interfaces and very deeply nested subtypes.) | |
3166 // This works in the same check above because of a tricky aliasing | |
3167 // between the super_cache and the primary super display elements. | |
3168 // (The 'super_check_addr' can address either, as the case requires.) | |
3169 // Note that the cache is updated below if it does not help us find | |
3170 // what we need immediately. | |
3171 // So if it was a primary super, we can just fail immediately. | |
3172 // Otherwise, it's the slow path for us (no success at this point). | |
3173 | |
3174 // Hacked ba(), which may only be used just before L_fallthrough. | |
3175 #define FINAL_JUMP(label) \ | |
3176 if (&(label) != &L_fallthrough) { \ | |
3177 ba(label); delayed()->nop(); \ | |
3178 } | |
3179 | |
3180 if (super_check_offset.is_register()) { | |
3181 brx(Assembler::equal, false, Assembler::pn, *L_success); | |
3182 delayed()->cmp(super_check_offset.as_register(), sc_offset); | |
3183 | |
3184 if (L_failure == &L_fallthrough) { | |
3185 brx(Assembler::equal, false, Assembler::pt, *L_slow_path); | |
3186 delayed()->nop(); | |
3187 } else { | |
3188 brx(Assembler::notEqual, false, Assembler::pn, *L_failure); | |
3189 delayed()->nop(); | |
3190 FINAL_JUMP(*L_slow_path); | |
3191 } | |
3192 } else if (super_check_offset.as_constant() == sc_offset) { | |
3193 // Need a slow path; fast failure is impossible. | |
3194 if (L_slow_path == &L_fallthrough) { | |
3195 brx(Assembler::equal, false, Assembler::pt, *L_success); | |
3196 delayed()->nop(); | |
3197 } else { | |
3198 brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path); | |
3199 delayed()->nop(); | |
3200 FINAL_JUMP(*L_success); | |
3201 } | |
3202 } else { | |
3203 // No slow path; it's a fast decision. | |
3204 if (L_failure == &L_fallthrough) { | |
3205 brx(Assembler::equal, false, Assembler::pt, *L_success); | |
3206 delayed()->nop(); | |
3207 } else { | |
3208 brx(Assembler::notEqual, false, Assembler::pn, *L_failure); | |
3209 delayed()->nop(); | |
3210 FINAL_JUMP(*L_success); | |
3211 } | |
3212 } | |
3213 | |
3214 bind(L_fallthrough); | |
3215 | |
3216 #undef FINAL_JUMP | |
3217 } | |
3218 | |
3219 | |
3220 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, | |
3221 Register super_klass, | |
3222 Register count_temp, | |
3223 Register scan_temp, | |
3224 Register scratch_reg, | |
3225 Register coop_reg, | |
3226 Label* L_success, | |
3227 Label* L_failure) { | |
3228 assert_different_registers(sub_klass, super_klass, | |
3229 count_temp, scan_temp, scratch_reg, coop_reg); | |
3230 | |
3231 Label L_fallthrough, L_loop; | |
3232 int label_nulls = 0; | |
3233 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } | |
3234 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } | |
3235 assert(label_nulls <= 1, "at most one NULL in the batch"); | |
3236 | |
3237 // a couple of useful fields in sub_klass: | |
3238 int ss_offset = in_bytes(Klass::secondary_supers_offset()); | |
3239 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); | |
3240 | |
3241 // Do a linear scan of the secondary super-klass chain. | |
3242 // This code is rarely used, so simplicity is a virtue here. | |
3243 | |
3244 #ifndef PRODUCT | |
3245 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; | |
3246 inc_counter((address) pst_counter, count_temp, scan_temp); | |
3247 #endif | |
3248 | |
3249 // We will consult the secondary-super array. | |
3250 ld_ptr(sub_klass, ss_offset, scan_temp); | |
3251 | |
3252 Register search_key = super_klass; | |
3253 | |
3254 // Load the array length. (Positive movl does right thing on LP64.) | |
3255 lduw(scan_temp, Array<Klass*>::length_offset_in_bytes(), count_temp); | |
3256 | |
3257 // Check for empty secondary super list | |
3258 tst(count_temp); | |
3259 | |
3260 // In the array of super classes elements are pointer sized. | |
3261 int element_size = wordSize; | |
3262 | |
3263 // Top of search loop | |
3264 bind(L_loop); | |
3265 br(Assembler::equal, false, Assembler::pn, *L_failure); | |
3266 delayed()->add(scan_temp, element_size, scan_temp); | |
3267 | |
3268 // Skip the array header in all array accesses. | |
3269 int elem_offset = Array<Klass*>::base_offset_in_bytes(); | |
3270 elem_offset -= element_size; // the scan pointer was pre-incremented also | |
3271 | |
3272 // Load next super to check | |
3273 ld_ptr( scan_temp, elem_offset, scratch_reg ); | |
3274 | |
3275 // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list | |
3276 cmp(scratch_reg, search_key); | |
3277 | |
3278 // A miss means we are NOT a subtype and need to keep looping | |
3279 brx(Assembler::notEqual, false, Assembler::pn, L_loop); | |
3280 delayed()->deccc(count_temp); // decrement trip counter in delay slot | |
3281 | |
3282 // Success. Cache the super we found and proceed in triumph. | |
3283 st_ptr(super_klass, sub_klass, sc_offset); | |
3284 | |
3285 if (L_success != &L_fallthrough) { | |
3286 ba(*L_success); | |
3287 delayed()->nop(); | |
3288 } | |
3289 | |
3290 bind(L_fallthrough); | |
3291 } | |
3292 | |
3293 | |
3294 RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot, | |
3295 Register temp_reg, | |
3296 int extra_slot_offset) { | |
3297 // cf. TemplateTable::prepare_invoke(), if (load_receiver). | |
3298 int stackElementSize = Interpreter::stackElementSize; | |
3299 int offset = extra_slot_offset * stackElementSize; | |
3300 if (arg_slot.is_constant()) { | |
3301 offset += arg_slot.as_constant() * stackElementSize; | |
3302 return offset; | |
3303 } else { | |
3304 assert(temp_reg != noreg, "must specify"); | |
3305 sll_ptr(arg_slot.as_register(), exact_log2(stackElementSize), temp_reg); | |
3306 if (offset != 0) | |
3307 add(temp_reg, offset, temp_reg); | |
3308 return temp_reg; | |
3309 } | |
3310 } | |
3311 | |
3312 | |
3313 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, | |
3314 Register temp_reg, | |
3315 int extra_slot_offset) { | |
3316 return Address(Gargs, argument_offset(arg_slot, temp_reg, extra_slot_offset)); | |
3317 } | |
3318 | |
3319 | |
3320 void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg, | |
3321 Register temp_reg, | |
3322 Label& done, Label* slow_case, | |
3323 BiasedLockingCounters* counters) { | |
3324 assert(UseBiasedLocking, "why call this otherwise?"); | |
3325 | |
3326 if (PrintBiasedLockingStatistics) { | |
3327 assert_different_registers(obj_reg, mark_reg, temp_reg, O7); | |
3328 if (counters == NULL) | |
3329 counters = BiasedLocking::counters(); | |
3330 } | |
3331 | |
3332 Label cas_label; | |
3333 | |
3334 // Biased locking | |
3335 // See whether the lock is currently biased toward our thread and | |
3336 // whether the epoch is still valid | |
3337 // Note that the runtime guarantees sufficient alignment of JavaThread | |
3338 // pointers to allow age to be placed into low bits | |
3339 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
3340 and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); | |
3341 cmp_and_brx_short(temp_reg, markOopDesc::biased_lock_pattern, Assembler::notEqual, Assembler::pn, cas_label); | |
3342 | |
3343 load_klass(obj_reg, temp_reg); | |
3344 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); | |
3345 or3(G2_thread, temp_reg, temp_reg); | |
3346 xor3(mark_reg, temp_reg, temp_reg); | |
3347 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg); | |
3348 if (counters != NULL) { | |
3349 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg); | |
3350 // Reload mark_reg as we may need it later | |
3351 ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg); | |
3352 } | |
3353 brx(Assembler::equal, true, Assembler::pt, done); | |
3354 delayed()->nop(); | |
3355 | |
3356 Label try_revoke_bias; | |
3357 Label try_rebias; | |
3358 Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes()); | |
3359 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3360 | |
3361 // At this point we know that the header has the bias pattern and | |
3362 // that we are not the bias owner in the current epoch. We need to | |
3363 // figure out more details about the state of the header in order to | |
3364 // know what operations can be legally performed on the object's | |
3365 // header. | |
3366 | |
3367 // If the low three bits in the xor result aren't clear, that means | |
3368 // the prototype header is no longer biased and we have to revoke | |
3369 // the bias on this object. | |
3370 btst(markOopDesc::biased_lock_mask_in_place, temp_reg); | |
3371 brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias); | |
3372 | |
3373 // Biasing is still enabled for this data type. See whether the | |
3374 // epoch of the current bias is still valid, meaning that the epoch | |
3375 // bits of the mark word are equal to the epoch bits of the | |
3376 // prototype header. (Note that the prototype header's epoch bits | |
3377 // only change at a safepoint.) If not, attempt to rebias the object | |
3378 // toward the current thread. Note that we must be absolutely sure | |
3379 // that the current epoch is invalid in order to do this because | |
3380 // otherwise the manipulations it performs on the mark word are | |
3381 // illegal. | |
3382 delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg); | |
3383 brx(Assembler::notZero, false, Assembler::pn, try_rebias); | |
3384 | |
3385 // The epoch of the current bias is still valid but we know nothing | |
3386 // about the owner; it might be set or it might be clear. Try to | |
3387 // acquire the bias of the object using an atomic operation. If this | |
3388 // fails we will go in to the runtime to revoke the object's bias. | |
3389 // Note that we first construct the presumed unbiased header so we | |
3390 // don't accidentally blow away another thread's valid bias. | |
3391 delayed()->and3(mark_reg, | |
3392 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place, | |
3393 mark_reg); | |
3394 or3(G2_thread, mark_reg, temp_reg); | |
3395 casn(mark_addr.base(), mark_reg, temp_reg); | |
3396 // If the biasing toward our thread failed, this means that | |
3397 // another thread succeeded in biasing it toward itself and we | |
3398 // need to revoke that bias. The revocation will occur in the | |
3399 // interpreter runtime in the slow case. | |
3400 cmp(mark_reg, temp_reg); | |
3401 if (counters != NULL) { | |
3402 cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg); | |
3403 } | |
3404 if (slow_case != NULL) { | |
3405 brx(Assembler::notEqual, true, Assembler::pn, *slow_case); | |
3406 delayed()->nop(); | |
3407 } | |
3408 ba_short(done); | |
3409 | |
3410 bind(try_rebias); | |
3411 // At this point we know the epoch has expired, meaning that the | |
3412 // current "bias owner", if any, is actually invalid. Under these | |
3413 // circumstances _only_, we are allowed to use the current header's | |
3414 // value as the comparison value when doing the cas to acquire the | |
3415 // bias in the current epoch. In other words, we allow transfer of | |
3416 // the bias from one thread to another directly in this situation. | |
3417 // | |
3418 // FIXME: due to a lack of registers we currently blow away the age | |
3419 // bits in this situation. Should attempt to preserve them. | |
3420 load_klass(obj_reg, temp_reg); | |
3421 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); | |
3422 or3(G2_thread, temp_reg, temp_reg); | |
3423 casn(mark_addr.base(), mark_reg, temp_reg); | |
3424 // If the biasing toward our thread failed, this means that | |
3425 // another thread succeeded in biasing it toward itself and we | |
3426 // need to revoke that bias. The revocation will occur in the | |
3427 // interpreter runtime in the slow case. | |
3428 cmp(mark_reg, temp_reg); | |
3429 if (counters != NULL) { | |
3430 cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg); | |
3431 } | |
3432 if (slow_case != NULL) { | |
3433 brx(Assembler::notEqual, true, Assembler::pn, *slow_case); | |
3434 delayed()->nop(); | |
3435 } | |
3436 ba_short(done); | |
3437 | |
3438 bind(try_revoke_bias); | |
3439 // The prototype mark in the klass doesn't have the bias bit set any | |
3440 // more, indicating that objects of this data type are not supposed | |
3441 // to be biased any more. We are going to try to reset the mark of | |
3442 // this object to the prototype value and fall through to the | |
3443 // CAS-based locking scheme. Note that if our CAS fails, it means | |
3444 // that another thread raced us for the privilege of revoking the | |
3445 // bias of this particular object, so it's okay to continue in the | |
3446 // normal locking code. | |
3447 // | |
3448 // FIXME: due to a lack of registers we currently blow away the age | |
3449 // bits in this situation. Should attempt to preserve them. | |
3450 load_klass(obj_reg, temp_reg); | |
3451 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); | |
3452 casn(mark_addr.base(), mark_reg, temp_reg); | |
3453 // Fall through to the normal CAS-based lock, because no matter what | |
3454 // the result of the above CAS, some thread must have succeeded in | |
3455 // removing the bias bit from the object's header. | |
3456 if (counters != NULL) { | |
3457 cmp(mark_reg, temp_reg); | |
3458 cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg); | |
3459 } | |
3460 | |
3461 bind(cas_label); | |
3462 } | |
3463 | |
3464 void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done, | |
3465 bool allow_delay_slot_filling) { | |
3466 // Check for biased locking unlock case, which is a no-op | |
3467 // Note: we do not have to check the thread ID for two reasons. | |
3468 // First, the interpreter checks for IllegalMonitorStateException at | |
3469 // a higher level. Second, if the bias was revoked while we held the | |
3470 // lock, the object could not be rebiased toward another thread, so | |
3471 // the bias bit would be clear. | |
3472 ld_ptr(mark_addr, temp_reg); | |
3473 and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); | |
3474 cmp(temp_reg, markOopDesc::biased_lock_pattern); | |
3475 brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done); | |
3476 delayed(); | |
3477 if (!allow_delay_slot_filling) { | |
3478 nop(); | |
3479 } | |
3480 } | |
3481 | |
3482 | |
3483 // CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by | |
3484 // Solaris/SPARC's "as". Another apt name would be cas_ptr() | |
3485 | |
3486 void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) { | |
3487 casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); | |
3488 } | |
3489 | |
3490 | |
3491 | |
3492 // compiler_lock_object() and compiler_unlock_object() are direct transliterations | |
3493 // of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments. | |
3494 // The code could be tightened up considerably. | |
3495 // | |
3496 // box->dhw disposition - post-conditions at DONE_LABEL. | |
3497 // - Successful inflated lock: box->dhw != 0. | |
3498 // Any non-zero value suffices. | |
3499 // Consider G2_thread, rsp, boxReg, or unused_mark() | |
3500 // - Successful Stack-lock: box->dhw == mark. | |
3501 // box->dhw must contain the displaced mark word value | |
3502 // - Failure -- icc.ZFlag == 0 and box->dhw is undefined. | |
3503 // The slow-path fast_enter() and slow_enter() operators | |
3504 // are responsible for setting box->dhw = NonZero (typically ::unused_mark). | |
3505 // - Biased: box->dhw is undefined | |
3506 // | |
3507 // SPARC refworkload performance - specifically jetstream and scimark - are | |
3508 // extremely sensitive to the size of the code emitted by compiler_lock_object | |
3509 // and compiler_unlock_object. Critically, the key factor is code size, not path | |
3510 // length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the | |
3511 // effect). | |
3512 | |
3513 | |
3514 void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark, | |
3515 Register Rbox, Register Rscratch, | |
3516 BiasedLockingCounters* counters, | |
3517 bool try_bias) { | |
3518 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes()); | |
3519 | |
3520 verify_oop(Roop); | |
3521 Label done ; | |
3522 | |
3523 if (counters != NULL) { | |
3524 inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch); | |
3525 } | |
3526 | |
3527 if (EmitSync & 1) { | |
3528 mov(3, Rscratch); | |
3529 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3530 cmp(SP, G0); | |
3531 return ; | |
3532 } | |
3533 | |
3534 if (EmitSync & 2) { | |
3535 | |
3536 // Fetch object's markword | |
3537 ld_ptr(mark_addr, Rmark); | |
3538 | |
3539 if (try_bias) { | |
3540 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); | |
3541 } | |
3542 | |
3543 // Save Rbox in Rscratch to be used for the cas operation | |
3544 mov(Rbox, Rscratch); | |
3545 | |
3546 // set Rmark to markOop | markOopDesc::unlocked_value | |
3547 or3(Rmark, markOopDesc::unlocked_value, Rmark); | |
3548 | |
3549 // Initialize the box. (Must happen before we update the object mark!) | |
3550 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3551 | |
3552 // compare object markOop with Rmark and if equal exchange Rscratch with object markOop | |
3553 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3554 casx_under_lock(mark_addr.base(), Rmark, Rscratch, | |
3555 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); | |
3556 | |
3557 // if compare/exchange succeeded we found an unlocked object and we now have locked it | |
3558 // hence we are done | |
3559 cmp(Rmark, Rscratch); | |
3560 #ifdef _LP64 | |
3561 sub(Rscratch, STACK_BIAS, Rscratch); | |
3562 #endif | |
3563 brx(Assembler::equal, false, Assembler::pt, done); | |
3564 delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot | |
3565 | |
3566 // we did not find an unlocked object so see if this is a recursive case | |
3567 // sub(Rscratch, SP, Rscratch); | |
3568 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); | |
3569 andcc(Rscratch, 0xfffff003, Rscratch); | |
3570 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3571 bind (done); | |
3572 return ; | |
3573 } | |
3574 | |
3575 Label Egress ; | |
3576 | |
3577 if (EmitSync & 256) { | |
3578 Label IsInflated ; | |
3579 | |
3580 ld_ptr(mark_addr, Rmark); // fetch obj->mark | |
3581 // Triage: biased, stack-locked, neutral, inflated | |
3582 if (try_bias) { | |
3583 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); | |
3584 // Invariant: if control reaches this point in the emitted stream | |
3585 // then Rmark has not been modified. | |
3586 } | |
3587 | |
3588 // Store mark into displaced mark field in the on-stack basic-lock "box" | |
3589 // Critically, this must happen before the CAS | |
3590 // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty. | |
3591 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3592 andcc(Rmark, 2, G0); | |
3593 brx(Assembler::notZero, false, Assembler::pn, IsInflated); | |
3594 delayed()-> | |
3595 | |
3596 // Try stack-lock acquisition. | |
3597 // Beware: the 1st instruction is in a delay slot | |
3598 mov(Rbox, Rscratch); | |
3599 or3(Rmark, markOopDesc::unlocked_value, Rmark); | |
3600 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3601 casn(mark_addr.base(), Rmark, Rscratch); | |
3602 cmp(Rmark, Rscratch); | |
3603 brx(Assembler::equal, false, Assembler::pt, done); | |
3604 delayed()->sub(Rscratch, SP, Rscratch); | |
3605 | |
3606 // Stack-lock attempt failed - check for recursive stack-lock. | |
3607 // See the comments below about how we might remove this case. | |
3608 #ifdef _LP64 | |
3609 sub(Rscratch, STACK_BIAS, Rscratch); | |
3610 #endif | |
3611 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); | |
3612 andcc(Rscratch, 0xfffff003, Rscratch); | |
3613 br(Assembler::always, false, Assembler::pt, done); | |
3614 delayed()-> st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3615 | |
3616 bind(IsInflated); | |
3617 if (EmitSync & 64) { | |
3618 // If m->owner != null goto IsLocked | |
3619 // Pessimistic form: Test-and-CAS vs CAS | |
3620 // The optimistic form avoids RTS->RTO cache line upgrades. | |
3621 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch); | |
3622 andcc(Rscratch, Rscratch, G0); | |
3623 brx(Assembler::notZero, false, Assembler::pn, done); | |
3624 delayed()->nop(); | |
3625 // m->owner == null : it's unlocked. | |
3626 } | |
3627 | |
3628 // Try to CAS m->owner from null to Self | |
3629 // Invariant: if we acquire the lock then _recursions should be 0. | |
3630 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark); | |
3631 mov(G2_thread, Rscratch); | |
3632 casn(Rmark, G0, Rscratch); | |
3633 cmp(Rscratch, G0); | |
3634 // Intentional fall-through into done | |
3635 } else { | |
3636 // Aggressively avoid the Store-before-CAS penalty | |
3637 // Defer the store into box->dhw until after the CAS | |
3638 Label IsInflated, Recursive ; | |
3639 | |
3640 // Anticipate CAS -- Avoid RTS->RTO upgrade | |
3641 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads); | |
3642 | |
3643 ld_ptr(mark_addr, Rmark); // fetch obj->mark | |
3644 // Triage: biased, stack-locked, neutral, inflated | |
3645 | |
3646 if (try_bias) { | |
3647 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); | |
3648 // Invariant: if control reaches this point in the emitted stream | |
3649 // then Rmark has not been modified. | |
3650 } | |
3651 andcc(Rmark, 2, G0); | |
3652 brx(Assembler::notZero, false, Assembler::pn, IsInflated); | |
3653 delayed()-> // Beware - dangling delay-slot | |
3654 | |
3655 // Try stack-lock acquisition. | |
3656 // Transiently install BUSY (0) encoding in the mark word. | |
3657 // if the CAS of 0 into the mark was successful then we execute: | |
3658 // ST box->dhw = mark -- save fetched mark in on-stack basiclock box | |
3659 // ST obj->mark = box -- overwrite transient 0 value | |
3660 // This presumes TSO, of course. | |
3661 | |
3662 mov(0, Rscratch); | |
3663 or3(Rmark, markOopDesc::unlocked_value, Rmark); | |
3664 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3665 casn(mark_addr.base(), Rmark, Rscratch); | |
3666 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads); | |
3667 cmp(Rscratch, Rmark); | |
3668 brx(Assembler::notZero, false, Assembler::pn, Recursive); | |
3669 delayed()->st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3670 if (counters != NULL) { | |
3671 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); | |
3672 } | |
3673 ba(done); | |
3674 delayed()->st_ptr(Rbox, mark_addr); | |
3675 | |
3676 bind(Recursive); | |
3677 // Stack-lock attempt failed - check for recursive stack-lock. | |
3678 // Tests show that we can remove the recursive case with no impact | |
3679 // on refworkload 0.83. If we need to reduce the size of the code | |
3680 // emitted by compiler_lock_object() the recursive case is perfect | |
3681 // candidate. | |
3682 // | |
3683 // A more extreme idea is to always inflate on stack-lock recursion. | |
3684 // This lets us eliminate the recursive checks in compiler_lock_object | |
3685 // and compiler_unlock_object and the (box->dhw == 0) encoding. | |
3686 // A brief experiment - requiring changes to synchronizer.cpp, interpreter, | |
3687 // and showed a performance *increase*. In the same experiment I eliminated | |
3688 // the fast-path stack-lock code from the interpreter and always passed | |
3689 // control to the "slow" operators in synchronizer.cpp. | |
3690 | |
3691 // RScratch contains the fetched obj->mark value from the failed CASN. | |
3692 #ifdef _LP64 | |
3693 sub(Rscratch, STACK_BIAS, Rscratch); | |
3694 #endif | |
3695 sub(Rscratch, SP, Rscratch); | |
3696 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); | |
3697 andcc(Rscratch, 0xfffff003, Rscratch); | |
3698 if (counters != NULL) { | |
3699 // Accounting needs the Rscratch register | |
3700 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3701 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); | |
3702 ba_short(done); | |
3703 } else { | |
3704 ba(done); | |
3705 delayed()->st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3706 } | |
3707 | |
3708 bind (IsInflated); | |
3709 if (EmitSync & 64) { | |
3710 // If m->owner != null goto IsLocked | |
3711 // Test-and-CAS vs CAS | |
3712 // Pessimistic form avoids futile (doomed) CAS attempts | |
3713 // The optimistic form avoids RTS->RTO cache line upgrades. | |
3714 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch); | |
3715 andcc(Rscratch, Rscratch, G0); | |
3716 brx(Assembler::notZero, false, Assembler::pn, done); | |
3717 delayed()->nop(); | |
3718 // m->owner == null : it's unlocked. | |
3719 } | |
3720 | |
3721 // Try to CAS m->owner from null to Self | |
3722 // Invariant: if we acquire the lock then _recursions should be 0. | |
3723 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark); | |
3724 mov(G2_thread, Rscratch); | |
3725 casn(Rmark, G0, Rscratch); | |
3726 cmp(Rscratch, G0); | |
3727 // ST box->displaced_header = NonZero. | |
3728 // Any non-zero value suffices: | |
3729 // unused_mark(), G2_thread, RBox, RScratch, rsp, etc. | |
3730 st_ptr(Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3731 // Intentional fall-through into done | |
3732 } | |
3733 | |
3734 bind (done); | |
3735 } | |
3736 | |
3737 void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark, | |
3738 Register Rbox, Register Rscratch, | |
3739 bool try_bias) { | |
3740 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes()); | |
3741 | |
3742 Label done ; | |
3743 | |
3744 if (EmitSync & 4) { | |
3745 cmp(SP, G0); | |
3746 return ; | |
3747 } | |
3748 | |
3749 if (EmitSync & 8) { | |
3750 if (try_bias) { | |
3751 biased_locking_exit(mark_addr, Rscratch, done); | |
3752 } | |
3753 | |
3754 // Test first if it is a fast recursive unlock | |
3755 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark); | |
3756 br_null_short(Rmark, Assembler::pt, done); | |
3757 | |
3758 // Check if it is still a light weight lock, this is is true if we see | |
3759 // the stack address of the basicLock in the markOop of the object | |
3760 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3761 casx_under_lock(mark_addr.base(), Rbox, Rmark, | |
3762 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); | |
3763 ba(done); | |
3764 delayed()->cmp(Rbox, Rmark); | |
3765 bind(done); | |
3766 return ; | |
3767 } | |
3768 | |
3769 // Beware ... If the aggregate size of the code emitted by CLO and CUO is | |
3770 // is too large performance rolls abruptly off a cliff. | |
3771 // This could be related to inlining policies, code cache management, or | |
3772 // I$ effects. | |
3773 Label LStacked ; | |
3774 | |
3775 if (try_bias) { | |
3776 // TODO: eliminate redundant LDs of obj->mark | |
3777 biased_locking_exit(mark_addr, Rscratch, done); | |
3778 } | |
3779 | |
3780 ld_ptr(Roop, oopDesc::mark_offset_in_bytes(), Rmark); | |
3781 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch); | |
3782 andcc(Rscratch, Rscratch, G0); | |
3783 brx(Assembler::zero, false, Assembler::pn, done); | |
3784 delayed()->nop(); // consider: relocate fetch of mark, above, into this DS | |
3785 andcc(Rmark, 2, G0); | |
3786 brx(Assembler::zero, false, Assembler::pt, LStacked); | |
3787 delayed()->nop(); | |
3788 | |
3789 // It's inflated | |
3790 // Conceptually we need a #loadstore|#storestore "release" MEMBAR before | |
3791 // the ST of 0 into _owner which releases the lock. This prevents loads | |
3792 // and stores within the critical section from reordering (floating) | |
3793 // past the store that releases the lock. But TSO is a strong memory model | |
3794 // and that particular flavor of barrier is a noop, so we can safely elide it. | |
3795 // Note that we use 1-0 locking by default for the inflated case. We | |
3796 // close the resultant (and rare) race by having contented threads in | |
3797 // monitorenter periodically poll _owner. | |
3798 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch); | |
3799 ld_ptr(Rmark, ObjectMonitor::recursions_offset_in_bytes() - 2, Rbox); | |
3800 xor3(Rscratch, G2_thread, Rscratch); | |
3801 orcc(Rbox, Rscratch, Rbox); | |
3802 brx(Assembler::notZero, false, Assembler::pn, done); | |
3803 delayed()-> | |
3804 ld_ptr(Rmark, ObjectMonitor::EntryList_offset_in_bytes() - 2, Rscratch); | |
3805 ld_ptr(Rmark, ObjectMonitor::cxq_offset_in_bytes() - 2, Rbox); | |
3806 orcc(Rbox, Rscratch, G0); | |
3807 if (EmitSync & 65536) { | |
3808 Label LSucc ; | |
3809 brx(Assembler::notZero, false, Assembler::pn, LSucc); | |
3810 delayed()->nop(); | |
3811 ba(done); | |
3812 delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2); | |
3813 | |
3814 bind(LSucc); | |
3815 st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2); | |
3816 if (os::is_MP()) { membar (StoreLoad); } | |
3817 ld_ptr(Rmark, ObjectMonitor::succ_offset_in_bytes() - 2, Rscratch); | |
3818 andcc(Rscratch, Rscratch, G0); | |
3819 brx(Assembler::notZero, false, Assembler::pt, done); | |
3820 delayed()->andcc(G0, G0, G0); | |
3821 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark); | |
3822 mov(G2_thread, Rscratch); | |
3823 casn(Rmark, G0, Rscratch); | |
3824 // invert icc.zf and goto done | |
3825 br_notnull(Rscratch, false, Assembler::pt, done); | |
3826 delayed()->cmp(G0, G0); | |
3827 ba(done); | |
3828 delayed()->cmp(G0, 1); | |
3829 } else { | |
3830 brx(Assembler::notZero, false, Assembler::pn, done); | |
3831 delayed()->nop(); | |
3832 ba(done); | |
3833 delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2); | |
3834 } | |
3835 | |
3836 bind (LStacked); | |
3837 // Consider: we could replace the expensive CAS in the exit | |
3838 // path with a simple ST of the displaced mark value fetched from | |
3839 // the on-stack basiclock box. That admits a race where a thread T2 | |
3840 // in the slow lock path -- inflating with monitor M -- could race a | |
3841 // thread T1 in the fast unlock path, resulting in a missed wakeup for T2. | |
3842 // More precisely T1 in the stack-lock unlock path could "stomp" the | |
3843 // inflated mark value M installed by T2, resulting in an orphan | |
3844 // object monitor M and T2 becoming stranded. We can remedy that situation | |
3845 // by having T2 periodically poll the object's mark word using timed wait | |
3846 // operations. If T2 discovers that a stomp has occurred it vacates | |
3847 // the monitor M and wakes any other threads stranded on the now-orphan M. | |
3848 // In addition the monitor scavenger, which performs deflation, | |
3849 // would also need to check for orpan monitors and stranded threads. | |
3850 // | |
3851 // Finally, inflation is also used when T2 needs to assign a hashCode | |
3852 // to O and O is stack-locked by T1. The "stomp" race could cause | |
3853 // an assigned hashCode value to be lost. We can avoid that condition | |
3854 // and provide the necessary hashCode stability invariants by ensuring | |
3855 // that hashCode generation is idempotent between copying GCs. | |
3856 // For example we could compute the hashCode of an object O as | |
3857 // O's heap address XOR some high quality RNG value that is refreshed | |
3858 // at GC-time. The monitor scavenger would install the hashCode | |
3859 // found in any orphan monitors. Again, the mechanism admits a | |
3860 // lost-update "stomp" WAW race but detects and recovers as needed. | |
3861 // | |
3862 // A prototype implementation showed excellent results, although | |
3863 // the scavenger and timeout code was rather involved. | |
3864 | |
3865 casn(mark_addr.base(), Rbox, Rscratch); | |
3866 cmp(Rbox, Rscratch); | |
3867 // Intentional fall through into done ... | |
3868 | |
3869 bind(done); | |
3870 } | |
3871 | |
3872 | |
3873 | |
3874 void MacroAssembler::print_CPU_state() { | |
3875 // %%%%% need to implement this | |
3876 } | |
3877 | |
3878 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
3879 // %%%%% need to implement this | |
3880 } | |
3881 | |
3882 void MacroAssembler::push_IU_state() { | |
3883 // %%%%% need to implement this | |
3884 } | |
3885 | |
3886 | |
3887 void MacroAssembler::pop_IU_state() { | |
3888 // %%%%% need to implement this | |
3889 } | |
3890 | |
3891 | |
3892 void MacroAssembler::push_FPU_state() { | |
3893 // %%%%% need to implement this | |
3894 } | |
3895 | |
3896 | |
3897 void MacroAssembler::pop_FPU_state() { | |
3898 // %%%%% need to implement this | |
3899 } | |
3900 | |
3901 | |
3902 void MacroAssembler::push_CPU_state() { | |
3903 // %%%%% need to implement this | |
3904 } | |
3905 | |
3906 | |
3907 void MacroAssembler::pop_CPU_state() { | |
3908 // %%%%% need to implement this | |
3909 } | |
3910 | |
3911 | |
3912 | |
3913 void MacroAssembler::verify_tlab() { | |
3914 #ifdef ASSERT | |
3915 if (UseTLAB && VerifyOops) { | |
3916 Label next, next2, ok; | |
3917 Register t1 = L0; | |
3918 Register t2 = L1; | |
3919 Register t3 = L2; | |
3920 | |
3921 save_frame(0); | |
3922 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); | |
3923 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2); | |
3924 or3(t1, t2, t3); | |
3925 cmp_and_br_short(t1, t2, Assembler::greaterEqual, Assembler::pn, next); | |
3926 STOP("assert(top >= start)"); | |
3927 should_not_reach_here(); | |
3928 | |
3929 bind(next); | |
3930 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); | |
3931 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2); | |
3932 or3(t3, t2, t3); | |
3933 cmp_and_br_short(t1, t2, Assembler::lessEqual, Assembler::pn, next2); | |
3934 STOP("assert(top <= end)"); | |
3935 should_not_reach_here(); | |
3936 | |
3937 bind(next2); | |
3938 and3(t3, MinObjAlignmentInBytesMask, t3); | |
3939 cmp_and_br_short(t3, 0, Assembler::lessEqual, Assembler::pn, ok); | |
3940 STOP("assert(aligned)"); | |
3941 should_not_reach_here(); | |
3942 | |
3943 bind(ok); | |
3944 restore(); | |
3945 } | |
3946 #endif | |
3947 } | |
3948 | |
3949 | |
3950 void MacroAssembler::eden_allocate( | |
3951 Register obj, // result: pointer to object after successful allocation | |
3952 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
3953 int con_size_in_bytes, // object size in bytes if known at compile time | |
3954 Register t1, // temp register | |
3955 Register t2, // temp register | |
3956 Label& slow_case // continuation point if fast allocation fails | |
3957 ){ | |
3958 // make sure arguments make sense | |
3959 assert_different_registers(obj, var_size_in_bytes, t1, t2); | |
3960 assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size"); | |
3961 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); | |
3962 | |
3963 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
3964 // No allocation in the shared eden. | |
3965 ba_short(slow_case); | |
3966 } else { | |
3967 // get eden boundaries | |
3968 // note: we need both top & top_addr! | |
3969 const Register top_addr = t1; | |
3970 const Register end = t2; | |
3971 | |
3972 CollectedHeap* ch = Universe::heap(); | |
3973 set((intx)ch->top_addr(), top_addr); | |
3974 intx delta = (intx)ch->end_addr() - (intx)ch->top_addr(); | |
3975 ld_ptr(top_addr, delta, end); | |
3976 ld_ptr(top_addr, 0, obj); | |
3977 | |
3978 // try to allocate | |
3979 Label retry; | |
3980 bind(retry); | |
3981 #ifdef ASSERT | |
3982 // make sure eden top is properly aligned | |
3983 { | |
3984 Label L; | |
3985 btst(MinObjAlignmentInBytesMask, obj); | |
3986 br(Assembler::zero, false, Assembler::pt, L); | |
3987 delayed()->nop(); | |
3988 STOP("eden top is not properly aligned"); | |
3989 bind(L); | |
3990 } | |
3991 #endif // ASSERT | |
3992 const Register free = end; | |
3993 sub(end, obj, free); // compute amount of free space | |
3994 if (var_size_in_bytes->is_valid()) { | |
3995 // size is unknown at compile time | |
3996 cmp(free, var_size_in_bytes); | |
3997 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case | |
3998 delayed()->add(obj, var_size_in_bytes, end); | |
3999 } else { | |
4000 // size is known at compile time | |
4001 cmp(free, con_size_in_bytes); | |
4002 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case | |
4003 delayed()->add(obj, con_size_in_bytes, end); | |
4004 } | |
4005 // Compare obj with the value at top_addr; if still equal, swap the value of | |
4006 // end with the value at top_addr. If not equal, read the value at top_addr | |
4007 // into end. | |
4008 casx_under_lock(top_addr, obj, end, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); | |
4009 // if someone beat us on the allocation, try again, otherwise continue | |
4010 cmp(obj, end); | |
4011 brx(Assembler::notEqual, false, Assembler::pn, retry); | |
4012 delayed()->mov(end, obj); // nop if successfull since obj == end | |
4013 | |
4014 #ifdef ASSERT | |
4015 // make sure eden top is properly aligned | |
4016 { | |
4017 Label L; | |
4018 const Register top_addr = t1; | |
4019 | |
4020 set((intx)ch->top_addr(), top_addr); | |
4021 ld_ptr(top_addr, 0, top_addr); | |
4022 btst(MinObjAlignmentInBytesMask, top_addr); | |
4023 br(Assembler::zero, false, Assembler::pt, L); | |
4024 delayed()->nop(); | |
4025 STOP("eden top is not properly aligned"); | |
4026 bind(L); | |
4027 } | |
4028 #endif // ASSERT | |
4029 } | |
4030 } | |
4031 | |
4032 | |
4033 void MacroAssembler::tlab_allocate( | |
4034 Register obj, // result: pointer to object after successful allocation | |
4035 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
4036 int con_size_in_bytes, // object size in bytes if known at compile time | |
4037 Register t1, // temp register | |
4038 Label& slow_case // continuation point if fast allocation fails | |
4039 ){ | |
4040 // make sure arguments make sense | |
4041 assert_different_registers(obj, var_size_in_bytes, t1); | |
4042 assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size"); | |
4043 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); | |
4044 | |
4045 const Register free = t1; | |
4046 | |
4047 verify_tlab(); | |
4048 | |
4049 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj); | |
4050 | |
4051 // calculate amount of free space | |
4052 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free); | |
4053 sub(free, obj, free); | |
4054 | |
4055 Label done; | |
4056 if (var_size_in_bytes == noreg) { | |
4057 cmp(free, con_size_in_bytes); | |
4058 } else { | |
4059 cmp(free, var_size_in_bytes); | |
4060 } | |
4061 br(Assembler::less, false, Assembler::pn, slow_case); | |
4062 // calculate the new top pointer | |
4063 if (var_size_in_bytes == noreg) { | |
4064 delayed()->add(obj, con_size_in_bytes, free); | |
4065 } else { | |
4066 delayed()->add(obj, var_size_in_bytes, free); | |
4067 } | |
4068 | |
4069 bind(done); | |
4070 | |
4071 #ifdef ASSERT | |
4072 // make sure new free pointer is properly aligned | |
4073 { | |
4074 Label L; | |
4075 btst(MinObjAlignmentInBytesMask, free); | |
4076 br(Assembler::zero, false, Assembler::pt, L); | |
4077 delayed()->nop(); | |
4078 STOP("updated TLAB free is not properly aligned"); | |
4079 bind(L); | |
4080 } | |
4081 #endif // ASSERT | |
4082 | |
4083 // update the tlab top pointer | |
4084 st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset())); | |
4085 verify_tlab(); | |
4086 } | |
4087 | |
4088 | |
4089 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) { | |
4090 Register top = O0; | |
4091 Register t1 = G1; | |
4092 Register t2 = G3; | |
4093 Register t3 = O1; | |
4094 assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */); | |
4095 Label do_refill, discard_tlab; | |
4096 | |
4097 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
4098 // No allocation in the shared eden. | |
4099 ba_short(slow_case); | |
4100 } | |
4101 | |
4102 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top); | |
4103 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1); | |
4104 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2); | |
4105 | |
4106 // calculate amount of free space | |
4107 sub(t1, top, t1); | |
4108 srl_ptr(t1, LogHeapWordSize, t1); | |
4109 | |
4110 // Retain tlab and allocate object in shared space if | |
4111 // the amount free in the tlab is too large to discard. | |
4112 cmp(t1, t2); | |
4113 brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab); | |
4114 | |
4115 // increment waste limit to prevent getting stuck on this slow path | |
4116 delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2); | |
4117 st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())); | |
4118 if (TLABStats) { | |
4119 // increment number of slow_allocations | |
4120 ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2); | |
4121 add(t2, 1, t2); | |
4122 stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset())); | |
4123 } | |
4124 ba_short(try_eden); | |
4125 | |
4126 bind(discard_tlab); | |
4127 if (TLABStats) { | |
4128 // increment number of refills | |
4129 ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2); | |
4130 add(t2, 1, t2); | |
4131 stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset())); | |
4132 // accumulate wastage | |
4133 ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2); | |
4134 add(t2, t1, t2); | |
4135 stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())); | |
4136 } | |
4137 | |
4138 // if tlab is currently allocated (top or end != null) then | |
4139 // fill [top, end + alignment_reserve) with array object | |
4140 br_null_short(top, Assembler::pn, do_refill); | |
4141 | |
4142 set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2); | |
4143 st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word | |
4144 // set klass to intArrayKlass | |
4145 sub(t1, typeArrayOopDesc::header_size(T_INT), t1); | |
4146 add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1); | |
4147 sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1); | |
4148 st(t1, top, arrayOopDesc::length_offset_in_bytes()); | |
4149 set((intptr_t)Universe::intArrayKlassObj_addr(), t2); | |
4150 ld_ptr(t2, 0, t2); | |
4151 // store klass last. concurrent gcs assumes klass length is valid if | |
4152 // klass field is not null. | |
4153 store_klass(t2, top); | |
4154 verify_oop(top); | |
4155 | |
4156 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t1); | |
4157 sub(top, t1, t1); // size of tlab's allocated portion | |
4158 incr_allocated_bytes(t1, t2, t3); | |
4159 | |
4160 // refill the tlab with an eden allocation | |
4161 bind(do_refill); | |
4162 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1); | |
4163 sll_ptr(t1, LogHeapWordSize, t1); | |
4164 // allocate new tlab, address returned in top | |
4165 eden_allocate(top, t1, 0, t2, t3, slow_case); | |
4166 | |
4167 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset())); | |
4168 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset())); | |
4169 #ifdef ASSERT | |
4170 // check that tlab_size (t1) is still valid | |
4171 { | |
4172 Label ok; | |
4173 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2); | |
4174 sll_ptr(t2, LogHeapWordSize, t2); | |
4175 cmp_and_br_short(t1, t2, Assembler::equal, Assembler::pt, ok); | |
4176 STOP("assert(t1 == tlab_size)"); | |
4177 should_not_reach_here(); | |
4178 | |
4179 bind(ok); | |
4180 } | |
4181 #endif // ASSERT | |
4182 add(top, t1, top); // t1 is tlab_size | |
4183 sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top); | |
4184 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset())); | |
4185 verify_tlab(); | |
4186 ba_short(retry); | |
4187 } | |
4188 | |
4189 void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes, | |
4190 Register t1, Register t2) { | |
4191 // Bump total bytes allocated by this thread | |
4192 assert(t1->is_global(), "must be global reg"); // so all 64 bits are saved on a context switch | |
4193 assert_different_registers(size_in_bytes.register_or_noreg(), t1, t2); | |
4194 // v8 support has gone the way of the dodo | |
4195 ldx(G2_thread, in_bytes(JavaThread::allocated_bytes_offset()), t1); | |
4196 add(t1, ensure_simm13_or_reg(size_in_bytes, t2), t1); | |
4197 stx(t1, G2_thread, in_bytes(JavaThread::allocated_bytes_offset())); | |
4198 } | |
4199 | |
4200 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { | |
4201 switch (cond) { | |
4202 // Note some conditions are synonyms for others | |
4203 case Assembler::never: return Assembler::always; | |
4204 case Assembler::zero: return Assembler::notZero; | |
4205 case Assembler::lessEqual: return Assembler::greater; | |
4206 case Assembler::less: return Assembler::greaterEqual; | |
4207 case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned; | |
4208 case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned; | |
4209 case Assembler::negative: return Assembler::positive; | |
4210 case Assembler::overflowSet: return Assembler::overflowClear; | |
4211 case Assembler::always: return Assembler::never; | |
4212 case Assembler::notZero: return Assembler::zero; | |
4213 case Assembler::greater: return Assembler::lessEqual; | |
4214 case Assembler::greaterEqual: return Assembler::less; | |
4215 case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned; | |
4216 case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned; | |
4217 case Assembler::positive: return Assembler::negative; | |
4218 case Assembler::overflowClear: return Assembler::overflowSet; | |
4219 } | |
4220 | |
4221 ShouldNotReachHere(); return Assembler::overflowClear; | |
4222 } | |
4223 | |
4224 void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr, | |
4225 Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) { | |
4226 Condition negated_cond = negate_condition(cond); | |
4227 Label L; | |
4228 brx(negated_cond, false, Assembler::pt, L); | |
4229 delayed()->nop(); | |
4230 inc_counter(counter_ptr, Rtmp1, Rtmp2); | |
4231 bind(L); | |
4232 } | |
4233 | |
4234 void MacroAssembler::inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2) { | |
4235 AddressLiteral addrlit(counter_addr); | |
4236 sethi(addrlit, Rtmp1); // Move hi22 bits into temporary register. | |
4237 Address addr(Rtmp1, addrlit.low10()); // Build an address with low10 bits. | |
4238 ld(addr, Rtmp2); | |
4239 inc(Rtmp2); | |
4240 st(Rtmp2, addr); | |
4241 } | |
4242 | |
4243 void MacroAssembler::inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2) { | |
4244 inc_counter((address) counter_addr, Rtmp1, Rtmp2); | |
4245 } | |
4246 | |
4247 SkipIfEqual::SkipIfEqual( | |
4248 MacroAssembler* masm, Register temp, const bool* flag_addr, | |
4249 Assembler::Condition condition) { | |
4250 _masm = masm; | |
4251 AddressLiteral flag(flag_addr); | |
4252 _masm->sethi(flag, temp); | |
4253 _masm->ldub(temp, flag.low10(), temp); | |
4254 _masm->tst(temp); | |
4255 _masm->br(condition, false, Assembler::pt, _label); | |
4256 _masm->delayed()->nop(); | |
4257 } | |
4258 | |
4259 SkipIfEqual::~SkipIfEqual() { | |
4260 _masm->bind(_label); | |
4261 } | |
4262 | |
4263 | |
4264 // Writes to stack successive pages until offset reached to check for | |
4265 // stack overflow + shadow pages. This clobbers tsp and scratch. | |
4266 void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp, | |
4267 Register Rscratch) { | |
4268 // Use stack pointer in temp stack pointer | |
4269 mov(SP, Rtsp); | |
4270 | |
4271 // Bang stack for total size given plus stack shadow page size. | |
4272 // Bang one page at a time because a large size can overflow yellow and | |
4273 // red zones (the bang will fail but stack overflow handling can't tell that | |
4274 // it was a stack overflow bang vs a regular segv). | |
4275 int offset = os::vm_page_size(); | |
4276 Register Roffset = Rscratch; | |
4277 | |
4278 Label loop; | |
4279 bind(loop); | |
4280 set((-offset)+STACK_BIAS, Rscratch); | |
4281 st(G0, Rtsp, Rscratch); | |
4282 set(offset, Roffset); | |
4283 sub(Rsize, Roffset, Rsize); | |
4284 cmp(Rsize, G0); | |
4285 br(Assembler::greater, false, Assembler::pn, loop); | |
4286 delayed()->sub(Rtsp, Roffset, Rtsp); | |
4287 | |
4288 // Bang down shadow pages too. | |
4289 // The -1 because we already subtracted 1 page. | |
4290 for (int i = 0; i< StackShadowPages-1; i++) { | |
4291 set((-i*offset)+STACK_BIAS, Rscratch); | |
4292 st(G0, Rtsp, Rscratch); | |
4293 } | |
4294 } | |
4295 | |
4296 /////////////////////////////////////////////////////////////////////////////////// | |
4297 #ifndef SERIALGC | |
4298 | |
4299 static address satb_log_enqueue_with_frame = NULL; | |
4300 static u_char* satb_log_enqueue_with_frame_end = NULL; | |
4301 | |
4302 static address satb_log_enqueue_frameless = NULL; | |
4303 static u_char* satb_log_enqueue_frameless_end = NULL; | |
4304 | |
4305 static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions? | |
4306 | |
4307 static void generate_satb_log_enqueue(bool with_frame) { | |
4308 BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize); | |
4309 CodeBuffer buf(bb); | |
4310 MacroAssembler masm(&buf); | |
4311 | |
4312 #define __ masm. | |
4313 | |
4314 address start = __ pc(); | |
4315 Register pre_val; | |
4316 | |
4317 Label refill, restart; | |
4318 if (with_frame) { | |
4319 __ save_frame(0); | |
4320 pre_val = I0; // Was O0 before the save. | |
4321 } else { | |
4322 pre_val = O0; | |
4323 } | |
4324 | |
4325 int satb_q_index_byte_offset = | |
4326 in_bytes(JavaThread::satb_mark_queue_offset() + | |
4327 PtrQueue::byte_offset_of_index()); | |
4328 | |
4329 int satb_q_buf_byte_offset = | |
4330 in_bytes(JavaThread::satb_mark_queue_offset() + | |
4331 PtrQueue::byte_offset_of_buf()); | |
4332 | |
4333 assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) && | |
4334 in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t), | |
4335 "check sizes in assembly below"); | |
4336 | |
4337 __ bind(restart); | |
4338 | |
4339 // Load the index into the SATB buffer. PtrQueue::_index is a size_t | |
4340 // so ld_ptr is appropriate. | |
4341 __ ld_ptr(G2_thread, satb_q_index_byte_offset, L0); | |
4342 | |
4343 // index == 0? | |
4344 __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill); | |
4345 | |
4346 __ ld_ptr(G2_thread, satb_q_buf_byte_offset, L1); | |
4347 __ sub(L0, oopSize, L0); | |
4348 | |
4349 __ st_ptr(pre_val, L1, L0); // [_buf + index] := I0 | |
4350 if (!with_frame) { | |
4351 // Use return-from-leaf | |
4352 __ retl(); | |
4353 __ delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset); | |
4354 } else { | |
4355 // Not delayed. | |
4356 __ st_ptr(L0, G2_thread, satb_q_index_byte_offset); | |
4357 } | |
4358 if (with_frame) { | |
4359 __ ret(); | |
4360 __ delayed()->restore(); | |
4361 } | |
4362 __ bind(refill); | |
4363 | |
4364 address handle_zero = | |
4365 CAST_FROM_FN_PTR(address, | |
4366 &SATBMarkQueueSet::handle_zero_index_for_thread); | |
4367 // This should be rare enough that we can afford to save all the | |
4368 // scratch registers that the calling context might be using. | |
4369 __ mov(G1_scratch, L0); | |
4370 __ mov(G3_scratch, L1); | |
4371 __ mov(G4, L2); | |
4372 // We need the value of O0 above (for the write into the buffer), so we | |
4373 // save and restore it. | |
4374 __ mov(O0, L3); | |
4375 // Since the call will overwrite O7, we save and restore that, as well. | |
4376 __ mov(O7, L4); | |
4377 __ call_VM_leaf(L5, handle_zero, G2_thread); | |
4378 __ mov(L0, G1_scratch); | |
4379 __ mov(L1, G3_scratch); | |
4380 __ mov(L2, G4); | |
4381 __ mov(L3, O0); | |
4382 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart); | |
4383 __ delayed()->mov(L4, O7); | |
4384 | |
4385 if (with_frame) { | |
4386 satb_log_enqueue_with_frame = start; | |
4387 satb_log_enqueue_with_frame_end = __ pc(); | |
4388 } else { | |
4389 satb_log_enqueue_frameless = start; | |
4390 satb_log_enqueue_frameless_end = __ pc(); | |
4391 } | |
4392 | |
4393 #undef __ | |
4394 } | |
4395 | |
4396 static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) { | |
4397 if (with_frame) { | |
4398 if (satb_log_enqueue_with_frame == 0) { | |
4399 generate_satb_log_enqueue(with_frame); | |
4400 assert(satb_log_enqueue_with_frame != 0, "postcondition."); | |
4401 if (G1SATBPrintStubs) { | |
4402 tty->print_cr("Generated with-frame satb enqueue:"); | |
4403 Disassembler::decode((u_char*)satb_log_enqueue_with_frame, | |
4404 satb_log_enqueue_with_frame_end, | |
4405 tty); | |
4406 } | |
4407 } | |
4408 } else { | |
4409 if (satb_log_enqueue_frameless == 0) { | |
4410 generate_satb_log_enqueue(with_frame); | |
4411 assert(satb_log_enqueue_frameless != 0, "postcondition."); | |
4412 if (G1SATBPrintStubs) { | |
4413 tty->print_cr("Generated frameless satb enqueue:"); | |
4414 Disassembler::decode((u_char*)satb_log_enqueue_frameless, | |
4415 satb_log_enqueue_frameless_end, | |
4416 tty); | |
4417 } | |
4418 } | |
4419 } | |
4420 } | |
4421 | |
4422 void MacroAssembler::g1_write_barrier_pre(Register obj, | |
4423 Register index, | |
4424 int offset, | |
4425 Register pre_val, | |
4426 Register tmp, | |
4427 bool preserve_o_regs) { | |
4428 Label filtered; | |
4429 | |
4430 if (obj == noreg) { | |
4431 // We are not loading the previous value so make | |
4432 // sure that we don't trash the value in pre_val | |
4433 // with the code below. | |
4434 assert_different_registers(pre_val, tmp); | |
4435 } else { | |
4436 // We will be loading the previous value | |
4437 // in this code so... | |
4438 assert(offset == 0 || index == noreg, "choose one"); | |
4439 assert(pre_val == noreg, "check this code"); | |
4440 } | |
4441 | |
4442 // Is marking active? | |
4443 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { | |
4444 ld(G2, | |
4445 in_bytes(JavaThread::satb_mark_queue_offset() + | |
4446 PtrQueue::byte_offset_of_active()), | |
4447 tmp); | |
4448 } else { | |
4449 guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1, | |
4450 "Assumption"); | |
4451 ldsb(G2, | |
4452 in_bytes(JavaThread::satb_mark_queue_offset() + | |
4453 PtrQueue::byte_offset_of_active()), | |
4454 tmp); | |
4455 } | |
4456 | |
4457 // Is marking active? | |
4458 cmp_and_br_short(tmp, G0, Assembler::equal, Assembler::pt, filtered); | |
4459 | |
4460 // Do we need to load the previous value? | |
4461 if (obj != noreg) { | |
4462 // Load the previous value... | |
4463 if (index == noreg) { | |
4464 if (Assembler::is_simm13(offset)) { | |
4465 load_heap_oop(obj, offset, tmp); | |
4466 } else { | |
4467 set(offset, tmp); | |
4468 load_heap_oop(obj, tmp, tmp); | |
4469 } | |
4470 } else { | |
4471 load_heap_oop(obj, index, tmp); | |
4472 } | |
4473 // Previous value has been loaded into tmp | |
4474 pre_val = tmp; | |
4475 } | |
4476 | |
4477 assert(pre_val != noreg, "must have a real register"); | |
4478 | |
4479 // Is the previous value null? | |
4480 cmp_and_brx_short(pre_val, G0, Assembler::equal, Assembler::pt, filtered); | |
4481 | |
4482 // OK, it's not filtered, so we'll need to call enqueue. In the normal | |
4483 // case, pre_val will be a scratch G-reg, but there are some cases in | |
4484 // which it's an O-reg. In the first case, do a normal call. In the | |
4485 // latter, do a save here and call the frameless version. | |
4486 | |
4487 guarantee(pre_val->is_global() || pre_val->is_out(), | |
4488 "Or we need to think harder."); | |
4489 | |
4490 if (pre_val->is_global() && !preserve_o_regs) { | |
4491 generate_satb_log_enqueue_if_necessary(true); // with frame | |
4492 | |
4493 call(satb_log_enqueue_with_frame); | |
4494 delayed()->mov(pre_val, O0); | |
4495 } else { | |
4496 generate_satb_log_enqueue_if_necessary(false); // frameless | |
4497 | |
4498 save_frame(0); | |
4499 call(satb_log_enqueue_frameless); | |
4500 delayed()->mov(pre_val->after_save(), O0); | |
4501 restore(); | |
4502 } | |
4503 | |
4504 bind(filtered); | |
4505 } | |
4506 | |
4507 static address dirty_card_log_enqueue = 0; | |
4508 static u_char* dirty_card_log_enqueue_end = 0; | |
4509 | |
4510 // This gets to assume that o0 contains the object address. | |
4511 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) { | |
4512 BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2); | |
4513 CodeBuffer buf(bb); | |
4514 MacroAssembler masm(&buf); | |
4515 #define __ masm. | |
4516 address start = __ pc(); | |
4517 | |
4518 Label not_already_dirty, restart, refill; | |
4519 | |
4520 #ifdef _LP64 | |
4521 __ srlx(O0, CardTableModRefBS::card_shift, O0); | |
4522 #else | |
4523 __ srl(O0, CardTableModRefBS::card_shift, O0); | |
4524 #endif | |
4525 AddressLiteral addrlit(byte_map_base); | |
4526 __ set(addrlit, O1); // O1 := <card table base> | |
4527 __ ldub(O0, O1, O2); // O2 := [O0 + O1] | |
4528 | |
4529 assert(CardTableModRefBS::dirty_card_val() == 0, "otherwise check this code"); | |
4530 __ cmp_and_br_short(O2, G0, Assembler::notEqual, Assembler::pt, not_already_dirty); | |
4531 | |
4532 // We didn't take the branch, so we're already dirty: return. | |
4533 // Use return-from-leaf | |
4534 __ retl(); | |
4535 __ delayed()->nop(); | |
4536 | |
4537 // Not dirty. | |
4538 __ bind(not_already_dirty); | |
4539 | |
4540 // Get O0 + O1 into a reg by itself | |
4541 __ add(O0, O1, O3); | |
4542 | |
4543 // First, dirty it. | |
4544 __ stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty). | |
4545 | |
4546 int dirty_card_q_index_byte_offset = | |
4547 in_bytes(JavaThread::dirty_card_queue_offset() + | |
4548 PtrQueue::byte_offset_of_index()); | |
4549 int dirty_card_q_buf_byte_offset = | |
4550 in_bytes(JavaThread::dirty_card_queue_offset() + | |
4551 PtrQueue::byte_offset_of_buf()); | |
4552 __ bind(restart); | |
4553 | |
4554 // Load the index into the update buffer. PtrQueue::_index is | |
4555 // a size_t so ld_ptr is appropriate here. | |
4556 __ ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0); | |
4557 | |
4558 // index == 0? | |
4559 __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill); | |
4560 | |
4561 __ ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1); | |
4562 __ sub(L0, oopSize, L0); | |
4563 | |
4564 __ st_ptr(O3, L1, L0); // [_buf + index] := I0 | |
4565 // Use return-from-leaf | |
4566 __ retl(); | |
4567 __ delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset); | |
4568 | |
4569 __ bind(refill); | |
4570 address handle_zero = | |
4571 CAST_FROM_FN_PTR(address, | |
4572 &DirtyCardQueueSet::handle_zero_index_for_thread); | |
4573 // This should be rare enough that we can afford to save all the | |
4574 // scratch registers that the calling context might be using. | |
4575 __ mov(G1_scratch, L3); | |
4576 __ mov(G3_scratch, L5); | |
4577 // We need the value of O3 above (for the write into the buffer), so we | |
4578 // save and restore it. | |
4579 __ mov(O3, L6); | |
4580 // Since the call will overwrite O7, we save and restore that, as well. | |
4581 __ mov(O7, L4); | |
4582 | |
4583 __ call_VM_leaf(L7_thread_cache, handle_zero, G2_thread); | |
4584 __ mov(L3, G1_scratch); | |
4585 __ mov(L5, G3_scratch); | |
4586 __ mov(L6, O3); | |
4587 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart); | |
4588 __ delayed()->mov(L4, O7); | |
4589 | |
4590 dirty_card_log_enqueue = start; | |
4591 dirty_card_log_enqueue_end = __ pc(); | |
4592 // XXX Should have a guarantee here about not going off the end! | |
4593 // Does it already do so? Do an experiment... | |
4594 | |
4595 #undef __ | |
4596 | |
4597 } | |
4598 | |
4599 static inline void | |
4600 generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) { | |
4601 if (dirty_card_log_enqueue == 0) { | |
4602 generate_dirty_card_log_enqueue(byte_map_base); | |
4603 assert(dirty_card_log_enqueue != 0, "postcondition."); | |
4604 if (G1SATBPrintStubs) { | |
4605 tty->print_cr("Generated dirty_card enqueue:"); | |
4606 Disassembler::decode((u_char*)dirty_card_log_enqueue, | |
4607 dirty_card_log_enqueue_end, | |
4608 tty); | |
4609 } | |
4610 } | |
4611 } | |
4612 | |
4613 | |
4614 void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) { | |
4615 | |
4616 Label filtered; | |
4617 MacroAssembler* post_filter_masm = this; | |
4618 | |
4619 if (new_val == G0) return; | |
4620 | |
4621 G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set(); | |
4622 assert(bs->kind() == BarrierSet::G1SATBCT || | |
4623 bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier"); | |
4624 | |
4625 if (G1RSBarrierRegionFilter) { | |
4626 xor3(store_addr, new_val, tmp); | |
4627 #ifdef _LP64 | |
4628 srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp); | |
4629 #else | |
4630 srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp); | |
4631 #endif | |
4632 | |
4633 // XXX Should I predict this taken or not? Does it matter? | |
4634 cmp_and_brx_short(tmp, G0, Assembler::equal, Assembler::pt, filtered); | |
4635 } | |
4636 | |
4637 // If the "store_addr" register is an "in" or "local" register, move it to | |
4638 // a scratch reg so we can pass it as an argument. | |
4639 bool use_scr = !(store_addr->is_global() || store_addr->is_out()); | |
4640 // Pick a scratch register different from "tmp". | |
4641 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch); | |
4642 // Make sure we use up the delay slot! | |
4643 if (use_scr) { | |
4644 post_filter_masm->mov(store_addr, scr); | |
4645 } else { | |
4646 post_filter_masm->nop(); | |
4647 } | |
4648 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base); | |
4649 save_frame(0); | |
4650 call(dirty_card_log_enqueue); | |
4651 if (use_scr) { | |
4652 delayed()->mov(scr, O0); | |
4653 } else { | |
4654 delayed()->mov(store_addr->after_save(), O0); | |
4655 } | |
4656 restore(); | |
4657 | |
4658 bind(filtered); | |
4659 } | |
4660 | |
4661 #endif // SERIALGC | |
4662 /////////////////////////////////////////////////////////////////////////////////// | |
4663 | |
4664 void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) { | |
4665 // If we're writing constant NULL, we can skip the write barrier. | |
4666 if (new_val == G0) return; | |
4667 CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set(); | |
4668 assert(bs->kind() == BarrierSet::CardTableModRef || | |
4669 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier"); | |
4670 card_table_write(bs->byte_map_base, tmp, store_addr); | |
4671 } | |
4672 | |
4673 void MacroAssembler::load_klass(Register src_oop, Register klass) { | |
4674 // The number of bytes in this code is used by | |
4675 // MachCallDynamicJavaNode::ret_addr_offset() | |
4676 // if this changes, change that. | |
4677 if (UseCompressedKlassPointers) { | |
4678 lduw(src_oop, oopDesc::klass_offset_in_bytes(), klass); | |
4679 decode_klass_not_null(klass); | |
4680 } else { | |
4681 ld_ptr(src_oop, oopDesc::klass_offset_in_bytes(), klass); | |
4682 } | |
4683 } | |
4684 | |
4685 void MacroAssembler::store_klass(Register klass, Register dst_oop) { | |
4686 if (UseCompressedKlassPointers) { | |
4687 assert(dst_oop != klass, "not enough registers"); | |
4688 encode_klass_not_null(klass); | |
4689 st(klass, dst_oop, oopDesc::klass_offset_in_bytes()); | |
4690 } else { | |
4691 st_ptr(klass, dst_oop, oopDesc::klass_offset_in_bytes()); | |
4692 } | |
4693 } | |
4694 | |
4695 void MacroAssembler::store_klass_gap(Register s, Register d) { | |
4696 if (UseCompressedKlassPointers) { | |
4697 assert(s != d, "not enough registers"); | |
4698 st(s, d, oopDesc::klass_gap_offset_in_bytes()); | |
4699 } | |
4700 } | |
4701 | |
4702 void MacroAssembler::load_heap_oop(const Address& s, Register d) { | |
4703 if (UseCompressedOops) { | |
4704 lduw(s, d); | |
4705 decode_heap_oop(d); | |
4706 } else { | |
4707 ld_ptr(s, d); | |
4708 } | |
4709 } | |
4710 | |
4711 void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) { | |
4712 if (UseCompressedOops) { | |
4713 lduw(s1, s2, d); | |
4714 decode_heap_oop(d, d); | |
4715 } else { | |
4716 ld_ptr(s1, s2, d); | |
4717 } | |
4718 } | |
4719 | |
4720 void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) { | |
4721 if (UseCompressedOops) { | |
4722 lduw(s1, simm13a, d); | |
4723 decode_heap_oop(d, d); | |
4724 } else { | |
4725 ld_ptr(s1, simm13a, d); | |
4726 } | |
4727 } | |
4728 | |
4729 void MacroAssembler::load_heap_oop(Register s1, RegisterOrConstant s2, Register d) { | |
4730 if (s2.is_constant()) load_heap_oop(s1, s2.as_constant(), d); | |
4731 else load_heap_oop(s1, s2.as_register(), d); | |
4732 } | |
4733 | |
4734 void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) { | |
4735 if (UseCompressedOops) { | |
4736 assert(s1 != d && s2 != d, "not enough registers"); | |
4737 encode_heap_oop(d); | |
4738 st(d, s1, s2); | |
4739 } else { | |
4740 st_ptr(d, s1, s2); | |
4741 } | |
4742 } | |
4743 | |
4744 void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) { | |
4745 if (UseCompressedOops) { | |
4746 assert(s1 != d, "not enough registers"); | |
4747 encode_heap_oop(d); | |
4748 st(d, s1, simm13a); | |
4749 } else { | |
4750 st_ptr(d, s1, simm13a); | |
4751 } | |
4752 } | |
4753 | |
4754 void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) { | |
4755 if (UseCompressedOops) { | |
4756 assert(a.base() != d, "not enough registers"); | |
4757 encode_heap_oop(d); | |
4758 st(d, a, offset); | |
4759 } else { | |
4760 st_ptr(d, a, offset); | |
4761 } | |
4762 } | |
4763 | |
4764 | |
4765 void MacroAssembler::encode_heap_oop(Register src, Register dst) { | |
4766 assert (UseCompressedOops, "must be compressed"); | |
4767 assert (Universe::heap() != NULL, "java heap should be initialized"); | |
4768 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); | |
4769 verify_oop(src); | |
4770 if (Universe::narrow_oop_base() == NULL) { | |
4771 srlx(src, LogMinObjAlignmentInBytes, dst); | |
4772 return; | |
4773 } | |
4774 Label done; | |
4775 if (src == dst) { | |
4776 // optimize for frequent case src == dst | |
4777 bpr(rc_nz, true, Assembler::pt, src, done); | |
4778 delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken | |
4779 bind(done); | |
4780 srlx(src, LogMinObjAlignmentInBytes, dst); | |
4781 } else { | |
4782 bpr(rc_z, false, Assembler::pn, src, done); | |
4783 delayed() -> mov(G0, dst); | |
4784 // could be moved before branch, and annulate delay, | |
4785 // but may add some unneeded work decoding null | |
4786 sub(src, G6_heapbase, dst); | |
4787 srlx(dst, LogMinObjAlignmentInBytes, dst); | |
4788 bind(done); | |
4789 } | |
4790 } | |
4791 | |
4792 | |
4793 void MacroAssembler::encode_heap_oop_not_null(Register r) { | |
4794 assert (UseCompressedOops, "must be compressed"); | |
4795 assert (Universe::heap() != NULL, "java heap should be initialized"); | |
4796 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); | |
4797 verify_oop(r); | |
4798 if (Universe::narrow_oop_base() != NULL) | |
4799 sub(r, G6_heapbase, r); | |
4800 srlx(r, LogMinObjAlignmentInBytes, r); | |
4801 } | |
4802 | |
4803 void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) { | |
4804 assert (UseCompressedOops, "must be compressed"); | |
4805 assert (Universe::heap() != NULL, "java heap should be initialized"); | |
4806 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); | |
4807 verify_oop(src); | |
4808 if (Universe::narrow_oop_base() == NULL) { | |
4809 srlx(src, LogMinObjAlignmentInBytes, dst); | |
4810 } else { | |
4811 sub(src, G6_heapbase, dst); | |
4812 srlx(dst, LogMinObjAlignmentInBytes, dst); | |
4813 } | |
4814 } | |
4815 | |
4816 // Same algorithm as oops.inline.hpp decode_heap_oop. | |
4817 void MacroAssembler::decode_heap_oop(Register src, Register dst) { | |
4818 assert (UseCompressedOops, "must be compressed"); | |
4819 assert (Universe::heap() != NULL, "java heap should be initialized"); | |
4820 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); | |
4821 sllx(src, LogMinObjAlignmentInBytes, dst); | |
4822 if (Universe::narrow_oop_base() != NULL) { | |
4823 Label done; | |
4824 bpr(rc_nz, true, Assembler::pt, dst, done); | |
4825 delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken | |
4826 bind(done); | |
4827 } | |
4828 verify_oop(dst); | |
4829 } | |
4830 | |
4831 void MacroAssembler::decode_heap_oop_not_null(Register r) { | |
4832 // Do not add assert code to this unless you change vtableStubs_sparc.cpp | |
4833 // pd_code_size_limit. | |
4834 // Also do not verify_oop as this is called by verify_oop. | |
4835 assert (UseCompressedOops, "must be compressed"); | |
4836 assert (Universe::heap() != NULL, "java heap should be initialized"); | |
4837 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); | |
4838 sllx(r, LogMinObjAlignmentInBytes, r); | |
4839 if (Universe::narrow_oop_base() != NULL) | |
4840 add(r, G6_heapbase, r); | |
4841 } | |
4842 | |
4843 void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) { | |
4844 // Do not add assert code to this unless you change vtableStubs_sparc.cpp | |
4845 // pd_code_size_limit. | |
4846 // Also do not verify_oop as this is called by verify_oop. | |
4847 assert (UseCompressedOops, "must be compressed"); | |
4848 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); | |
4849 sllx(src, LogMinObjAlignmentInBytes, dst); | |
4850 if (Universe::narrow_oop_base() != NULL) | |
4851 add(dst, G6_heapbase, dst); | |
4852 } | |
4853 | |
4854 void MacroAssembler::encode_klass_not_null(Register r) { | |
4855 assert(Metaspace::is_initialized(), "metaspace should be initialized"); | |
4856 assert (UseCompressedKlassPointers, "must be compressed"); | |
4857 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); | |
4858 if (Universe::narrow_klass_base() != NULL) | |
4859 sub(r, G6_heapbase, r); | |
4860 srlx(r, LogKlassAlignmentInBytes, r); | |
4861 } | |
4862 | |
4863 void MacroAssembler::encode_klass_not_null(Register src, Register dst) { | |
4864 assert(Metaspace::is_initialized(), "metaspace should be initialized"); | |
4865 assert (UseCompressedKlassPointers, "must be compressed"); | |
4866 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); | |
4867 if (Universe::narrow_klass_base() == NULL) { | |
4868 srlx(src, LogKlassAlignmentInBytes, dst); | |
4869 } else { | |
4870 sub(src, G6_heapbase, dst); | |
4871 srlx(dst, LogKlassAlignmentInBytes, dst); | |
4872 } | |
4873 } | |
4874 | |
4875 void MacroAssembler::decode_klass_not_null(Register r) { | |
4876 assert(Metaspace::is_initialized(), "metaspace should be initialized"); | |
4877 // Do not add assert code to this unless you change vtableStubs_sparc.cpp | |
4878 // pd_code_size_limit. | |
4879 assert (UseCompressedKlassPointers, "must be compressed"); | |
4880 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); | |
4881 sllx(r, LogKlassAlignmentInBytes, r); | |
4882 if (Universe::narrow_klass_base() != NULL) | |
4883 add(r, G6_heapbase, r); | |
4884 } | |
4885 | |
4886 void MacroAssembler::decode_klass_not_null(Register src, Register dst) { | |
4887 assert(Metaspace::is_initialized(), "metaspace should be initialized"); | |
4888 // Do not add assert code to this unless you change vtableStubs_sparc.cpp | |
4889 // pd_code_size_limit. | |
4890 assert (UseCompressedKlassPointers, "must be compressed"); | |
4891 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); | |
4892 sllx(src, LogKlassAlignmentInBytes, dst); | |
4893 if (Universe::narrow_klass_base() != NULL) | |
4894 add(dst, G6_heapbase, dst); | |
4895 } | |
4896 | |
4897 void MacroAssembler::reinit_heapbase() { | |
4898 if (UseCompressedOops || UseCompressedKlassPointers) { | |
4899 AddressLiteral base(Universe::narrow_ptrs_base_addr()); | |
4900 load_ptr_contents(base, G6_heapbase); | |
4901 } | |
4902 } | |
4903 | |
4904 // Compare char[] arrays aligned to 4 bytes. | |
4905 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2, | |
4906 Register limit, Register result, | |
4907 Register chr1, Register chr2, Label& Ldone) { | |
4908 Label Lvector, Lloop; | |
4909 assert(chr1 == result, "should be the same"); | |
4910 | |
4911 // Note: limit contains number of bytes (2*char_elements) != 0. | |
4912 andcc(limit, 0x2, chr1); // trailing character ? | |
4913 br(Assembler::zero, false, Assembler::pt, Lvector); | |
4914 delayed()->nop(); | |
4915 | |
4916 // compare the trailing char | |
4917 sub(limit, sizeof(jchar), limit); | |
4918 lduh(ary1, limit, chr1); | |
4919 lduh(ary2, limit, chr2); | |
4920 cmp(chr1, chr2); | |
4921 br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
4922 delayed()->mov(G0, result); // not equal | |
4923 | |
4924 // only one char ? | |
4925 cmp_zero_and_br(zero, limit, Ldone, true, Assembler::pn); | |
4926 delayed()->add(G0, 1, result); // zero-length arrays are equal | |
4927 | |
4928 // word by word compare, dont't need alignment check | |
4929 bind(Lvector); | |
4930 // Shift ary1 and ary2 to the end of the arrays, negate limit | |
4931 add(ary1, limit, ary1); | |
4932 add(ary2, limit, ary2); | |
4933 neg(limit, limit); | |
4934 | |
4935 lduw(ary1, limit, chr1); | |
4936 bind(Lloop); | |
4937 lduw(ary2, limit, chr2); | |
4938 cmp(chr1, chr2); | |
4939 br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
4940 delayed()->mov(G0, result); // not equal | |
4941 inccc(limit, 2*sizeof(jchar)); | |
4942 // annul LDUW if branch is not taken to prevent access past end of array | |
4943 br(Assembler::notZero, true, Assembler::pt, Lloop); | |
4944 delayed()->lduw(ary1, limit, chr1); // hoisted | |
4945 | |
4946 // Caller should set it: | |
4947 // add(G0, 1, result); // equals | |
4948 } | |
4949 | |
4950 // Use BIS for zeroing (count is in bytes). | |
4951 void MacroAssembler::bis_zeroing(Register to, Register count, Register temp, Label& Ldone) { | |
4952 assert(UseBlockZeroing && VM_Version::has_block_zeroing(), "only works with BIS zeroing"); | |
4953 Register end = count; | |
4954 int cache_line_size = VM_Version::prefetch_data_size(); | |
4955 // Minimum count when BIS zeroing can be used since | |
4956 // it needs membar which is expensive. | |
4957 int block_zero_size = MAX2(cache_line_size*3, (int)BlockZeroingLowLimit); | |
4958 | |
4959 Label small_loop; | |
4960 // Check if count is negative (dead code) or zero. | |
4961 // Note, count uses 64bit in 64 bit VM. | |
4962 cmp_and_brx_short(count, 0, Assembler::lessEqual, Assembler::pn, Ldone); | |
4963 | |
4964 // Use BIS zeroing only for big arrays since it requires membar. | |
4965 if (Assembler::is_simm13(block_zero_size)) { // < 4096 | |
4966 cmp(count, block_zero_size); | |
4967 } else { | |
4968 set(block_zero_size, temp); | |
4969 cmp(count, temp); | |
4970 } | |
4971 br(Assembler::lessUnsigned, false, Assembler::pt, small_loop); | |
4972 delayed()->add(to, count, end); | |
4973 | |
4974 // Note: size is >= three (32 bytes) cache lines. | |
4975 | |
4976 // Clean the beginning of space up to next cache line. | |
4977 for (int offs = 0; offs < cache_line_size; offs += 8) { | |
4978 stx(G0, to, offs); | |
4979 } | |
4980 | |
4981 // align to next cache line | |
4982 add(to, cache_line_size, to); | |
4983 and3(to, -cache_line_size, to); | |
4984 | |
4985 // Note: size left >= two (32 bytes) cache lines. | |
4986 | |
4987 // BIS should not be used to zero tail (64 bytes) | |
4988 // to avoid zeroing a header of the following object. | |
4989 sub(end, (cache_line_size*2)-8, end); | |
4990 | |
4991 Label bis_loop; | |
4992 bind(bis_loop); | |
4993 stxa(G0, to, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); | |
4994 add(to, cache_line_size, to); | |
4995 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, bis_loop); | |
4996 | |
4997 // BIS needs membar. | |
4998 membar(Assembler::StoreLoad); | |
4999 | |
5000 add(end, (cache_line_size*2)-8, end); // restore end | |
5001 cmp_and_brx_short(to, end, Assembler::greaterEqualUnsigned, Assembler::pn, Ldone); | |
5002 | |
5003 // Clean the tail. | |
5004 bind(small_loop); | |
5005 stx(G0, to, 0); | |
5006 add(to, 8, to); | |
5007 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, small_loop); | |
5008 nop(); // Separate short branches | |
5009 } |