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diff mx/mx_graal.py @ 20992:0a4bbeae6e31

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[SPARC] Configure registers right for register pressure in gate run
author Stefan Anzinger <stefan.anzinger@oracle.com>
date Thu, 16 Apr 2015 17:00:53 +0200
parents f61ff7f01bc2
children 68ff637e95b1
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line diff
--- a/mx/mx_graal.py	Thu Apr 16 16:21:09 2015 +0200
+++ b/mx/mx_graal.py	Thu Apr 16 17:00:53 2015 +0200
@@ -1543,7 +1543,9 @@
 
     with VM('graal', 'product'):
         with Task('BootstrapWithRegisterPressure:product', tasks) as t:
-            if t: vm(['-XX:-TieredCompilation', '-G:RegisterPressure=rbx,r11,r10,r14,xmm3,xmm11,xmm14', '-esa', '-version'])
+            if t: 
+                registers = 'o0,o1,o2,o3,f8,f9,d32,d34' if platform.processor() == 'sparc' else 'rbx,r11,r10,r14,xmm3,xmm11,xmm14'
+                vm(['-XX:-TieredCompilation', '-G:RegisterPressure=' + registers, '-esa', '-version'])
 
     with VM('graal', 'product'):
         with Task('BootstrapWithImmutableCode:product', tasks) as t: