Mercurial > hg > truffle
diff src/cpu/x86/vm/x86_64.ad @ 3854:1af104d6cf99
7079329: Adjust allocation prefetching for T4
Summary: on T4 2 BIS instructions should be issued to prefetch 64 bytes
Reviewed-by: iveresov, phh, twisti
author | kvn |
---|---|
date | Tue, 16 Aug 2011 16:59:46 -0700 |
parents | 95134e034042 |
children | d8cb48376797 |
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--- a/src/cpu/x86/vm/x86_64.ad Tue Aug 16 11:53:57 2011 -0700 +++ b/src/cpu/x86/vm/x86_64.ad Tue Aug 16 16:59:46 2011 -0700 @@ -6617,8 +6617,9 @@ ins_cost(125); format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} - opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */ - ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); + ins_encode %{ + __ prefetchr($mem$$Address); + %} ins_pipe(ialu_mem); %} @@ -6628,8 +6629,9 @@ ins_cost(125); format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} - opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ - ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); + ins_encode %{ + __ prefetchnta($mem$$Address); + %} ins_pipe(ialu_mem); %} @@ -6639,8 +6641,9 @@ ins_cost(125); format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} - opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ - ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); + ins_encode %{ + __ prefetcht0($mem$$Address); + %} ins_pipe(ialu_mem); %} @@ -6650,52 +6653,70 @@ ins_cost(125); format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} - opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ - ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem)); - ins_pipe(ialu_mem); -%} - -instruct prefetchw( memory mem ) %{ - predicate(AllocatePrefetchInstr==3); - match(PrefetchWrite mem); - ins_cost(125); - - format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %} - opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ - ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); + ins_encode %{ + __ prefetcht2($mem$$Address); + %} ins_pipe(ialu_mem); %} instruct prefetchwNTA( memory mem ) %{ - predicate(AllocatePrefetchInstr==0); match(PrefetchWrite mem); ins_cost(125); format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} - opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ - ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); + ins_encode %{ + __ prefetchnta($mem$$Address); + %} ins_pipe(ialu_mem); %} -instruct prefetchwT0( memory mem ) %{ - predicate(AllocatePrefetchInstr==1); - match(PrefetchWrite mem); +// Prefetch instructions for allocation. + +instruct prefetchAlloc( memory mem ) %{ + predicate(AllocatePrefetchInstr==3); + match(PrefetchAllocation mem); + ins_cost(125); + + format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %} + ins_encode %{ + __ prefetchw($mem$$Address); + %} + ins_pipe(ialu_mem); +%} + +instruct prefetchAllocNTA( memory mem ) %{ + predicate(AllocatePrefetchInstr==0); + match(PrefetchAllocation mem); ins_cost(125); - format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %} - opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ - ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); + format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %} + ins_encode %{ + __ prefetchnta($mem$$Address); + %} ins_pipe(ialu_mem); %} -instruct prefetchwT2( memory mem ) %{ - predicate(AllocatePrefetchInstr==2); - match(PrefetchWrite mem); +instruct prefetchAllocT0( memory mem ) %{ + predicate(AllocatePrefetchInstr==1); + match(PrefetchAllocation mem); ins_cost(125); - format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %} - opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ - ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem)); + format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %} + ins_encode %{ + __ prefetcht0($mem$$Address); + %} + ins_pipe(ialu_mem); +%} + +instruct prefetchAllocT2( memory mem ) %{ + predicate(AllocatePrefetchInstr==2); + match(PrefetchAllocation mem); + ins_cost(125); + + format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %} + ins_encode %{ + __ prefetcht2($mem$$Address); + %} ins_pipe(ialu_mem); %}