Mercurial > hg > truffle
diff src/share/vm/utilities/globalDefinitions.hpp @ 14521:29ccc4cbabca
Merge
author | Gilles Duboscq <duboscq@ssw.jku.at> |
---|---|
date | Wed, 12 Mar 2014 13:30:08 +0100 |
parents | d8041d695d19 |
children | 24cd779e5d94 |
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--- a/src/share/vm/utilities/globalDefinitions.hpp Tue Mar 11 15:34:06 2014 +0100 +++ b/src/share/vm/utilities/globalDefinitions.hpp Wed Mar 12 13:30:08 2014 +0100 @@ -38,6 +38,9 @@ #ifdef TARGET_COMPILER_sparcWorks # include "utilities/globalDefinitions_sparcWorks.hpp" #endif +#ifdef TARGET_COMPILER_xlc +# include "utilities/globalDefinitions_xlc.hpp" +#endif #include "utilities/macros.hpp" @@ -149,7 +152,7 @@ // The larger HeapWordSize for 64bit requires larger heaps // for the same application running in 64bit. See bug 4967770. // The minimum alignment to a heap word size is done. Other -// parts of the memory system may required additional alignment +// parts of the memory system may require additional alignment // and are responsible for those alignments. #ifdef _LP64 #define ScaleForWordSize(x) align_size_down_((x) * 13 / 10, HeapWordSize) @@ -395,6 +398,17 @@ #define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1 #endif +// To assure the IRIW property on processors that are not multiple copy +// atomic, sync instructions must be issued between volatile reads to +// assure their ordering, instead of after volatile stores. +// (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models" +// by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge) +#ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC +const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true; +#else +const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false; +#endif + // The byte alignment to be used by Arena::Amalloc. See bugid 4169348. // Note: this value must be a power of 2