Mercurial > hg > truffle
diff src/share/vm/utilities/globalDefinitions.hpp @ 17794:3514ee402842
8029101: PPC64 (part 211): ordering of Independent Reads of Independent Writes
Reviewed-by: dholmes, kvn
Contributed-by: martin.doerr@sap.com
| author | goetz |
|---|---|
| date | Thu, 16 Jan 2014 14:25:51 +0100 |
| parents | da862781b584 |
| children | 8a9bb7821e28 62c54fcc0a35 |
line wrap: on
line diff
--- a/src/share/vm/utilities/globalDefinitions.hpp Tue Jan 07 17:24:59 2014 +0100 +++ b/src/share/vm/utilities/globalDefinitions.hpp Thu Jan 16 14:25:51 2014 +0100 @@ -398,6 +398,17 @@ #define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1 #endif +// To assure the IRIW property on processors that are not multiple copy +// atomic, sync instructions must be issued between volatile reads to +// assure their ordering, instead of after volatile stores. +// (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models" +// by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge) +#ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC +const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true; +#else +const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false; +#endif + // The byte alignment to be used by Arena::Amalloc. See bugid 4169348. // Note: this value must be a power of 2