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diff src/cpu/sparc/vm/sparc.ad @ 1575:3657cb01ffc5

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6954029: Improve implicit null check generation with compressed oops Summary: Hoist DecodeN instruction above null check Reviewed-by: never, twisti
author kvn
date Wed, 02 Jun 2010 09:49:32 -0700
parents 2d127394260e
children e9ff18c4ace7
line wrap: on
line diff
--- a/src/cpu/sparc/vm/sparc.ad	Sat May 29 19:22:32 2010 -0700
+++ b/src/cpu/sparc/vm/sparc.ad	Wed Jun 02 09:49:32 2010 -0700
@@ -1760,6 +1760,12 @@
 // registers?  True for Intel but false for most RISCs
 const bool Matcher::clone_shift_expressions = false;
 
+bool Matcher::narrow_oop_use_complex_address() {
+  NOT_LP64(ShouldNotCallThis());
+  assert(UseCompressedOops, "only for compressed oops code");
+  return false;
+}
+
 // Is it better to copy float constants, or load them directly from memory?
 // Intel can load a float constant from a direct address, requiring no
 // extra registers.  Most RISCs will have to materialize an address into a