Mercurial > hg > truffle
diff src/cpu/sparc/vm/sparc.ad @ 14457:45467c53f178
Merge
author | kvn |
---|---|
date | Tue, 28 Jan 2014 12:28:17 -0800 |
parents | abec000618bf 7e8bd81ce93e |
children | cd5d10655495 |
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--- a/src/cpu/sparc/vm/sparc.ad Tue Jan 28 12:25:34 2014 -0800 +++ b/src/cpu/sparc/vm/sparc.ad Tue Jan 28 12:28:17 2014 -0800 @@ -3369,8 +3369,8 @@ interface(CONST_INTER); %} -// Unsigned (positive) Integer Immediate: 13-bit -operand immU13() %{ +// Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) +operand immU12() %{ predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); match(ConI); op_cost(0); @@ -3406,6 +3406,17 @@ interface(CONST_INTER); %} +// Int Immediate non-negative +operand immU31() +%{ + predicate(n->get_int() >= 0); + match(ConI); + + op_cost(0); + format %{ %} + interface(CONST_INTER); +%} + // Integer Immediate: 0-bit operand immI0() %{ predicate(n->get_int() == 0); @@ -5734,7 +5745,6 @@ effect(TEMP dst, TEMP tmp); ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); - size((3+1)*4); // set may use two instructions. format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" "SET $mask,$tmp\n\t" "AND $dst,$tmp,$dst" %} @@ -5856,13 +5866,13 @@ ins_pipe(iload_mem); %} -// Load Integer with a 13-bit mask into a Long Register -instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ +// Load Integer with a 12-bit mask into a Long Register +instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ match(Set dst (ConvI2L (AndI (LoadI mem) mask))); ins_cost(MEMORY_REF_COST + DEFAULT_COST); size(2*4); - format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" + format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" "AND $dst,$mask,$dst" %} ins_encode %{ Register Rdst = $dst$$Register; @@ -5872,14 +5882,13 @@ ins_pipe(iload_mem); %} -// Load Integer with a 32-bit mask into a Long Register -instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ +// Load Integer with a 31-bit mask into a Long Register +instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ match(Set dst (ConvI2L (AndI (LoadI mem) mask))); effect(TEMP dst, TEMP tmp); ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); - size((3+1)*4); // set may use two instructions. - format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" + format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" "SET $mask,$tmp\n\t" "AND $dst,$tmp,$dst" %} ins_encode %{ @@ -8976,7 +8985,7 @@ ins_pipe(ialu_cconly_reg_reg); %} -instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ +instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ match(Set icc (CmpU op1 op2)); size(4);