Mercurial > hg > truffle
diff src/cpu/sparc/vm/sparc.ad @ 14909:4ca6dc0799b6
Backout jdk9 merge
author | Gilles Duboscq <duboscq@ssw.jku.at> |
---|---|
date | Tue, 01 Apr 2014 13:57:07 +0200 |
parents | cd5d10655495 |
children | 89152779163c |
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--- a/src/cpu/sparc/vm/sparc.ad Tue Apr 01 14:09:03 2014 +0200 +++ b/src/cpu/sparc/vm/sparc.ad Tue Apr 01 13:57:07 2014 +0200 @@ -757,7 +757,7 @@ #endif -void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary, +void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, int src1_enc, int disp32, int src2_enc, int dst_enc) { #ifdef ASSERT @@ -912,14 +912,8 @@ uint index = src2_enc; int disp = disp32; - if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) { + if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) disp += STACK_BIAS; - // Quick fix for JDK-8029668: check that stack offset fits, bailout if not - if (!Assembler::is_simm13(disp)) { - ra->C->record_method_not_compilable("unable to handle large constant offsets"); - return; - } - } // We should have a compiler bailout here rather than a guarantee. // Better yet would be some mechanism to handle variable-size matches correctly. @@ -1040,11 +1034,6 @@ } } -bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } -void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { - ShouldNotReachHere(); -} - void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { Compile* C = ra_->C; Compile::ConstantTable& constant_table = C->constant_table(); @@ -1290,15 +1279,20 @@ return rc_float; } -static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { - if (cbuf) { - emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); +static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { + if( cbuf ) { + // Better yet would be some mechanism to handle variable-size matches correctly + if (!Assembler::is_simm13(offset + STACK_BIAS)) { + ra_->C->record_method_not_compilable("unable to handle large constant offsets"); + } else { + emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); + } } #ifndef PRODUCT - else if (!do_size) { - if (size != 0) st->print("\n\t"); - if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); - else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); + else if( !do_size ) { + if( size != 0 ) st->print("\n\t"); + if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); + else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); } #endif return size+4; @@ -1853,12 +1847,6 @@ return false; } -// Current (2013) SPARC platforms need to read original key -// to construct decryption expanded key -const bool Matcher::pass_original_key_for_aes() { - return true; -} - // USII supports fxtof through the whole range of number, USIII doesn't const bool Matcher::convL2FSupported(void) { return VM_Version::has_fast_fxtof(); @@ -1896,9 +1884,6 @@ return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; } -// Does the CPU require late expand (see block.cpp for description of late expand)? -const bool Matcher::require_postalloc_expand = false; - // Should the Matcher clone shifts on addressing modes, expecting them to // be subsumed into complex addressing expressions or compute them into // registers? True for Intel but false for most RISCs @@ -2037,6 +2022,19 @@ return L7_REGP_mask(); } +const RegMask Matcher::mathExactI_result_proj_mask() { + return G1_REGI_mask(); +} + +const RegMask Matcher::mathExactL_result_proj_mask() { + return G1_REGL_mask(); +} + +const RegMask Matcher::mathExactI_flags_proj_mask() { + return INT_FLAGS_mask(); +} + + %} @@ -2089,22 +2087,22 @@ %} enc_class form3_mem_reg( memory mem, iRegI dst ) %{ - emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary, + emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); %} enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ - emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, + emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); %} enc_class form3_mem_prefetch_read( memory mem ) %{ - emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, + emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); %} enc_class form3_mem_prefetch_write( memory mem ) %{ - emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, + emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); %} @@ -2112,8 +2110,8 @@ assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); guarantee($mem$$index == R_G0_enc, "double index?"); - emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); - emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); + emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); + emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); %} @@ -2123,14 +2121,14 @@ assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); guarantee($mem$$index == R_G0_enc, "double index?"); // Load long with 2 instructions - emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); - emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); + emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); + emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); %} //%%% form3_mem_plus_4_reg is a hack--get rid of it enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); - emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); + emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); %} enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ @@ -3243,7 +3241,7 @@ // C. c_calling_convention %{ // This is obviously always outgoing - (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); + (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); %} // Location of native (C/C++) and interpreter return values. This is specified to @@ -3356,8 +3354,8 @@ interface(CONST_INTER); %} -// Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) -operand immU12() %{ +// Unsigned (positive) Integer Immediate: 13-bit +operand immU13() %{ predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); match(ConI); op_cost(0); @@ -3393,17 +3391,6 @@ interface(CONST_INTER); %} -// Int Immediate non-negative -operand immU31() -%{ - predicate(n->get_int() >= 0); - match(ConI); - - op_cost(0); - format %{ %} - interface(CONST_INTER); -%} - // Integer Immediate: 0-bit operand immI0() %{ predicate(n->get_int() == 0); @@ -5732,6 +5719,7 @@ effect(TEMP dst, TEMP tmp); ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); + size((3+1)*4); // set may use two instructions. format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" "SET $mask,$tmp\n\t" "AND $dst,$tmp,$dst" %} @@ -5853,13 +5841,13 @@ ins_pipe(iload_mem); %} -// Load Integer with a 12-bit mask into a Long Register -instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ +// Load Integer with a 13-bit mask into a Long Register +instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ match(Set dst (ConvI2L (AndI (LoadI mem) mask))); ins_cost(MEMORY_REF_COST + DEFAULT_COST); size(2*4); - format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" + format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" "AND $dst,$mask,$dst" %} ins_encode %{ Register Rdst = $dst$$Register; @@ -5869,13 +5857,14 @@ ins_pipe(iload_mem); %} -// Load Integer with a 31-bit mask into a Long Register -instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ +// Load Integer with a 32-bit mask into a Long Register +instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ match(Set dst (ConvI2L (AndI (LoadI mem) mask))); effect(TEMP dst, TEMP tmp); ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); - format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" + size((3+1)*4); // set may use two instructions. + format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" "SET $mask,$tmp\n\t" "AND $dst,$tmp,$dst" %} ins_encode %{ @@ -6654,7 +6643,6 @@ instruct membar_acquire() %{ match(MemBarAcquire); - match(LoadFence); ins_cost(4*MEMORY_REF_COST); size(0); @@ -6675,7 +6663,6 @@ instruct membar_release() %{ match(MemBarRelease); - match(StoreFence); ins_cost(4*MEMORY_REF_COST); size(0); @@ -8972,7 +8959,7 @@ ins_pipe(ialu_cconly_reg_reg); %} -instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ +instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ match(Set icc (CmpU op1 op2)); size(4); @@ -9177,7 +9164,7 @@ size(4); ins_cost(BRANCH_COST); format %{ "BA $labl\t! short branch" %} - ins_encode %{ + ins_encode %{ Label* L = $labl$$label; assert(__ use_cbcond(*L), "back to back cbcond"); __ ba_short(*L);