Mercurial > hg > truffle
diff src/share/vm/utilities/globalDefinitions.hpp @ 14460:8a9bb7821e28
Merge
author | kvn |
---|---|
date | Wed, 19 Feb 2014 12:08:49 -0800 |
parents | 63a4eb8bcd23 c6d7e7406136 |
children | d8041d695d19 |
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--- a/src/share/vm/utilities/globalDefinitions.hpp Thu Feb 13 17:57:27 2014 +0100 +++ b/src/share/vm/utilities/globalDefinitions.hpp Wed Feb 19 12:08:49 2014 -0800 @@ -38,6 +38,9 @@ #ifdef TARGET_COMPILER_sparcWorks # include "utilities/globalDefinitions_sparcWorks.hpp" #endif +#ifdef TARGET_COMPILER_xlc +# include "utilities/globalDefinitions_xlc.hpp" +#endif #include "utilities/macros.hpp" @@ -395,6 +398,17 @@ #define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1 #endif +// To assure the IRIW property on processors that are not multiple copy +// atomic, sync instructions must be issued between volatile reads to +// assure their ordering, instead of after volatile stores. +// (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models" +// by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge) +#ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC +const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true; +#else +const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false; +#endif + // The byte alignment to be used by Arena::Amalloc. See bugid 4169348. // Note: this value must be a power of 2