Mercurial > hg > truffle
diff src/cpu/x86/vm/x86_32.ad @ 6179:8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
Summary: Increase vector size up to 256-bits for YMM AVX registers on x86.
Reviewed-by: never, twisti, roland
| author | kvn |
|---|---|
| date | Fri, 15 Jun 2012 01:25:19 -0700 |
| parents | 8b0a4867acf0 |
| children | 006050192a5a |
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--- a/src/cpu/x86/vm/x86_32.ad Thu Jun 14 14:59:52 2012 -0700 +++ b/src/cpu/x86/vm/x86_32.ad Fri Jun 15 01:25:19 2012 -0700 @@ -74,9 +74,6 @@ reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); -// Special Registers -reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad()); - // Float registers. We treat TOS/FPR0 special. It is invisible to the // allocator, and only shows up in the encodings. reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); @@ -105,27 +102,6 @@ reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); -// XMM registers. 128-bit registers or 4 words each, labeled a-d. -// Word a in each register holds a Float, words ab hold a Double. -// We currently do not use the SIMD capabilities, so registers cd -// are unused at the moment. -reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); -reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); -reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); -reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); -reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); -reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); -reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); -reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); -reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); -reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); -reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); -reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); -reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); -reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); -reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); -reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); - // Specify priority of register selection within phases of register // allocation. Highest priority is first. A useful heuristic is to // give registers a low priority when they are required by machine @@ -138,15 +114,6 @@ FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, FPR6L, FPR6H, FPR7L, FPR7H ); -alloc_class chunk1( XMM0a, XMM0b, - XMM1a, XMM1b, - XMM2a, XMM2b, - XMM3a, XMM3b, - XMM4a, XMM4b, - XMM5a, XMM5b, - XMM6a, XMM6b, - XMM7a, XMM7b, EFLAGS); - //----------Architecture Description Register Classes-------------------------- // Several register classes are automatically defined based upon information in @@ -159,12 +126,12 @@ // Class for all registers reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); // Class for general registers -reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); +reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); // Class for general registers which may be used for implicit null checks on win95 // Also safe for use by tailjump. We don't want to allocate in rbp, -reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); +reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); // Class of "X" registers -reg_class x_reg(EBX, ECX, EDX, EAX); +reg_class int_x_reg(EBX, ECX, EDX, EAX); // Class of registers that can appear in an address with no offset. // EBP and ESP require an extra instruction byte for zero offset. // Used in fast-unlock @@ -193,8 +160,6 @@ reg_class sp_reg(ESP); // Singleton class for instruction pointer // reg_class ip_reg(EIP); -// Singleton class for condition codes -reg_class int_flags(EFLAGS); // Class of integer register pairs reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); // Class of integer register pairs that aligns with calling convention @@ -206,29 +171,18 @@ // Floating point registers. Notice FPR0 is not a choice. // FPR0 is not ever allocated; we use clever encodings to fake // a 2-address instructions out of Intels FP stack. -reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); - -// make a register class for SSE registers -reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a); - -// make a double register class for SSE2 registers -reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b, - XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b ); - -reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, - FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, - FPR7L,FPR7H ); - -reg_class flt_reg0( FPR1L ); -reg_class dbl_reg0( FPR1L,FPR1H ); -reg_class dbl_reg1( FPR2L,FPR2H ); -reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, - FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); - -// XMM6 and XMM7 could be used as temporary registers for long, float and -// double values for SSE2. -reg_class xdb_reg6( XMM6a,XMM6b ); -reg_class xdb_reg7( XMM7a,XMM7b ); +reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); + +reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, + FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, + FPR7L,FPR7H ); + +reg_class fp_flt_reg0( FPR1L ); +reg_class fp_dbl_reg0( FPR1L,FPR1H ); +reg_class fp_dbl_reg1( FPR2L,FPR2H ); +reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, + FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); + %} @@ -412,7 +366,7 @@ } } - // eRegI ereg, memory mem) %{ // emit_reg_mem + // rRegI ereg, memory mem) %{ // emit_reg_mem void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) { // There is no index & no scale, use form without SIB byte if ((index == 0x4) && @@ -787,7 +741,7 @@ #endif } int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); - // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes. + // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. return size+5+offset_size; } @@ -821,7 +775,7 @@ } #endif } - // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes. + // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix. // Only MOVAPS SSE prefix uses 1 byte. int sz = 4; if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) && @@ -903,6 +857,108 @@ return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); } +// Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. +static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, + int src_hi, int dst_hi, uint ireg, outputStream* st); + +static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, + int stack_offset, int reg, uint ireg, outputStream* st); + +static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset, + int dst_offset, uint ireg, outputStream* st) { + int calc_size = 0; + int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); + int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); + switch (ireg) { + case Op_VecS: + calc_size = 3+src_offset_size + 3+dst_offset_size; + break; + case Op_VecD: + calc_size = 3+src_offset_size + 3+dst_offset_size; + src_offset += 4; + dst_offset += 4; + src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); + dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); + calc_size += 3+src_offset_size + 3+dst_offset_size; + break; + case Op_VecX: + calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; + break; + case Op_VecY: + calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; + break; + default: + ShouldNotReachHere(); + } + if (cbuf) { + MacroAssembler _masm(cbuf); + int offset = __ offset(); + switch (ireg) { + case Op_VecS: + __ pushl(Address(rsp, src_offset)); + __ popl (Address(rsp, dst_offset)); + break; + case Op_VecD: + __ pushl(Address(rsp, src_offset)); + __ popl (Address(rsp, dst_offset)); + __ pushl(Address(rsp, src_offset+4)); + __ popl (Address(rsp, dst_offset+4)); + break; + case Op_VecX: + __ movdqu(Address(rsp, -16), xmm0); + __ movdqu(xmm0, Address(rsp, src_offset)); + __ movdqu(Address(rsp, dst_offset), xmm0); + __ movdqu(xmm0, Address(rsp, -16)); + break; + case Op_VecY: + __ vmovdqu(Address(rsp, -32), xmm0); + __ vmovdqu(xmm0, Address(rsp, src_offset)); + __ vmovdqu(Address(rsp, dst_offset), xmm0); + __ vmovdqu(xmm0, Address(rsp, -32)); + break; + default: + ShouldNotReachHere(); + } + int size = __ offset() - offset; + assert(size == calc_size, "incorrect size calculattion"); + return size; +#ifndef PRODUCT + } else if (!do_size) { + switch (ireg) { + case Op_VecS: + st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t" + "popl [rsp + #%d]", + src_offset, dst_offset); + break; + case Op_VecD: + st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t" + "popq [rsp + #%d]\n\t" + "pushl [rsp + #%d]\n\t" + "popq [rsp + #%d]", + src_offset, dst_offset, src_offset+4, dst_offset+4); + break; + case Op_VecX: + st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t" + "movdqu xmm0, [rsp + #%d]\n\t" + "movdqu [rsp + #%d], xmm0\n\t" + "movdqu xmm0, [rsp - #16]", + src_offset, dst_offset); + break; + case Op_VecY: + st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" + "vmovdqu xmm0, [rsp + #%d]\n\t" + "vmovdqu [rsp + #%d], xmm0\n\t" + "vmovdqu xmm0, [rsp - #32]", + src_offset, dst_offset); + break; + default: + ShouldNotReachHere(); + } +#endif + } + return calc_size; +} + uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { // Get registers to move OptoReg::Name src_second = ra_->get_reg_second(in(1)); @@ -923,6 +979,29 @@ if( src_first == dst_first && src_second == dst_second ) return size; // Self copy, no move + if (bottom_type()->isa_vect() != NULL) { + uint ireg = ideal_reg(); + assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); + assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity"); + assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); + if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { + // mem -> mem + int src_offset = ra_->reg2offset(src_first); + int dst_offset = ra_->reg2offset(dst_first); + return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st); + } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { + return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st); + } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { + int stack_offset = ra_->reg2offset(dst_first); + return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st); + } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) { + int stack_offset = ra_->reg2offset(src_first); + return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st); + } else { + ShouldNotReachHere(); + } + } + // -------------------------------------- // Check for mem-mem move. push/pop to move. if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { @@ -1313,16 +1392,6 @@ return true; } -// Vector width in bytes -const uint Matcher::vector_width_in_bytes(void) { - return UseSSE >= 2 ? 8 : 0; -} - -// Vector ideal reg -const uint Matcher::vector_ideal_reg(void) { - return Op_RegD; -} - // Is this branch offset short enough that a short branch can be used? // // NOTE: If the platform does not provide any short branch variants, then @@ -1452,7 +1521,7 @@ // arguments in those registers not be available to the callee. bool Matcher::can_be_java_arg( int reg ) { if( reg == ECX_num || reg == EDX_num ) return true; - if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true; + if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true; if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; return false; } @@ -1565,16 +1634,16 @@ emit_opcode(cbuf,0x66); %} - enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) + enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); %} - enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many) + enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many) emit_opcode(cbuf,$opcode$$constant); emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); %} - enc_class mov_r32_imm0( eRegI dst ) %{ + enc_class mov_r32_imm0( rRegI dst ) %{ emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 %} @@ -1621,7 +1690,7 @@ %} // Dense encoding for older common ops - enc_class Opc_plus(immI opcode, eRegI reg) %{ + enc_class Opc_plus(immI opcode, rRegI reg) %{ emit_opcode(cbuf, $opcode$$constant + $reg$$reg); %} @@ -1637,7 +1706,7 @@ } %} - enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m + enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m // Emit primary opcode and set sign-extend bit // Check for 8-bit immediate, and set sign extend bit in opcode if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { @@ -1682,7 +1751,7 @@ else emit_d32(cbuf,con); %} - enc_class OpcSReg (eRegI dst) %{ // BSWAP + enc_class OpcSReg (rRegI dst) %{ // BSWAP emit_cc(cbuf, $secondary, $dst$$reg ); %} @@ -1700,7 +1769,7 @@ emit_rm(cbuf, 0x3, destlo, desthi); %} - enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ... + enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ... emit_rm(cbuf, 0x3, $secondary, $div$$reg ); %} @@ -1891,20 +1960,20 @@ // runtime_call_Relocation::spec(), RELOC_IMM32 ); // %} - enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR + enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR $$$emit8$primary; emit_rm(cbuf, 0x3, $secondary, $dst$$reg); $$$emit8$shift$$constant; %} - enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate + enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate // Load immediate does not have a zero or sign extended version // for 8-bit immediates emit_opcode(cbuf, 0xB8 + $dst$$reg); $$$emit32$src$$constant; %} - enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate + enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate // Load immediate does not have a zero or sign extended version // for 8-bit immediates emit_opcode(cbuf, $primary + $dst$$reg); @@ -1943,15 +2012,15 @@ // Encode a reg-reg copy. If it is useless, then empty encoding. - enc_class enc_Copy( eRegI dst, eRegI src ) %{ + enc_class enc_Copy( rRegI dst, rRegI src ) %{ encode_Copy( cbuf, $dst$$reg, $src$$reg ); %} - enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{ + enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{ encode_Copy( cbuf, $dst$$reg, $src$$reg ); %} - enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) + enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); %} @@ -1973,7 +2042,7 @@ emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); %} - enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{ + enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{ emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); %} @@ -2068,7 +2137,7 @@ cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand %} - enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem + enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem int reg_encoding = $ereg$$reg; int base = $mem$$base; int index = $mem$$index; @@ -2132,7 +2201,7 @@ // Clone of RegMem but accepts an extra parameter to access each // half of a double in memory; it never needs relocation info. - enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{ + enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{ emit_opcode(cbuf,$opcode$$constant); int reg_encoding = $rm_reg$$reg; int base = $mem$$base; @@ -2168,7 +2237,7 @@ encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); %} - enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea + enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea int reg_encoding = $dst$$reg; int base = $src0$$reg; // 0xFFFFFFFF indicates no base int index = 0x04; // 0x04 indicates no index @@ -2178,7 +2247,7 @@ encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); %} - enc_class min_enc (eRegI dst, eRegI src) %{ // MIN + enc_class min_enc (rRegI dst, rRegI src) %{ // MIN // Compare dst,src emit_opcode(cbuf,0x3B); emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); @@ -2190,7 +2259,7 @@ emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); %} - enc_class max_enc (eRegI dst, eRegI src) %{ // MAX + enc_class max_enc (rRegI dst, rRegI src) %{ // MAX // Compare dst,src emit_opcode(cbuf,0x3B); emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); @@ -2221,7 +2290,7 @@ encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); %} - enc_class neg_reg(eRegI dst) %{ + enc_class neg_reg(rRegI dst) %{ // NEG $dst emit_opcode(cbuf,0xF7); emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); @@ -2251,7 +2320,7 @@ emit_rm(cbuf, 0x3, $p$$reg, tmpReg); %} - enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT + enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT int tmpReg = $tmp$$reg; // SUB $p,$q @@ -2390,12 +2459,12 @@ %} // Special case for moving an integer register to a stack slot. - enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS + enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); %} // Special case for moving a register to a stack slot. - enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS + enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS // Opcode already emitted emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte @@ -2640,7 +2709,7 @@ // equal_result = 0; // nan_result = -1; - enc_class CmpF_Result(eRegI dst) %{ + enc_class CmpF_Result(rRegI dst) %{ // fnstsw_ax(); emit_opcode( cbuf, 0xDF); emit_opcode( cbuf, 0xE0); @@ -2685,7 +2754,7 @@ // done: %} - enc_class convert_int_long( regL dst, eRegI src ) %{ + enc_class convert_int_long( regL dst, rRegI src ) %{ // mov $dst.lo,$src int dst_encoding = $dst$$reg; int src_encoding = $src$$reg; @@ -2754,7 +2823,7 @@ emit_rm( cbuf, 0x3, 0x4, $src$$reg); %} - enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{ + enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{ // Basic idea: lo(result) = lo(x_lo * y_lo) // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) // MOV $tmp,$src.lo @@ -2780,7 +2849,7 @@ emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); %} - enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{ + enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{ // Basic idea: lo(result) = lo(src * y_lo) // hi(result) = hi(src * y_lo) + lo(src * y_hi) // IMUL $tmp,EDX,$src @@ -2836,7 +2905,7 @@ emit_d8(cbuf, 4*4); %} - enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{ + enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{ // MOV $tmp,$src.lo emit_opcode(cbuf, 0x8B); emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); @@ -2857,7 +2926,7 @@ emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); %} - enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{ + enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{ // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits emit_opcode( cbuf, 0x3B ); emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); @@ -2869,7 +2938,7 @@ emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); %} - enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{ + enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{ // XOR $tmp,$tmp emit_opcode(cbuf,0x33); // XOR emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); @@ -3762,9 +3831,9 @@ // in SSE2+ mode we want to keep the FPU stack clean so pretend // that C functions return float and double results in XMM0. if( ideal_reg == Op_RegD && UseSSE>=2 ) - return OptoRegPair(XMM0b_num,XMM0a_num); + return OptoRegPair(XMM0b_num,XMM0_num); if( ideal_reg == Op_RegF && UseSSE>=2 ) - return OptoRegPair(OptoReg::Bad,XMM0a_num); + return OptoRegPair(OptoReg::Bad,XMM0_num); return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); %} @@ -3775,9 +3844,9 @@ static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; if( ideal_reg == Op_RegD && UseSSE>=2 ) - return OptoRegPair(XMM0b_num,XMM0a_num); + return OptoRegPair(XMM0b_num,XMM0_num); if( ideal_reg == Op_RegF && UseSSE>=1 ) - return OptoRegPair(OptoReg::Bad,XMM0a_num); + return OptoRegPair(OptoReg::Bad,XMM0_num); return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); %} @@ -4147,8 +4216,8 @@ // Register Operands // Integer Register -operand eRegI() %{ - constraint(ALLOC_IN_RC(e_reg)); +operand rRegI() %{ + constraint(ALLOC_IN_RC(int_reg)); match(RegI); match(xRegI); match(eAXRegI); @@ -4163,8 +4232,8 @@ %} // Subset of Integer Register -operand xRegI(eRegI reg) %{ - constraint(ALLOC_IN_RC(x_reg)); +operand xRegI(rRegI reg) %{ + constraint(ALLOC_IN_RC(int_x_reg)); match(reg); match(eAXRegI); match(eBXRegI); @@ -4179,7 +4248,7 @@ operand eAXRegI(xRegI reg) %{ constraint(ALLOC_IN_RC(eax_reg)); match(reg); - match(eRegI); + match(rRegI); format %{ "EAX" %} interface(REG_INTER); @@ -4189,7 +4258,7 @@ operand eBXRegI(xRegI reg) %{ constraint(ALLOC_IN_RC(ebx_reg)); match(reg); - match(eRegI); + match(rRegI); format %{ "EBX" %} interface(REG_INTER); @@ -4198,7 +4267,7 @@ operand eCXRegI(xRegI reg) %{ constraint(ALLOC_IN_RC(ecx_reg)); match(reg); - match(eRegI); + match(rRegI); format %{ "ECX" %} interface(REG_INTER); @@ -4207,7 +4276,7 @@ operand eDXRegI(xRegI reg) %{ constraint(ALLOC_IN_RC(edx_reg)); match(reg); - match(eRegI); + match(rRegI); format %{ "EDX" %} interface(REG_INTER); @@ -4216,7 +4285,7 @@ operand eDIRegI(xRegI reg) %{ constraint(ALLOC_IN_RC(edi_reg)); match(reg); - match(eRegI); + match(rRegI); format %{ "EDI" %} interface(REG_INTER); @@ -4263,7 +4332,7 @@ operand eSIRegI(xRegI reg) %{ constraint(ALLOC_IN_RC(esi_reg)); match(reg); - match(eRegI); + match(rRegI); format %{ "ESI" %} interface(REG_INTER); @@ -4284,7 +4353,7 @@ %} operand eRegP() %{ - constraint(ALLOC_IN_RC(e_reg)); + constraint(ALLOC_IN_RC(int_reg)); match(RegP); match(eAXRegP); match(eBXRegP); @@ -4297,7 +4366,7 @@ // On windows95, EBP is not safe to use for implicit null tests. operand eRegP_no_EBP() %{ - constraint(ALLOC_IN_RC(e_reg_no_rbp)); + constraint(ALLOC_IN_RC(int_reg_no_rbp)); match(RegP); match(eAXRegP); match(eBXRegP); @@ -4477,7 +4546,7 @@ // Float register operands operand regDPR() %{ predicate( UseSSE < 2 ); - constraint(ALLOC_IN_RC(dbl_reg)); + constraint(ALLOC_IN_RC(fp_dbl_reg)); match(RegD); match(regDPR1); match(regDPR2); @@ -4487,7 +4556,7 @@ operand regDPR1(regDPR reg) %{ predicate( UseSSE < 2 ); - constraint(ALLOC_IN_RC(dbl_reg0)); + constraint(ALLOC_IN_RC(fp_dbl_reg0)); match(reg); format %{ "FPR1" %} interface(REG_INTER); @@ -4495,7 +4564,7 @@ operand regDPR2(regDPR reg) %{ predicate( UseSSE < 2 ); - constraint(ALLOC_IN_RC(dbl_reg1)); + constraint(ALLOC_IN_RC(fp_dbl_reg1)); match(reg); format %{ "FPR2" %} interface(REG_INTER); @@ -4503,45 +4572,16 @@ operand regnotDPR1(regDPR reg) %{ predicate( UseSSE < 2 ); - constraint(ALLOC_IN_RC(dbl_notreg0)); + constraint(ALLOC_IN_RC(fp_dbl_notreg0)); match(reg); format %{ %} interface(REG_INTER); %} -// XMM Double register operands -operand regD() %{ - predicate( UseSSE>=2 ); - constraint(ALLOC_IN_RC(xdb_reg)); - match(RegD); - match(regD6); - match(regD7); - format %{ %} - interface(REG_INTER); -%} - -// XMM6 double register operands -operand regD6(regD reg) %{ - predicate( UseSSE>=2 ); - constraint(ALLOC_IN_RC(xdb_reg6)); - match(reg); - format %{ "XMM6" %} - interface(REG_INTER); -%} - -// XMM7 double register operands -operand regD7(regD reg) %{ - predicate( UseSSE>=2 ); - constraint(ALLOC_IN_RC(xdb_reg7)); - match(reg); - format %{ "XMM7" %} - interface(REG_INTER); -%} - // Float register operands operand regFPR() %{ predicate( UseSSE < 2 ); - constraint(ALLOC_IN_RC(flt_reg)); + constraint(ALLOC_IN_RC(fp_flt_reg)); match(RegF); match(regFPR1); format %{ %} @@ -4551,21 +4591,30 @@ // Float register operands operand regFPR1(regFPR reg) %{ predicate( UseSSE < 2 ); - constraint(ALLOC_IN_RC(flt_reg0)); + constraint(ALLOC_IN_RC(fp_flt_reg0)); match(reg); format %{ "FPR1" %} interface(REG_INTER); %} -// XMM register operands +// XMM Float register operands operand regF() %{ predicate( UseSSE>=1 ); - constraint(ALLOC_IN_RC(xmm_reg)); + constraint(ALLOC_IN_RC(float_reg)); match(RegF); format %{ %} interface(REG_INTER); %} +// XMM Double register operands +operand regD() %{ + predicate( UseSSE>=2 ); + constraint(ALLOC_IN_RC(double_reg)); + match(RegD); + format %{ %} + interface(REG_INTER); +%} + //----------Memory Operands---------------------------------------------------- // Direct Memory Operand @@ -4583,7 +4632,7 @@ // Indirect Memory Operand operand indirect(eRegP reg) %{ - constraint(ALLOC_IN_RC(e_reg)); + constraint(ALLOC_IN_RC(int_reg)); match(reg); format %{ "[$reg]" %} @@ -4622,7 +4671,7 @@ %} // Indirect Memory Plus Long Offset Operand -operand indOffset32X(eRegI reg, immP off) %{ +operand indOffset32X(rRegI reg, immP off) %{ match(AddP off reg); format %{ "[$reg + $off]" %} @@ -4635,7 +4684,7 @@ %} // Indirect Memory Plus Index Register Plus Offset Operand -operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{ +operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{ match(AddP (AddP reg ireg) off); op_cost(10); @@ -4649,7 +4698,7 @@ %} // Indirect Memory Plus Index Register Plus Offset Operand -operand indIndex(eRegP reg, eRegI ireg) %{ +operand indIndex(eRegP reg, rRegI ireg) %{ match(AddP reg ireg); op_cost(10); @@ -4667,7 +4716,7 @@ // // ------------------------------------------------------------------------- // // Scaled Memory Operands // // Indirect Memory Times Scale Plus Offset Operand -// operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{ +// operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{ // match(AddP off (LShiftI ireg scale)); // // op_cost(10); @@ -4681,7 +4730,7 @@ // %} // Indirect Memory Times Scale Plus Index Register -operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{ +operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{ match(AddP reg (LShiftI ireg scale)); op_cost(10); @@ -4695,7 +4744,7 @@ %} // Indirect Memory Times Scale Plus Index Register Plus Offset Operand -operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{ +operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{ match(AddP (AddP reg (LShiftI ireg scale)) off); op_cost(10); @@ -4823,7 +4872,7 @@ // Indirect Memory Operand operand indirect_win95_safe(eRegP_no_EBP reg) %{ - constraint(ALLOC_IN_RC(e_reg)); + constraint(ALLOC_IN_RC(int_reg)); match(reg); op_cost(100); @@ -4867,7 +4916,7 @@ %} // Indirect Memory Plus Index Register Plus Offset Operand -operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off) +operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off) %{ match(AddP (AddP reg ireg) off); @@ -4882,7 +4931,7 @@ %} // Indirect Memory Times Scale Plus Index Register -operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale) +operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale) %{ match(AddP reg (LShiftI ireg scale)); @@ -4897,7 +4946,7 @@ %} // Indirect Memory Times Scale Plus Index Register Plus Offset Operand -operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale) +operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale) %{ match(AddP (AddP reg (LShiftI ireg scale)) off); @@ -5086,7 +5135,7 @@ // Or: _mem if it requires the big decoder and a memory unit. // Integer ALU reg operation -pipe_class ialu_reg(eRegI dst) %{ +pipe_class ialu_reg(rRegI dst) %{ single_instruction; dst : S4(write); dst : S3(read); @@ -5104,7 +5153,7 @@ %} // Integer ALU reg operation using big decoder -pipe_class ialu_reg_fat(eRegI dst) %{ +pipe_class ialu_reg_fat(rRegI dst) %{ single_instruction; dst : S4(write); dst : S3(read); @@ -5122,7 +5171,7 @@ %} // Integer ALU reg-reg operation -pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{ +pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{ single_instruction; dst : S4(write); src : S3(read); @@ -5140,7 +5189,7 @@ %} // Integer ALU reg-reg operation -pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{ +pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{ single_instruction; dst : S4(write); src : S3(read); @@ -5158,7 +5207,7 @@ %} // Integer ALU reg-mem operation -pipe_class ialu_reg_mem(eRegI dst, memory mem) %{ +pipe_class ialu_reg_mem(rRegI dst, memory mem) %{ single_instruction; dst : S5(write); mem : S3(read); @@ -5187,7 +5236,7 @@ %} // Integer Store to Memory -pipe_class ialu_mem_reg(memory mem, eRegI src) %{ +pipe_class ialu_mem_reg(memory mem, rRegI src) %{ single_instruction; mem : S3(read); src : S5(read); @@ -5216,7 +5265,7 @@ %} // Integer ALU0 reg-reg operation -pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{ +pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{ single_instruction; dst : S4(write); src : S3(read); @@ -5225,7 +5274,7 @@ %} // Integer ALU0 reg-mem operation -pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{ +pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{ single_instruction; dst : S5(write); mem : S3(read); @@ -5235,7 +5284,7 @@ %} // Integer ALU reg-reg operation -pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{ +pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{ single_instruction; cr : S4(write); src1 : S3(read); @@ -5245,7 +5294,7 @@ %} // Integer ALU reg-imm operation -pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{ +pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{ single_instruction; cr : S4(write); src1 : S3(read); @@ -5254,7 +5303,7 @@ %} // Integer ALU reg-mem operation -pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{ +pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{ single_instruction; cr : S4(write); src1 : S3(read); @@ -5265,7 +5314,7 @@ %} // Conditional move reg-reg -pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{ +pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{ instruction_count(4); y : S4(read); q : S3(read); @@ -5274,7 +5323,7 @@ %} // Conditional move reg-reg -pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{ +pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{ single_instruction; dst : S4(write); src : S3(read); @@ -5283,7 +5332,7 @@ %} // Conditional move reg-mem -pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{ +pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{ single_instruction; dst : S4(write); src : S3(read); @@ -5534,7 +5583,7 @@ // in the encode section of the architecture description. //----------BSWAP-Instruction-------------------------------------------------- -instruct bytes_reverse_int(eRegI dst) %{ +instruct bytes_reverse_int(rRegI dst) %{ match(Set dst (ReverseBytesI dst)); format %{ "BSWAP $dst" %} @@ -5555,7 +5604,7 @@ ins_pipe( ialu_reg_reg); %} -instruct bytes_reverse_unsigned_short(eRegI dst, eFlagsReg cr) %{ +instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{ match(Set dst (ReverseBytesUS dst)); effect(KILL cr); @@ -5568,7 +5617,7 @@ ins_pipe( ialu_reg ); %} -instruct bytes_reverse_short(eRegI dst, eFlagsReg cr) %{ +instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{ match(Set dst (ReverseBytesS dst)); effect(KILL cr); @@ -5584,7 +5633,7 @@ //---------- Zeros Count Instructions ------------------------------------------ -instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ +instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ predicate(UseCountLeadingZerosInstruction); match(Set dst (CountLeadingZerosI src)); effect(KILL cr); @@ -5596,7 +5645,7 @@ ins_pipe(ialu_reg); %} -instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{ +instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{ predicate(!UseCountLeadingZerosInstruction); match(Set dst (CountLeadingZerosI src)); effect(KILL cr); @@ -5621,7 +5670,7 @@ ins_pipe(ialu_reg); %} -instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{ +instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ predicate(UseCountLeadingZerosInstruction); match(Set dst (CountLeadingZerosL src)); effect(TEMP dst, KILL cr); @@ -5644,7 +5693,7 @@ ins_pipe(ialu_reg); %} -instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{ +instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{ predicate(!UseCountLeadingZerosInstruction); match(Set dst (CountLeadingZerosL src)); effect(TEMP dst, KILL cr); @@ -5680,7 +5729,7 @@ ins_pipe(ialu_reg); %} -instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ +instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ match(Set dst (CountTrailingZerosI src)); effect(KILL cr); @@ -5699,7 +5748,7 @@ ins_pipe(ialu_reg); %} -instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{ +instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ match(Set dst (CountTrailingZerosL src)); effect(TEMP dst, KILL cr); @@ -5731,7 +5780,7 @@ //---------- Population Count Instructions ------------------------------------- -instruct popCountI(eRegI dst, eRegI src, eFlagsReg cr) %{ +instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{ predicate(UsePopCountInstruction); match(Set dst (PopCountI src)); effect(KILL cr); @@ -5743,7 +5792,7 @@ ins_pipe(ialu_reg); %} -instruct popCountI_mem(eRegI dst, memory mem, eFlagsReg cr) %{ +instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{ predicate(UsePopCountInstruction); match(Set dst (PopCountI (LoadI mem))); effect(KILL cr); @@ -5756,7 +5805,7 @@ %} // Note: Long.bitCount(long) returns an int. -instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ +instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ predicate(UsePopCountInstruction); match(Set dst (PopCountL src)); effect(KILL cr, TEMP tmp, TEMP dst); @@ -5773,7 +5822,7 @@ %} // Note: Long.bitCount(long) returns an int. -instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{ +instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{ predicate(UsePopCountInstruction); match(Set dst (PopCountL (LoadL mem))); effect(KILL cr, TEMP tmp, TEMP dst); @@ -5877,7 +5926,7 @@ %} // Load Short (16bit signed) -instruct loadS(eRegI dst, memory mem) %{ +instruct loadS(rRegI dst, memory mem) %{ match(Set dst (LoadS mem)); ins_cost(125); @@ -5891,7 +5940,7 @@ %} // Load Short (16 bit signed) to Byte (8 bit signed) -instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{ +instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); ins_cost(125); @@ -5922,7 +5971,7 @@ %} // Load Unsigned Short/Char (16bit unsigned) -instruct loadUS(eRegI dst, memory mem) %{ +instruct loadUS(rRegI dst, memory mem) %{ match(Set dst (LoadUS mem)); ins_cost(125); @@ -5936,7 +5985,7 @@ %} // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) -instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{ +instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); ins_cost(125); @@ -5997,7 +6046,7 @@ %} // Load Integer -instruct loadI(eRegI dst, memory mem) %{ +instruct loadI(rRegI dst, memory mem) %{ match(Set dst (LoadI mem)); ins_cost(125); @@ -6011,7 +6060,7 @@ %} // Load Integer (32 bit signed) to Byte (8 bit signed) -instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{ +instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); ins_cost(125); @@ -6023,7 +6072,7 @@ %} // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) -instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{ +instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ match(Set dst (AndI (LoadI mem) mask)); ins_cost(125); @@ -6035,7 +6084,7 @@ %} // Load Integer (32 bit signed) to Short (16 bit signed) -instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{ +instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); ins_cost(125); @@ -6047,7 +6096,7 @@ %} // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) -instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{ +instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ match(Set dst (AndI (LoadI mem) mask)); ins_cost(125); @@ -6208,7 +6257,7 @@ %} // Load Range -instruct loadRange(eRegI dst, memory mem) %{ +instruct loadRange(rRegI dst, memory mem) %{ match(Set dst (LoadRange mem)); ins_cost(125); @@ -6305,66 +6354,6 @@ ins_pipe( fpu_reg_mem ); %} -// Load Aligned Packed Byte to XMM register -instruct loadA8B(regD dst, memory mem) %{ - predicate(UseSSE>=1); - match(Set dst (Load8B mem)); - ins_cost(125); - format %{ "MOVQ $dst,$mem\t! packed8B" %} - ins_encode %{ - __ movq($dst$$XMMRegister, $mem$$Address); - %} - ins_pipe( pipe_slow ); -%} - -// Load Aligned Packed Short to XMM register -instruct loadA4S(regD dst, memory mem) %{ - predicate(UseSSE>=1); - match(Set dst (Load4S mem)); - ins_cost(125); - format %{ "MOVQ $dst,$mem\t! packed4S" %} - ins_encode %{ - __ movq($dst$$XMMRegister, $mem$$Address); - %} - ins_pipe( pipe_slow ); -%} - -// Load Aligned Packed Char to XMM register -instruct loadA4C(regD dst, memory mem) %{ - predicate(UseSSE>=1); - match(Set dst (Load4C mem)); - ins_cost(125); - format %{ "MOVQ $dst,$mem\t! packed4C" %} - ins_encode %{ - __ movq($dst$$XMMRegister, $mem$$Address); - %} - ins_pipe( pipe_slow ); -%} - -// Load Aligned Packed Integer to XMM register -instruct load2IU(regD dst, memory mem) %{ - predicate(UseSSE>=1); - match(Set dst (Load2I mem)); - ins_cost(125); - format %{ "MOVQ $dst,$mem\t! packed2I" %} - ins_encode %{ - __ movq($dst$$XMMRegister, $mem$$Address); - %} - ins_pipe( pipe_slow ); -%} - -// Load Aligned Packed Single to XMM -instruct loadA2F(regD dst, memory mem) %{ - predicate(UseSSE>=1); - match(Set dst (Load2F mem)); - ins_cost(145); - format %{ "MOVQ $dst,$mem\t! packed2F" %} - ins_encode %{ - __ movq($dst$$XMMRegister, $mem$$Address); - %} - ins_pipe( pipe_slow ); -%} - // Load Effective Address instruct leaP8(eRegP dst, indOffset8 mem) %{ match(Set dst mem); @@ -6417,7 +6406,7 @@ %} // Load Constant -instruct loadConI(eRegI dst, immI src) %{ +instruct loadConI(rRegI dst, immI src) %{ match(Set dst src); format %{ "MOV $dst,$src" %} @@ -6426,7 +6415,7 @@ %} // Load Constant zero -instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{ +instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{ match(Set dst src); effect(KILL cr); @@ -6594,7 +6583,7 @@ %} // Load Stack Slot -instruct loadSSI(eRegI dst, stackSlotI src) %{ +instruct loadSSI(rRegI dst, stackSlotI src) %{ match(Set dst src); ins_cost(125); @@ -6821,7 +6810,7 @@ %} // Store Char/Short -instruct storeC(memory mem, eRegI src) %{ +instruct storeC(memory mem, rRegI src) %{ match(Set mem (StoreC mem src)); ins_cost(125); @@ -6832,7 +6821,7 @@ %} // Store Integer -instruct storeI(memory mem, eRegI src) %{ +instruct storeI(memory mem, rRegI src) %{ match(Set mem (StoreI mem src)); ins_cost(125); @@ -6976,42 +6965,6 @@ ins_pipe( ialu_mem_imm ); %} -// Store Aligned Packed Byte XMM register to memory -instruct storeA8B(memory mem, regD src) %{ - predicate(UseSSE>=1); - match(Set mem (Store8B mem src)); - ins_cost(145); - format %{ "MOVQ $mem,$src\t! packed8B" %} - ins_encode %{ - __ movq($mem$$Address, $src$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -// Store Aligned Packed Char/Short XMM register to memory -instruct storeA4C(memory mem, regD src) %{ - predicate(UseSSE>=1); - match(Set mem (Store4C mem src)); - ins_cost(145); - format %{ "MOVQ $mem,$src\t! packed4C" %} - ins_encode %{ - __ movq($mem$$Address, $src$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - -// Store Aligned Packed Integer XMM register to memory -instruct storeA2I(memory mem, regD src) %{ - predicate(UseSSE>=1); - match(Set mem (Store2I mem src)); - ins_cost(145); - format %{ "MOVQ $mem,$src\t! packed2I" %} - ins_encode %{ - __ movq($mem$$Address, $src$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - // Store CMS card-mark Immediate instruct storeImmCM(memory mem, immI8 src) %{ match(Set mem (StoreCM mem src)); @@ -7073,18 +7026,6 @@ ins_pipe( pipe_slow ); %} -// Store Aligned Packed Single Float XMM register to memory -instruct storeA2F(memory mem, regD src) %{ - predicate(UseSSE>=1); - match(Set mem (Store2F mem src)); - ins_cost(145); - format %{ "MOVQ $mem,$src\t! packed2F" %} - ins_encode %{ - __ movq($mem$$Address, $src$$XMMRegister); - %} - ins_pipe( pipe_slow ); -%} - // Store Float instruct storeFPR( memory mem, regFPR1 src) %{ predicate(UseSSE==0); @@ -7146,7 +7087,7 @@ %} // Store Integer to stack slot -instruct storeSSI(stackSlotI dst, eRegI src) %{ +instruct storeSSI(stackSlotI dst, rRegI src) %{ match(Set dst src); ins_cost(100); @@ -7271,7 +7212,7 @@ ins_pipe(empty); %} -instruct castP2X(eRegI dst, eRegP src ) %{ +instruct castP2X(rRegI dst, eRegP src ) %{ match(Set dst (CastP2X src)); ins_cost(50); format %{ "MOV $dst, $src\t# CastP2X" %} @@ -7281,7 +7222,7 @@ //----------Conditional Move--------------------------------------------------- // Conditional move -instruct jmovI_reg(cmpOp cop, eFlagsReg cr, eRegI dst, eRegI src) %{ +instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{ predicate(!VM_Version::supports_cmov() ); match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); ins_cost(200); @@ -7298,7 +7239,7 @@ ins_pipe( pipe_cmov_reg ); %} -instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src) %{ +instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{ predicate(!VM_Version::supports_cmov() ); match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); ins_cost(200); @@ -7315,7 +7256,7 @@ ins_pipe( pipe_cmov_reg ); %} -instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{ +instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{ predicate(VM_Version::supports_cmov() ); match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); ins_cost(200); @@ -7325,7 +7266,7 @@ ins_pipe( pipe_cmov_reg ); %} -instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{ +instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{ predicate(VM_Version::supports_cmov() ); match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); ins_cost(200); @@ -7335,7 +7276,7 @@ ins_pipe( pipe_cmov_reg ); %} -instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{ +instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{ predicate(VM_Version::supports_cmov() ); match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); ins_cost(200); @@ -7345,7 +7286,7 @@ %} // Conditional move -instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{ +instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{ predicate(VM_Version::supports_cmov() ); match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); ins_cost(250); @@ -7356,7 +7297,7 @@ %} // Conditional move -instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{ +instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{ predicate(VM_Version::supports_cmov() ); match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); ins_cost(250); @@ -7366,7 +7307,7 @@ ins_pipe( pipe_cmov_mem ); %} -instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{ +instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{ predicate(VM_Version::supports_cmov() ); match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); ins_cost(250); @@ -7620,7 +7561,7 @@ //----------Arithmetic Instructions-------------------------------------------- //----------Addition Instructions---------------------------------------------- // Integer Addition Instructions -instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ +instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ match(Set dst (AddI dst src)); effect(KILL cr); @@ -7631,7 +7572,7 @@ ins_pipe( ialu_reg_reg ); %} -instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ +instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ match(Set dst (AddI dst src)); effect(KILL cr); @@ -7641,7 +7582,7 @@ ins_pipe( ialu_reg ); %} -instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ +instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ predicate(UseIncDec); match(Set dst (AddI dst src)); effect(KILL cr); @@ -7653,7 +7594,7 @@ ins_pipe( ialu_reg ); %} -instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{ +instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{ match(Set dst (AddI src0 src1)); ins_cost(110); @@ -7673,7 +7614,7 @@ ins_pipe( ialu_reg_reg ); %} -instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{ +instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{ predicate(UseIncDec); match(Set dst (AddI dst src)); effect(KILL cr); @@ -7685,7 +7626,7 @@ ins_pipe( ialu_reg ); %} -instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{ +instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{ match(Set dst (AddP dst src)); effect(KILL cr); @@ -7707,7 +7648,7 @@ ins_pipe( ialu_reg ); %} -instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ +instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ match(Set dst (AddI dst (LoadI src))); effect(KILL cr); @@ -7718,7 +7659,7 @@ ins_pipe( ialu_reg_mem ); %} -instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ +instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ match(Set dst (StoreI dst (AddI (LoadI dst) src))); effect(KILL cr); @@ -7780,7 +7721,7 @@ ins_pipe( empty ); %} -instruct castII( eRegI dst ) %{ +instruct castII( rRegI dst ) %{ match(Set dst (CastII dst)); format %{ "#castII of $dst" %} ins_encode( /*empty encoding*/ ); @@ -7814,7 +7755,7 @@ // Conditional-store of an int value. // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. -instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{ +instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{ match(Set cr (StoreIConditional mem (Binary oldval newval))); effect(KILL oldval); format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} @@ -7847,7 +7788,7 @@ // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them -instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ +instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); effect(KILL cr, KILL oldval); format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" @@ -7860,7 +7801,7 @@ ins_pipe( pipe_cmpxchg ); %} -instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ +instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); effect(KILL cr, KILL oldval); format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" @@ -7872,7 +7813,7 @@ ins_pipe( pipe_cmpxchg ); %} -instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ +instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); effect(KILL cr, KILL oldval); format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" @@ -7886,7 +7827,7 @@ //----------Subtraction Instructions------------------------------------------- // Integer Subtraction Instructions -instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ +instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ match(Set dst (SubI dst src)); effect(KILL cr); @@ -7897,7 +7838,7 @@ ins_pipe( ialu_reg_reg ); %} -instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ +instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ match(Set dst (SubI dst src)); effect(KILL cr); @@ -7908,7 +7849,7 @@ ins_pipe( ialu_reg ); %} -instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ +instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ match(Set dst (SubI dst (LoadI src))); effect(KILL cr); @@ -7919,7 +7860,7 @@ ins_pipe( ialu_reg_mem ); %} -instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ +instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ match(Set dst (StoreI dst (SubI (LoadI dst) src))); effect(KILL cr); @@ -7931,7 +7872,7 @@ %} // Subtract from a pointer -instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{ +instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{ match(Set dst (AddP dst (SubI zero src))); effect(KILL cr); @@ -7942,7 +7883,7 @@ ins_pipe( ialu_reg_reg ); %} -instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{ +instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{ match(Set dst (SubI zero dst)); effect(KILL cr); @@ -7957,7 +7898,7 @@ //----------Multiplication/Division Instructions------------------------------- // Integer Multiplication Instructions // Multiply Register -instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ +instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ match(Set dst (MulI dst src)); effect(KILL cr); @@ -7970,7 +7911,7 @@ %} // Multiply 32-bit Immediate -instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{ +instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{ match(Set dst (MulI src imm)); effect(KILL cr); @@ -8026,7 +7967,7 @@ %} // Multiply Memory 32-bit Immediate -instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{ +instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{ match(Set dst (MulI (LoadI src) imm)); effect(KILL cr); @@ -8038,7 +7979,7 @@ %} // Multiply Memory -instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{ +instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{ match(Set dst (MulI dst (LoadI src))); effect(KILL cr); @@ -8075,7 +8016,7 @@ %} // Multiply Register Long -instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ +instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ match(Set dst (MulL dst src)); effect(KILL cr, TEMP tmp); ins_cost(4*100+3*400); @@ -8093,7 +8034,7 @@ %} // Multiply Register Long where the left operand's high 32 bits are zero -instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ +instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ predicate(is_operand_hi32_zero(n->in(1))); match(Set dst (MulL dst src)); effect(KILL cr, TEMP tmp); @@ -8114,7 +8055,7 @@ %} // Multiply Register Long where the right operand's high 32 bits are zero -instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ +instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ predicate(is_operand_hi32_zero(n->in(2))); match(Set dst (MulL dst src)); effect(KILL cr, TEMP tmp); @@ -8150,7 +8091,7 @@ %} // Multiply Register Long by small constant -instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{ +instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{ match(Set dst (MulL dst src)); effect(KILL cr, TEMP tmp); ins_cost(2*100+2*400); @@ -8248,7 +8189,7 @@ %} // Divide Register Long (no special case since divisor != -1) -instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{ +instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ match(Set dst (DivL dst imm)); effect( TEMP tmp, TEMP tmp2, KILL cr ); ins_cost(1000); @@ -8319,7 +8260,7 @@ %} // Remainder Register Long (remainder fit into 32 bits) -instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{ +instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ match(Set dst (ModL dst imm)); effect( TEMP tmp, TEMP tmp2, KILL cr ); ins_cost(1000); @@ -8387,7 +8328,7 @@ // Integer Shift Instructions // Shift Left by one -instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ +instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ match(Set dst (LShiftI dst shift)); effect(KILL cr); @@ -8399,7 +8340,7 @@ %} // Shift Left by 8-bit immediate -instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ +instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ match(Set dst (LShiftI dst shift)); effect(KILL cr); @@ -8411,7 +8352,7 @@ %} // Shift Left by variable -instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ +instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ match(Set dst (LShiftI dst shift)); effect(KILL cr); @@ -8423,7 +8364,7 @@ %} // Arithmetic shift right by one -instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ +instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ match(Set dst (RShiftI dst shift)); effect(KILL cr); @@ -8445,7 +8386,7 @@ %} // Arithmetic Shift Right by 8-bit immediate -instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ +instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ match(Set dst (RShiftI dst shift)); effect(KILL cr); @@ -8468,7 +8409,7 @@ %} // Arithmetic Shift Right by variable -instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ +instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ match(Set dst (RShiftI dst shift)); effect(KILL cr); @@ -8480,7 +8421,7 @@ %} // Logical shift right by one -instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ +instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ match(Set dst (URShiftI dst shift)); effect(KILL cr); @@ -8492,7 +8433,7 @@ %} // Logical Shift Right by 8-bit immediate -instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ +instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ match(Set dst (URShiftI dst shift)); effect(KILL cr); @@ -8506,7 +8447,7 @@ // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. // This idiom is used by the compiler for the i2b bytecode. -instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{ +instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{ match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); size(3); @@ -8519,7 +8460,7 @@ // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. // This idiom is used by the compiler the i2s bytecode. -instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{ +instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{ match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); size(3); @@ -8532,7 +8473,7 @@ // Logical Shift Right by variable -instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ +instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ match(Set dst (URShiftI dst shift)); effect(KILL cr); @@ -8548,7 +8489,7 @@ //----------Integer Logical Instructions--------------------------------------- // And Instructions // And Register with Register -instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ +instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ match(Set dst (AndI dst src)); effect(KILL cr); @@ -8560,7 +8501,7 @@ %} // And Register with Immediate -instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ +instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ match(Set dst (AndI dst src)); effect(KILL cr); @@ -8572,7 +8513,7 @@ %} // And Register with Memory -instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ +instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ match(Set dst (AndI dst (LoadI src))); effect(KILL cr); @@ -8584,7 +8525,7 @@ %} // And Memory with Register -instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ +instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ match(Set dst (StoreI dst (AndI (LoadI dst) src))); effect(KILL cr); @@ -8610,7 +8551,7 @@ // Or Instructions // Or Register with Register -instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ +instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ match(Set dst (OrI dst src)); effect(KILL cr); @@ -8621,7 +8562,7 @@ ins_pipe( ialu_reg_reg ); %} -instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{ +instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{ match(Set dst (OrI dst (CastP2X src))); effect(KILL cr); @@ -8634,7 +8575,7 @@ // Or Register with Immediate -instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ +instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ match(Set dst (OrI dst src)); effect(KILL cr); @@ -8646,7 +8587,7 @@ %} // Or Register with Memory -instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ +instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ match(Set dst (OrI dst (LoadI src))); effect(KILL cr); @@ -8658,7 +8599,7 @@ %} // Or Memory with Register -instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ +instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ match(Set dst (StoreI dst (OrI (LoadI dst) src))); effect(KILL cr); @@ -8684,7 +8625,7 @@ // ROL/ROR // ROL expand -instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ +instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ effect(USE_DEF dst, USE shift, KILL cr); format %{ "ROL $dst, $shift" %} @@ -8693,7 +8634,7 @@ ins_pipe( ialu_reg ); %} -instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ +instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ effect(USE_DEF dst, USE shift, KILL cr); format %{ "ROL $dst, $shift" %} @@ -8713,7 +8654,7 @@ // end of ROL expand // ROL 32bit by one once -instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ +instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); expand %{ @@ -8722,7 +8663,7 @@ %} // ROL 32bit var by imm8 once -instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ +instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); @@ -8750,7 +8691,7 @@ %} // ROR expand -instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ +instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ effect(USE_DEF dst, USE shift, KILL cr); format %{ "ROR $dst, $shift" %} @@ -8759,7 +8700,7 @@ ins_pipe( ialu_reg ); %} -instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ +instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ effect (USE_DEF dst, USE shift, KILL cr); format %{ "ROR $dst, $shift" %} @@ -8779,7 +8720,7 @@ // end of ROR expand // ROR right once -instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ +instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); expand %{ @@ -8788,7 +8729,7 @@ %} // ROR 32bit by immI8 once -instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ +instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); @@ -8817,7 +8758,7 @@ // Xor Instructions // Xor Register with Register -instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ +instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ match(Set dst (XorI dst src)); effect(KILL cr); @@ -8829,7 +8770,7 @@ %} // Xor Register with Immediate -1 -instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{ +instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{ match(Set dst (XorI dst imm)); size(2); @@ -8841,7 +8782,7 @@ %} // Xor Register with Immediate -instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ +instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ match(Set dst (XorI dst src)); effect(KILL cr); @@ -8853,7 +8794,7 @@ %} // Xor Register with Memory -instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ +instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ match(Set dst (XorI dst (LoadI src))); effect(KILL cr); @@ -8865,7 +8806,7 @@ %} // Xor Memory with Register -instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ +instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ match(Set dst (StoreI dst (XorI (LoadI dst) src))); effect(KILL cr); @@ -8890,14 +8831,14 @@ //----------Convert Int to Boolean--------------------------------------------- -instruct movI_nocopy(eRegI dst, eRegI src) %{ +instruct movI_nocopy(rRegI dst, rRegI src) %{ effect( DEF dst, USE src ); format %{ "MOV $dst,$src" %} ins_encode( enc_Copy( dst, src) ); ins_pipe( ialu_reg_reg ); %} -instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{ +instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{ effect( USE_DEF dst, USE src, KILL cr ); size(4); @@ -8908,7 +8849,7 @@ ins_pipe( ialu_reg_reg_long ); %} -instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{ +instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{ match(Set dst (Conv2B src)); expand %{ @@ -8917,14 +8858,14 @@ %} %} -instruct movP_nocopy(eRegI dst, eRegP src) %{ +instruct movP_nocopy(rRegI dst, eRegP src) %{ effect( DEF dst, USE src ); format %{ "MOV $dst,$src" %} ins_encode( enc_Copy( dst, src) ); ins_pipe( ialu_reg_reg ); %} -instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{ +instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{ effect( USE_DEF dst, USE src, KILL cr ); format %{ "NEG $dst\n\t" "ADC $dst,$src" %} @@ -8933,7 +8874,7 @@ ins_pipe( ialu_reg_reg_long ); %} -instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{ +instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{ match(Set dst (Conv2B src)); expand %{ @@ -8958,7 +8899,7 @@ ins_pipe( pipe_slow ); %} -instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{ +instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{ match(Set dst (CmpLTMask dst zero)); effect( DEF dst, KILL cr ); ins_cost(100); @@ -9430,7 +9371,7 @@ %} // Compare vs zero into -1,0,1 -instruct cmpDPR_0(eRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{ +instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{ predicate(UseSSE<=1); match(Set dst (CmpD3 src1 zero)); effect(KILL cr, KILL rax); @@ -9444,7 +9385,7 @@ %} // Compare into -1,0,1 -instruct cmpDPR_reg(eRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{ +instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{ predicate(UseSSE<=1); match(Set dst (CmpD3 src1 src2)); effect(KILL cr, KILL rax); @@ -10222,7 +10163,7 @@ %} // Compare vs zero into -1,0,1 -instruct cmpFPR_0(eRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{ +instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{ predicate(UseSSE == 0); match(Set dst (CmpF3 src1 zero)); effect(KILL cr, KILL rax); @@ -10236,7 +10177,7 @@ %} // Compare into -1,0,1 -instruct cmpFPR_reg(eRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ +instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ predicate(UseSSE == 0); match(Set dst (CmpF3 src1 src2)); effect(KILL cr, KILL rax); @@ -11156,7 +11097,7 @@ ins_pipe( fpu_reg_mem ); %} -instruct convI2D_reg(regD dst, eRegI src) %{ +instruct convI2D_reg(regD dst, rRegI src) %{ predicate( UseSSE>=2 && !UseXmmI2D ); match(Set dst (ConvI2D src)); format %{ "CVTSI2SD $dst,$src" %} @@ -11176,7 +11117,7 @@ ins_pipe( pipe_slow ); %} -instruct convXI2D_reg(regD dst, eRegI src) +instruct convXI2D_reg(regD dst, rRegI src) %{ predicate( UseSSE>=2 && UseXmmI2D ); match(Set dst (ConvI2D src)); @@ -11264,7 +11205,7 @@ %} // Convert an int to a float in xmm; no rounding step needed. -instruct convI2F_reg(regF dst, eRegI src) %{ +instruct convI2F_reg(regF dst, rRegI src) %{ predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); match(Set dst (ConvI2F src)); format %{ "CVTSI2SS $dst, $src" %} @@ -11274,7 +11215,7 @@ ins_pipe( pipe_slow ); %} - instruct convXI2F_reg(regF dst, eRegI src) + instruct convXI2F_reg(regF dst, rRegI src) %{ predicate( UseSSE>=2 && UseXmmI2F ); match(Set dst (ConvI2F src)); @@ -11288,7 +11229,7 @@ ins_pipe(pipe_slow); // XXX %} -instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{ +instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{ match(Set dst (ConvI2L src)); effect(KILL cr); ins_cost(375); @@ -11300,7 +11241,7 @@ %} // Zero-extend convert int to long -instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{ +instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{ match(Set dst (AndL (ConvI2L src) mask) ); effect( KILL flags ); ins_cost(250); @@ -11380,7 +11321,7 @@ ins_pipe( pipe_slow ); %} -instruct convL2I_reg( eRegI dst, eRegL src ) %{ +instruct convL2I_reg( rRegI dst, eRegL src ) %{ match(Set dst (ConvL2I src)); effect( DEF dst, USE src ); format %{ "MOV $dst,$src.lo" %} @@ -11389,7 +11330,7 @@ %} -instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{ +instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ match(Set dst (MoveF2I src)); effect( DEF dst, USE src ); ins_cost(100); @@ -11424,7 +11365,7 @@ ins_pipe( pipe_slow ); %} -instruct MoveF2I_reg_reg_sse(eRegI dst, regF src) %{ +instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{ predicate(UseSSE>=2); match(Set dst (MoveF2I src)); effect( DEF dst, USE src ); @@ -11436,7 +11377,7 @@ ins_pipe( pipe_slow ); %} -instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{ +instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ match(Set dst (MoveI2F src)); effect( DEF dst, USE src ); @@ -11476,7 +11417,7 @@ ins_pipe( pipe_slow ); %} -instruct MoveI2F_reg_reg_sse(regF dst, eRegI src) %{ +instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{ predicate(UseSSE>=2); match(Set dst (MoveI2F src)); effect( DEF dst, USE src ); @@ -11610,186 +11551,6 @@ ins_pipe( pipe_slow ); %} -// Replicate scalar to packed byte (1 byte) values in xmm -instruct Repl8B_reg(regD dst, regD src) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate8B src)); - format %{ "MOVDQA $dst,$src\n\t" - "PUNPCKLBW $dst,$dst\n\t" - "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} - ins_encode %{ - if ($dst$$reg != $src$$reg) { - __ movdqa($dst$$XMMRegister, $src$$XMMRegister); - } - __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); - __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); - %} - ins_pipe( pipe_slow ); -%} - -// Replicate scalar to packed byte (1 byte) values in xmm -instruct Repl8B_eRegI(regD dst, eRegI src) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate8B src)); - format %{ "MOVD $dst,$src\n\t" - "PUNPCKLBW $dst,$dst\n\t" - "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} - ins_encode %{ - __ movdl($dst$$XMMRegister, $src$$Register); - __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); - __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); - %} - ins_pipe( pipe_slow ); -%} - -// Replicate scalar zero to packed byte (1 byte) values in xmm -instruct Repl8B_immI0(regD dst, immI0 zero) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate8B zero)); - format %{ "PXOR $dst,$dst\t! replicate8B" %} - ins_encode %{ - __ pxor($dst$$XMMRegister, $dst$$XMMRegister); - %} - ins_pipe( fpu_reg_reg ); -%} - -// Replicate scalar to packed shore (2 byte) values in xmm -instruct Repl4S_reg(regD dst, regD src) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate4S src)); - format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} - ins_encode %{ - __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00); - %} - ins_pipe( fpu_reg_reg ); -%} - -// Replicate scalar to packed shore (2 byte) values in xmm -instruct Repl4S_eRegI(regD dst, eRegI src) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate4S src)); - format %{ "MOVD $dst,$src\n\t" - "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} - ins_encode %{ - __ movdl($dst$$XMMRegister, $src$$Register); - __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); - %} - ins_pipe( fpu_reg_reg ); -%} - -// Replicate scalar zero to packed short (2 byte) values in xmm -instruct Repl4S_immI0(regD dst, immI0 zero) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate4S zero)); - format %{ "PXOR $dst,$dst\t! replicate4S" %} - ins_encode %{ - __ pxor($dst$$XMMRegister, $dst$$XMMRegister); - %} - ins_pipe( fpu_reg_reg ); -%} - -// Replicate scalar to packed char (2 byte) values in xmm -instruct Repl4C_reg(regD dst, regD src) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate4C src)); - format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} - ins_encode %{ - __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00); - %} - ins_pipe( fpu_reg_reg ); -%} - -// Replicate scalar to packed char (2 byte) values in xmm -instruct Repl4C_eRegI(regD dst, eRegI src) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate4C src)); - format %{ "MOVD $dst,$src\n\t" - "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} - ins_encode %{ - __ movdl($dst$$XMMRegister, $src$$Register); - __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); - %} - ins_pipe( fpu_reg_reg ); -%} - -// Replicate scalar zero to packed char (2 byte) values in xmm -instruct Repl4C_immI0(regD dst, immI0 zero) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate4C zero)); - format %{ "PXOR $dst,$dst\t! replicate4C" %} - ins_encode %{ - __ pxor($dst$$XMMRegister, $dst$$XMMRegister); - %} - ins_pipe( fpu_reg_reg ); -%} - -// Replicate scalar to packed integer (4 byte) values in xmm -instruct Repl2I_reg(regD dst, regD src) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate2I src)); - format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} - ins_encode %{ - __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); - %} - ins_pipe( fpu_reg_reg ); -%} - -// Replicate scalar to packed integer (4 byte) values in xmm -instruct Repl2I_eRegI(regD dst, eRegI src) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate2I src)); - format %{ "MOVD $dst,$src\n\t" - "PSHUFD $dst,$dst,0x00\t! replicate2I" %} - ins_encode %{ - __ movdl($dst$$XMMRegister, $src$$Register); - __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); - %} - ins_pipe( fpu_reg_reg ); -%} - -// Replicate scalar zero to packed integer (2 byte) values in xmm -instruct Repl2I_immI0(regD dst, immI0 zero) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate2I zero)); - format %{ "PXOR $dst,$dst\t! replicate2I" %} - ins_encode %{ - __ pxor($dst$$XMMRegister, $dst$$XMMRegister); - %} - ins_pipe( fpu_reg_reg ); -%} - -// Replicate scalar to packed single precision floating point values in xmm -instruct Repl2F_reg(regD dst, regD src) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate2F src)); - format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} - ins_encode %{ - __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0); - %} - ins_pipe( fpu_reg_reg ); -%} - -// Replicate scalar to packed single precision floating point values in xmm -instruct Repl2F_regF(regD dst, regF src) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate2F src)); - format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} - ins_encode %{ - __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0); - %} - ins_pipe( fpu_reg_reg ); -%} - -// Replicate scalar to packed single precision floating point values in xmm -instruct Repl2F_immF0(regD dst, immF0 zero) %{ - predicate(UseSSE>=2); - match(Set dst (Replicate2F zero)); - format %{ "PXOR $dst,$dst\t! replicate2F" %} - ins_encode %{ - __ pxor($dst$$XMMRegister, $dst$$XMMRegister); - %} - ins_pipe( fpu_reg_reg ); -%} // ======================================================================= // fast clearing of an array @@ -11898,7 +11659,7 @@ //----------Control Flow Instructions------------------------------------------ // Signed compare Instructions -instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{ +instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{ match(Set cr (CmpI op1 op2)); effect( DEF cr, USE op1, USE op2 ); format %{ "CMP $op1,$op2" %} @@ -11907,7 +11668,7 @@ ins_pipe( ialu_cr_reg_reg ); %} -instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{ +instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{ match(Set cr (CmpI op1 op2)); effect( DEF cr, USE op1 ); format %{ "CMP $op1,$op2" %} @@ -11918,7 +11679,7 @@ %} // Cisc-spilled version of cmpI_eReg -instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{ +instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{ match(Set cr (CmpI op1 (LoadI op2))); format %{ "CMP $op1,$op2" %} @@ -11928,7 +11689,7 @@ ins_pipe( ialu_cr_reg_mem ); %} -instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{ +instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{ match(Set cr (CmpI src zero)); effect( DEF cr, USE src ); @@ -11938,7 +11699,7 @@ ins_pipe( ialu_cr_reg_imm ); %} -instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{ +instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{ match(Set cr (CmpI (AndI src con) zero)); format %{ "TEST $src,$con" %} @@ -11947,7 +11708,7 @@ ins_pipe( ialu_cr_reg_imm ); %} -instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{ +instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{ match(Set cr (CmpI (AndI src mem) zero)); format %{ "TEST $src,$mem" %} @@ -11958,7 +11719,7 @@ // Unsigned compare Instructions; really, same as signed except they // produce an eFlagsRegU instead of eFlagsReg. -instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{ +instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{ match(Set cr (CmpU op1 op2)); format %{ "CMPu $op1,$op2" %} @@ -11967,7 +11728,7 @@ ins_pipe( ialu_cr_reg_reg ); %} -instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{ +instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{ match(Set cr (CmpU op1 op2)); format %{ "CMPu $op1,$op2" %} @@ -11977,7 +11738,7 @@ %} // // Cisc-spilled version of cmpU_eReg -instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{ +instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{ match(Set cr (CmpU op1 (LoadI op2))); format %{ "CMPu $op1,$op2" %} @@ -11988,7 +11749,7 @@ %} // // Cisc-spilled version of cmpU_eReg -//instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{ +//instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{ // match(Set cr (CmpU (LoadI op1) op2)); // // format %{ "CMPu $op1,$op2" %} @@ -11997,7 +11758,7 @@ // ins_encode( OpcP, RegMem( op1, op2) ); //%} -instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{ +instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{ match(Set cr (CmpU src zero)); format %{ "TESTu $src,$src" %} @@ -12093,7 +11854,7 @@ // *** Min and Max using the conditional move are slower than the // *** branch version on a Pentium III. // // Conditional move for min -//instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ +//instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ // effect( USE_DEF op2, USE op1, USE cr ); // format %{ "CMOVlt $op2,$op1\t! min" %} // opcode(0x4C,0x0F); @@ -12102,7 +11863,7 @@ //%} // //// Min Register with Register (P6 version) -//instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{ +//instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{ // predicate(VM_Version::supports_cmov() ); // match(Set op2 (MinI op1 op2)); // ins_cost(200); @@ -12114,7 +11875,7 @@ //%} // Min Register with Register (generic version) -instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ +instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ match(Set dst (MinI dst src)); effect(KILL flags); ins_cost(300); @@ -12129,7 +11890,7 @@ // *** Min and Max using the conditional move are slower than the // *** branch version on a Pentium III. // // Conditional move for max -//instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ +//instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ // effect( USE_DEF op2, USE op1, USE cr ); // format %{ "CMOVgt $op2,$op1\t! max" %} // opcode(0x4F,0x0F); @@ -12138,7 +11899,7 @@ //%} // // // Max Register with Register (P6 version) -//instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{ +//instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{ // predicate(VM_Version::supports_cmov() ); // match(Set op2 (MaxI op1 op2)); // ins_cost(200); @@ -12150,7 +11911,7 @@ //%} // Max Register with Register (generic version) -instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ +instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ match(Set dst (MaxI dst src)); effect(KILL flags); ins_cost(300); @@ -12211,7 +11972,7 @@ // ============================================================================ // Branch Instructions // Jump Table -instruct jumpXtnd(eRegI switch_val) %{ +instruct jumpXtnd(rRegI switch_val) %{ match(Jump switch_val); ins_cost(350); format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} @@ -12629,7 +12390,7 @@ // Manifest a CmpL result in the normal flags. Only good for LT or GE // compares. Can be used for LE or GT compares by reversing arguments. // NOT GOOD FOR EQ/NE tests. -instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{ +instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{ match( Set flags (CmpL src1 src2 )); effect( TEMP tmp ); ins_cost(300); @@ -12675,7 +12436,7 @@ %} // Compare 2 longs and CMOVE ints. -instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{ +instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{ predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); ins_cost(200); @@ -12685,7 +12446,7 @@ ins_pipe( pipe_cmov_reg ); %} -instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{ +instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{ predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); ins_cost(250); @@ -12746,7 +12507,7 @@ //====== // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. -instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{ +instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{ match( Set flags (CmpL src zero )); effect(TEMP tmp); ins_cost(200); @@ -12803,7 +12564,7 @@ %} // Compare 2 longs and CMOVE ints. -instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{ +instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{ predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); ins_cost(200); @@ -12813,7 +12574,7 @@ ins_pipe( pipe_cmov_reg ); %} -instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{ +instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{ predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); ins_cost(250); @@ -12875,7 +12636,7 @@ //====== // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. // Same as cmpL_reg_flags_LEGT except must negate src -instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{ +instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{ match( Set flags (CmpL src zero )); effect( TEMP tmp ); ins_cost(300); @@ -12889,7 +12650,7 @@ // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands // requires a commuted test to get the same result. -instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{ +instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{ match( Set flags (CmpL src1 src2 )); effect( TEMP tmp ); ins_cost(300); @@ -12936,7 +12697,7 @@ %} // Compare 2 longs and CMOVE ints. -instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{ +instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{ predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); ins_cost(200); @@ -12946,7 +12707,7 @@ ins_pipe( pipe_cmov_reg ); %} -instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{ +instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{ predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); ins_cost(250); @@ -13275,11 +13036,11 @@ // ---------EXAMPLE---------------------------------------------------------- // // // pertinent parts of existing instructions in architecture description -// instruct movI(eRegI dst, eRegI src) %{ +// instruct movI(rRegI dst, rRegI src) %{ // match(Set dst (CopyI src)); // %} // -// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ +// instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ // match(Set dst (AddI dst src)); // effect(KILL cr); // %} @@ -13324,11 +13085,11 @@ // %} // // Change load of spilled value to only a spill -// instruct storeI(memory mem, eRegI src) %{ +// instruct storeI(memory mem, rRegI src) %{ // match(Set mem (StoreI mem src)); // %} // -// instruct loadI(eRegI dst, memory mem) %{ +// instruct loadI(rRegI dst, memory mem) %{ // match(Set dst (LoadI mem)); // %} //