Mercurial > hg > truffle
diff src/cpu/sparc/vm/sparc.ad @ 1367:9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
Summary: Use BIS instruction for allocation prefetch on Sparc
Reviewed-by: twisti
author | kvn |
---|---|
date | Wed, 07 Apr 2010 12:39:27 -0700 |
parents | 2883969d09e7 |
children | d7f654633cfe |
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--- a/src/cpu/sparc/vm/sparc.ad Wed Apr 07 10:35:56 2010 -0700 +++ b/src/cpu/sparc/vm/sparc.ad Wed Apr 07 12:39:27 2010 -0700 @@ -471,6 +471,9 @@ source %{ #define __ _masm. +// Block initializing store +#define ASI_BLK_INIT_QUAD_LDD_P 0xE2 + // tertiary op of a LoadP or StoreP encoding #define REGP_OP true @@ -6147,6 +6150,7 @@ %} instruct prefetchw( memory mem ) %{ + predicate(AllocatePrefetchStyle != 3 ); match( PrefetchWrite mem ); ins_cost(MEMORY_REF_COST); @@ -6156,6 +6160,23 @@ ins_pipe(iload_mem); %} +// Use BIS instruction to prefetch. +instruct prefetchw_bis( memory mem ) %{ + predicate(AllocatePrefetchStyle == 3); + match( PrefetchWrite mem ); + ins_cost(MEMORY_REF_COST); + + format %{ "STXA G0,$mem\t! // Block initializing store" %} + ins_encode %{ + Register base = as_Register($mem$$base); + int disp = $mem$$disp; + if (disp != 0) { + __ add(base, AllocatePrefetchStepSize, base); + } + __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P); + %} + ins_pipe(istore_mem_reg); +%} //----------Store Instructions------------------------------------------------- // Store Byte