Mercurial > hg > truffle
diff src/share/vm/utilities/globalDefinitions.hpp @ 17812:a7d4d4655766
Merge
author | kvn |
---|---|
date | Wed, 26 Mar 2014 18:21:05 -0700 |
parents | 62c54fcc0a35 |
children | 7384f6a12fc1 |
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--- a/src/share/vm/utilities/globalDefinitions.hpp Mon Mar 24 10:48:44 2014 -0700 +++ b/src/share/vm/utilities/globalDefinitions.hpp Wed Mar 26 18:21:05 2014 -0700 @@ -38,6 +38,9 @@ #ifdef TARGET_COMPILER_sparcWorks # include "utilities/globalDefinitions_sparcWorks.hpp" #endif +#ifdef TARGET_COMPILER_xlc +# include "utilities/globalDefinitions_xlc.hpp" +#endif #include "utilities/macros.hpp" @@ -410,6 +413,17 @@ #define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1 #endif +// To assure the IRIW property on processors that are not multiple copy +// atomic, sync instructions must be issued between volatile reads to +// assure their ordering, instead of after volatile stores. +// (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models" +// by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge) +#ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC +const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true; +#else +const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false; +#endif + // The byte alignment to be used by Arena::Amalloc. See bugid 4169348. // Note: this value must be a power of 2