diff src/share/vm/opto/divnode.cpp @ 400:cc80376deb0c

6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop Summary: Fix loop's probability. Add optimizations to avoid spilling. Change InlineSmallCode to product flag. Reviewed-by: never
author kvn
date Thu, 02 Oct 2008 08:37:44 -0700
parents ab075d07f1ba
children 78c058bc5cdc
line wrap: on
line diff
--- a/src/share/vm/opto/divnode.cpp	Tue Sep 30 15:53:55 2008 -0700
+++ b/src/share/vm/opto/divnode.cpp	Thu Oct 02 08:37:44 2008 -0700
@@ -110,10 +110,13 @@
     } else if( dividend->Opcode() == Op_AndI ) {
       // An AND mask of sufficient size clears the low bits and
       // I can avoid rounding.
-      const TypeInt *andconi = phase->type( dividend->in(2) )->isa_int();
-      if( andconi && andconi->is_con(-d) ) {
-        dividend = dividend->in(1);
-        needs_rounding = false;
+      const TypeInt *andconi_t = phase->type( dividend->in(2) )->isa_int();
+      if( andconi_t && andconi_t->is_con() ) {
+        jint andconi = andconi_t->get_con();
+        if( andconi < 0 && is_power_of_2(-andconi) && (-andconi) >= d ) {
+          dividend = dividend->in(1);
+          needs_rounding = false;
+        }
       }
     }
 
@@ -316,10 +319,13 @@
     } else if( dividend->Opcode() == Op_AndL ) {
       // An AND mask of sufficient size clears the low bits and
       // I can avoid rounding.
-      const TypeLong *andconl = phase->type( dividend->in(2) )->isa_long();
-      if( andconl && andconl->is_con(-d)) {
-        dividend = dividend->in(1);
-        needs_rounding = false;
+      const TypeLong *andconl_t = phase->type( dividend->in(2) )->isa_long();
+      if( andconl_t && andconl_t->is_con() ) {
+        jlong andconl = andconl_t->get_con();
+        if( andconl < 0 && is_power_of_2_long(-andconl) && (-andconl) >= d ) {
+          dividend = dividend->in(1);
+          needs_rounding = false;
+        }
       }
     }