--- a/src/cpu/sparc/vm/sparc.ad	Wed Nov 20 11:08:09 2013 -0800
+++ b/src/cpu/sparc/vm/sparc.ad	Thu Nov 21 12:30:35 2013 -0800
@@ -2924,6 +2924,9 @@
       __ bind(LSkip2);
     }
 
+    // We have no guarantee that on 64 bit the higher half of limit_reg is 0
+    __ signx(limit_reg);
+
     __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
     __ br(Assembler::equal, true, Assembler::pn, Ldone);
     __ delayed()->mov(O7, result_reg);  // result is difference in lengths
@@ -2981,6 +2984,9 @@
     Register  chr1_reg = result_reg;
     Register  chr2_reg =   tmp1_reg;
 
+    // We have no guarantee that on 64 bit the higher half of limit_reg is 0
+    __ signx(limit_reg);
+
     //check for alignment and position the pointers to the ends
     __ or3(str1_reg, str2_reg, chr1_reg);
     __ andcc(chr1_reg, 0x3, chr1_reg);