Mercurial > hg > truffle
diff src/cpu/sparc/vm/icBuffer_sparc.cpp @ 6725:da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
Summary: Remove PermGen, allocate meta-data in metaspace linked to class loaders, rewrite GC walking, rewrite and rename metadata to be C++ classes
Reviewed-by: jmasa, stefank, never, coleenp, kvn, brutisso, mgerdin, dholmes, jrose, twisti, roland
Contributed-by: jmasa <jon.masamitsu@oracle.com>, stefank <stefan.karlsson@oracle.com>, mgerdin <mikael.gerdin@oracle.com>, never <tom.rodriguez@oracle.com>
author | coleenp |
---|---|
date | Sat, 01 Sep 2012 13:25:18 -0400 |
parents | f95d63e2154a |
children | f0c2369fda5a |
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--- a/src/cpu/sparc/vm/icBuffer_sparc.cpp Fri Aug 31 16:39:35 2012 -0700 +++ b/src/cpu/sparc/vm/icBuffer_sparc.cpp Sat Sep 01 13:25:18 2012 -0400 @@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -45,18 +45,17 @@ #endif } -void InlineCacheBuffer::assemble_ic_buffer_code(address code_begin, oop cached_oop, address entry_point) { +void InlineCacheBuffer::assemble_ic_buffer_code(address code_begin, void* cached_value, address entry_point) { ResourceMark rm; CodeBuffer code(code_begin, ic_stub_code_size()); MacroAssembler* masm = new MacroAssembler(&code); - // note: even though the code contains an embedded oop, we do not need reloc info + // note: even though the code contains an embedded metadata, we do not need reloc info // because - // (1) the oop is old (i.e., doesn't matter for scavenges) + // (1) the metadata is old (i.e., doesn't matter for scavenges) // (2) these ICStubs are removed *before* a GC happens, so the roots disappear - assert(cached_oop == NULL || cached_oop->is_perm(), "must be old oop"); - AddressLiteral cached_oop_addrlit(cached_oop, relocInfo::none); + AddressLiteral cached_value_addrlit((address)cached_value, relocInfo::none); // Force the set to generate the fixed sequence so next_instruction_address works - masm->patchable_set(cached_oop_addrlit, G5_inline_cache_reg); + masm->patchable_set(cached_value_addrlit, G5_inline_cache_reg); assert(G3_scratch != G5_method, "Do not clobber the method oop in the transition stub"); assert(G3_scratch != G5_inline_cache_reg, "Do not clobber the inline cache register in the transition stub"); AddressLiteral entry(entry_point); @@ -73,8 +72,9 @@ } -oop InlineCacheBuffer::ic_buffer_cached_oop(address code_begin) { +void* InlineCacheBuffer::ic_buffer_cached_value(address code_begin) { NativeMovConstReg* move = nativeMovConstReg_at(code_begin); // creation also verifies the object NativeJump* jump = nativeJump_at(move->next_instruction_address()); - return (oop)move->data(); + void* o = (void*)move->data(); + return o; }