//
// Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License version 2 only, as
// published by the Free Software Foundation.
//
// This code is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// version 2 for more details (a copy is included in the LICENSE file that
// accompanied this code).
//
// You should have received a copy of the GNU General Public License version
// 2 along with this work; if not, write to the Free Software Foundation,
// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
//
// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
// or visit www.oracle.com if you need additional information or have any
// questions.
//
//

// AMD64 Bsd Architecture Description File

//----------OS-DEPENDENT ENCODING BLOCK----------------------------------------
// This block specifies the encoding classes used by the compiler to
// output byte streams.  Encoding classes generate functions which are
// called by Machine Instruction Nodes in order to generate the bit
// encoding of the instruction.  Operands specify their base encoding
// interface with the interface keyword.  There are currently
// supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
// COND_INTER.  REG_INTER causes an operand to generate a function
// which returns its register number when queried.  CONST_INTER causes
// an operand to generate a function which returns the value of the
// constant when queried.  MEMORY_INTER causes an operand to generate
// four functions which return the Base Register, the Index Register,
// the Scale Value, and the Offset Value of the operand when queried.
// COND_INTER causes an operand to generate six functions which return
// the encoding code (ie - encoding bits for the instruction)
// associated with each basic boolean condition for a conditional
// instruction.  Instructions specify two basic values for encoding.
// They use the ins_encode keyword to specify their encoding class
// (which must be one of the class names specified in the encoding
// block), and they use the opcode keyword to specify, in order, their
// primary, secondary, and tertiary opcode.  Only the opcode sections
// which a particular instruction needs for encoding need to be
// specified.
encode %{
  // Build emit functions for each basic byte or larger field in the intel
  // encoding scheme (opcode, rm, sib, immediate), and call them from C++
  // code in the enc_class source block.  Emit functions will live in the
  // main source block for now.  In future, we can generalize this by
  // adding a syntax that specifies the sizes of fields in an order,
  // so that the adlc can build the emit functions automagically

  enc_class Java_To_Runtime(method meth) %{
    // No relocation needed

    // movq r10, <meth>
    emit_opcode(cbuf, Assembler::REX_WB);
    emit_opcode(cbuf, 0xB8 | (R10_enc - 8));
    emit_d64(cbuf, (int64_t) $meth$$method);

    // call (r10)
    emit_opcode(cbuf, Assembler::REX_B);
    emit_opcode(cbuf, 0xFF);
    emit_opcode(cbuf, 0xD0 | (R10_enc - 8));
  %}

%}


// Platform dependent source

source %{

int MachCallRuntimeNode::ret_addr_offset() {
  return 13; // movq r10,#addr; callq (r10)
}

%}