# HG changeset patch # User goetz # Date 1385089257 28800 # Node ID 15120a36272d6379397c25526cd7483ba843f4c9 # Parent b0133e4187d300d5c8cf3fe0ccedd9cf299c32e6 8028767: PPC64: (part 121): smaller shared changes needed to build C2 Summary: smaller shared changes required to build the C2 compiler on PPC64. Reviewed-by: kvn diff -r b0133e4187d3 -r 15120a36272d src/share/vm/adlc/output_h.cpp --- a/src/share/vm/adlc/output_h.cpp Thu Nov 21 18:29:34 2013 -0800 +++ b/src/share/vm/adlc/output_h.cpp Thu Nov 21 19:00:57 2013 -0800 @@ -26,7 +26,11 @@ #include "adlc.hpp" // The comment delimiter used in format statements after assembler instructions. +#if defined(PPC64) +#define commentSeperator "\t//" +#else #define commentSeperator "!" +#endif // Generate the #define that describes the number of registers. static void defineRegCount(FILE *fp, RegisterForm *registers) { diff -r b0133e4187d3 -r 15120a36272d src/share/vm/asm/assembler.hpp --- a/src/share/vm/asm/assembler.hpp Thu Nov 21 18:29:34 2013 -0800 +++ b/src/share/vm/asm/assembler.hpp Thu Nov 21 19:00:57 2013 -0800 @@ -204,10 +204,11 @@ CodeSection* _code_section; // section within the code buffer OopRecorder* _oop_recorder; // support for relocInfo::oop_type + public: // Code emission & accessing address addr_at(int pos) const { return code_section()->start() + pos; } - + protected: // This routine is called with a label is used for an address. // Labels and displacements truck in offsets, but target must return a PC. address target(Label& L) { return code_section()->target(L, pc()); } diff -r b0133e4187d3 -r 15120a36272d src/share/vm/compiler/compileBroker.cpp --- a/src/share/vm/compiler/compileBroker.cpp Thu Nov 21 18:29:34 2013 -0800 +++ b/src/share/vm/compiler/compileBroker.cpp Thu Nov 21 19:00:57 2013 -0800 @@ -998,7 +998,7 @@ void CompileBroker::init_compiler_threads(int c1_compiler_count, int c2_compiler_count) { EXCEPTION_MARK; -#if !defined(ZERO) && !defined(SHARK) && !defined(PPC64) +#if !defined(ZERO) && !defined(SHARK) assert(c2_compiler_count > 0 || c1_compiler_count > 0, "No compilers?"); #endif // !ZERO && !SHARK // Initialize the compilation queue diff -r b0133e4187d3 -r 15120a36272d src/share/vm/memory/metaspace.hpp --- a/src/share/vm/memory/metaspace.hpp Thu Nov 21 18:29:34 2013 -0800 +++ b/src/share/vm/memory/metaspace.hpp Thu Nov 21 19:00:57 2013 -0800 @@ -117,9 +117,12 @@ // Aligned size of the metaspace. static size_t _compressed_class_space_size; + public: static size_t compressed_class_space_size() { return _compressed_class_space_size; } + + private: static void set_compressed_class_space_size(size_t size) { _compressed_class_space_size = size; } diff -r b0133e4187d3 -r 15120a36272d src/share/vm/opto/c2_globals.hpp --- a/src/share/vm/opto/c2_globals.hpp Thu Nov 21 18:29:34 2013 -0800 +++ b/src/share/vm/opto/c2_globals.hpp Thu Nov 21 19:00:57 2013 -0800 @@ -229,7 +229,8 @@ diagnostic(bool, UnrollLimitCheck, true, \ "Additional overflow checks during loop unroll") \ \ - product(bool, OptimizeFill, true, \ + /* OptimizeFill not yet supported on PowerPC. */ \ + product(bool, OptimizeFill, true PPC64_ONLY(&& false), \ "convert fill/copy loops into intrinsic") \ \ develop(bool, TraceOptimizeFill, false, \ diff -r b0133e4187d3 -r 15120a36272d src/share/vm/opto/chaitin.cpp --- a/src/share/vm/opto/chaitin.cpp Thu Nov 21 18:29:34 2013 -0800 +++ b/src/share/vm/opto/chaitin.cpp Thu Nov 21 19:00:57 2013 -0800 @@ -761,7 +761,7 @@ // processes as vector in RA. if (RegMask::is_vector(ireg)) lrg._is_vector = 1; - assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD, + assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD || ireg == Op_RegL, "vector must be in vector registers"); // Check for bound register masks @@ -961,7 +961,7 @@ int kreg = n->in(k)->ideal_reg(); bool is_vect = RegMask::is_vector(kreg); assert(n->in(k)->bottom_type()->isa_vect() == NULL || - is_vect || kreg == Op_RegD, + is_vect || kreg == Op_RegD || kreg == Op_RegL, "vector must be in vector registers"); if (lrgmask.is_bound(kreg)) lrg._is_bound = 1; diff -r b0133e4187d3 -r 15120a36272d src/share/vm/opto/machnode.cpp --- a/src/share/vm/opto/machnode.cpp Thu Nov 21 18:29:34 2013 -0800 +++ b/src/share/vm/opto/machnode.cpp Thu Nov 21 19:00:57 2013 -0800 @@ -397,6 +397,17 @@ return skipped; } +int MachNode::operand_index(const MachOper *oper) const { + uint skipped = oper_input_base(); // Sum of leaves skipped so far + uint opcnt; + for (opcnt = 1; opcnt < num_opnds(); opcnt++) { + if (_opnds[opcnt] == oper) break; + uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand + skipped += num_edges; + } + if (_opnds[opcnt] != oper) return -1; + return skipped; +} //------------------------------peephole--------------------------------------- // Apply peephole rule(s) to this instruction diff -r b0133e4187d3 -r 15120a36272d src/share/vm/opto/machnode.hpp --- a/src/share/vm/opto/machnode.hpp Thu Nov 21 18:29:34 2013 -0800 +++ b/src/share/vm/opto/machnode.hpp Thu Nov 21 19:00:57 2013 -0800 @@ -31,6 +31,7 @@ #include "opto/node.hpp" #include "opto/regmask.hpp" +class BiasedLockingCounters; class BufferBlob; class CodeBuffer; class JVMState; @@ -206,6 +207,7 @@ // First index in _in[] corresponding to operand, or -1 if there is none int operand_index(uint operand) const; + int operand_index(const MachOper *oper) const; // Register class input is expected in virtual const RegMask &in_RegMask(uint) const; diff -r b0133e4187d3 -r 15120a36272d src/share/vm/opto/regalloc.cpp --- a/src/share/vm/opto/regalloc.cpp Thu Nov 21 18:29:34 2013 -0800 +++ b/src/share/vm/opto/regalloc.cpp Thu Nov 21 19:00:57 2013 -0800 @@ -77,7 +77,9 @@ assert( reg < _matcher._old_SP || (reg >= OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots()) && reg < _matcher._in_arg_limit) || - reg >= OptoReg::add(_matcher._new_SP,C->out_preserve_stack_slots()), + reg >= OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) || + // Allow return_addr in the out-preserve area. + reg == _matcher.return_addr(), "register allocated in a preserve area" ); return reg2offset_unchecked( reg ); } diff -r b0133e4187d3 -r 15120a36272d src/share/vm/opto/type.cpp --- a/src/share/vm/opto/type.cpp Thu Nov 21 18:29:34 2013 -0800 +++ b/src/share/vm/opto/type.cpp Thu Nov 21 19:00:57 2013 -0800 @@ -61,17 +61,22 @@ { Bad, T_ILLEGAL, "tuple:", false, Node::NotAMachineReg, relocInfo::none }, // Tuple { Bad, T_ARRAY, "array:", false, Node::NotAMachineReg, relocInfo::none }, // Array -#ifndef SPARC +#ifdef SPARC + { Bad, T_ILLEGAL, "vectors:", false, 0, relocInfo::none }, // VectorS + { Bad, T_ILLEGAL, "vectord:", false, Op_RegD, relocInfo::none }, // VectorD + { Bad, T_ILLEGAL, "vectorx:", false, 0, relocInfo::none }, // VectorX + { Bad, T_ILLEGAL, "vectory:", false, 0, relocInfo::none }, // VectorY +#elif defined(PPC64) + { Bad, T_ILLEGAL, "vectors:", false, 0, relocInfo::none }, // VectorS + { Bad, T_ILLEGAL, "vectord:", false, Op_RegL, relocInfo::none }, // VectorD + { Bad, T_ILLEGAL, "vectorx:", false, 0, relocInfo::none }, // VectorX + { Bad, T_ILLEGAL, "vectory:", false, 0, relocInfo::none }, // VectorY +#else // all other { Bad, T_ILLEGAL, "vectors:", false, Op_VecS, relocInfo::none }, // VectorS { Bad, T_ILLEGAL, "vectord:", false, Op_VecD, relocInfo::none }, // VectorD { Bad, T_ILLEGAL, "vectorx:", false, Op_VecX, relocInfo::none }, // VectorX { Bad, T_ILLEGAL, "vectory:", false, Op_VecY, relocInfo::none }, // VectorY -#else - { Bad, T_ILLEGAL, "vectors:", false, 0, relocInfo::none }, // VectorS - { Bad, T_ILLEGAL, "vectord:", false, Op_RegD, relocInfo::none }, // VectorD - { Bad, T_ILLEGAL, "vectorx:", false, 0, relocInfo::none }, // VectorX - { Bad, T_ILLEGAL, "vectory:", false, 0, relocInfo::none }, // VectorY -#endif // IA32 || AMD64 +#endif { Bad, T_ADDRESS, "anyptr:", false, Op_RegP, relocInfo::none }, // AnyPtr { Bad, T_ADDRESS, "rawptr:", false, Op_RegP, relocInfo::none }, // RawPtr { Bad, T_OBJECT, "oop:", true, Op_RegP, relocInfo::oop_type }, // OopPtr @@ -2035,6 +2040,7 @@ switch (Matcher::vector_ideal_reg(size)) { case Op_VecS: return (TypeVect*)(new TypeVectS(elem, length))->hashcons(); + case Op_RegL: case Op_VecD: case Op_RegD: return (TypeVect*)(new TypeVectD(elem, length))->hashcons(); diff -r b0133e4187d3 -r 15120a36272d src/share/vm/opto/type.hpp --- a/src/share/vm/opto/type.hpp Thu Nov 21 18:29:34 2013 -0800 +++ b/src/share/vm/opto/type.hpp Thu Nov 21 19:00:57 2013 -0800 @@ -524,6 +524,9 @@ bool is_con(int i) const { return is_con() && _lo == i; } jlong get_con() const { assert( is_con(), "" ); return _lo; } + // Check for positive 32-bit value. + int is_positive_int() const { return _lo >= 0 && _hi <= (jlong)max_jint; } + virtual bool is_finite() const; // Has a finite value virtual const Type *xmeet( const Type *t ) const;