# HG changeset patch
# User Roland Schatz <roland.schatz@oracle.com>
# Date 1362579621 -3600
# Node ID 73536049fa29aca448a29424f7b8f683f099da5c
# Parent  22bbd34705ed1a932e0e6f13352167f897bd48d8
Use int instead of Register for opcode extensions that are encoded in the ModR/M byte.

diff -r 22bbd34705ed -r 73536049fa29 graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java
--- a/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java	Wed Mar 06 13:24:11 2013 +0100
+++ b/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java	Wed Mar 06 15:20:21 2013 +0100
@@ -203,16 +203,16 @@
     }
 
     // immediate-to-memory forms
-    private void emitArithOperand(int op1, Register rm, AMD64Address adr, int imm32) {
+    private void emitArithOperand(int op1, int op2, AMD64Address adr, int imm32) {
         assert (op1 & 0x01) == 1 : "should be 32bit operation";
         assert (op1 & 0x02) == 0 : "sign-extension bit should not be set";
         if (isByte(imm32)) {
             emitByte(op1 | 0x02); // set sign bit
-            emitOperandHelper(rm, adr);
+            emitOperandHelper(op2, adr);
             emitByte(imm32 & 0xFF);
         } else {
             emitByte(op1);
-            emitOperandHelper(rm, adr);
+            emitOperandHelper(op2, adr);
             emitInt(imm32);
         }
     }
@@ -224,6 +224,14 @@
     }
 
     protected void emitOperandHelper(Register reg, AMD64Address addr) {
+        assert reg != Register.None;
+        emitOperandHelper(encode(reg), addr);
+    }
+
+    protected void emitOperandHelper(int reg, AMD64Address addr) {
+        assert (reg & 0x07) == reg;
+        int regenc = reg << 3;
+
         Register base = isLegal(addr.getBase()) ? asRegister(addr.getBase()) : Register.None;
         Register index = isLegal(addr.getIndex()) ? asRegister(addr.getIndex()) : Register.None;
 
@@ -235,11 +243,6 @@
             base = frameRegister;
         }
 
-        // Encode the registers as needed in the fields they are used in
-
-        assert reg != Register.None;
-        int regenc = encode(reg) << 3;
-
         if (base == AMD64.rip) { // also matches Placeholder
             // [00 000 101] disp32
             assert index == Register.None : "cannot use RIP relative addressing with index register";
@@ -331,7 +334,7 @@
 
     public final void addl(AMD64Address dst, int imm32) {
         prefix(dst);
-        emitArithOperand(0x81, rax, dst, imm32);
+        emitArithOperand(0x81, 0, dst, imm32);
     }
 
     public final void addl(Register dst, int imm32) {
@@ -600,7 +603,7 @@
     protected final void decl(AMD64Address dst) {
         prefix(dst);
         emitByte(0xFF);
-        emitOperandHelper(rcx, dst);
+        emitOperandHelper(1, dst);
     }
 
     public final void divsd(Register dst, AMD64Address src) {
@@ -687,7 +690,7 @@
     protected final void incl(AMD64Address dst) {
         prefix(dst);
         emitByte(0xFF);
-        emitOperandHelper(rax, dst);
+        emitOperandHelper(0, dst);
     }
 
     private void jcc(ConditionFlag cc, int jumpTarget, boolean forceDisp32) {
@@ -863,7 +866,7 @@
     public final void movb(AMD64Address dst, int imm8) {
         prefix(dst);
         emitByte(0xC6);
-        emitOperandHelper(rax, dst);
+        emitOperandHelper(0, dst);
         emitByte(imm8);
     }
 
@@ -914,7 +917,7 @@
     public final void movl(AMD64Address dst, int imm32) {
         prefix(dst);
         emitByte(0xC7);
-        emitOperandHelper(rax, dst);
+        emitOperandHelper(0, dst);
         emitInt(imm32);
     }
 
@@ -1061,7 +1064,7 @@
         emitByte(0x66); // switch to 16-bit mode
         prefix(dst);
         emitByte(0xC7);
-        emitOperandHelper(rax, dst);
+        emitOperandHelper(0, dst);
         emitShort(imm16);
     }
 
@@ -1468,15 +1471,7 @@
 
     public final void subl(AMD64Address dst, int imm32) {
         prefix(dst);
-        if (isByte(imm32)) {
-            emitByte(0x83);
-            emitOperandHelper(rbp, dst);
-            emitByte(imm32 & 0xFF);
-        } else {
-            emitByte(0x81);
-            emitOperandHelper(rbp, dst);
-            emitInt(imm32);
-        }
+        emitArithOperand(0x81, 5, dst, imm32);
     }
 
     public final void subl(Register dst, int imm32) {
@@ -2010,7 +2005,7 @@
     protected final void decq(AMD64Address dst) {
         prefixq(dst);
         emitByte(0xFF);
-        emitOperandHelper(rcx, dst);
+        emitOperandHelper(1, dst);
     }
 
     public final void divq(Register src) {
@@ -2092,7 +2087,7 @@
     public final void movslq(AMD64Address dst, int imm32) {
         prefixq(dst);
         emitByte(0xC7);
-        emitOperandHelper(rax, dst);
+        emitOperandHelper(0, dst);
         emitInt(imm32);
     }
 
@@ -2333,7 +2328,7 @@
 
     public final void fld(AMD64Address src) {
         emitByte(0xDD);
-        emitOperandHelper(rax, src);
+        emitOperandHelper(0, src);
     }
 
     public final void fldln2() {
@@ -2353,7 +2348,7 @@
 
     public final void fstp(AMD64Address src) {
         emitByte(0xDD);
-        emitOperandHelper(rbx, src);
+        emitOperandHelper(3, src);
     }
 
     public final void fsin() {