# HG changeset patch
# User Roland Schatz <roland.schatz@oracle.com>
# Date 1392983906 -3600
# Node ID 79114edb513098ad566b1336d49d80fb0de96274
# Parent  958c99d0790cfa397a056256dea3ad274e004b22
Explicit x2L instructions in AMD64 backend.

diff -r 958c99d0790c -r 79114edb5130 graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java
--- a/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java	Fri Feb 21 11:53:48 2014 +0100
+++ b/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java	Fri Feb 21 12:58:26 2014 +0100
@@ -1034,6 +1034,20 @@
         emitByte(0xC0 | encode);
     }
 
+    public final void movsbq(Register dst, AMD64Address src) {
+        prefixq(src, dst);
+        emitByte(0x0F);
+        emitByte(0xBE);
+        emitOperandHelper(dst, src);
+    }
+
+    public final void movsbq(Register dst, Register src) {
+        int encode = prefixqAndEncode(dst.encoding, src.encoding);
+        emitByte(0x0F);
+        emitByte(0xBE);
+        emitByte(0xC0 | encode);
+    }
+
     public final void movsd(Register dst, Register src) {
         assert dst.getRegisterCategory() == AMD64.XMM;
         assert src.getRegisterCategory() == AMD64.XMM;
@@ -1104,6 +1118,20 @@
         emitByte(0xC0 | encode);
     }
 
+    public final void movswq(Register dst, AMD64Address src) {
+        prefixq(src, dst);
+        emitByte(0x0F);
+        emitByte(0xBF);
+        emitOperandHelper(dst, src);
+    }
+
+    public final void movswq(Register dst, Register src) {
+        int encode = prefixqAndEncode(dst.encoding, src.encoding);
+        emitByte(0x0F);
+        emitByte(0xBF);
+        emitByte(0xC0 | encode);
+    }
+
     public final void movw(AMD64Address dst, int imm16) {
         emitByte(0x66); // switch to 16-bit mode
         prefix(dst);
diff -r 958c99d0790c -r 79114edb5130 graal/com.oracle.graal.compiler.amd64/src/com/oracle/graal/compiler/amd64/AMD64LIRGenerator.java
--- a/graal/com.oracle.graal.compiler.amd64/src/com/oracle/graal/compiler/amd64/AMD64LIRGenerator.java	Fri Feb 21 11:53:48 2014 +0100
+++ b/graal/com.oracle.graal.compiler.amd64/src/com/oracle/graal/compiler/amd64/AMD64LIRGenerator.java	Fri Feb 21 12:58:26 2014 +0100
@@ -802,22 +802,23 @@
             return inputVal;
         } else if (toBits > 32) {
             // sign extend to 64 bits
-            if (fromBits == 32) {
-                return emitConvert2Op(Kind.Long, I2L, asAllocatable(inputVal));
-            } else if (fromBits < 32) {
-                // TODO implement direct x2L sign extension conversions
-                Value intVal = emitSignExtend(inputVal, fromBits, 32);
-                return emitSignExtend(intVal, 32, toBits);
-            } else {
-                throw GraalInternalError.unimplemented("unsupported sign extension (" + fromBits + " bit -> " + toBits + " bit)");
+            switch (fromBits) {
+                case 8:
+                    return emitConvert2Op(Kind.Long, B2L, asAllocatable(inputVal));
+                case 16:
+                    return emitConvert2Op(Kind.Long, S2L, asAllocatable(inputVal));
+                case 32:
+                    return emitConvert2Op(Kind.Long, I2L, asAllocatable(inputVal));
+                default:
+                    throw GraalInternalError.unimplemented("unsupported sign extension (" + fromBits + " bit -> " + toBits + " bit)");
             }
         } else {
             // sign extend to 32 bits (smaller values are internally represented as 32 bit values)
             switch (fromBits) {
                 case 8:
-                    return emitConvert2Op(Kind.Int, I2B, asAllocatable(inputVal));
+                    return emitConvert2Op(Kind.Int, B2I, asAllocatable(inputVal));
                 case 16:
-                    return emitConvert2Op(Kind.Int, I2S, asAllocatable(inputVal));
+                    return emitConvert2Op(Kind.Int, S2I, asAllocatable(inputVal));
                 case 32:
                     return inputVal;
                 default:
diff -r 958c99d0790c -r 79114edb5130 graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java	Fri Feb 21 11:53:48 2014 +0100
+++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java	Fri Feb 21 12:58:26 2014 +0100
@@ -44,7 +44,7 @@
     DADD, DSUB, DMUL, DDIV, DREM, DAND, DOR, DXOR,
     INEG, LNEG, INOT, LNOT,
     SQRT,
-    I2L, L2I, I2B, I2C, I2S,
+    L2I, B2I, S2I, B2L, S2L, I2L,
     F2D, D2F,
     I2F, I2D,
     L2F, L2D,
@@ -373,9 +373,6 @@
             case L2I:
                 masm.andl(asIntReg(result), 0xFFFFFFFF);
                 break;
-            case I2C:
-                masm.andl(asIntReg(result), 0xFFFF);
-                break;
             default:
                 throw GraalInternalError.shouldNotReachHere();
         }
@@ -495,12 +492,18 @@
                     masm.sqrtsd(asDoubleReg(dst), asDoubleReg(src));
                     break;
 
-                case I2B:
+                case B2I:
                     masm.movsbl(asIntReg(dst), asIntReg(src));
                     break;
-                case I2S:
+                case S2I:
                     masm.movswl(asIntReg(dst), asIntReg(src));
                     break;
+                case B2L:
+                    masm.movsbq(asLongReg(dst), asIntReg(src));
+                    break;
+                case S2L:
+                    masm.movswq(asLongReg(dst), asIntReg(src));
+                    break;
                 case I2L:
                     masm.movslq(asLongReg(dst), asIntReg(src));
                     break;
@@ -755,12 +758,18 @@
                     masm.sqrtsd(asDoubleReg(dst), (AMD64Address) crb.asDoubleAddr(src));
                     break;
 
-                case I2B:
+                case B2I:
                     masm.movsbl(asIntReg(dst), (AMD64Address) crb.asIntAddr(src));
                     break;
-                case I2S:
+                case S2I:
                     masm.movswl(asIntReg(dst), (AMD64Address) crb.asIntAddr(src));
                     break;
+                case B2L:
+                    masm.movsbq(asLongReg(dst), (AMD64Address) crb.asIntAddr(src));
+                    break;
+                case S2L:
+                    masm.movswq(asLongReg(dst), (AMD64Address) crb.asIntAddr(src));
+                    break;
                 case I2L:
                     masm.movslq(asLongReg(dst), (AMD64Address) crb.asIntAddr(src));
                     break;